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iio: adc: ad7768-1: Ensure SYNC_IN pulse minimum timing requirement

The SYNC_IN pulse width must be at least 1.5 x Tmclk, corresponding to
~2.5 µs at the lowest supported MCLK frequency. Add a 3 µs delay to
ensure reliable synchronization timing even for the worst-case scenario.

Signed-off-by: Jonathan Santos <Jonathan.Santos@analog.com>
Reviewed-by: David Lechner <dlechner@baylibre.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://patch.msgid.link/d3ee92a533cd1207cf5c5cc4d7bdbb5c6c267f68.1749063024.git.Jonathan.Santos@analog.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

authored by

Jonathan Santos and committed by
Jonathan Cameron 7e54d932 a238572b

+19 -4
+19 -4
drivers/iio/adc/ad7768-1.c
··· 252 252 .max_register = AD7768_REG24_COEFF_DATA, 253 253 }; 254 254 255 + static int ad7768_send_sync_pulse(struct ad7768_state *st) 256 + { 257 + /* 258 + * The datasheet specifies a minimum SYNC_IN pulse width of 1.5 × Tmclk, 259 + * where Tmclk is the MCLK period. The supported MCLK frequencies range 260 + * from 0.6 MHz to 17 MHz, which corresponds to a minimum SYNC_IN pulse 261 + * width of approximately 2.5 µs in the worst-case scenario (0.6 MHz). 262 + * 263 + * Add a delay to ensure the pulse width is always sufficient to 264 + * trigger synchronization. 265 + */ 266 + gpiod_set_value_cansleep(st->gpio_sync_in, 1); 267 + fsleep(3); 268 + gpiod_set_value_cansleep(st->gpio_sync_in, 0); 269 + 270 + return 0; 271 + } 272 + 255 273 static int ad7768_set_mode(struct ad7768_state *st, 256 274 enum ad7768_conv_mode mode) 257 275 { ··· 357 339 return ret; 358 340 359 341 /* A sync-in pulse is required every time the filter dec rate changes */ 360 - gpiod_set_value(st->gpio_sync_in, 1); 361 - gpiod_set_value(st->gpio_sync_in, 0); 362 - 363 - return 0; 342 + return ad7768_send_sync_pulse(st); 364 343 } 365 344 366 345 static int ad7768_set_freq(struct ad7768_state *st,