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Merge branch '4.14-fixes' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS fixes from Ralf Baechle:

- Fix a build error on MSP71xx which used to rely on somehow magically
<asm/setup.h> being pulled in which no longer happens.

- Fix the __write_64bit_c0_split inline assembler where there was the
theoretical possibility of GCC interpret the constraints such that
bad code could result.

- A __init was causing section mismatch errors on Alchemy. Just to be
on the safe side, Manuel's patch does away with all of them.

- Fix perf event init.

* '4.14-fixes' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
MIPS: PCI: fix pcibios_map_irq section mismatch
MIPS: Fix input modify in __write_64bit_c0_split()
MIPS: MSP71xx: Include asm/setup.h
MIPS: Fix perf event init

+37 -33
+9 -6
arch/mips/include/asm/mipsregs.h
··· 1377 1377 1378 1378 #define __write_64bit_c0_split(source, sel, val) \ 1379 1379 do { \ 1380 + unsigned long long __tmp; \ 1380 1381 unsigned long __flags; \ 1381 1382 \ 1382 1383 local_irq_save(__flags); \ 1383 1384 if (sel == 0) \ 1384 1385 __asm__ __volatile__( \ 1385 1386 ".set\tmips64\n\t" \ 1386 - "dsll\t%L0, %L0, 32\n\t" \ 1387 + "dsll\t%L0, %L1, 32\n\t" \ 1387 1388 "dsrl\t%L0, %L0, 32\n\t" \ 1388 - "dsll\t%M0, %M0, 32\n\t" \ 1389 + "dsll\t%M0, %M1, 32\n\t" \ 1389 1390 "or\t%L0, %L0, %M0\n\t" \ 1390 1391 "dmtc0\t%L0, " #source "\n\t" \ 1391 1392 ".set\tmips0" \ 1392 - : : "r" (val)); \ 1393 + : "=&r,r" (__tmp) \ 1394 + : "r,0" (val)); \ 1393 1395 else \ 1394 1396 __asm__ __volatile__( \ 1395 1397 ".set\tmips64\n\t" \ 1396 - "dsll\t%L0, %L0, 32\n\t" \ 1398 + "dsll\t%L0, %L1, 32\n\t" \ 1397 1399 "dsrl\t%L0, %L0, 32\n\t" \ 1398 - "dsll\t%M0, %M0, 32\n\t" \ 1400 + "dsll\t%M0, %M1, 32\n\t" \ 1399 1401 "or\t%L0, %L0, %M0\n\t" \ 1400 1402 "dmtc0\t%L0, " #source ", " #sel "\n\t" \ 1401 1403 ".set\tmips0" \ 1402 - : : "r" (val)); \ 1404 + : "=&r,r" (__tmp) \ 1405 + : "r,0" (val)); \ 1403 1406 local_irq_restore(__flags); \ 1404 1407 } while (0) 1405 1408
+1 -2
arch/mips/kernel/perf_event_mipsxx.c
··· 618 618 return -ENOENT; 619 619 } 620 620 621 - if ((unsigned int)event->cpu >= nr_cpumask_bits || 622 - (event->cpu >= 0 && !cpu_online(event->cpu))) 621 + if (event->cpu >= 0 && !cpu_online(event->cpu)) 623 622 return -ENODEV; 624 623 625 624 if (!atomic_inc_not_zero(&active_events)) {
+1 -1
arch/mips/pci/fixup-capcella.c
··· 38 38 [14] = { -1, INTA, INTB, INTC, INTD } 39 39 }; 40 40 41 - int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 41 + int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 42 42 { 43 43 return irq_tab_capcella[slot][pin]; 44 44 }
+1 -1
arch/mips/pci/fixup-cobalt.c
··· 174 174 [COBALT_PCICONF_ETH1] = ETH1_IRQ 175 175 }; 176 176 177 - int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 177 + int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 178 178 { 179 179 if (cobalt_board_id <= COBALT_BRD_ID_QUBE1) 180 180 return irq_tab_qube1[slot];
+1 -1
arch/mips/pci/fixup-emma2rh.c
··· 85 85 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_EMMA2RH, 86 86 emma2rh_pci_host_fixup); 87 87 88 - int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 88 + int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 89 89 { 90 90 return irq_map[slot][pin]; 91 91 }
+1 -1
arch/mips/pci/fixup-fuloong2e.c
··· 19 19 /* South bridge slot number is set by the pci probe process */ 20 20 static u8 sb_slot = 5; 21 21 22 - int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 22 + int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 23 23 { 24 24 int irq = 0; 25 25
+1 -1
arch/mips/pci/fixup-ip32.c
··· 39 39 * irqs. I suppose a device without a pin A will thank us for doing it 40 40 * right if there exists such a broken piece of crap. 41 41 */ 42 - int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 42 + int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 43 43 { 44 44 return irq_tab_mace[slot][pin]; 45 45 }
+1 -1
arch/mips/pci/fixup-lantiq.c
··· 23 23 return 0; 24 24 } 25 25 26 - int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 26 + int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 27 27 { 28 28 return of_irq_parse_and_map_pci(dev, slot, pin); 29 29 }
+1 -1
arch/mips/pci/fixup-lemote2f.c
··· 51 51 {0, 0, 0, 0, 0}, /* 27: Unused */ 52 52 }; 53 53 54 - int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 54 + int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 55 55 { 56 56 int virq; 57 57
+1 -1
arch/mips/pci/fixup-loongson3.c
··· 32 32 pdev->vendor, pdev->device, pdev->irq); 33 33 } 34 34 35 - int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 35 + int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 36 36 { 37 37 print_fixup_info(dev); 38 38 return dev->irq;
+1 -1
arch/mips/pci/fixup-malta.c
··· 38 38 {0, PCID, PCIA, PCIB, PCIC } /* 21: PCI Slot 4 */ 39 39 }; 40 40 41 - int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 41 + int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 42 42 { 43 43 int virq; 44 44 virq = irq_tab[slot][pin];
+1 -1
arch/mips/pci/fixup-mpc30x.c
··· 34 34 [29] = MQ200_IRQ, 35 35 }; 36 36 37 - int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 37 + int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 38 38 { 39 39 if (slot == 30) 40 40 return internal_func_irqs[PCI_FUNC(dev->devfn)];
+1 -1
arch/mips/pci/fixup-pmcmsp.c
··· 202 202 * RETURNS: IRQ number 203 203 * 204 204 ****************************************************************************/ 205 - int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 205 + int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 206 206 { 207 207 #if !defined(CONFIG_PMC_MSP7120_GW) && !defined(CONFIG_PMC_MSP7120_EVAL) 208 208 printk(KERN_WARNING "PCI: unknown board, no PCI IRQs assigned.\n");
+1 -1
arch/mips/pci/fixup-sni.c
··· 130 130 return (csmsr & 0xa0) == 0x20; 131 131 } 132 132 133 - int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 133 + int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 134 134 { 135 135 switch (sni_brd_type) { 136 136 case SNI_BRD_PCI_TOWER_CPLUS:
+1 -1
arch/mips/pci/fixup-tb0219.c
··· 23 23 24 24 #include <asm/vr41xx/tb0219.h> 25 25 26 - int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 26 + int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 27 27 { 28 28 int irq = -1; 29 29
+1 -1
arch/mips/pci/fixup-tb0226.c
··· 23 23 #include <asm/vr41xx/giu.h> 24 24 #include <asm/vr41xx/tb0226.h> 25 25 26 - int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 26 + int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 27 27 { 28 28 int irq = -1; 29 29
+1 -1
arch/mips/pci/fixup-tb0287.c
··· 22 22 23 23 #include <asm/vr41xx/tb0287.h> 24 24 25 - int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 25 + int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 26 26 { 27 27 unsigned char bus; 28 28 int irq = -1;
+1 -1
arch/mips/pci/pci-alchemy.c
··· 522 522 arch_initcall(alchemy_pci_init); 523 523 524 524 525 - int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 525 + int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 526 526 { 527 527 struct alchemy_pci_context *ctx = dev->sysdata; 528 528 if (ctx && ctx->board_map_irq)
+1 -1
arch/mips/pci/pci-bcm47xx.c
··· 28 28 #include <linux/bcma/bcma.h> 29 29 #include <bcm47xx.h> 30 30 31 - int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 31 + int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 32 32 { 33 33 return 0; 34 34 }
+1 -1
arch/mips/pci/pci-lasat.c
··· 61 61 #define LASAT_IRQ_PCIC (LASAT_IRQ_BASE + 7) 62 62 #define LASAT_IRQ_PCID (LASAT_IRQ_BASE + 8) 63 63 64 - int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 64 + int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 65 65 { 66 66 switch (slot) { 67 67 case 1:
+1 -1
arch/mips/pci/pci-mt7620.c
··· 361 361 return 0; 362 362 } 363 363 364 - int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 364 + int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 365 365 { 366 366 u16 cmd; 367 367 u32 val;
+2 -2
arch/mips/pci/pci-octeon.c
··· 59 59 } s; 60 60 }; 61 61 62 - int __initconst (*octeon_pcibios_map_irq)(const struct pci_dev *dev, 62 + int (*octeon_pcibios_map_irq)(const struct pci_dev *dev, 63 63 u8 slot, u8 pin); 64 64 enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID; 65 65 ··· 74 74 * as it goes through each bridge. 75 75 * Returns Interrupt number for the device 76 76 */ 77 - int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 77 + int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 78 78 { 79 79 if (octeon_pcibios_map_irq) 80 80 return octeon_pcibios_map_irq(dev, slot, pin);
+1 -1
arch/mips/pci/pci-rt2880.c
··· 181 181 spin_unlock_irqrestore(&rt2880_pci_lock, flags); 182 182 } 183 183 184 - int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 184 + int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 185 185 { 186 186 u16 cmd; 187 187 int irq = -1;
+1 -1
arch/mips/pci/pci-rt3883.c
··· 564 564 return err; 565 565 } 566 566 567 - int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 567 + int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 568 568 { 569 569 return of_irq_parse_and_map_pci(dev, slot, pin); 570 570 }
+1 -1
arch/mips/pci/pci-xlp.c
··· 205 205 return PCI_SLOT(lnkdev->devfn) / 8; 206 206 } 207 207 208 - int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 208 + int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 209 209 { 210 210 struct pci_dev *lnkdev; 211 211 int lnkfunc, node;
+1 -1
arch/mips/pci/pci-xlr.c
··· 315 315 } 316 316 } 317 317 318 - int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 318 + int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 319 319 { 320 320 return get_irq_vector(dev); 321 321 }
+2
arch/mips/pmcs-msp71xx/msp_smp.c
··· 22 22 #include <linux/smp.h> 23 23 #include <linux/interrupt.h> 24 24 25 + #include <asm/setup.h> 26 + 25 27 #ifdef CONFIG_MIPS_MT_SMP 26 28 #define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */ 27 29 #define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for call */