Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
perf/x86/intel/cstate: Add Nova Lake support
Similar to Lunar Lake and Panther Lake, Nova Lake supports CC1/CC6/CC7
and PC2/PC6/PC10 residency counters; it also adds support for MC6.
Signed-off-by: Zide Chen <zide.chen@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Link: https://patch.msgid.link/20251215182520.115822-2-zide.chen@intel.com
authored by
Zide Chen
and committed by
Ingo Molnar
7e760ac4
6d4b8d05
+22
-7
+22
-7
arch/x86/events/intel/cstate.c
+22
-7
arch/x86/events/intel/cstate.c
···
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* MSR_CORE_C1_RES: CORE C1 Residency Counter
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* perf code: 0x00
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* Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL
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-
* MTL,SRF,GRR,ARL,LNL,PTL,WCL
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* MTL,SRF,GRR,ARL,LNL,PTL,WCL,NVL
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* Scope: Core (each processor core has a MSR)
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* MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
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* perf code: 0x01
···
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* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
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* SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
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* TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
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-
* GRR,ARL,LNL,PTL,WCL
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* GRR,ARL,LNL,PTL,WCL,NVL
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* Scope: Core
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* MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
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* perf code: 0x03
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* Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,
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* ICL,TGL,RKL,ADL,RPL,MTL,ARL,LNL,
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* PTL,WCL
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* PTL,WCL,NVL
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* Scope: Core
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* MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter.
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* perf code: 0x00
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* Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
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* KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL,
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* RPL,SPR,MTL,ARL,LNL,SRF,PTL,WCL
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* RPL,SPR,MTL,ARL,LNL,SRF,PTL,WCL,
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* NVL
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* Scope: Package (physical package)
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* MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter.
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* perf code: 0x01
···
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* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
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* SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
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* TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
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* ARL,LNL,PTL,WCL
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* ARL,LNL,PTL,WCL,NVL
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* Scope: Package (physical package)
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* MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
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* perf code: 0x03
···
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* perf code: 0x06
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* Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL,
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* TNT,RKL,ADL,RPL,MTL,ARL,LNL,PTL,
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* WCL
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* WCL,NVL
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* Scope: Package (physical package)
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* MSR_MODULE_C6_RES_MS: Module C6 Residency Counter.
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* perf code: 0x00
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-
* Available model: SRF,GRR
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* Available model: SRF,GRR,NVL
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* Scope: A cluster of cores shared L2 cache
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*
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*/
···
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BIT(PERF_CSTATE_PKG_C10_RES),
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};
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+
static const struct cstate_model nvl_cstates __initconst = {
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.core_events = BIT(PERF_CSTATE_CORE_C1_RES) |
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BIT(PERF_CSTATE_CORE_C6_RES) |
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BIT(PERF_CSTATE_CORE_C7_RES),
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.module_events = BIT(PERF_CSTATE_MODULE_C6_RES),
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+
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.pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) |
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BIT(PERF_CSTATE_PKG_C6_RES) |
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BIT(PERF_CSTATE_PKG_C10_RES),
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};
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+
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static const struct cstate_model slm_cstates __initconst = {
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.core_events = BIT(PERF_CSTATE_CORE_C1_RES) |
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BIT(PERF_CSTATE_CORE_C6_RES),
···
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X86_MATCH_VFM(INTEL_LUNARLAKE_M, &lnl_cstates),
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X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &lnl_cstates),
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X86_MATCH_VFM(INTEL_WILDCATLAKE_L, &lnl_cstates),
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X86_MATCH_VFM(INTEL_NOVALAKE, &nvl_cstates),
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X86_MATCH_VFM(INTEL_NOVALAKE_L, &nvl_cstates),
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{ },
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};
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MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);