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net: stmmac: imx: fix iMX93 register definitions

When looking at the iMX93 documentation, the definitions in the driver
do not correspond with the documentation, which makes the driver
confusing.

The driver, for example, re-uses a definition for bit 0 for two
different registers, where this bit have completely different purposes.

Fix this by renaming the second register, and adding a definition that
reflects the true purpose of bit 0 in the first register (EQOS enable.)

Replace MX93_GPR_ENET_QOS_INTF_MODE_MASK with MX93_GPR_ENET_QOS_ENABLE
and MX93_GPR_ENET_QOS_INTF_SEL_MASK as MX93_GPR_ENET_QOS_INTF_MODE_MASK
is not a register field.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/E1vnaGl-00000007i9f-0ZMw@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

authored by

Russell King (Oracle) and committed by
Jakub Kicinski 7e7fcfb0 85d05e28

+14 -11
+14 -11
drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
··· 28 28 #define GPR_ENET_QOS_CLK_TX_CLK_SEL (0x1 << 20) 29 29 #define GPR_ENET_QOS_RGMII_EN (0x1 << 21) 30 30 31 - #define MX93_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 0) 32 31 #define MX93_GPR_ENET_QOS_INTF_SEL_MASK GENMASK(3, 1) 33 - #define MX93_GPR_ENET_QOS_CLK_GEN_EN (0x1 << 0) 34 - #define MX93_GPR_ENET_QOS_CLK_SEL_MASK BIT_MASK(0) 35 - #define MX93_GPR_CLK_SEL_OFFSET (4) 32 + #define MX93_GPR_ENET_QOS_ENABLE BIT(0) 33 + 34 + #define MX93_ENET_CLK_SEL_OFFSET (4) 35 + #define MX93_ENET_QOS_CLK_TX_SEL_MASK BIT_MASK(0) 36 36 37 37 #define DMA_BUS_MODE 0x00001000 38 38 #define DMA_BUS_MODE_SFT_RESET (0x1 << 0) ··· 95 95 if (phy_intf_sel == PHY_INTF_SEL_RMII && dwmac->rmii_refclk_ext) { 96 96 ret = regmap_clear_bits(dwmac->intf_regmap, 97 97 dwmac->intf_reg_off + 98 - MX93_GPR_CLK_SEL_OFFSET, 99 - MX93_GPR_ENET_QOS_CLK_SEL_MASK); 98 + MX93_ENET_CLK_SEL_OFFSET, 99 + MX93_ENET_QOS_CLK_TX_SEL_MASK); 100 100 if (ret) 101 101 return ret; 102 102 } 103 103 104 104 val = FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, phy_intf_sel) | 105 - MX93_GPR_ENET_QOS_CLK_GEN_EN; 105 + MX93_GPR_ENET_QOS_ENABLE; 106 106 107 107 return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off, 108 - MX93_GPR_ENET_QOS_INTF_MODE_MASK, val); 108 + MX93_GPR_ENET_QOS_INTF_SEL_MASK | 109 + MX93_GPR_ENET_QOS_ENABLE, val); 109 110 }; 110 111 111 112 static int imx_dwmac_clks_config(void *priv, bool enabled) ··· 206 205 old_ctrl = readl(dwmac->base_addr + MAC_CTRL_REG); 207 206 ctrl = old_ctrl & ~CTRL_SPEED_MASK; 208 207 regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off, 209 - MX93_GPR_ENET_QOS_INTF_MODE_MASK, 0); 208 + MX93_GPR_ENET_QOS_INTF_SEL_MASK | 209 + MX93_GPR_ENET_QOS_ENABLE, 0); 210 210 writel(ctrl, dwmac->base_addr + MAC_CTRL_REG); 211 211 212 212 /* Ensure the settings for CTRL are applied. */ ··· 215 213 216 214 usleep_range(10, 20); 217 215 iface &= MX93_GPR_ENET_QOS_INTF_SEL_MASK; 218 - iface |= MX93_GPR_ENET_QOS_CLK_GEN_EN; 216 + iface |= MX93_GPR_ENET_QOS_ENABLE; 219 217 regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off, 220 - MX93_GPR_ENET_QOS_INTF_MODE_MASK, iface); 218 + MX93_GPR_ENET_QOS_INTF_SEL_MASK | 219 + MX93_GPR_ENET_QOS_ENABLE, iface); 221 220 222 221 writel(old_ctrl, dwmac->base_addr + MAC_CTRL_REG); 223 222 }