Merge tag 'hwmon-for-v5.10-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging

+1 -1

drivers/hwmon/amd_energy.c

··· 171 171 enum hwmon_sensor_types type, 172 172 u32 attr, int channel) 173 173 { 174 - return 0444; 174 + return 0440; 175 175 } 176 176 177 177 static int energy_accumulator(void *p)

+82 -48

drivers/hwmon/applesmc.c

··· 32 32 #include <linux/hwmon.h> 33 33 #include <linux/workqueue.h> 34 34 #include <linux/err.h> 35 + #include <linux/bits.h> 35 36 36 37 /* data port used by Apple SMC */ 37 38 #define APPLESMC_DATA_PORT 0x300 ··· 43 42 44 43 #define APPLESMC_MAX_DATA_LENGTH 32 45 44 46 - /* wait up to 128 ms for a status change. */ 47 - #define APPLESMC_MIN_WAIT 0x0010 48 - #define APPLESMC_RETRY_WAIT 0x0100 49 - #define APPLESMC_MAX_WAIT 0x20000 45 + /* Apple SMC status bits */ 46 + #define SMC_STATUS_AWAITING_DATA BIT(0) /* SMC has data waiting to be read */ 47 + #define SMC_STATUS_IB_CLOSED BIT(1) /* Will ignore any input */ 48 + #define SMC_STATUS_BUSY BIT(2) /* Command in progress */ 49 + 50 + /* Initial wait is 8us */ 51 + #define APPLESMC_MIN_WAIT 0x0008 50 52 51 53 #define APPLESMC_READ_CMD 0x10 52 54 #define APPLESMC_WRITE_CMD 0x11 ··· 155 151 static struct workqueue_struct *applesmc_led_wq; 156 152 157 153 /* 158 - * wait_read - Wait for a byte to appear on SMC port. Callers must 159 - * hold applesmc_lock. 154 + * Wait for specific status bits with a mask on the SMC. 155 + * Used before all transactions. 156 + * This does 10 fast loops of 8us then exponentially backs off for a 157 + * minimum total wait of 262ms. Depending on usleep_range this could 158 + * run out past 500ms. 160 159 */ 161 - static int wait_read(void) 160 + 161 + static int wait_status(u8 val, u8 mask) 162 162 { 163 - unsigned long end = jiffies + (APPLESMC_MAX_WAIT * HZ) / USEC_PER_SEC; 164 163 u8 status; 165 164 int us; 165 + int i; 166 166 167 - for (us = APPLESMC_MIN_WAIT; us < APPLESMC_MAX_WAIT; us <<= 1) { 168 - usleep_range(us, us * 16); 167 + us = APPLESMC_MIN_WAIT; 168 + for (i = 0; i < 24 ; i++) { 169 169 status = inb(APPLESMC_CMD_PORT); 170 - /* read: wait for smc to settle */ 171 - if (status & 0x01) 170 + if ((status & mask) == val) 172 171 return 0; 173 - /* timeout: give up */ 174 - if (time_after(jiffies, end)) 175 - break; 172 + usleep_range(us, us * 2); 173 + if (i > 9) 174 + us <<= 1; 176 175 } 177 - 178 - pr_warn("wait_read() fail: 0x%02x\n", status); 179 176 return -EIO; 180 177 } 181 178 182 - /* 183 - * send_byte - Write to SMC port, retrying when necessary. Callers 184 - * must hold applesmc_lock. 185 - */ 179 + /* send_byte - Write to SMC data port. Callers must hold applesmc_lock. */ 180 + 186 181 static int send_byte(u8 cmd, u16 port) 187 182 { 188 - u8 status; 189 - int us; 190 - unsigned long end = jiffies + (APPLESMC_MAX_WAIT * HZ) / USEC_PER_SEC; 183 + int status; 184 + 185 + status = wait_status(0, SMC_STATUS_IB_CLOSED); 186 + if (status) 187 + return status; 188 + /* 189 + * This needs to be a separate read looking for bit 0x04 190 + * after bit 0x02 falls. If consolidated with the wait above 191 + * this extra read may not happen if status returns both 192 + * simultaneously and this would appear to be required. 193 + */ 194 + status = wait_status(SMC_STATUS_BUSY, SMC_STATUS_BUSY); 195 + if (status) 196 + return status; 191 197 192 198 outb(cmd, port); 193 - for (us = APPLESMC_MIN_WAIT; us < APPLESMC_MAX_WAIT; us <<= 1) { 194 - usleep_range(us, us * 16); 195 - status = inb(APPLESMC_CMD_PORT); 196 - /* write: wait for smc to settle */ 197 - if (status & 0x02) 198 - continue; 199 - /* ready: cmd accepted, return */ 200 - if (status & 0x04) 201 - return 0; 202 - /* timeout: give up */ 203 - if (time_after(jiffies, end)) 204 - break; 205 - /* busy: long wait and resend */ 206 - udelay(APPLESMC_RETRY_WAIT); 207 - outb(cmd, port); 208 - } 209 - 210 - pr_warn("send_byte(0x%02x, 0x%04x) fail: 0x%02x\n", cmd, port, status); 211 - return -EIO; 199 + return 0; 212 200 } 201 + 202 + /* send_command - Write a command to the SMC. Callers must hold applesmc_lock. */ 213 203 214 204 static int send_command(u8 cmd) 215 205 { 216 - return send_byte(cmd, APPLESMC_CMD_PORT); 206 + int ret; 207 + 208 + ret = wait_status(0, SMC_STATUS_IB_CLOSED); 209 + if (ret) 210 + return ret; 211 + outb(cmd, APPLESMC_CMD_PORT); 212 + return 0; 213 + } 214 + 215 + /* 216 + * Based on logic from the Apple driver. This is issued before any interaction 217 + * If busy is stuck high, issue a read command to reset the SMC state machine. 218 + * If busy is stuck high after the command then the SMC is jammed. 219 + */ 220 + 221 + static int smc_sane(void) 222 + { 223 + int ret; 224 + 225 + ret = wait_status(0, SMC_STATUS_BUSY); 226 + if (!ret) 227 + return ret; 228 + ret = send_command(APPLESMC_READ_CMD); 229 + if (ret) 230 + return ret; 231 + return wait_status(0, SMC_STATUS_BUSY); 217 232 } 218 233 219 234 static int send_argument(const char *key) ··· 249 226 { 250 227 u8 status, data = 0; 251 228 int i; 229 + int ret; 230 + 231 + ret = smc_sane(); 232 + if (ret) 233 + return ret; 252 234 253 235 if (send_command(cmd) || send_argument(key)) { 254 236 pr_warn("%.4s: read arg fail\n", key); ··· 267 239 } 268 240 269 241 for (i = 0; i < len; i++) { 270 - if (wait_read()) { 242 + if (wait_status(SMC_STATUS_AWAITING_DATA | SMC_STATUS_BUSY, 243 + SMC_STATUS_AWAITING_DATA | SMC_STATUS_BUSY)) { 271 244 pr_warn("%.4s: read data[%d] fail\n", key, i); 272 245 return -EIO; 273 246 } ··· 279 250 for (i = 0; i < 16; i++) { 280 251 udelay(APPLESMC_MIN_WAIT); 281 252 status = inb(APPLESMC_CMD_PORT); 282 - if (!(status & 0x01)) 253 + if (!(status & SMC_STATUS_AWAITING_DATA)) 283 254 break; 284 255 data = inb(APPLESMC_DATA_PORT); 285 256 } 286 257 if (i) 287 258 pr_warn("flushed %d bytes, last value is: %d\n", i, data); 288 259 289 - return 0; 260 + return wait_status(0, SMC_STATUS_BUSY); 290 261 } 291 262 292 263 static int write_smc(u8 cmd, const char *key, const u8 *buffer, u8 len) 293 264 { 294 265 int i; 266 + int ret; 267 + 268 + ret = smc_sane(); 269 + if (ret) 270 + return ret; 295 271 296 272 if (send_command(cmd) || send_argument(key)) { 297 273 pr_warn("%s: write arg fail\n", key); ··· 315 281 } 316 282 } 317 283 318 - return 0; 284 + return wait_status(0, SMC_STATUS_BUSY); 319 285 } 320 286 321 287 static int read_register_count(unsigned int *count)

+13 -13

drivers/hwmon/pmbus/max20730.c

··· 122 122 switch (idx) { 123 123 case MAX20730_DEBUGFS_VOUT_MIN: 124 124 ret = VOLT_FROM_REG(data->mfr_voutmin * 10000); 125 - len = snprintf(tbuf, DEBUG_FS_DATA_MAX, "%d.%d\n", 126 - ret / 10000, ret % 10000); 125 + len = scnprintf(tbuf, DEBUG_FS_DATA_MAX, "%d.%d\n", 126 + ret / 10000, ret % 10000); 127 127 break; 128 128 case MAX20730_DEBUGFS_FREQUENCY: 129 129 val = (data->mfr_devset1 & MAX20730_MFR_DEVSET1_FSW_MASK) ··· 141 141 ret = 800; 142 142 else 143 143 ret = 900; 144 - len = snprintf(tbuf, DEBUG_FS_DATA_MAX, "%d\n", ret); 144 + len = scnprintf(tbuf, DEBUG_FS_DATA_MAX, "%d\n", ret); 145 145 break; 146 146 case MAX20730_DEBUGFS_PG_DELAY: 147 147 val = (data->mfr_devset1 & MAX20730_MFR_DEVSET1_TSTAT_MASK) ··· 223 223 case MAX20730_DEBUGFS_OC_PROTECT_MODE: 224 224 ret = (data->mfr_devset2 & MAX20730_MFR_DEVSET2_OCPM_MASK) 225 225 >> MAX20730_MFR_DEVSET2_OCPM_BIT_POS; 226 - len = snprintf(tbuf, DEBUG_FS_DATA_MAX, "%d\n", ret); 226 + len = scnprintf(tbuf, DEBUG_FS_DATA_MAX, "%d\n", ret); 227 227 break; 228 228 case MAX20730_DEBUGFS_SS_TIMING: 229 229 val = (data->mfr_devset2 & MAX20730_MFR_DEVSET2_SS_MASK) ··· 241 241 case MAX20730_DEBUGFS_IMAX: 242 242 ret = (data->mfr_devset2 & MAX20730_MFR_DEVSET2_IMAX_MASK) 243 243 >> MAX20730_MFR_DEVSET2_IMAX_BIT_POS; 244 - len = snprintf(tbuf, DEBUG_FS_DATA_MAX, "%d\n", ret); 244 + len = scnprintf(tbuf, DEBUG_FS_DATA_MAX, "%d\n", ret); 245 245 break; 246 246 case MAX20730_DEBUGFS_OPERATION: 247 247 ret = i2c_smbus_read_byte_data(psu->client, PMBUS_OPERATION); 248 248 if (ret < 0) 249 249 return ret; 250 - len = snprintf(tbuf, DEBUG_FS_DATA_MAX, "%d\n", ret); 250 + len = scnprintf(tbuf, DEBUG_FS_DATA_MAX, "%d\n", ret); 251 251 break; 252 252 case MAX20730_DEBUGFS_ON_OFF_CONFIG: 253 253 ret = i2c_smbus_read_byte_data(psu->client, PMBUS_ON_OFF_CONFIG); 254 254 if (ret < 0) 255 255 return ret; 256 - len = snprintf(tbuf, DEBUG_FS_DATA_MAX, "%d\n", ret); 256 + len = scnprintf(tbuf, DEBUG_FS_DATA_MAX, "%d\n", ret); 257 257 break; 258 258 case MAX20730_DEBUGFS_SMBALERT_MASK: 259 259 ret = i2c_smbus_read_word_data(psu->client, 260 260 PMBUS_SMB_ALERT_MASK); 261 261 if (ret < 0) 262 262 return ret; 263 - len = snprintf(tbuf, DEBUG_FS_DATA_MAX, "%d\n", ret); 263 + len = scnprintf(tbuf, DEBUG_FS_DATA_MAX, "%d\n", ret); 264 264 break; 265 265 case MAX20730_DEBUGFS_VOUT_MODE: 266 266 ret = i2c_smbus_read_byte_data(psu->client, PMBUS_VOUT_MODE); 267 267 if (ret < 0) 268 268 return ret; 269 - len = snprintf(tbuf, DEBUG_FS_DATA_MAX, "%d\n", ret); 269 + len = scnprintf(tbuf, DEBUG_FS_DATA_MAX, "%d\n", ret); 270 270 break; 271 271 case MAX20730_DEBUGFS_VOUT_COMMAND: 272 272 ret = i2c_smbus_read_word_data(psu->client, PMBUS_VOUT_COMMAND); ··· 274 274 return ret; 275 275 276 276 ret = VOLT_FROM_REG(ret * 10000); 277 - len = snprintf(tbuf, DEBUG_FS_DATA_MAX, 278 - "%d.%d\n", ret / 10000, ret % 10000); 277 + len = scnprintf(tbuf, DEBUG_FS_DATA_MAX, 278 + "%d.%d\n", ret / 10000, ret % 10000); 279 279 break; 280 280 case MAX20730_DEBUGFS_VOUT_MAX: 281 281 ret = i2c_smbus_read_word_data(psu->client, PMBUS_VOUT_MAX); ··· 283 283 return ret; 284 284 285 285 ret = VOLT_FROM_REG(ret * 10000); 286 - len = snprintf(tbuf, DEBUG_FS_DATA_MAX, 287 - "%d.%d\n", ret / 10000, ret % 10000); 286 + len = scnprintf(tbuf, DEBUG_FS_DATA_MAX, 287 + "%d.%d\n", ret / 10000, ret % 10000); 288 288 break; 289 289 default: 290 290 len = strlcpy(tbuf, "Invalid\n", DEBUG_FS_DATA_MAX);

+10 -3

drivers/hwmon/pmbus/pmbus_core.c

··· 941 941 struct i2c_client *client = to_i2c_client(dev->parent); 942 942 struct pmbus_sensor *sensor = to_pmbus_sensor(devattr); 943 943 struct pmbus_data *data = i2c_get_clientdata(client); 944 + ssize_t ret; 944 945 946 + mutex_lock(&data->update_lock); 945 947 pmbus_update_sensor_data(client, sensor); 946 948 if (sensor->data < 0) 947 - return sensor->data; 948 - 949 - return snprintf(buf, PAGE_SIZE, "%lld\n", pmbus_reg2data(data, sensor)); 949 + ret = sensor->data; 950 + else 951 + ret = snprintf(buf, PAGE_SIZE, "%lld\n", pmbus_reg2data(data, sensor)); 952 + mutex_unlock(&data->update_lock); 953 + return ret; 950 954 } 951 955 952 956 static ssize_t pmbus_set_sensor(struct device *dev, ··· 2016 2012 int val; 2017 2013 struct i2c_client *client = to_i2c_client(dev->parent); 2018 2014 struct pmbus_samples_reg *reg = to_samples_reg(devattr); 2015 + struct pmbus_data *data = i2c_get_clientdata(client); 2019 2016 2017 + mutex_lock(&data->update_lock); 2020 2018 val = _pmbus_read_word_data(client, reg->page, 0xff, reg->attr->reg); 2019 + mutex_unlock(&data->update_lock); 2021 2020 if (val < 0) 2022 2021 return val; 2023 2022

+9 -7

drivers/hwmon/pwm-fan.c

··· 54 54 static void sample_timer(struct timer_list *t) 55 55 { 56 56 struct pwm_fan_ctx *ctx = from_timer(ctx, t, rpm_timer); 57 + unsigned int delta = ktime_ms_delta(ktime_get(), ctx->sample_start); 57 58 int pulses; 58 - u64 tmp; 59 59 60 - pulses = atomic_read(&ctx->pulses); 61 - atomic_sub(pulses, &ctx->pulses); 62 - tmp = (u64)pulses * ktime_ms_delta(ktime_get(), ctx->sample_start) * 60; 63 - do_div(tmp, ctx->pulses_per_revolution * 1000); 64 - ctx->rpm = tmp; 60 + if (delta) { 61 + pulses = atomic_read(&ctx->pulses); 62 + atomic_sub(pulses, &ctx->pulses); 63 + ctx->rpm = (unsigned int)(pulses * 1000 * 60) / 64 + (ctx->pulses_per_revolution * delta); 65 65 66 - ctx->sample_start = ktime_get(); 66 + ctx->sample_start = ktime_get(); 67 + } 68 + 67 69 mod_timer(&ctx->rpm_timer, jiffies + HZ); 68 70 } 69 71

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