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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ASoC: mediatek: mt8189: add platform driver
Add mt8189 platform driver.
Signed-off-by: Cyril Chao <Cyril.Chao@mediatek.com>
Link: https://patch.msgid.link/20251031073216.8662-9-Cyril.Chao@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
authored by
Cyril Chao
and committed by
Mark Brown
7eb15358
22e9bd51
+2643
+10
sound/soc/mediatek/Kconfig
+10
sound/soc/mediatek/Kconfig
···
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Select Y if you have such device.
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If unsure select "N".
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config SND_SOC_MT8189
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tristate "ASoC support for Mediatek MT8189 chip"
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depends on ARCH_MEDIATEK
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select SND_SOC_MEDIATEK
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help
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This adds ASoC driver for Mediatek MT8189 boards
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that can be used with other codecs.
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Select Y if you have such device.
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If unsure select "N".
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+
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config SND_SOC_MT8192
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tristate "ASoC support for Mediatek MT8192 chip"
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depends on ARCH_MEDIATEK
+1
sound/soc/mediatek/Makefile
+1
sound/soc/mediatek/Makefile
+15
sound/soc/mediatek/mt8189/Makefile
+15
sound/soc/mediatek/mt8189/Makefile
···
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# SPDX-License-Identifier: GPL-2.0
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# common include path
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subdir-ccflags-y += -I$(srctree)/sound/soc/mediatek/common
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# platform driver
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snd-soc-mt8189-afe-objs += \
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mt8189-afe-pcm.o \
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mt8189-afe-clk.o \
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mt8189-dai-adda.o \
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mt8189-dai-i2s.o \
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mt8189-dai-pcm.o \
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mt8189-dai-tdm.o
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+
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obj-$(CONFIG_SND_SOC_MT8189) += snd-soc-mt8189-afe.o
+2617
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
+2617
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
···
1
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Mediatek ALSA SoC AFE platform driver for 8189
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*
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* Copyright (c) 2025 MediaTek Inc.
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* Author: Darren Ye <darren.ye@mediatek.com>
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*/
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+
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_reserved_mem.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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+
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#include <sound/pcm.h>
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#include <sound/soc.h>
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+
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#include "mt8189-afe-clk.h"
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#include "mt8189-afe-common.h"
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#include "mt8189-interconnection.h"
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+
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#include "../common/mtk-afe-fe-dai.h"
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#include "../common/mtk-afe-platform-driver.h"
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+
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static const struct snd_pcm_hardware mt8189_afe_hardware = {
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.info = (SNDRV_PCM_INFO_MMAP |
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SNDRV_PCM_INFO_NO_PERIOD_WAKEUP |
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SNDRV_PCM_INFO_INTERLEAVED |
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SNDRV_PCM_INFO_MMAP_VALID),
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.formats = (SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S24_LE |
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SNDRV_PCM_FMTBIT_S32_LE),
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.period_bytes_min = 96,
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.period_bytes_max = 4 * 48 * 1024,
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.periods_min = 2,
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.periods_max = 256,
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.buffer_bytes_max = 256 * 1024,
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.fifo_size = 0,
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};
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+
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static unsigned int mt8189_rate_transform(struct device *dev, unsigned int rate)
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{
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switch (rate) {
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case 8000:
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return MTK_AFE_IPM2P0_RATE_8K;
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+
case 11025:
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return MTK_AFE_IPM2P0_RATE_11K;
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case 12000:
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return MTK_AFE_IPM2P0_RATE_12K;
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+
case 16000:
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return MTK_AFE_IPM2P0_RATE_16K;
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case 22050:
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return MTK_AFE_IPM2P0_RATE_22K;
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case 24000:
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return MTK_AFE_IPM2P0_RATE_24K;
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+
case 32000:
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return MTK_AFE_IPM2P0_RATE_32K;
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+
case 44100:
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return MTK_AFE_IPM2P0_RATE_44K;
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case 48000:
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return MTK_AFE_IPM2P0_RATE_48K;
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case 88200:
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return MTK_AFE_IPM2P0_RATE_88K;
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case 96000:
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return MTK_AFE_IPM2P0_RATE_96K;
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case 176400:
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return MTK_AFE_IPM2P0_RATE_176K;
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case 192000:
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return MTK_AFE_IPM2P0_RATE_192K;
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/* not support 260K */
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case 352800:
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return MTK_AFE_IPM2P0_RATE_352K;
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case 384000:
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return MTK_AFE_IPM2P0_RATE_384K;
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default:
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dev_warn(dev, "rate %u invalid, use %d!!!\n",
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rate, MTK_AFE_IPM2P0_RATE_48K);
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return MTK_AFE_IPM2P0_RATE_48K;
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}
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}
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+
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static inline unsigned int calculate_cm_update(unsigned int rate,
87
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unsigned int ch)
88
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{
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return (((26000000 / rate) - 10) / (ch / 2)) - 1;
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}
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+
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static int mt8189_set_cm(struct mtk_base_afe *afe, int id,
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bool update, bool swap, unsigned int ch)
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{
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struct mt8189_afe_private *afe_priv = afe->platform_priv;
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unsigned int rate = afe_priv->cm_rate[id];
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unsigned int rate_val = mt8189_rate_transform(afe->dev, rate);
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unsigned int update_val = update ? calculate_cm_update(rate, ch) : 0x64;
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int reg = AFE_CM0_CON0 + 0x10 * id;
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+
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dev_dbg(afe->dev, "%s()-0, CM%d, rate %d, update %d, swap %d, ch %d\n",
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__func__, id, rate, update, swap, ch);
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/* update cnt */
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regmap_update_bits(afe->regmap, reg,
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AFE_CM_UPDATE_CNT_MASK << AFE_CM_UPDATE_CNT_SFT,
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update_val << AFE_CM_UPDATE_CNT_SFT);
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/* rate */
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regmap_update_bits(afe->regmap, reg,
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AFE_CM_1X_EN_SEL_FS_MASK << AFE_CM_1X_EN_SEL_FS_SFT,
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rate_val << AFE_CM_1X_EN_SEL_FS_SFT);
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+
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/* ch num */
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regmap_update_bits(afe->regmap, reg,
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AFE_CM_CH_NUM_MASK << AFE_CM_CH_NUM_SFT,
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(ch - 1) << AFE_CM_CH_NUM_SFT);
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/* swap */
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regmap_update_bits(afe->regmap, reg,
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AFE_CM_BYTE_SWAP_MASK << AFE_CM_BYTE_SWAP_SFT,
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swap << AFE_CM_BYTE_SWAP_SFT);
123
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return 0;
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}
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+
127
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static int mt8189_enable_cm_bypass(struct mtk_base_afe *afe, int id, bool en)
128
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{
129
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return regmap_update_bits(afe->regmap, AFE_CM0_CON0 + 0x10 * id,
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AFE_CM_BYPASS_MODE_MASK <<
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AFE_CM_BYPASS_MODE_SFT,
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en << AFE_CM_BYPASS_MODE_SFT);
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}
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+
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static int mt8189_fe_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
137
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{
138
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struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
139
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struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
140
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struct snd_pcm_runtime *runtime = substream->runtime;
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struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
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int memif_num = cpu_dai->id;
143
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struct mtk_base_afe_memif *memif = &afe->memif[memif_num];
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const struct snd_pcm_hardware *mtk_afe_hardware = afe->mtk_afe_hardware;
145
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int ret;
146
+
147
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dev_dbg(afe->dev, "%s(), memif_num: %d.\n", __func__, memif_num);
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memif->substream = substream;
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+
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snd_pcm_hw_constraint_step(substream->runtime, 0,
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SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 16);
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snd_soc_set_runtime_hwparams(substream, mtk_afe_hardware);
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ret = snd_pcm_hw_constraint_integer(runtime,
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SNDRV_PCM_HW_PARAM_PERIODS);
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if (ret < 0)
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dev_warn(afe->dev, "snd_pcm_hw_constraint_integer failed\n");
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+
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/* dynamic allocate irq to memif */
162
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if (memif->irq_usage < 0) {
163
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int irq_id = mtk_dynamic_irq_acquire(afe);
164
+
165
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if (irq_id != afe->irqs_size) {
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/* link */
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memif->irq_usage = irq_id;
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} else {
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dev_err(afe->dev, "%s() error: no more asys irq\n",
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__func__);
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ret = -EBUSY;
172
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}
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}
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+
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return ret;
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}
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+
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static void mt8189_fe_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
180
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{
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struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
182
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struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
183
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struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
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int memif_num = cpu_dai->id;
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struct mtk_base_afe_memif *memif = &afe->memif[memif_num];
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int irq_id = memif->irq_usage;
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+
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dev_dbg(afe->dev, "%s(), memif_num: %d.\n", __func__, memif_num);
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+
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memif->substream = NULL;
191
+
192
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if (!memif->const_irq) {
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mtk_dynamic_irq_release(afe, irq_id);
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memif->irq_usage = -1;
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memif->substream = NULL;
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}
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}
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+
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static int mt8189_fe_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
202
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{
203
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struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
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struct mt8189_afe_private *afe_priv = afe->platform_priv;
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int id = dai->id;
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int cm;
207
+
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switch (id) {
209
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case MT8189_MEMIF_VUL8:
210
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case MT8189_MEMIF_VUL_CM0:
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cm = CM0;
212
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break;
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case MT8189_MEMIF_VUL9:
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case MT8189_MEMIF_VUL_CM1:
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cm = CM1;
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break;
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default:
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cm = CM0;
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break;
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}
221
+
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afe_priv->cm_rate[cm] = params_rate(params);
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afe_priv->cm_channels = params_channels(params);
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+
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return mtk_afe_fe_hw_params(substream, params, dai);
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}
227
+
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static int mt8189_fe_trigger(struct snd_pcm_substream *substream, int cmd,
229
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struct snd_soc_dai *dai)
230
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{
231
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struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
232
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struct snd_pcm_runtime *const runtime = substream->runtime;
233
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struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
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struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
235
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int id = cpu_dai->id;
236
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struct mtk_base_afe_memif *memif = &afe->memif[id];
237
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int irq_id = memif->irq_usage;
238
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struct mtk_base_afe_irq *irqs = &afe->irqs[irq_id];
239
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const struct mtk_base_irq_data *irq_data = irqs->irq_data;
240
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unsigned int counter = runtime->period_size;
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unsigned int rate = runtime->rate;
242
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unsigned int tmp_reg;
243
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int fs;
244
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int ret;
245
+
246
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dev_dbg(afe->dev, "%s(), %s cmd %d, irq_id %d, dai_id %d\n", __func__,
247
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memif->data->name, cmd, irq_id, id);
248
+
249
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switch (cmd) {
250
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case SNDRV_PCM_TRIGGER_START:
251
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case SNDRV_PCM_TRIGGER_RESUME:
252
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ret = mtk_memif_set_enable(afe, id);
253
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if (ret) {
254
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dev_err(afe->dev, "id %d, memif enable fail.\n", id);
255
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return ret;
256
+
}
257
+
258
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/*
259
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* for small latency record
260
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* ul memif need read some data before irq enable
261
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* the context of this triger ops is atmoic, so it cannot sleep
262
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*/
263
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
264
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if ((runtime->period_size * 1000) / rate <= 10)
265
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udelay(300);
266
+
267
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regmap_update_bits(afe->regmap,
268
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irq_data->irq_cnt_reg,
269
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irq_data->irq_cnt_maskbit <<
270
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irq_data->irq_cnt_shift,
271
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counter << irq_data->irq_cnt_shift);
272
+
273
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/* set irq fs */
274
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fs = afe->irq_fs(substream, rate);
275
+
if (fs < 0)
276
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return -EINVAL;
277
+
278
+
if (irq_data->irq_fs_reg >= 0)
279
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regmap_update_bits(afe->regmap,
280
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irq_data->irq_fs_reg,
281
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irq_data->irq_fs_maskbit <<
282
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irq_data->irq_fs_shift,
283
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fs << irq_data->irq_fs_shift);
284
+
285
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/* enable interrupt */
286
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regmap_update_bits(afe->regmap,
287
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irq_data->irq_en_reg,
288
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1 << irq_data->irq_en_shift,
289
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1 << irq_data->irq_en_shift);
290
+
291
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return 0;
292
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case SNDRV_PCM_TRIGGER_STOP:
293
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case SNDRV_PCM_TRIGGER_SUSPEND:
294
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ret = mtk_memif_set_disable(afe, id);
295
+
if (ret)
296
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dev_warn(afe->dev, "id %d, memif disable fail\n", id);
297
+
298
+
/* disable interrupt */
299
+
regmap_update_bits(afe->regmap,
300
+
irq_data->irq_en_reg,
301
+
1 << irq_data->irq_en_shift,
302
+
0 << irq_data->irq_en_shift);
303
+
304
+
/*
305
+
* clear pending IRQ, if the register read as one, there is no
306
+
* need to write one to clear operation.
307
+
*/
308
+
regmap_read(afe->regmap, irq_data->irq_clr_reg, &tmp_reg);
309
+
regmap_update_bits(afe->regmap, irq_data->irq_clr_reg,
310
+
AFE_IRQ_CLR_CFG_MASK_SFT |
311
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AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT,
312
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tmp_reg ^ (AFE_IRQ_CLR_CFG_MASK_SFT |
313
+
AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT));
314
+
315
+
return ret;
316
+
default:
317
+
return -EINVAL;
318
+
}
319
+
}
320
+
321
+
static int mt8189_memif_fs(struct snd_pcm_substream *substream,
322
+
unsigned int rate)
323
+
{
324
+
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
325
+
struct snd_soc_component *component =
326
+
snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
327
+
struct mtk_base_afe *afe = NULL;
328
+
329
+
if (!component)
330
+
return -EINVAL;
331
+
332
+
afe = snd_soc_component_get_drvdata(component);
333
+
if (!afe)
334
+
return -EINVAL;
335
+
336
+
return mt8189_rate_transform(afe->dev, rate);
337
+
}
338
+
339
+
static int mt8189_get_dai_fs(struct mtk_base_afe *afe,
340
+
int dai_id, unsigned int rate)
341
+
{
342
+
return mt8189_rate_transform(afe->dev, rate);
343
+
}
344
+
345
+
static int mt8189_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
346
+
{
347
+
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
348
+
struct snd_soc_component *component =
349
+
snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
350
+
struct mtk_base_afe *afe = NULL;
351
+
352
+
if (!component)
353
+
return -EINVAL;
354
+
afe = snd_soc_component_get_drvdata(component);
355
+
356
+
return mt8189_rate_transform(afe->dev, rate);
357
+
}
358
+
359
+
static int mt8189_get_memif_pbuf_size(struct snd_pcm_substream *substream)
360
+
{
361
+
struct snd_pcm_runtime *runtime = substream->runtime;
362
+
363
+
if ((runtime->period_size * 1000) / runtime->rate > 10)
364
+
return MT8189_MEMIF_PBUF_SIZE_256_BYTES;
365
+
366
+
return MT8189_MEMIF_PBUF_SIZE_32_BYTES;
367
+
}
368
+
369
+
/* FE DAIs */
370
+
static const struct snd_soc_dai_ops mt8189_memif_dai_ops = {
371
+
.startup = mt8189_fe_startup,
372
+
.shutdown = mt8189_fe_shutdown,
373
+
.hw_params = mt8189_fe_hw_params,
374
+
.hw_free = mtk_afe_fe_hw_free,
375
+
.prepare = mtk_afe_fe_prepare,
376
+
.trigger = mt8189_fe_trigger,
377
+
};
378
+
379
+
#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 | \
380
+
SNDRV_PCM_RATE_88200 | \
381
+
SNDRV_PCM_RATE_96000 | \
382
+
SNDRV_PCM_RATE_176400 | \
383
+
SNDRV_PCM_RATE_192000)
384
+
385
+
#define MTK_PCM_DAI_RATES (SNDRV_PCM_RATE_8000 | \
386
+
SNDRV_PCM_RATE_16000 | \
387
+
SNDRV_PCM_RATE_32000 | \
388
+
SNDRV_PCM_RATE_48000)
389
+
390
+
#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
391
+
SNDRV_PCM_FMTBIT_S24_LE | \
392
+
SNDRV_PCM_FMTBIT_S32_LE)
393
+
394
+
#define MT8189_FE_DAI_PLAYBACK(_name, _id, max_ch) \
395
+
{ \
396
+
.name = #_name, \
397
+
.id = _id, \
398
+
.playback = { \
399
+
.stream_name = #_name, \
400
+
.channels_min = 1, \
401
+
.channels_max = max_ch, \
402
+
.rates = MTK_PCM_RATES, \
403
+
.formats = MTK_PCM_FORMATS, \
404
+
}, \
405
+
.ops = &mt8189_memif_dai_ops, \
406
+
}
407
+
408
+
#define MT8189_FE_DAI_CAPTURE(_name, _id, max_ch) \
409
+
{ \
410
+
.name = #_name, \
411
+
.id = _id, \
412
+
.capture = { \
413
+
.stream_name = #_name, \
414
+
.channels_min = 1, \
415
+
.channels_max = max_ch, \
416
+
.rates = MTK_PCM_RATES, \
417
+
.formats = MTK_PCM_FORMATS, \
418
+
}, \
419
+
.ops = &mt8189_memif_dai_ops, \
420
+
}
421
+
422
+
static struct snd_soc_dai_driver mt8189_memif_dai_driver[] = {
423
+
/* FE DAIs: memory interfaces to CPU */
424
+
/* Playback */
425
+
MT8189_FE_DAI_PLAYBACK(DL0, MT8189_MEMIF_DL0, 2),
426
+
MT8189_FE_DAI_PLAYBACK(DL1, MT8189_MEMIF_DL1, 2),
427
+
MT8189_FE_DAI_PLAYBACK(DL2, MT8189_MEMIF_DL2, 2),
428
+
MT8189_FE_DAI_PLAYBACK(DL3, MT8189_MEMIF_DL3, 2),
429
+
MT8189_FE_DAI_PLAYBACK(DL4, MT8189_MEMIF_DL4, 2),
430
+
MT8189_FE_DAI_PLAYBACK(DL5, MT8189_MEMIF_DL5, 2),
431
+
MT8189_FE_DAI_PLAYBACK(DL6, MT8189_MEMIF_DL6, 2),
432
+
MT8189_FE_DAI_PLAYBACK(DL7, MT8189_MEMIF_DL7, 2),
433
+
MT8189_FE_DAI_PLAYBACK(DL8, MT8189_MEMIF_DL8, 2),
434
+
MT8189_FE_DAI_PLAYBACK(DL23, MT8189_MEMIF_DL23, 2),
435
+
MT8189_FE_DAI_PLAYBACK(DL24, MT8189_MEMIF_DL24, 2),
436
+
MT8189_FE_DAI_PLAYBACK(DL25, MT8189_MEMIF_DL25, 2),
437
+
MT8189_FE_DAI_PLAYBACK(DL_24CH, MT8189_MEMIF_DL_24CH, 8),
438
+
MT8189_FE_DAI_PLAYBACK(HDMI, MT8189_MEMIF_HDMI, 8),
439
+
/* Capture */
440
+
MT8189_FE_DAI_CAPTURE(UL0, MT8189_MEMIF_VUL0, 2),
441
+
MT8189_FE_DAI_CAPTURE(UL1, MT8189_MEMIF_VUL1, 2),
442
+
MT8189_FE_DAI_CAPTURE(UL2, MT8189_MEMIF_VUL2, 2),
443
+
MT8189_FE_DAI_CAPTURE(UL3, MT8189_MEMIF_VUL3, 2),
444
+
MT8189_FE_DAI_CAPTURE(UL4, MT8189_MEMIF_VUL4, 2),
445
+
MT8189_FE_DAI_CAPTURE(UL5, MT8189_MEMIF_VUL5, 2),
446
+
MT8189_FE_DAI_CAPTURE(UL6, MT8189_MEMIF_VUL6, 2),
447
+
MT8189_FE_DAI_CAPTURE(UL7, MT8189_MEMIF_VUL7, 2),
448
+
MT8189_FE_DAI_CAPTURE(UL8, MT8189_MEMIF_VUL8, 2),
449
+
MT8189_FE_DAI_CAPTURE(UL9, MT8189_MEMIF_VUL9, 16),
450
+
MT8189_FE_DAI_CAPTURE(UL10, MT8189_MEMIF_VUL10, 2),
451
+
MT8189_FE_DAI_CAPTURE(UL24, MT8189_MEMIF_VUL24, 2),
452
+
MT8189_FE_DAI_CAPTURE(UL25, MT8189_MEMIF_VUL25, 2),
453
+
MT8189_FE_DAI_CAPTURE(UL_CM0, MT8189_MEMIF_VUL_CM0, 8),
454
+
MT8189_FE_DAI_CAPTURE(UL_CM1, MT8189_MEMIF_VUL_CM1, 16),
455
+
MT8189_FE_DAI_CAPTURE(UL_ETDM_IN0, MT8189_MEMIF_ETDM_IN0, 2),
456
+
MT8189_FE_DAI_CAPTURE(UL_ETDM_IN1, MT8189_MEMIF_ETDM_IN1, 2),
457
+
};
458
+
459
+
static int ul_cm0_event(struct snd_soc_dapm_widget *w,
460
+
struct snd_kcontrol *kcontrol,
461
+
int event)
462
+
{
463
+
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
464
+
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
465
+
struct mt8189_afe_private *afe_priv = afe->platform_priv;
466
+
unsigned int channels = afe_priv->cm_channels;
467
+
468
+
dev_dbg(afe->dev, "%s(), event 0x%x, name %s, channels %d\n",
469
+
__func__, event, w->name, channels);
470
+
471
+
switch (event) {
472
+
case SND_SOC_DAPM_PRE_PMU:
473
+
mt8189_enable_cm_bypass(afe, CM0, false);
474
+
mt8189_set_cm(afe, CM0, true, false, channels);
475
+
regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
476
+
PDN_CM0_MASK_SFT, 0 << PDN_CM0_SFT);
477
+
478
+
break;
479
+
case SND_SOC_DAPM_PRE_PMD:
480
+
mt8189_enable_cm_bypass(afe, CM0, true);
481
+
regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
482
+
PDN_CM0_MASK_SFT, 1 << PDN_CM0_SFT);
483
+
break;
484
+
default:
485
+
break;
486
+
}
487
+
488
+
return 0;
489
+
}
490
+
491
+
static int ul_cm1_event(struct snd_soc_dapm_widget *w,
492
+
struct snd_kcontrol *kcontrol,
493
+
int event)
494
+
{
495
+
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
496
+
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
497
+
struct mt8189_afe_private *afe_priv = afe->platform_priv;
498
+
unsigned int channels = afe_priv->cm_channels;
499
+
500
+
dev_dbg(afe->dev, "%s(), event 0x%x, name %s, channels %d\n",
501
+
__func__, event, w->name, channels);
502
+
503
+
switch (event) {
504
+
case SND_SOC_DAPM_PRE_PMU:
505
+
mt8189_enable_cm_bypass(afe, CM1, false);
506
+
mt8189_set_cm(afe, CM1, true, false, channels);
507
+
regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
508
+
PDN_CM1_MASK_SFT, 0 << PDN_CM1_SFT);
509
+
break;
510
+
case SND_SOC_DAPM_POST_PMD:
511
+
mt8189_enable_cm_bypass(afe, CM1, true);
512
+
regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
513
+
PDN_CM1_MASK_SFT, 1 << PDN_CM1_SFT);
514
+
break;
515
+
default:
516
+
break;
517
+
}
518
+
519
+
return 0;
520
+
}
521
+
522
+
/*
523
+
* dma widget & routes
524
+
* The mixer controls and routes are by no means fully implemented,
525
+
* only the ones that are intended to be used are, as other wise a fully
526
+
* interconnected switch bar mixer would introduce way too many unused
527
+
* controls.
528
+
*/
529
+
static const struct snd_kcontrol_new memif_ul0_ch1_mix[] = {
530
+
/* Normal record */
531
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN018_0,
532
+
I_ADDA_UL_CH1, 1, 0),
533
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN018_0,
534
+
I_ADDA_UL_CH2, 1, 0),
535
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN018_0,
536
+
I_ADDA_UL_CH3, 1, 0),
537
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN018_0,
538
+
I_ADDA_UL_CH4, 1, 0),
539
+
/* AP DMIC */
540
+
SOC_DAPM_SINGLE_AUTODISABLE("AP_DMIC_UL_CH1", AFE_CONN018_0,
541
+
I_DMIC0_CH1, 1, 0),
542
+
SOC_DAPM_SINGLE_AUTODISABLE("AP_DMIC_UL_CH2", AFE_CONN018_0,
543
+
I_DMIC0_CH2, 1, 0),
544
+
SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN018_1,
545
+
I_DL0_CH1, 1, 0),
546
+
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN018_1,
547
+
I_DL1_CH1, 1, 0),
548
+
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN018_1,
549
+
I_DL2_CH1, 1, 0),
550
+
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN018_1,
551
+
I_DL3_CH1, 1, 0),
552
+
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN018_1,
553
+
I_DL4_CH1, 1, 0),
554
+
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN018_1,
555
+
I_DL6_CH1, 1, 0),
556
+
SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN018_1,
557
+
I_DL7_CH1, 1, 0),
558
+
SOC_DAPM_SINGLE_AUTODISABLE("DL23_CH1", AFE_CONN018_2,
559
+
I_DL23_CH1, 1, 0),
560
+
SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN018_1,
561
+
I_DL_24CH_CH1, 1, 0),
562
+
SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN018_4,
563
+
I_PCM_0_CAP_CH1, 1, 0),
564
+
SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH1", AFE_CONN018_4,
565
+
I_I2SIN0_CH1, 1, 0),
566
+
SOC_DAPM_SINGLE_AUTODISABLE("I2SIN1_CH1", AFE_CONN018_4,
567
+
I_I2SIN1_CH1, 1, 0),
568
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_0_OUT_CH1", AFE_CONN018_6,
569
+
I_SRC_0_OUT_CH1, 1, 0),
570
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH1", AFE_CONN018_6,
571
+
I_SRC_2_OUT_CH1, 1, 0),
572
+
};
573
+
574
+
static const struct snd_kcontrol_new memif_ul0_ch2_mix[] = {
575
+
/* Normal record */
576
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN019_0,
577
+
I_ADDA_UL_CH1, 1, 0),
578
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN019_0,
579
+
I_ADDA_UL_CH2, 1, 0),
580
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN019_0,
581
+
I_ADDA_UL_CH3, 1, 0),
582
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN019_0,
583
+
I_ADDA_UL_CH4, 1, 0),
584
+
/* AP DMIC */
585
+
SOC_DAPM_SINGLE_AUTODISABLE("AP_DMIC_UL_CH2", AFE_CONN019_0,
586
+
I_DMIC0_CH2, 1, 0),
587
+
SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN019_1,
588
+
I_DL0_CH2, 1, 0),
589
+
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN019_1,
590
+
I_DL1_CH2, 1, 0),
591
+
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN019_1,
592
+
I_DL2_CH2, 1, 0),
593
+
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN019_1,
594
+
I_DL3_CH2, 1, 0),
595
+
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN019_1,
596
+
I_DL4_CH2, 1, 0),
597
+
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN019_1,
598
+
I_DL6_CH2, 1, 0),
599
+
SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN019_1,
600
+
I_DL7_CH2, 1, 0),
601
+
SOC_DAPM_SINGLE_AUTODISABLE("DL23_CH2", AFE_CONN018_2,
602
+
I_DL23_CH2, 1, 0),
603
+
SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN019_1,
604
+
I_DL_24CH_CH2, 1, 0),
605
+
SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN019_4,
606
+
I_PCM_0_CAP_CH1, 1, 0),
607
+
SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN019_4,
608
+
I_PCM_0_CAP_CH2, 1, 0),
609
+
SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH2", AFE_CONN019_4,
610
+
I_I2SIN0_CH2, 1, 0),
611
+
SOC_DAPM_SINGLE_AUTODISABLE("I2SIN1_CH2", AFE_CONN019_4,
612
+
I_I2SIN1_CH2, 1, 0),
613
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_0_OUT_CH2", AFE_CONN019_6,
614
+
I_SRC_0_OUT_CH2, 1, 0),
615
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH2", AFE_CONN019_6,
616
+
I_SRC_2_OUT_CH2, 1, 0),
617
+
};
618
+
619
+
static const struct snd_kcontrol_new memif_ul1_ch1_mix[] = {
620
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN020_0,
621
+
I_ADDA_UL_CH1, 1, 0),
622
+
SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN020_1,
623
+
I_DL0_CH1, 1, 0),
624
+
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN020_1,
625
+
I_DL1_CH1, 1, 0),
626
+
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN020_1,
627
+
I_DL2_CH1, 1, 0),
628
+
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN020_1,
629
+
I_DL3_CH1, 1, 0),
630
+
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN020_1,
631
+
I_DL4_CH1, 1, 0),
632
+
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN020_1,
633
+
I_DL6_CH1, 1, 0),
634
+
SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH1", AFE_CONN020_1,
635
+
I_DL7_CH1, 1, 0),
636
+
SOC_DAPM_SINGLE_AUTODISABLE("DL23_CH1", AFE_CONN020_2,
637
+
I_DL23_CH1, 1, 0),
638
+
SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN020_1,
639
+
I_DL_24CH_CH1, 1, 0),
640
+
SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN020_4,
641
+
I_PCM_0_CAP_CH1, 1, 0),
642
+
SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH1", AFE_CONN020_4,
643
+
I_I2SIN0_CH1, 1, 0),
644
+
SOC_DAPM_SINGLE_AUTODISABLE("I2SIN1_CH1", AFE_CONN020_4,
645
+
I_I2SIN1_CH1, 1, 0),
646
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_0_OUT_CH1", AFE_CONN020_6,
647
+
I_SRC_0_OUT_CH1, 1, 0),
648
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH1", AFE_CONN020_6,
649
+
I_SRC_2_OUT_CH1, 1, 0),
650
+
};
651
+
652
+
static const struct snd_kcontrol_new memif_ul1_ch2_mix[] = {
653
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN021_0,
654
+
I_ADDA_UL_CH2, 1, 0),
655
+
SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN021_1,
656
+
I_DL0_CH2, 1, 0),
657
+
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN021_1,
658
+
I_DL1_CH2, 1, 0),
659
+
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN021_1,
660
+
I_DL2_CH2, 1, 0),
661
+
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN021_1,
662
+
I_DL3_CH2, 1, 0),
663
+
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN021_1,
664
+
I_DL4_CH2, 1, 0),
665
+
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN021_1,
666
+
I_DL6_CH2, 1, 0),
667
+
SOC_DAPM_SINGLE_AUTODISABLE("DL7_CH2", AFE_CONN021_1,
668
+
I_DL7_CH2, 1, 0),
669
+
SOC_DAPM_SINGLE_AUTODISABLE("DL23_CH2", AFE_CONN021_2,
670
+
I_DL23_CH2, 1, 0),
671
+
SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN021_1,
672
+
I_DL_24CH_CH2, 1, 0),
673
+
SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN021_4,
674
+
I_PCM_0_CAP_CH1, 1, 0),
675
+
SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN021_4,
676
+
I_PCM_0_CAP_CH2, 1, 0),
677
+
SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH2", AFE_CONN021_4,
678
+
I_I2SIN0_CH2, 1, 0),
679
+
SOC_DAPM_SINGLE_AUTODISABLE("I2SIN1_CH2", AFE_CONN021_4,
680
+
I_I2SIN1_CH2, 1, 0),
681
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_0_OUT_CH2", AFE_CONN021_6,
682
+
I_SRC_0_OUT_CH2, 1, 0),
683
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH2", AFE_CONN021_6,
684
+
I_SRC_2_OUT_CH2, 1, 0),
685
+
};
686
+
687
+
static const struct snd_kcontrol_new memif_ul2_ch1_mix[] = {
688
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN022_0,
689
+
I_ADDA_UL_CH1, 1, 0),
690
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN022_0,
691
+
I_ADDA_UL_CH2, 1, 0),
692
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN022_0,
693
+
I_ADDA_UL_CH3, 1, 0),
694
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN022_0,
695
+
I_ADDA_UL_CH4, 1, 0),
696
+
/* AP DMIC */
697
+
SOC_DAPM_SINGLE_AUTODISABLE("AP_DMIC_UL_CH3", AFE_CONN022_0,
698
+
I_DMIC1_CH1, 1, 0),
699
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN1_OUT_CH1", AFE_CONN022_0,
700
+
I_GAIN1_OUT_CH1, 1, 0),
701
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_1_OUT_CH1", AFE_CONN022_6,
702
+
I_SRC_1_OUT_CH1, 1, 0),
703
+
};
704
+
705
+
static const struct snd_kcontrol_new memif_ul2_ch2_mix[] = {
706
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN023_0,
707
+
I_ADDA_UL_CH1, 1, 0),
708
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN023_0,
709
+
I_ADDA_UL_CH2, 1, 0),
710
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN023_0,
711
+
I_ADDA_UL_CH3, 1, 0),
712
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN023_0,
713
+
I_ADDA_UL_CH4, 1, 0),
714
+
/* AP DMIC */
715
+
SOC_DAPM_SINGLE_AUTODISABLE("AP_DMIC_UL_CH4", AFE_CONN023_0,
716
+
I_DMIC1_CH2, 1, 0),
717
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN1_OUT_CH2", AFE_CONN023_0,
718
+
I_GAIN1_OUT_CH2, 1, 0),
719
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_1_OUT_CH2", AFE_CONN023_6,
720
+
I_SRC_1_OUT_CH2, 1, 0),
721
+
};
722
+
723
+
static const struct snd_kcontrol_new memif_ul3_ch1_mix[] = {
724
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN024_0,
725
+
I_ADDA_UL_CH1, 1, 0),
726
+
SOC_DAPM_SINGLE_AUTODISABLE("I2SIN1_CH1", AFE_CONN024_4,
727
+
I_I2SIN1_CH1, 1, 0),
728
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_3_OUT_CH1", AFE_CONN024_6,
729
+
I_SRC_3_OUT_CH1, 1, 0),
730
+
};
731
+
732
+
static const struct snd_kcontrol_new memif_ul3_ch2_mix[] = {
733
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN025_0,
734
+
I_ADDA_UL_CH2, 1, 0),
735
+
SOC_DAPM_SINGLE_AUTODISABLE("I2SIN1_CH2", AFE_CONN025_4,
736
+
I_I2SIN1_CH2, 1, 0),
737
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_3_OUT_CH2", AFE_CONN025_6,
738
+
I_SRC_3_OUT_CH2, 1, 0),
739
+
};
740
+
741
+
static const struct snd_kcontrol_new memif_ul4_ch1_mix[] = {
742
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN026_0,
743
+
I_ADDA_UL_CH1, 1, 0),
744
+
SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN026_1,
745
+
I_DL0_CH1, 1, 0),
746
+
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN026_1,
747
+
I_DL1_CH1, 1, 0),
748
+
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN026_1,
749
+
I_DL6_CH1, 1, 0),
750
+
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN026_1,
751
+
I_DL2_CH1, 1, 0),
752
+
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN026_1,
753
+
I_DL3_CH1, 1, 0),
754
+
SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN026_1,
755
+
I_DL_24CH_CH1, 1, 0),
756
+
SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN026_4,
757
+
I_PCM_0_CAP_CH1, 1, 0),
758
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH1", AFE_CONN026_0,
759
+
I_GAIN0_OUT_CH1, 1, 0),
760
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_3_OUT_CH1", AFE_CONN026_6,
761
+
I_SRC_3_OUT_CH1, 1, 0),
762
+
};
763
+
764
+
static const struct snd_kcontrol_new memif_ul4_ch2_mix[] = {
765
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN027_0,
766
+
I_ADDA_UL_CH2, 1, 0),
767
+
SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN027_1,
768
+
I_DL0_CH2, 1, 0),
769
+
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN027_1,
770
+
I_DL1_CH2, 1, 0),
771
+
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN027_1,
772
+
I_DL6_CH2, 1, 0),
773
+
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN027_1,
774
+
I_DL2_CH2, 1, 0),
775
+
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN027_1,
776
+
I_DL3_CH2, 1, 0),
777
+
SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN027_1,
778
+
I_DL_24CH_CH2, 1, 0),
779
+
SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN027_4,
780
+
I_PCM_0_CAP_CH1, 1, 0),
781
+
SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN027_4,
782
+
I_PCM_0_CAP_CH2, 1, 0),
783
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN0_OUT_CH2", AFE_CONN027_0,
784
+
I_GAIN0_OUT_CH2, 1, 0),
785
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_3_OUT_CH2", AFE_CONN027_6,
786
+
I_SRC_3_OUT_CH2, 1, 0),
787
+
};
788
+
789
+
static const struct snd_kcontrol_new memif_ul5_ch1_mix[] = {
790
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN028_0,
791
+
I_ADDA_UL_CH1, 1, 0),
792
+
SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN028_1,
793
+
I_DL0_CH1, 1, 0),
794
+
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN028_1,
795
+
I_DL1_CH1, 1, 0),
796
+
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN028_1,
797
+
I_DL6_CH1, 1, 0),
798
+
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN028_1,
799
+
I_DL2_CH1, 1, 0),
800
+
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN028_1,
801
+
I_DL3_CH1, 1, 0),
802
+
SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH1", AFE_CONN028_1,
803
+
I_DL_24CH_CH1, 1, 0),
804
+
SOC_DAPM_SINGLE_AUTODISABLE("GAIN0_OUT_CH1", AFE_CONN028_0,
805
+
I_GAIN0_OUT_CH1, 1, 0),
806
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_3_OUT_CH1", AFE_CONN028_6,
807
+
I_SRC_3_OUT_CH1, 1, 0),
808
+
};
809
+
810
+
static const struct snd_kcontrol_new memif_ul5_ch2_mix[] = {
811
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN029_0,
812
+
I_ADDA_UL_CH2, 1, 0),
813
+
SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN029_1,
814
+
I_DL0_CH2, 1, 0),
815
+
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN029_1,
816
+
I_DL1_CH2, 1, 0),
817
+
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN029_1,
818
+
I_DL6_CH2, 1, 0),
819
+
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN029_1,
820
+
I_DL2_CH2, 1, 0),
821
+
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN029_1,
822
+
I_DL3_CH2, 1, 0),
823
+
SOC_DAPM_SINGLE_AUTODISABLE("DL_24CH_CH2", AFE_CONN029_1,
824
+
I_DL_24CH_CH2, 1, 0),
825
+
SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN029_4,
826
+
I_PCM_0_CAP_CH1, 1, 0),
827
+
SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN029_4,
828
+
I_PCM_0_CAP_CH2, 1, 0),
829
+
SOC_DAPM_SINGLE_AUTODISABLE("GAIN0_OUT_CH2", AFE_CONN029_0,
830
+
I_GAIN0_OUT_CH2, 1, 0),
831
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_3_OUT_CH2", AFE_CONN029_6,
832
+
I_SRC_3_OUT_CH2, 1, 0),
833
+
};
834
+
835
+
static const struct snd_kcontrol_new memif_ul6_ch1_mix[] = {
836
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN030_0,
837
+
I_ADDA_UL_CH1, 1, 0),
838
+
SOC_DAPM_SINGLE_AUTODISABLE("AP_DMIC_UL_CH1", AFE_CONN030_0,
839
+
I_DMIC0_CH1, 1, 0),
840
+
SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN030_1,
841
+
I_DL1_CH1, 1, 0),
842
+
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN030_1,
843
+
I_DL2_CH1, 1, 0),
844
+
SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH1", AFE_CONN030_4,
845
+
I_I2SIN0_CH1, 1, 0),
846
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_4_OUT_CH1", AFE_CONN030_6,
847
+
I_SRC_4_OUT_CH1, 1, 0),
848
+
};
849
+
850
+
static const struct snd_kcontrol_new memif_ul6_ch2_mix[] = {
851
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN031_0,
852
+
I_ADDA_UL_CH2, 1, 0),
853
+
SOC_DAPM_SINGLE_AUTODISABLE("AP_DMIC_UL_CH2", AFE_CONN031_0,
854
+
I_DMIC0_CH2, 1, 0),
855
+
SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN031_1,
856
+
I_DL1_CH2, 1, 0),
857
+
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN031_1,
858
+
I_DL2_CH2, 1, 0),
859
+
SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH2", AFE_CONN031_4,
860
+
I_I2SIN0_CH2, 1, 0),
861
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_4_OUT_CH2", AFE_CONN031_6,
862
+
I_SRC_4_OUT_CH2, 1, 0),
863
+
};
864
+
865
+
static const struct snd_kcontrol_new memif_ul7_ch1_mix[] = {
866
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN032_0,
867
+
I_ADDA_UL_CH1, 1, 0),
868
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN032_0,
869
+
I_ADDA_UL_CH2, 1, 0),
870
+
SOC_DAPM_SINGLE_AUTODISABLE("AP_DMIC_UL_CH3", AFE_CONN032_0,
871
+
I_DMIC1_CH1, 1, 0),
872
+
SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH1", AFE_CONN032_1,
873
+
I_DL1_CH1, 1, 0),
874
+
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN032_1,
875
+
I_DL2_CH1, 1, 0),
876
+
SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH1", AFE_CONN032_4,
877
+
I_I2SIN0_CH1, 1, 0),
878
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_4_OUT_CH1", AFE_CONN032_6,
879
+
I_SRC_4_OUT_CH1, 1, 0),
880
+
};
881
+
882
+
static const struct snd_kcontrol_new memif_ul7_ch2_mix[] = {
883
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN033_0,
884
+
I_ADDA_UL_CH1, 1, 0),
885
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN033_0,
886
+
I_ADDA_UL_CH2, 1, 0),
887
+
SOC_DAPM_SINGLE_AUTODISABLE("AP_DMIC_UL_CH4", AFE_CONN033_0,
888
+
I_DMIC1_CH2, 1, 0),
889
+
SOC_DAPM_SINGLE_AUTODISABLE("DL0_CH2", AFE_CONN033_1,
890
+
I_DL1_CH2, 1, 0),
891
+
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN033_1,
892
+
I_DL2_CH2, 1, 0),
893
+
SOC_DAPM_SINGLE_AUTODISABLE("I2SIN0_CH2", AFE_CONN033_4,
894
+
I_I2SIN0_CH2, 1, 0),
895
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_4_OUT_CH2", AFE_CONN033_6,
896
+
I_SRC_4_OUT_CH2, 1, 0),
897
+
};
898
+
899
+
static const struct snd_kcontrol_new memif_ul8_ch1_mix[] = {
900
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN034_0,
901
+
I_ADDA_UL_CH1, 1, 0),
902
+
};
903
+
904
+
static const struct snd_kcontrol_new memif_ul8_ch2_mix[] = {
905
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN035_0,
906
+
I_ADDA_UL_CH1, 1, 0),
907
+
SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH1", AFE_CONN035_4,
908
+
I_PCM_0_CAP_CH1, 1, 0),
909
+
SOC_DAPM_SINGLE_AUTODISABLE("PCM_0_CAP_CH2", AFE_CONN035_4,
910
+
I_PCM_0_CAP_CH2, 1, 0),
911
+
};
912
+
913
+
static const struct snd_kcontrol_new memif_ul9_ch1_mix[] = {
914
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN036_0,
915
+
I_ADDA_UL_CH1, 1, 0),
916
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN036_0,
917
+
I_ADDA_UL_CH2, 1, 0),
918
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN036_0,
919
+
I_ADDA_UL_CH3, 1, 0),
920
+
};
921
+
922
+
static const struct snd_kcontrol_new memif_ul9_ch2_mix[] = {
923
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN037_0,
924
+
I_ADDA_UL_CH1, 1, 0),
925
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN037_0,
926
+
I_ADDA_UL_CH2, 1, 0),
927
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN037_0,
928
+
I_ADDA_UL_CH3, 1, 0),
929
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN037_0,
930
+
I_ADDA_UL_CH4, 1, 0),
931
+
};
932
+
933
+
static const struct snd_kcontrol_new memif_ul24_ch1_mix[] = {
934
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN066_0,
935
+
I_ADDA_UL_CH1, 1, 0),
936
+
};
937
+
938
+
static const struct snd_kcontrol_new memif_ul24_ch2_mix[] = {
939
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN067_0,
940
+
I_ADDA_UL_CH2, 1, 0),
941
+
};
942
+
943
+
static const struct snd_kcontrol_new memif_ul_cm0_ch1_mix[] = {
944
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN040_0,
945
+
I_ADDA_UL_CH1, 1, 0),
946
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN040_0,
947
+
I_ADDA_UL_CH2, 1, 0),
948
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN040_0,
949
+
I_ADDA_UL_CH3, 1, 0),
950
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN040_0,
951
+
I_ADDA_UL_CH4, 1, 0),
952
+
SOC_DAPM_SINGLE_AUTODISABLE("AP_DMIC_UL_CH1", AFE_CONN040_0,
953
+
I_DMIC0_CH1, 1, 0),
954
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN1_OUT_CH1", AFE_CONN040_0,
955
+
I_GAIN1_OUT_CH1, 1, 0),
956
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_0_OUT_CH1", AFE_CONN040_6,
957
+
I_SRC_0_OUT_CH1, 1, 0),
958
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_1_OUT_CH1", AFE_CONN040_6,
959
+
I_SRC_1_OUT_CH1, 1, 0),
960
+
};
961
+
962
+
static const struct snd_kcontrol_new memif_ul_cm0_ch2_mix[] = {
963
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN041_0,
964
+
I_ADDA_UL_CH1, 1, 0),
965
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN041_0,
966
+
I_ADDA_UL_CH2, 1, 0),
967
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN041_0,
968
+
I_ADDA_UL_CH3, 1, 0),
969
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN041_0,
970
+
I_ADDA_UL_CH4, 1, 0),
971
+
SOC_DAPM_SINGLE_AUTODISABLE("AP_DMIC_UL_CH2", AFE_CONN041_0,
972
+
I_DMIC0_CH1, 1, 0),
973
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN1_OUT_CH2", AFE_CONN041_0,
974
+
I_GAIN1_OUT_CH2, 1, 0),
975
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_0_OUT_CH2", AFE_CONN041_6,
976
+
I_SRC_0_OUT_CH2, 1, 0),
977
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_1_OUT_CH2", AFE_CONN041_6,
978
+
I_SRC_1_OUT_CH2, 1, 0),
979
+
};
980
+
981
+
static const struct snd_kcontrol_new memif_ul_cm0_ch3_mix[] = {
982
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN042_0,
983
+
I_ADDA_UL_CH1, 1, 0),
984
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN042_0,
985
+
I_ADDA_UL_CH2, 1, 0),
986
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN042_0,
987
+
I_ADDA_UL_CH3, 1, 0),
988
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN042_0,
989
+
I_ADDA_UL_CH4, 1, 0),
990
+
SOC_DAPM_SINGLE_AUTODISABLE("AP_DMIC_UL_CH3", AFE_CONN042_0,
991
+
I_DMIC1_CH1, 1, 0),
992
+
};
993
+
994
+
static const struct snd_kcontrol_new memif_ul_cm0_ch4_mix[] = {
995
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN043_0,
996
+
I_ADDA_UL_CH1, 1, 0),
997
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN043_0,
998
+
I_ADDA_UL_CH2, 1, 0),
999
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN043_0,
1000
+
I_ADDA_UL_CH3, 1, 0),
1001
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN043_0,
1002
+
I_ADDA_UL_CH4, 1, 0),
1003
+
SOC_DAPM_SINGLE_AUTODISABLE("AP_DMIC_UL_CH4", AFE_CONN043_0,
1004
+
I_DMIC1_CH2, 1, 0),
1005
+
};
1006
+
1007
+
static const struct snd_kcontrol_new memif_ul_cm0_ch5_mix[] = {
1008
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN044_0,
1009
+
I_ADDA_UL_CH1, 1, 0),
1010
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN044_0,
1011
+
I_ADDA_UL_CH2, 1, 0),
1012
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN044_0,
1013
+
I_ADDA_UL_CH3, 1, 0),
1014
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN044_0,
1015
+
I_ADDA_UL_CH4, 1, 0),
1016
+
};
1017
+
1018
+
static const struct snd_kcontrol_new memif_ul_cm0_ch6_mix[] = {
1019
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN045_0,
1020
+
I_ADDA_UL_CH1, 1, 0),
1021
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN045_0,
1022
+
I_ADDA_UL_CH2, 1, 0),
1023
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN045_0,
1024
+
I_ADDA_UL_CH3, 1, 0),
1025
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN045_0,
1026
+
I_ADDA_UL_CH4, 1, 0),
1027
+
};
1028
+
1029
+
static const struct snd_kcontrol_new memif_ul_cm0_ch7_mix[] = {
1030
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN046_0,
1031
+
I_ADDA_UL_CH1, 1, 0),
1032
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN046_0,
1033
+
I_ADDA_UL_CH2, 1, 0),
1034
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN046_0,
1035
+
I_ADDA_UL_CH3, 1, 0),
1036
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN046_0,
1037
+
I_ADDA_UL_CH4, 1, 0),
1038
+
};
1039
+
1040
+
static const struct snd_kcontrol_new memif_ul_cm0_ch8_mix[] = {
1041
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN047_0,
1042
+
I_ADDA_UL_CH1, 1, 0),
1043
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN047_0,
1044
+
I_ADDA_UL_CH2, 1, 0),
1045
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN047_0,
1046
+
I_ADDA_UL_CH3, 1, 0),
1047
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN047_0,
1048
+
I_ADDA_UL_CH4, 1, 0),
1049
+
};
1050
+
1051
+
static const struct snd_kcontrol_new memif_ul_cm1_ch1_mix[] = {
1052
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN048_0,
1053
+
I_ADDA_UL_CH1, 1, 0),
1054
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN048_0,
1055
+
I_ADDA_UL_CH2, 1, 0),
1056
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN048_0,
1057
+
I_ADDA_UL_CH3, 1, 0),
1058
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN048_0,
1059
+
I_ADDA_UL_CH4, 1, 0),
1060
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN048_0,
1061
+
I_ADDA_UL_CH5, 1, 0),
1062
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN048_0,
1063
+
I_ADDA_UL_CH6, 1, 0),
1064
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_0_OUT_CH1", AFE_CONN048_6,
1065
+
I_SRC_0_OUT_CH1, 1, 0),
1066
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_3_OUT_CH1", AFE_CONN048_6,
1067
+
I_SRC_3_OUT_CH1, 1, 0),
1068
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_4_OUT_CH1", AFE_CONN048_6,
1069
+
I_SRC_4_OUT_CH1, 1, 0),
1070
+
};
1071
+
1072
+
static const struct snd_kcontrol_new memif_ul_cm1_ch2_mix[] = {
1073
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN049_0,
1074
+
I_ADDA_UL_CH1, 1, 0),
1075
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN049_0,
1076
+
I_ADDA_UL_CH2, 1, 0),
1077
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN049_0,
1078
+
I_ADDA_UL_CH3, 1, 0),
1079
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN049_0,
1080
+
I_ADDA_UL_CH4, 1, 0),
1081
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN049_0,
1082
+
I_ADDA_UL_CH5, 1, 0),
1083
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN049_0,
1084
+
I_ADDA_UL_CH6, 1, 0),
1085
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_0_OUT_CH2", AFE_CONN049_6,
1086
+
I_SRC_0_OUT_CH2, 1, 0),
1087
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_3_OUT_CH2", AFE_CONN049_6,
1088
+
I_SRC_3_OUT_CH2, 1, 0),
1089
+
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_4_OUT_CH2", AFE_CONN049_6,
1090
+
I_SRC_4_OUT_CH2, 1, 0),
1091
+
};
1092
+
1093
+
static const struct snd_kcontrol_new memif_ul_cm1_ch3_mix[] = {
1094
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN050_0,
1095
+
I_ADDA_UL_CH1, 1, 0),
1096
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN050_0,
1097
+
I_ADDA_UL_CH2, 1, 0),
1098
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN050_0,
1099
+
I_ADDA_UL_CH3, 1, 0),
1100
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN050_0,
1101
+
I_ADDA_UL_CH4, 1, 0),
1102
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN050_0,
1103
+
I_ADDA_UL_CH5, 1, 0),
1104
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN050_0,
1105
+
I_ADDA_UL_CH6, 1, 0),
1106
+
};
1107
+
1108
+
static const struct snd_kcontrol_new memif_ul_cm1_ch4_mix[] = {
1109
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN051_0,
1110
+
I_ADDA_UL_CH1, 1, 0),
1111
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN051_0,
1112
+
I_ADDA_UL_CH2, 1, 0),
1113
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN051_0,
1114
+
I_ADDA_UL_CH3, 1, 0),
1115
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN051_0,
1116
+
I_ADDA_UL_CH4, 1, 0),
1117
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN051_0,
1118
+
I_ADDA_UL_CH5, 1, 0),
1119
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN051_0,
1120
+
I_ADDA_UL_CH6, 1, 0),
1121
+
};
1122
+
1123
+
static const struct snd_kcontrol_new memif_ul_cm1_ch5_mix[] = {
1124
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN052_0,
1125
+
I_ADDA_UL_CH1, 1, 0),
1126
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN052_0,
1127
+
I_ADDA_UL_CH2, 1, 0),
1128
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN052_0,
1129
+
I_ADDA_UL_CH3, 1, 0),
1130
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN052_0,
1131
+
I_ADDA_UL_CH4, 1, 0),
1132
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN052_0,
1133
+
I_ADDA_UL_CH5, 1, 0),
1134
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN052_0,
1135
+
I_ADDA_UL_CH6, 1, 0),
1136
+
};
1137
+
1138
+
static const struct snd_kcontrol_new memif_ul_cm1_ch6_mix[] = {
1139
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN053_0,
1140
+
I_ADDA_UL_CH1, 1, 0),
1141
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN053_0,
1142
+
I_ADDA_UL_CH2, 1, 0),
1143
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN053_0,
1144
+
I_ADDA_UL_CH3, 1, 0),
1145
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN053_0,
1146
+
I_ADDA_UL_CH4, 1, 0),
1147
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH5", AFE_CONN053_0,
1148
+
I_ADDA_UL_CH5, 1, 0),
1149
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH6", AFE_CONN053_0,
1150
+
I_ADDA_UL_CH6, 1, 0),
1151
+
};
1152
+
1153
+
static const struct snd_kcontrol_new memif_ul_cm1_ch7_mix[] = {
1154
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN054_0,
1155
+
I_ADDA_UL_CH1, 1, 0),
1156
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN054_0,
1157
+
I_ADDA_UL_CH2, 1, 0),
1158
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN054_0,
1159
+
I_ADDA_UL_CH3, 1, 0),
1160
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN054_0,
1161
+
I_ADDA_UL_CH4, 1, 0),
1162
+
};
1163
+
1164
+
static const struct snd_kcontrol_new memif_ul_cm1_ch8_mix[] = {
1165
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN055_0,
1166
+
I_ADDA_UL_CH1, 1, 0),
1167
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN055_0,
1168
+
I_ADDA_UL_CH2, 1, 0),
1169
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN055_0,
1170
+
I_ADDA_UL_CH3, 1, 0),
1171
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN055_0,
1172
+
I_ADDA_UL_CH4, 1, 0),
1173
+
};
1174
+
1175
+
static const struct snd_kcontrol_new memif_ul_cm1_ch9_mix[] = {
1176
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN056_0,
1177
+
I_ADDA_UL_CH1, 1, 0),
1178
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN056_0,
1179
+
I_ADDA_UL_CH2, 1, 0),
1180
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN056_0,
1181
+
I_ADDA_UL_CH3, 1, 0),
1182
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN056_0,
1183
+
I_ADDA_UL_CH4, 1, 0),
1184
+
};
1185
+
1186
+
static const struct snd_kcontrol_new memif_ul_cm1_ch10_mix[] = {
1187
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN057_0,
1188
+
I_ADDA_UL_CH1, 1, 0),
1189
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN057_0,
1190
+
I_ADDA_UL_CH2, 1, 0),
1191
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN057_0,
1192
+
I_ADDA_UL_CH3, 1, 0),
1193
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN057_0,
1194
+
I_ADDA_UL_CH4, 1, 0),
1195
+
};
1196
+
1197
+
static const struct snd_kcontrol_new memif_ul_cm1_ch11_mix[] = {
1198
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN058_0,
1199
+
I_ADDA_UL_CH1, 1, 0),
1200
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN058_0,
1201
+
I_ADDA_UL_CH2, 1, 0),
1202
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN058_0,
1203
+
I_ADDA_UL_CH3, 1, 0),
1204
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN058_0,
1205
+
I_ADDA_UL_CH4, 1, 0),
1206
+
};
1207
+
1208
+
static const struct snd_kcontrol_new memif_ul_cm1_ch12_mix[] = {
1209
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN059_0,
1210
+
I_ADDA_UL_CH1, 1, 0),
1211
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN059_0,
1212
+
I_ADDA_UL_CH2, 1, 0),
1213
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN059_0,
1214
+
I_ADDA_UL_CH3, 1, 0),
1215
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN059_0,
1216
+
I_ADDA_UL_CH4, 1, 0),
1217
+
};
1218
+
1219
+
static const struct snd_kcontrol_new memif_ul_cm1_ch13_mix[] = {
1220
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN060_0,
1221
+
I_ADDA_UL_CH1, 1, 0),
1222
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN060_0,
1223
+
I_ADDA_UL_CH2, 1, 0),
1224
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN060_0,
1225
+
I_ADDA_UL_CH3, 1, 0),
1226
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN060_0,
1227
+
I_ADDA_UL_CH4, 1, 0),
1228
+
};
1229
+
1230
+
static const struct snd_kcontrol_new memif_ul_cm1_ch14_mix[] = {
1231
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN061_0,
1232
+
I_ADDA_UL_CH1, 1, 0),
1233
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN061_0,
1234
+
I_ADDA_UL_CH2, 1, 0),
1235
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN061_0,
1236
+
I_ADDA_UL_CH3, 1, 0),
1237
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN061_0,
1238
+
I_ADDA_UL_CH4, 1, 0),
1239
+
};
1240
+
1241
+
static const struct snd_kcontrol_new memif_ul_cm1_ch15_mix[] = {
1242
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN062_0,
1243
+
I_ADDA_UL_CH1, 1, 0),
1244
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN062_0,
1245
+
I_ADDA_UL_CH2, 1, 0),
1246
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN062_0,
1247
+
I_ADDA_UL_CH3, 1, 0),
1248
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN062_0,
1249
+
I_ADDA_UL_CH4, 1, 0),
1250
+
};
1251
+
1252
+
static const struct snd_kcontrol_new memif_ul_cm1_ch16_mix[] = {
1253
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN063_0,
1254
+
I_ADDA_UL_CH1, 1, 0),
1255
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN063_0,
1256
+
I_ADDA_UL_CH2, 1, 0),
1257
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN063_0,
1258
+
I_ADDA_UL_CH3, 1, 0),
1259
+
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN063_0,
1260
+
I_ADDA_UL_CH4, 1, 0),
1261
+
};
1262
+
1263
+
static const char * const cm0_mux_texts[] = {
1264
+
"CM0_2CH_PATH",
1265
+
"CM0_8CH_PATH",
1266
+
};
1267
+
1268
+
static const char * const cm1_mux_map_texts[] = {
1269
+
"CM1_2CH_PATH",
1270
+
"CM1_16CH_PATH",
1271
+
};
1272
+
1273
+
static SOC_ENUM_SINGLE_DECL(ul_cm0_mux_map_enum,
1274
+
AFE_CM0_CON0,
1275
+
AFE_CM0_OUTPUT_MUX_SFT,
1276
+
cm0_mux_texts);
1277
+
static SOC_ENUM_SINGLE_DECL(ul_cm1_mux_map_enum,
1278
+
AFE_CM1_CON0,
1279
+
AFE_CM1_OUTPUT_MUX_SFT,
1280
+
cm1_mux_map_texts);
1281
+
1282
+
static const struct snd_kcontrol_new ul_cm0_mux_control =
1283
+
SOC_DAPM_ENUM("CM0_UL_MUX Route", ul_cm0_mux_map_enum);
1284
+
static const struct snd_kcontrol_new ul_cm1_mux_control =
1285
+
SOC_DAPM_ENUM("CM1_UL_MUX Route", ul_cm1_mux_map_enum);
1286
+
1287
+
static const struct snd_soc_dapm_widget mt8189_memif_widgets[] = {
1288
+
/* inter-connections */
1289
+
SND_SOC_DAPM_MIXER("UL0_CH1", SND_SOC_NOPM, 0, 0,
1290
+
memif_ul0_ch1_mix, ARRAY_SIZE(memif_ul0_ch1_mix)),
1291
+
SND_SOC_DAPM_MIXER("UL0_CH2", SND_SOC_NOPM, 0, 0,
1292
+
memif_ul0_ch2_mix, ARRAY_SIZE(memif_ul0_ch2_mix)),
1293
+
1294
+
SND_SOC_DAPM_MIXER("UL1_CH1", SND_SOC_NOPM, 0, 0,
1295
+
memif_ul1_ch1_mix, ARRAY_SIZE(memif_ul1_ch1_mix)),
1296
+
SND_SOC_DAPM_MIXER("UL1_CH2", SND_SOC_NOPM, 0, 0,
1297
+
memif_ul1_ch2_mix, ARRAY_SIZE(memif_ul1_ch2_mix)),
1298
+
1299
+
SND_SOC_DAPM_MIXER("UL2_CH1", SND_SOC_NOPM, 0, 0,
1300
+
memif_ul2_ch1_mix, ARRAY_SIZE(memif_ul2_ch1_mix)),
1301
+
SND_SOC_DAPM_MIXER("UL2_CH2", SND_SOC_NOPM, 0, 0,
1302
+
memif_ul2_ch2_mix, ARRAY_SIZE(memif_ul2_ch2_mix)),
1303
+
1304
+
SND_SOC_DAPM_MIXER("UL3_CH1", SND_SOC_NOPM, 0, 0,
1305
+
memif_ul3_ch1_mix, ARRAY_SIZE(memif_ul3_ch1_mix)),
1306
+
SND_SOC_DAPM_MIXER("UL3_CH2", SND_SOC_NOPM, 0, 0,
1307
+
memif_ul3_ch2_mix, ARRAY_SIZE(memif_ul3_ch2_mix)),
1308
+
1309
+
SND_SOC_DAPM_MIXER("UL4_CH1", SND_SOC_NOPM, 0, 0,
1310
+
memif_ul4_ch1_mix, ARRAY_SIZE(memif_ul4_ch1_mix)),
1311
+
SND_SOC_DAPM_MIXER("UL4_CH2", SND_SOC_NOPM, 0, 0,
1312
+
memif_ul4_ch2_mix, ARRAY_SIZE(memif_ul4_ch2_mix)),
1313
+
1314
+
SND_SOC_DAPM_MIXER("UL5_CH1", SND_SOC_NOPM, 0, 0,
1315
+
memif_ul5_ch1_mix, ARRAY_SIZE(memif_ul5_ch1_mix)),
1316
+
SND_SOC_DAPM_MIXER("UL5_CH2", SND_SOC_NOPM, 0, 0,
1317
+
memif_ul5_ch2_mix, ARRAY_SIZE(memif_ul5_ch2_mix)),
1318
+
1319
+
SND_SOC_DAPM_MIXER("UL6_CH1", SND_SOC_NOPM, 0, 0,
1320
+
memif_ul6_ch1_mix, ARRAY_SIZE(memif_ul6_ch1_mix)),
1321
+
SND_SOC_DAPM_MIXER("UL6_CH2", SND_SOC_NOPM, 0, 0,
1322
+
memif_ul6_ch2_mix, ARRAY_SIZE(memif_ul6_ch2_mix)),
1323
+
1324
+
SND_SOC_DAPM_MIXER("UL7_CH1", SND_SOC_NOPM, 0, 0,
1325
+
memif_ul7_ch1_mix, ARRAY_SIZE(memif_ul7_ch1_mix)),
1326
+
SND_SOC_DAPM_MIXER("UL7_CH2", SND_SOC_NOPM, 0, 0,
1327
+
memif_ul7_ch2_mix, ARRAY_SIZE(memif_ul7_ch2_mix)),
1328
+
1329
+
SND_SOC_DAPM_MIXER("UL8_CH1", SND_SOC_NOPM, 0, 0,
1330
+
memif_ul8_ch1_mix, ARRAY_SIZE(memif_ul8_ch1_mix)),
1331
+
SND_SOC_DAPM_MIXER("UL8_CH2", SND_SOC_NOPM, 0, 0,
1332
+
memif_ul8_ch2_mix, ARRAY_SIZE(memif_ul8_ch2_mix)),
1333
+
1334
+
SND_SOC_DAPM_MIXER("UL9_CH1", SND_SOC_NOPM, 0, 0,
1335
+
memif_ul9_ch1_mix, ARRAY_SIZE(memif_ul9_ch1_mix)),
1336
+
SND_SOC_DAPM_MIXER("UL9_CH2", SND_SOC_NOPM, 0, 0,
1337
+
memif_ul9_ch2_mix, ARRAY_SIZE(memif_ul9_ch2_mix)),
1338
+
1339
+
SND_SOC_DAPM_MIXER("UL24_CH1", SND_SOC_NOPM, 0, 0,
1340
+
memif_ul24_ch1_mix, ARRAY_SIZE(memif_ul24_ch1_mix)),
1341
+
SND_SOC_DAPM_MIXER("UL24_CH2", SND_SOC_NOPM, 0, 0,
1342
+
memif_ul24_ch2_mix, ARRAY_SIZE(memif_ul24_ch2_mix)),
1343
+
1344
+
SND_SOC_DAPM_MIXER("UL_CM0_CH1", SND_SOC_NOPM, 0, 0,
1345
+
memif_ul_cm0_ch1_mix, ARRAY_SIZE(memif_ul_cm0_ch1_mix)),
1346
+
SND_SOC_DAPM_MIXER("UL_CM0_CH2", SND_SOC_NOPM, 0, 0,
1347
+
memif_ul_cm0_ch2_mix, ARRAY_SIZE(memif_ul_cm0_ch2_mix)),
1348
+
SND_SOC_DAPM_MIXER("UL_CM0_CH3", SND_SOC_NOPM, 0, 0,
1349
+
memif_ul_cm0_ch3_mix, ARRAY_SIZE(memif_ul_cm0_ch3_mix)),
1350
+
SND_SOC_DAPM_MIXER("UL_CM0_CH4", SND_SOC_NOPM, 0, 0,
1351
+
memif_ul_cm0_ch4_mix, ARRAY_SIZE(memif_ul_cm0_ch4_mix)),
1352
+
SND_SOC_DAPM_MIXER("UL_CM0_CH5", SND_SOC_NOPM, 0, 0,
1353
+
memif_ul_cm0_ch5_mix, ARRAY_SIZE(memif_ul_cm0_ch5_mix)),
1354
+
SND_SOC_DAPM_MIXER("UL_CM0_CH6", SND_SOC_NOPM, 0, 0,
1355
+
memif_ul_cm0_ch6_mix, ARRAY_SIZE(memif_ul_cm0_ch6_mix)),
1356
+
SND_SOC_DAPM_MIXER("UL_CM0_CH7", SND_SOC_NOPM, 0, 0,
1357
+
memif_ul_cm0_ch7_mix, ARRAY_SIZE(memif_ul_cm0_ch7_mix)),
1358
+
SND_SOC_DAPM_MIXER("UL_CM0_CH8", SND_SOC_NOPM, 0, 0,
1359
+
memif_ul_cm0_ch8_mix, ARRAY_SIZE(memif_ul_cm0_ch8_mix)),
1360
+
SND_SOC_DAPM_MUX_E("CM0_UL_MUX", SND_SOC_NOPM, 0, 0,
1361
+
&ul_cm0_mux_control,
1362
+
ul_cm0_event,
1363
+
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1364
+
1365
+
SND_SOC_DAPM_MIXER("UL_CM1_CH1", SND_SOC_NOPM, 0, 0,
1366
+
memif_ul_cm1_ch1_mix, ARRAY_SIZE(memif_ul_cm1_ch1_mix)),
1367
+
SND_SOC_DAPM_MIXER("UL_CM1_CH2", SND_SOC_NOPM, 0, 0,
1368
+
memif_ul_cm1_ch2_mix, ARRAY_SIZE(memif_ul_cm1_ch2_mix)),
1369
+
SND_SOC_DAPM_MIXER("UL_CM1_CH3", SND_SOC_NOPM, 0, 0,
1370
+
memif_ul_cm1_ch3_mix, ARRAY_SIZE(memif_ul_cm1_ch3_mix)),
1371
+
SND_SOC_DAPM_MIXER("UL_CM1_CH4", SND_SOC_NOPM, 0, 0,
1372
+
memif_ul_cm1_ch4_mix, ARRAY_SIZE(memif_ul_cm1_ch4_mix)),
1373
+
SND_SOC_DAPM_MIXER("UL_CM1_CH5", SND_SOC_NOPM, 0, 0,
1374
+
memif_ul_cm1_ch5_mix, ARRAY_SIZE(memif_ul_cm1_ch5_mix)),
1375
+
SND_SOC_DAPM_MIXER("UL_CM1_CH6", SND_SOC_NOPM, 0, 0,
1376
+
memif_ul_cm1_ch6_mix, ARRAY_SIZE(memif_ul_cm1_ch6_mix)),
1377
+
SND_SOC_DAPM_MIXER("UL_CM1_CH7", SND_SOC_NOPM, 0, 0,
1378
+
memif_ul_cm1_ch7_mix, ARRAY_SIZE(memif_ul_cm1_ch7_mix)),
1379
+
SND_SOC_DAPM_MIXER("UL_CM1_CH8", SND_SOC_NOPM, 0, 0,
1380
+
memif_ul_cm1_ch8_mix, ARRAY_SIZE(memif_ul_cm1_ch8_mix)),
1381
+
SND_SOC_DAPM_MIXER("UL_CM1_CH9", SND_SOC_NOPM, 0, 0,
1382
+
memif_ul_cm1_ch9_mix, ARRAY_SIZE(memif_ul_cm1_ch9_mix)),
1383
+
SND_SOC_DAPM_MIXER("UL_CM1_CH10", SND_SOC_NOPM, 0, 0,
1384
+
memif_ul_cm1_ch10_mix, ARRAY_SIZE(memif_ul_cm1_ch10_mix)),
1385
+
SND_SOC_DAPM_MIXER("UL_CM1_CH11", SND_SOC_NOPM, 0, 0,
1386
+
memif_ul_cm1_ch11_mix, ARRAY_SIZE(memif_ul_cm1_ch11_mix)),
1387
+
SND_SOC_DAPM_MIXER("UL_CM1_CH12", SND_SOC_NOPM, 0, 0,
1388
+
memif_ul_cm1_ch12_mix, ARRAY_SIZE(memif_ul_cm1_ch12_mix)),
1389
+
SND_SOC_DAPM_MIXER("UL_CM1_CH13", SND_SOC_NOPM, 0, 0,
1390
+
memif_ul_cm1_ch13_mix, ARRAY_SIZE(memif_ul_cm1_ch13_mix)),
1391
+
SND_SOC_DAPM_MIXER("UL_CM1_CH14", SND_SOC_NOPM, 0, 0,
1392
+
memif_ul_cm1_ch14_mix, ARRAY_SIZE(memif_ul_cm1_ch14_mix)),
1393
+
SND_SOC_DAPM_MIXER("UL_CM1_CH15", SND_SOC_NOPM, 0, 0,
1394
+
memif_ul_cm1_ch15_mix, ARRAY_SIZE(memif_ul_cm1_ch15_mix)),
1395
+
SND_SOC_DAPM_MIXER("UL_CM1_CH16", SND_SOC_NOPM, 0, 0,
1396
+
memif_ul_cm1_ch16_mix, ARRAY_SIZE(memif_ul_cm1_ch16_mix)),
1397
+
SND_SOC_DAPM_MUX("CM1_UL_MUX", SND_SOC_NOPM, 0, 0,
1398
+
&ul_cm1_mux_control),
1399
+
SND_SOC_DAPM_SUPPLY("CM0_Enable",
1400
+
AFE_CM0_CON0, AFE_CM0_ON_SFT, 0,
1401
+
ul_cm0_event,
1402
+
SND_SOC_DAPM_PRE_PMU |
1403
+
SND_SOC_DAPM_PRE_PMD),
1404
+
1405
+
SND_SOC_DAPM_SUPPLY("CM1_Enable",
1406
+
AFE_CM1_CON0, AFE_CM0_ON_SFT, 0,
1407
+
ul_cm1_event,
1408
+
SND_SOC_DAPM_PRE_PMU |
1409
+
SND_SOC_DAPM_PRE_PMD),
1410
+
1411
+
/* dynamic pinctrl */
1412
+
SND_SOC_DAPM_PINCTRL("I2S0_PIN", "aud-gpio-i2s0-on", "aud-gpio-i2s0-off"),
1413
+
SND_SOC_DAPM_PINCTRL("I2S1_PIN", "aud-gpio-i2s1-on", "aud-gpio-i2s1-off"),
1414
+
SND_SOC_DAPM_PINCTRL("PCM0_PIN", "aud-gpio-pcm-on", "aud-gpio-pcm-off"),
1415
+
SND_SOC_DAPM_PINCTRL("AP_DMIC0_PIN", "aud-gpio-ap-dmic-on", "aud-gpio-ap-dmic-off"),
1416
+
SND_SOC_DAPM_PINCTRL("AP_DMIC1_PIN", "aud-gpio-ap-dmic1-on", "aud-gpio-ap-dmic1-off"),
1417
+
};
1418
+
1419
+
static const struct snd_soc_dapm_route mt8189_memif_routes[] = {
1420
+
{"UL0", NULL, "UL0_CH1"},
1421
+
{"UL0", NULL, "UL0_CH2"},
1422
+
/* Normal record */
1423
+
{"UL0_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
1424
+
{"UL0_CH1", "ADDA_UL_CH2", "ADDA_UL_Mux"},
1425
+
{"UL0_CH1", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"},
1426
+
{"UL0_CH1", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"},
1427
+
{"UL0_CH2", "ADDA_UL_CH1", "ADDA_UL_Mux"},
1428
+
{"UL0_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},
1429
+
{"UL0_CH2", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"},
1430
+
{"UL0_CH2", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"},
1431
+
1432
+
{"UL0_CH1", "AP_DMIC_UL_CH1", "AP DMIC Capture"},
1433
+
{"UL0_CH1", "AP_DMIC_UL_CH2", "AP DMIC Capture"},
1434
+
{"UL0_CH2", "AP_DMIC_UL_CH2", "AP DMIC Capture"},
1435
+
1436
+
{"UL0_CH1", "I2SIN0_CH1", "I2SIN0"},
1437
+
{"UL0_CH2", "I2SIN0_CH2", "I2SIN0"},
1438
+
{"UL0_CH1", "I2SIN1_CH1", "I2SIN1"},
1439
+
{"UL0_CH2", "I2SIN1_CH2", "I2SIN1"},
1440
+
1441
+
{"UL0_CH1", "PCM_0_CAP_CH1", "PCM 0 Capture"},
1442
+
{"UL0_CH2", "PCM_0_CAP_CH1", "PCM 0 Capture"},
1443
+
1444
+
{"UL1", NULL, "UL1_CH1"},
1445
+
{"UL1", NULL, "UL1_CH2"},
1446
+
1447
+
{"UL1_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
1448
+
{"UL1_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},
1449
+
1450
+
{"UL1_CH1", "I2SIN0_CH1", "I2SIN0"},
1451
+
{"UL1_CH2", "I2SIN0_CH2", "I2SIN0"},
1452
+
{"UL1_CH1", "I2SIN1_CH1", "I2SIN1"},
1453
+
{"UL1_CH2", "I2SIN1_CH2", "I2SIN1"},
1454
+
1455
+
{"UL1_CH1", "PCM_0_CAP_CH1", "PCM 0 Capture"},
1456
+
{"UL1_CH2", "PCM_0_CAP_CH1", "PCM 0 Capture"},
1457
+
1458
+
{"UL2", NULL, "UL2_CH1"},
1459
+
{"UL2", NULL, "UL2_CH2"},
1460
+
1461
+
{"UL2_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
1462
+
{"UL2_CH1", "ADDA_UL_CH2", "ADDA_UL_Mux"},
1463
+
{"UL2_CH1", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"},
1464
+
{"UL2_CH1", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"},
1465
+
{"UL2_CH2", "ADDA_UL_CH1", "ADDA_UL_Mux"},
1466
+
{"UL2_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},
1467
+
{"UL2_CH2", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"},
1468
+
{"UL2_CH2", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"},
1469
+
1470
+
{"UL2_CH1", "AP_DMIC_UL_CH3", "AP DMIC CH34 Capture"},
1471
+
{"UL2_CH2", "AP_DMIC_UL_CH4", "AP DMIC CH34 Capture"},
1472
+
1473
+
{"UL3", NULL, "UL3_CH1"},
1474
+
{"UL3", NULL, "UL3_CH2"},
1475
+
1476
+
{"UL3_CH1", "ADDA_UL_CH1", "ADDA Capture"},
1477
+
{"UL3_CH2", "ADDA_UL_CH2", "ADDA Capture"},
1478
+
{"UL3_CH1", "I2SIN1_CH1", "I2SIN1"},
1479
+
{"UL3_CH2", "I2SIN1_CH2", "I2SIN1"},
1480
+
1481
+
{"UL4", NULL, "UL4_CH1"},
1482
+
{"UL4", NULL, "UL4_CH2"},
1483
+
{"UL4_CH1", "ADDA_UL_CH1", "ADDA Capture"},
1484
+
{"UL4_CH2", "ADDA_UL_CH2", "ADDA Capture"},
1485
+
1486
+
{"UL4_CH1", "PCM_0_CAP_CH1", "PCM 0 Capture"},
1487
+
{"UL4_CH2", "PCM_0_CAP_CH1", "PCM 0 Capture"},
1488
+
1489
+
{"UL5", NULL, "UL5_CH1"},
1490
+
{"UL5", NULL, "UL5_CH2"},
1491
+
1492
+
{"UL5_CH1", "ADDA_UL_CH1", "ADDA Capture"},
1493
+
{"UL5_CH2", "ADDA_UL_CH2", "ADDA Capture"},
1494
+
1495
+
{"UL6", NULL, "UL6_CH1"},
1496
+
{"UL6", NULL, "UL6_CH2"},
1497
+
{"UL6_CH1", "ADDA_UL_CH1", "ADDA Capture"},
1498
+
{"UL6_CH2", "ADDA_UL_CH2", "ADDA Capture"},
1499
+
{"UL6_CH1", "I2SIN0_CH1", "I2SIN0"},
1500
+
{"UL6_CH2", "I2SIN0_CH2", "I2SIN0"},
1501
+
{"UL6_CH1", "AP_DMIC_UL_CH1", "AP DMIC Capture"},
1502
+
{"UL6_CH2", "AP_DMIC_UL_CH2", "AP DMIC Capture"},
1503
+
1504
+
{"UL7", NULL, "UL7_CH1"},
1505
+
{"UL7", NULL, "UL7_CH2"},
1506
+
{"UL7_CH1", "ADDA_UL_CH1", "ADDA Capture"},
1507
+
{"UL7_CH1", "ADDA_UL_CH2", "ADDA Capture"},
1508
+
{"UL7_CH2", "ADDA_UL_CH1", "ADDA Capture"},
1509
+
{"UL7_CH2", "ADDA_UL_CH2", "ADDA Capture"},
1510
+
{"UL7_CH1", "I2SIN0_CH1", "I2SIN0"},
1511
+
{"UL7_CH2", "I2SIN0_CH2", "I2SIN0"},
1512
+
{"UL7_CH1", "AP_DMIC_UL_CH3", "AP DMIC CH34 Capture"},
1513
+
{"UL7_CH2", "AP_DMIC_UL_CH4", "AP DMIC CH34 Capture"},
1514
+
1515
+
{"UL8", NULL, "CM0_UL_MUX"},
1516
+
{"CM0_UL_MUX", "CM0_2CH_PATH", "UL8_CH1"},
1517
+
{"CM0_UL_MUX", "CM0_2CH_PATH", "UL8_CH2"},
1518
+
{"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH1"},
1519
+
{"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH2"},
1520
+
{"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH3"},
1521
+
{"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH4"},
1522
+
{"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH5"},
1523
+
{"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH6"},
1524
+
{"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH7"},
1525
+
{"CM0_UL_MUX", "CM0_8CH_PATH", "UL_CM0_CH8"},
1526
+
1527
+
{"UL_CM0", NULL, "CM0_Enable"},
1528
+
1529
+
{"UL9", NULL, "CM1_UL_MUX"},
1530
+
{"CM1_UL_MUX", "CM1_2CH_PATH", "UL9_CH1"},
1531
+
{"CM1_UL_MUX", "CM1_2CH_PATH", "UL9_CH2"},
1532
+
{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH1"},
1533
+
{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH2"},
1534
+
{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH3"},
1535
+
{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH4"},
1536
+
{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH5"},
1537
+
{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH6"},
1538
+
{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH7"},
1539
+
{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH8"},
1540
+
{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH9"},
1541
+
{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH10"},
1542
+
{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH11"},
1543
+
{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH12"},
1544
+
{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH13"},
1545
+
{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH14"},
1546
+
{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH15"},
1547
+
{"CM1_UL_MUX", "CM1_16CH_PATH", "UL_CM1_CH16"},
1548
+
1549
+
{"UL_CM1", NULL, "CM1_Enable"},
1550
+
1551
+
/* UL9 o36o37 <- ADDA */
1552
+
{"UL9_CH1", "ADDA_UL_CH1", "ADDA Capture"},
1553
+
{"UL9_CH1", "ADDA_UL_CH2", "ADDA Capture"},
1554
+
{"UL9_CH2", "ADDA_UL_CH1", "ADDA Capture"},
1555
+
{"UL9_CH2", "ADDA_UL_CH2", "ADDA Capture"},
1556
+
1557
+
{"UL24", NULL, "UL24_CH1"},
1558
+
{"UL24", NULL, "UL24_CH2"},
1559
+
{"UL24_CH1", "ADDA_UL_CH1", "ADDA Capture"},
1560
+
1561
+
{"UL_CM0", NULL, "UL_CM0_CH1"},
1562
+
{"UL_CM0", NULL, "UL_CM0_CH2"},
1563
+
{"UL_CM0", NULL, "UL_CM0_CH3"},
1564
+
{"UL_CM0", NULL, "UL_CM0_CH4"},
1565
+
{"UL_CM0", NULL, "UL_CM0_CH5"},
1566
+
{"UL_CM0", NULL, "UL_CM0_CH6"},
1567
+
{"UL_CM0", NULL, "UL_CM0_CH7"},
1568
+
{"UL_CM0", NULL, "UL_CM0_CH8"},
1569
+
{"UL_CM0_CH1", "ADDA_UL_CH1", "ADDA Capture"},
1570
+
{"UL_CM0_CH1", "ADDA_UL_CH2", "ADDA Capture"},
1571
+
{"UL_CM0_CH2", "ADDA_UL_CH1", "ADDA Capture"},
1572
+
{"UL_CM0_CH2", "ADDA_UL_CH2", "ADDA Capture"},
1573
+
{"UL_CM0_CH3", "ADDA_UL_CH1", "ADDA Capture"},
1574
+
{"UL_CM0_CH3", "ADDA_UL_CH2", "ADDA Capture"},
1575
+
{"UL_CM0_CH4", "ADDA_UL_CH1", "ADDA Capture"},
1576
+
{"UL_CM0_CH4", "ADDA_UL_CH2", "ADDA Capture"},
1577
+
{"UL_CM0_CH1", "AP_DMIC_UL_CH1", "AP DMIC Capture"},
1578
+
{"UL_CM0_CH2", "AP_DMIC_UL_CH2", "AP DMIC Capture"},
1579
+
{"UL_CM0_CH3", "AP_DMIC_UL_CH3", "AP DMIC CH34 Capture"},
1580
+
{"UL_CM0_CH4", "AP_DMIC_UL_CH4", "AP DMIC CH34 Capture"},
1581
+
1582
+
{"UL_CM1", NULL, "UL_CM1_CH1"},
1583
+
{"UL_CM1", NULL, "UL_CM1_CH2"},
1584
+
{"UL_CM1", NULL, "UL_CM1_CH3"},
1585
+
{"UL_CM1", NULL, "UL_CM1_CH4"},
1586
+
{"UL_CM1", NULL, "UL_CM1_CH5"},
1587
+
{"UL_CM1", NULL, "UL_CM1_CH6"},
1588
+
{"UL_CM1", NULL, "UL_CM1_CH7"},
1589
+
{"UL_CM1", NULL, "UL_CM1_CH8"},
1590
+
{"UL_CM1", NULL, "UL_CM1_CH9"},
1591
+
{"UL_CM1", NULL, "UL_CM1_CH10"},
1592
+
{"UL_CM1", NULL, "UL_CM1_CH11"},
1593
+
{"UL_CM1", NULL, "UL_CM1_CH12"},
1594
+
{"UL_CM1", NULL, "UL_CM1_CH13"},
1595
+
{"UL_CM1", NULL, "UL_CM1_CH14"},
1596
+
{"UL_CM1", NULL, "UL_CM1_CH15"},
1597
+
{"UL_CM1", NULL, "UL_CM1_CH16"},
1598
+
{"UL_CM1_CH1", "ADDA_UL_CH1", "ADDA Capture"},
1599
+
{"UL_CM1_CH1", "ADDA_UL_CH2", "ADDA Capture"},
1600
+
{"UL_CM1_CH2", "ADDA_UL_CH1", "ADDA Capture"},
1601
+
{"UL_CM1_CH2", "ADDA_UL_CH2", "ADDA Capture"},
1602
+
{"UL_CM1_CH3", "ADDA_UL_CH1", "ADDA Capture"},
1603
+
{"UL_CM1_CH3", "ADDA_UL_CH2", "ADDA Capture"},
1604
+
{"UL_CM1_CH4", "ADDA_UL_CH1", "ADDA Capture"},
1605
+
{"UL_CM1_CH4", "ADDA_UL_CH2", "ADDA Capture"},
1606
+
{"UL_CM1_CH5", "ADDA_UL_CH1", "ADDA Capture"},
1607
+
{"UL_CM1_CH5", "ADDA_UL_CH2", "ADDA Capture"},
1608
+
{"UL_CM1_CH6", "ADDA_UL_CH1", "ADDA Capture"},
1609
+
{"UL_CM1_CH6", "ADDA_UL_CH2", "ADDA Capture"},
1610
+
1611
+
/* Audio Pin */
1612
+
{"I2SOUT0", NULL, "I2S0_PIN"},
1613
+
{"I2SIN0", NULL, "I2S0_PIN"},
1614
+
{"I2SOUT1", NULL, "I2S1_PIN"},
1615
+
{"I2SIN1", NULL, "I2S1_PIN"},
1616
+
{"PCM 0 Playback", NULL, "PCM0_PIN"},
1617
+
{"AP DMIC Capture", NULL, "AP_DMIC0_PIN"},
1618
+
{"AP DMIC CH34 Capture", NULL, "AP_DMIC1_PIN"},
1619
+
};
1620
+
1621
+
#define MT8189_DL_MEMIF(_id) \
1622
+
[MT8189_MEMIF_##_id] = { \
1623
+
.name = #_id, \
1624
+
.id = MT8189_MEMIF_##_id, \
1625
+
.reg_ofs_base = AFE_##_id##_BASE, \
1626
+
.reg_ofs_cur = AFE_##_id##_CUR, \
1627
+
.reg_ofs_end = AFE_##_id##_END, \
1628
+
.reg_ofs_base_msb = AFE_##_id##_BASE_MSB, \
1629
+
.reg_ofs_cur_msb = AFE_##_id##_CUR_MSB, \
1630
+
.reg_ofs_end_msb = AFE_##_id##_END_MSB, \
1631
+
.fs_reg = AFE_##_id##_CON0, \
1632
+
.fs_shift = _id##_SEL_FS_SFT, \
1633
+
.fs_maskbit = _id##_SEL_FS_MASK, \
1634
+
.mono_reg = AFE_##_id##_CON0, \
1635
+
.mono_shift = _id##_MONO_SFT, \
1636
+
.enable_reg = AFE_##_id##_CON0, \
1637
+
.enable_shift = _id##_ON_SFT, \
1638
+
.hd_reg = AFE_##_id##_CON0, \
1639
+
.hd_shift = _id##_HD_MODE_SFT, \
1640
+
.hd_align_reg = AFE_##_id##_CON0, \
1641
+
.hd_align_mshift = _id##_HALIGN_SFT, \
1642
+
.agent_disable_reg = -1, \
1643
+
.agent_disable_shift = -1, \
1644
+
.msb_reg = -1, \
1645
+
.msb_shift = -1, \
1646
+
.pbuf_reg = AFE_##_id##_CON0, \
1647
+
.pbuf_mask = _id##_PBUF_SIZE_MASK, \
1648
+
.pbuf_shift = _id##_PBUF_SIZE_SFT, \
1649
+
.minlen_reg = AFE_##_id##_CON0, \
1650
+
.minlen_mask = _id##_MINLEN_MASK, \
1651
+
.minlen_shift = _id##_MINLEN_SFT, \
1652
+
}
1653
+
1654
+
#define MT8189_MULTI_DL_MEMIF(_id) \
1655
+
[MT8189_MEMIF_##_id] = { \
1656
+
.name = #_id, \
1657
+
.id = MT8189_MEMIF_##_id, \
1658
+
.reg_ofs_base = AFE_##_id##_BASE, \
1659
+
.reg_ofs_cur = AFE_##_id##_CUR, \
1660
+
.reg_ofs_end = AFE_##_id##_END, \
1661
+
.reg_ofs_base_msb = AFE_##_id##_BASE_MSB, \
1662
+
.reg_ofs_cur_msb = AFE_##_id##_CUR_MSB, \
1663
+
.reg_ofs_end_msb = AFE_##_id##_END_MSB, \
1664
+
.fs_reg = AFE_##_id##_CON0, \
1665
+
.fs_shift = _id##_SEL_FS_SFT, \
1666
+
.fs_maskbit = _id##_SEL_FS_MASK, \
1667
+
.mono_reg = -1, \
1668
+
.mono_shift = -1, \
1669
+
.enable_reg = AFE_##_id##_CON0, \
1670
+
.enable_shift = _id##_ON_SFT, \
1671
+
.hd_reg = AFE_##_id##_CON0, \
1672
+
.hd_shift = _id##_HD_MODE_SFT, \
1673
+
.hd_align_reg = AFE_##_id##_CON0, \
1674
+
.hd_align_mshift = _id##_HALIGN_SFT, \
1675
+
.agent_disable_reg = -1, \
1676
+
.agent_disable_shift = -1, \
1677
+
.msb_reg = -1, \
1678
+
.msb_shift = -1, \
1679
+
.pbuf_reg = AFE_##_id##_CON0, \
1680
+
.pbuf_mask = _id##_PBUF_SIZE_MASK, \
1681
+
.pbuf_shift = _id##_PBUF_SIZE_SFT, \
1682
+
.minlen_reg = AFE_##_id##_CON0, \
1683
+
.minlen_mask = _id##_MINLEN_MASK, \
1684
+
.minlen_shift = _id##_MINLEN_SFT, \
1685
+
.ch_num_reg = AFE_##_id##_CON0, \
1686
+
.ch_num_maskbit = _id##_NUM_MASK, \
1687
+
.ch_num_shift = _id##_NUM_SFT, \
1688
+
}
1689
+
1690
+
#define MT8189_UL_MEMIF(_id, _fs_shift, _fs_maskbit, _mono_shift) \
1691
+
[MT8189_MEMIF_##_id] = { \
1692
+
.name = #_id, \
1693
+
.id = MT8189_MEMIF_##_id, \
1694
+
.reg_ofs_base = AFE_##_id##_BASE, \
1695
+
.reg_ofs_cur = AFE_##_id##_CUR, \
1696
+
.reg_ofs_end = AFE_##_id##_END, \
1697
+
.reg_ofs_base_msb = AFE_##_id##_BASE_MSB, \
1698
+
.reg_ofs_cur_msb = AFE_##_id##_CUR_MSB, \
1699
+
.reg_ofs_end_msb = AFE_##_id##_END_MSB, \
1700
+
.fs_reg = AFE_##_id##_CON0, \
1701
+
.fs_shift = _fs_shift, \
1702
+
.fs_maskbit = _fs_maskbit, \
1703
+
.mono_reg = AFE_##_id##_CON0, \
1704
+
.mono_shift = _mono_shift, \
1705
+
.enable_reg = AFE_##_id##_CON0, \
1706
+
.enable_shift = _id##_ON_SFT, \
1707
+
.hd_reg = AFE_##_id##_CON0, \
1708
+
.hd_shift = _id##_HD_MODE_SFT, \
1709
+
.hd_align_reg = AFE_##_id##_CON0, \
1710
+
.hd_align_mshift = _id##_HALIGN_SFT, \
1711
+
.agent_disable_reg = -1, \
1712
+
.agent_disable_shift = -1, \
1713
+
.msb_reg = -1, \
1714
+
.msb_shift = -1, \
1715
+
}
1716
+
1717
+
/* For convenience with macros: missing register fields */
1718
+
#define HDMI_SEL_FS_SFT -1
1719
+
#define HDMI_SEL_FS_MASK -1
1720
+
1721
+
/* For convenience with macros: register name differences */
1722
+
#define AFE_HDMI_BASE AFE_HDMI_OUT_BASE
1723
+
#define AFE_HDMI_CUR AFE_HDMI_OUT_CUR
1724
+
#define AFE_HDMI_END AFE_HDMI_OUT_END
1725
+
#define AFE_HDMI_BASE_MSB AFE_HDMI_OUT_BASE_MSB
1726
+
#define AFE_HDMI_CUR_MSB AFE_HDMI_OUT_CUR_MSB
1727
+
#define AFE_HDMI_END_MSB AFE_HDMI_OUT_END_MSB
1728
+
#define AFE_HDMI_CON0 AFE_HDMI_OUT_CON0
1729
+
#define HDMI_ON_SFT HDMI_OUT_ON_SFT
1730
+
#define HDMI_HD_MODE_SFT HDMI_OUT_HD_MODE_SFT
1731
+
#define HDMI_HALIGN_SFT HDMI_OUT_HALIGN_SFT
1732
+
#define HDMI_PBUF_SIZE_MASK HDMI_OUT_PBUF_SIZE_MASK
1733
+
#define HDMI_PBUF_SIZE_SFT HDMI_OUT_PBUF_SIZE_SFT
1734
+
#define HDMI_MINLEN_MASK HDMI_OUT_MINLEN_MASK
1735
+
#define HDMI_MINLEN_SFT HDMI_OUT_MINLEN_SFT
1736
+
#define HDMI_NUM_MASK HDMI_CH_NUM_MASK
1737
+
#define HDMI_NUM_SFT HDMI_CH_NUM_SFT
1738
+
1739
+
static const struct mtk_base_memif_data memif_data[MT8189_MEMIF_NUM] = {
1740
+
MT8189_DL_MEMIF(DL0),
1741
+
MT8189_DL_MEMIF(DL1),
1742
+
MT8189_DL_MEMIF(DL2),
1743
+
MT8189_DL_MEMIF(DL3),
1744
+
MT8189_DL_MEMIF(DL4),
1745
+
MT8189_DL_MEMIF(DL5),
1746
+
MT8189_DL_MEMIF(DL6),
1747
+
MT8189_DL_MEMIF(DL7),
1748
+
MT8189_DL_MEMIF(DL8),
1749
+
MT8189_DL_MEMIF(DL23),
1750
+
MT8189_DL_MEMIF(DL24),
1751
+
MT8189_DL_MEMIF(DL25),
1752
+
MT8189_MULTI_DL_MEMIF(DL_24CH),
1753
+
MT8189_MULTI_DL_MEMIF(HDMI),
1754
+
MT8189_UL_MEMIF(VUL0, VUL0_SEL_FS_SFT, VUL0_SEL_FS_MASK, VUL0_MONO_SFT),
1755
+
MT8189_UL_MEMIF(VUL1, VUL1_SEL_FS_SFT, VUL1_SEL_FS_MASK, VUL1_MONO_SFT),
1756
+
MT8189_UL_MEMIF(VUL2, VUL2_SEL_FS_SFT, VUL2_SEL_FS_MASK, VUL2_MONO_SFT),
1757
+
MT8189_UL_MEMIF(VUL3, VUL3_SEL_FS_SFT, VUL3_SEL_FS_MASK, VUL3_MONO_SFT),
1758
+
MT8189_UL_MEMIF(VUL4, VUL4_SEL_FS_SFT, VUL4_SEL_FS_MASK, VUL4_MONO_SFT),
1759
+
MT8189_UL_MEMIF(VUL5, VUL5_SEL_FS_SFT, VUL5_SEL_FS_MASK, VUL5_MONO_SFT),
1760
+
MT8189_UL_MEMIF(VUL6, VUL6_SEL_FS_SFT, VUL6_SEL_FS_MASK, VUL6_MONO_SFT),
1761
+
MT8189_UL_MEMIF(VUL7, VUL7_SEL_FS_SFT, VUL7_SEL_FS_MASK, VUL7_MONO_SFT),
1762
+
MT8189_UL_MEMIF(VUL8, VUL8_SEL_FS_SFT, VUL8_SEL_FS_MASK, VUL8_MONO_SFT),
1763
+
MT8189_UL_MEMIF(VUL9, VUL9_SEL_FS_SFT, VUL9_SEL_FS_MASK, VUL9_MONO_SFT),
1764
+
MT8189_UL_MEMIF(VUL10, VUL10_SEL_FS_SFT, VUL10_SEL_FS_MASK, VUL10_MONO_SFT),
1765
+
MT8189_UL_MEMIF(VUL24, VUL24_SEL_FS_SFT, VUL24_SEL_FS_MASK, VUL24_MONO_SFT),
1766
+
MT8189_UL_MEMIF(VUL25, VUL25_SEL_FS_SFT, VUL25_SEL_FS_MASK, VUL25_MONO_SFT),
1767
+
MT8189_UL_MEMIF(VUL_CM0, -1, -1, -1),
1768
+
MT8189_UL_MEMIF(VUL_CM1, -1, -1, -1),
1769
+
MT8189_UL_MEMIF(ETDM_IN0, REG_FS_TIMING_SEL_SFT, REG_FS_TIMING_SEL_MASK, -1),
1770
+
MT8189_UL_MEMIF(ETDM_IN1, REG_FS_TIMING_SEL_SFT, REG_FS_TIMING_SEL_MASK, -1),
1771
+
};
1772
+
1773
+
#define MT8189_AFE_IRQ(_id) \
1774
+
[MT8189_IRQ_##_id] = { \
1775
+
.id = MT8189_IRQ_##_id, \
1776
+
.irq_cnt_reg = AFE_IRQ##_id##_MCU_CFG1, \
1777
+
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT, \
1778
+
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK, \
1779
+
.irq_fs_reg = AFE_IRQ##_id##_MCU_CFG0, \
1780
+
.irq_fs_shift = AFE_IRQ##_id##_MCU_FS_SFT, \
1781
+
.irq_fs_maskbit = AFE_IRQ##_id##_MCU_FS_MASK, \
1782
+
.irq_en_reg = AFE_IRQ##_id##_MCU_CFG0, \
1783
+
.irq_en_shift = AFE_IRQ##_id##_MCU_ON_SFT, \
1784
+
.irq_clr_reg = AFE_IRQ##_id##_MCU_CFG1, \
1785
+
.irq_clr_shift = AFE_IRQ##_id##_CLR_CFG_SFT, \
1786
+
}
1787
+
1788
+
#define MT8189_AFE_TDM_IRQ(_id) \
1789
+
[MT8189_IRQ_##_id] = { \
1790
+
.id = MT8189_CUS_IRQ_TDM, \
1791
+
.irq_cnt_reg = AFE_CUSTOM_IRQ0_MCU_CFG1, \
1792
+
.irq_cnt_shift = AFE_CUSTOM_IRQ0_MCU_CNT_SFT, \
1793
+
.irq_cnt_maskbit = AFE_CUSTOM_IRQ0_MCU_CNT_MASK, \
1794
+
.irq_fs_reg = -1, \
1795
+
.irq_fs_shift = -1, \
1796
+
.irq_fs_maskbit = -1, \
1797
+
.irq_en_reg = AFE_CUSTOM_IRQ0_MCU_CFG0, \
1798
+
.irq_en_shift = AFE_CUSTOM_IRQ0_MCU_ON_SFT, \
1799
+
.irq_clr_reg = AFE_CUSTOM_IRQ0_MCU_CFG1, \
1800
+
.irq_clr_shift = AFE_CUSTOM_IRQ0_CLR_CFG_SFT, \
1801
+
}
1802
+
1803
+
static const struct mtk_base_irq_data irq_data[MT8189_IRQ_NUM] = {
1804
+
MT8189_AFE_IRQ(0),
1805
+
MT8189_AFE_IRQ(1),
1806
+
MT8189_AFE_IRQ(2),
1807
+
MT8189_AFE_IRQ(3),
1808
+
MT8189_AFE_IRQ(4),
1809
+
MT8189_AFE_IRQ(5),
1810
+
MT8189_AFE_IRQ(6),
1811
+
MT8189_AFE_IRQ(7),
1812
+
MT8189_AFE_IRQ(8),
1813
+
MT8189_AFE_IRQ(9),
1814
+
MT8189_AFE_IRQ(10),
1815
+
MT8189_AFE_IRQ(11),
1816
+
MT8189_AFE_IRQ(12),
1817
+
MT8189_AFE_IRQ(13),
1818
+
MT8189_AFE_IRQ(14),
1819
+
MT8189_AFE_IRQ(15),
1820
+
MT8189_AFE_IRQ(16),
1821
+
MT8189_AFE_IRQ(17),
1822
+
MT8189_AFE_IRQ(18),
1823
+
MT8189_AFE_IRQ(19),
1824
+
MT8189_AFE_IRQ(20),
1825
+
MT8189_AFE_IRQ(21),
1826
+
MT8189_AFE_IRQ(22),
1827
+
MT8189_AFE_IRQ(23),
1828
+
MT8189_AFE_IRQ(24),
1829
+
MT8189_AFE_IRQ(25),
1830
+
MT8189_AFE_IRQ(26),
1831
+
MT8189_AFE_TDM_IRQ(31),
1832
+
};
1833
+
1834
+
static const int memif_irq_usage[MT8189_MEMIF_NUM] = {
1835
+
/* TODO: verify each memif & irq */
1836
+
[MT8189_MEMIF_DL0] = MT8189_IRQ_0,
1837
+
[MT8189_MEMIF_DL1] = MT8189_IRQ_1,
1838
+
[MT8189_MEMIF_DL2] = MT8189_IRQ_2,
1839
+
[MT8189_MEMIF_DL3] = MT8189_IRQ_3,
1840
+
[MT8189_MEMIF_DL4] = MT8189_IRQ_4,
1841
+
[MT8189_MEMIF_DL5] = MT8189_IRQ_5,
1842
+
[MT8189_MEMIF_DL6] = MT8189_IRQ_6,
1843
+
[MT8189_MEMIF_DL7] = MT8189_IRQ_7,
1844
+
[MT8189_MEMIF_DL8] = MT8189_IRQ_8,
1845
+
[MT8189_MEMIF_DL23] = MT8189_IRQ_9,
1846
+
[MT8189_MEMIF_DL24] = MT8189_IRQ_10,
1847
+
[MT8189_MEMIF_DL25] = MT8189_IRQ_11,
1848
+
[MT8189_MEMIF_DL_24CH] = MT8189_IRQ_12,
1849
+
[MT8189_MEMIF_VUL0] = MT8189_IRQ_13,
1850
+
[MT8189_MEMIF_VUL1] = MT8189_IRQ_14,
1851
+
[MT8189_MEMIF_VUL2] = MT8189_IRQ_15,
1852
+
[MT8189_MEMIF_VUL3] = MT8189_IRQ_16,
1853
+
[MT8189_MEMIF_VUL4] = MT8189_IRQ_17,
1854
+
[MT8189_MEMIF_VUL5] = MT8189_IRQ_18,
1855
+
[MT8189_MEMIF_VUL6] = MT8189_IRQ_19,
1856
+
[MT8189_MEMIF_VUL7] = MT8189_IRQ_20,
1857
+
[MT8189_MEMIF_VUL8] = MT8189_IRQ_21,
1858
+
[MT8189_MEMIF_VUL9] = MT8189_IRQ_22,
1859
+
[MT8189_MEMIF_VUL10] = MT8189_IRQ_23,
1860
+
[MT8189_MEMIF_VUL24] = MT8189_IRQ_24,
1861
+
[MT8189_MEMIF_VUL25] = MT8189_IRQ_25,
1862
+
[MT8189_MEMIF_VUL_CM0] = MT8189_IRQ_26,
1863
+
[MT8189_MEMIF_VUL_CM1] = MT8189_IRQ_0,
1864
+
[MT8189_MEMIF_ETDM_IN0] = MT8189_IRQ_0,
1865
+
[MT8189_MEMIF_ETDM_IN1] = MT8189_IRQ_0,
1866
+
[MT8189_MEMIF_HDMI] = MT8189_IRQ_31
1867
+
};
1868
+
1869
+
static bool mt8189_is_volatile_reg(struct device *dev, unsigned int reg)
1870
+
{
1871
+
/* these auto-gen reg has read-only bit, so put it as volatile */
1872
+
/* volatile reg cannot be cached, so cannot be set when power off */
1873
+
switch (reg) {
1874
+
case AUDIO_TOP_CON0:
1875
+
case AUDIO_TOP_CON1:
1876
+
case AUDIO_TOP_CON2:
1877
+
case AUDIO_TOP_CON3:
1878
+
case AUDIO_TOP_CON4:
1879
+
case AFE_APLL1_TUNER_MON0:
1880
+
case AFE_APLL2_TUNER_MON0:
1881
+
case AFE_SPM_CONTROL_ACK:
1882
+
case AUDIO_TOP_IP_VERSION:
1883
+
case AUDIO_ENGEN_CON0_MON:
1884
+
case AFE_CONNSYS_I2S_IPM_VER_MON:
1885
+
case AFE_CONNSYS_I2S_MON:
1886
+
case AFE_PCM_INTF_MON:
1887
+
case AFE_PCM_TOP_IP_VERSION:
1888
+
case AFE_IRQ_MCU_STATUS:
1889
+
case AFE_CUSTOM_IRQ_MCU_STATUS:
1890
+
case AFE_IRQ_MCU_MON0:
1891
+
case AFE_IRQ_MCU_MON1:
1892
+
case AFE_IRQ_MCU_MON2:
1893
+
case AFE_IRQ0_CNT_MON:
1894
+
case AFE_IRQ1_CNT_MON:
1895
+
case AFE_IRQ2_CNT_MON:
1896
+
case AFE_IRQ3_CNT_MON:
1897
+
case AFE_IRQ4_CNT_MON:
1898
+
case AFE_IRQ5_CNT_MON:
1899
+
case AFE_IRQ6_CNT_MON:
1900
+
case AFE_IRQ7_CNT_MON:
1901
+
case AFE_IRQ8_CNT_MON:
1902
+
case AFE_IRQ9_CNT_MON:
1903
+
case AFE_IRQ10_CNT_MON:
1904
+
case AFE_IRQ11_CNT_MON:
1905
+
case AFE_IRQ12_CNT_MON:
1906
+
case AFE_IRQ13_CNT_MON:
1907
+
case AFE_IRQ14_CNT_MON:
1908
+
case AFE_IRQ15_CNT_MON:
1909
+
case AFE_IRQ16_CNT_MON:
1910
+
case AFE_IRQ17_CNT_MON:
1911
+
case AFE_IRQ18_CNT_MON:
1912
+
case AFE_IRQ19_CNT_MON:
1913
+
case AFE_IRQ20_CNT_MON:
1914
+
case AFE_IRQ21_CNT_MON:
1915
+
case AFE_IRQ22_CNT_MON:
1916
+
case AFE_IRQ23_CNT_MON:
1917
+
case AFE_IRQ24_CNT_MON:
1918
+
case AFE_IRQ25_CNT_MON:
1919
+
case AFE_IRQ26_CNT_MON:
1920
+
case AFE_CM0_MON:
1921
+
case AFE_CM0_IP_VERSION:
1922
+
case AFE_CM1_MON:
1923
+
case AFE_CM1_IP_VERSION:
1924
+
case AFE_ADDA_UL0_SRC_DEBUG_MON0:
1925
+
case AFE_ADDA_UL0_SRC_MON0:
1926
+
case AFE_ADDA_UL0_SRC_MON1:
1927
+
case AFE_ADDA_UL0_IP_VERSION:
1928
+
case AFE_ADDA_DMIC0_SRC_DEBUG_MON0:
1929
+
case AFE_ADDA_DMIC0_SRC_MON0:
1930
+
case AFE_ADDA_DMIC0_SRC_MON1:
1931
+
case AFE_ADDA_DMIC0_IP_VERSION:
1932
+
case AFE_ADDA_DMIC1_SRC_DEBUG_MON0:
1933
+
case AFE_ADDA_DMIC1_SRC_MON0:
1934
+
case AFE_ADDA_DMIC1_SRC_MON1:
1935
+
case AFE_ADDA_DMIC1_IP_VERSION:
1936
+
case AFE_MTKAIF_IPM_VER_MON:
1937
+
case AFE_MTKAIF_MON:
1938
+
case AFE_AUD_PAD_TOP_MON:
1939
+
case AFE_ADDA_MTKAIFV4_MON0:
1940
+
case AFE_ADDA_MTKAIFV4_MON1:
1941
+
case AFE_ADDA6_MTKAIFV4_MON0:
1942
+
case ETDM_IN0_MON:
1943
+
case ETDM_IN1_MON:
1944
+
case ETDM_OUT0_MON:
1945
+
case ETDM_OUT1_MON:
1946
+
case ETDM_OUT4_MON:
1947
+
case AFE_CONN_MON0:
1948
+
case AFE_CONN_MON1:
1949
+
case AFE_CONN_MON2:
1950
+
case AFE_CONN_MON3:
1951
+
case AFE_CONN_MON4:
1952
+
case AFE_CONN_MON5:
1953
+
case AFE_CBIP_SLV_DECODER_MON0:
1954
+
case AFE_CBIP_SLV_DECODER_MON1:
1955
+
case AFE_CBIP_SLV_MUX_MON0:
1956
+
case AFE_CBIP_SLV_MUX_MON1:
1957
+
case AFE_DL0_CUR_MSB:
1958
+
case AFE_DL0_CUR:
1959
+
case AFE_DL0_RCH_MON:
1960
+
case AFE_DL0_LCH_MON:
1961
+
case AFE_DL1_CUR_MSB:
1962
+
case AFE_DL1_CUR:
1963
+
case AFE_DL1_RCH_MON:
1964
+
case AFE_DL1_LCH_MON:
1965
+
case AFE_DL2_CUR_MSB:
1966
+
case AFE_DL2_CUR:
1967
+
case AFE_DL2_RCH_MON:
1968
+
case AFE_DL2_LCH_MON:
1969
+
case AFE_DL3_CUR_MSB:
1970
+
case AFE_DL3_CUR:
1971
+
case AFE_DL3_RCH_MON:
1972
+
case AFE_DL3_LCH_MON:
1973
+
case AFE_DL4_CUR_MSB:
1974
+
case AFE_DL4_CUR:
1975
+
case AFE_DL4_RCH_MON:
1976
+
case AFE_DL4_LCH_MON:
1977
+
case AFE_DL5_CUR_MSB:
1978
+
case AFE_DL5_CUR:
1979
+
case AFE_DL5_RCH_MON:
1980
+
case AFE_DL5_LCH_MON:
1981
+
case AFE_DL6_CUR_MSB:
1982
+
case AFE_DL6_CUR:
1983
+
case AFE_DL6_RCH_MON:
1984
+
case AFE_DL6_LCH_MON:
1985
+
case AFE_DL7_CUR_MSB:
1986
+
case AFE_DL7_CUR:
1987
+
case AFE_DL7_RCH_MON:
1988
+
case AFE_DL7_LCH_MON:
1989
+
case AFE_DL8_CUR_MSB:
1990
+
case AFE_DL8_CUR:
1991
+
case AFE_DL8_RCH_MON:
1992
+
case AFE_DL8_LCH_MON:
1993
+
case AFE_DL_24CH_CUR_MSB:
1994
+
case AFE_DL_24CH_CUR:
1995
+
case AFE_DL23_CUR_MSB:
1996
+
case AFE_DL23_CUR:
1997
+
case AFE_DL23_RCH_MON:
1998
+
case AFE_DL23_LCH_MON:
1999
+
case AFE_DL24_CUR_MSB:
2000
+
case AFE_DL24_CUR:
2001
+
case AFE_DL24_RCH_MON:
2002
+
case AFE_DL24_LCH_MON:
2003
+
case AFE_DL25_CUR_MSB:
2004
+
case AFE_DL25_CUR:
2005
+
case AFE_DL25_RCH_MON:
2006
+
case AFE_DL25_LCH_MON:
2007
+
case AFE_VUL0_CUR_MSB:
2008
+
case AFE_VUL0_CUR:
2009
+
case AFE_VUL1_CUR_MSB:
2010
+
case AFE_VUL1_CUR:
2011
+
case AFE_VUL2_CUR_MSB:
2012
+
case AFE_VUL2_CUR:
2013
+
case AFE_VUL3_CUR_MSB:
2014
+
case AFE_VUL3_CUR:
2015
+
case AFE_VUL4_CUR_MSB:
2016
+
case AFE_VUL4_CUR:
2017
+
case AFE_VUL5_CUR_MSB:
2018
+
case AFE_VUL5_CUR:
2019
+
case AFE_VUL6_CUR_MSB:
2020
+
case AFE_VUL6_CUR:
2021
+
case AFE_VUL7_CUR_MSB:
2022
+
case AFE_VUL7_CUR:
2023
+
case AFE_VUL8_CUR_MSB:
2024
+
case AFE_VUL8_CUR:
2025
+
case AFE_VUL9_CUR_MSB:
2026
+
case AFE_VUL9_CUR:
2027
+
case AFE_VUL10_CUR_MSB:
2028
+
case AFE_VUL10_CUR:
2029
+
case AFE_VUL24_CUR_MSB:
2030
+
case AFE_VUL24_CUR:
2031
+
case AFE_VUL25_CUR_MSB:
2032
+
case AFE_VUL25_CUR:
2033
+
case AFE_VUL_CM0_CUR_MSB:
2034
+
case AFE_VUL_CM0_CUR:
2035
+
case AFE_VUL_CM1_CUR_MSB:
2036
+
case AFE_VUL_CM1_CUR:
2037
+
case AFE_ETDM_IN0_CUR_MSB:
2038
+
case AFE_ETDM_IN0_CUR:
2039
+
case AFE_ETDM_IN1_CUR_MSB:
2040
+
case AFE_ETDM_IN1_CUR:
2041
+
case AFE_HDMI_OUT_CUR_MSB:
2042
+
case AFE_HDMI_OUT_CUR:
2043
+
case AFE_HDMI_OUT_END:
2044
+
case AFE_HDMI_OUT_MON0:
2045
+
case AFE_PROT_SIDEBAND0_MON:
2046
+
case AFE_PROT_SIDEBAND1_MON:
2047
+
case AFE_PROT_SIDEBAND2_MON:
2048
+
case AFE_PROT_SIDEBAND3_MON:
2049
+
case AFE_DOMAIN_SIDEBAND0_MON:
2050
+
case AFE_DOMAIN_SIDEBAND1_MON:
2051
+
case AFE_DOMAIN_SIDEBAND2_MON:
2052
+
case AFE_DOMAIN_SIDEBAND3_MON:
2053
+
case AFE_DOMAIN_SIDEBAND4_MON:
2054
+
case AFE_DOMAIN_SIDEBAND5_MON:
2055
+
case AFE_DOMAIN_SIDEBAND6_MON:
2056
+
case AFE_DOMAIN_SIDEBAND7_MON:
2057
+
case AFE_DOMAIN_SIDEBAND8_MON:
2058
+
case AFE_DOMAIN_SIDEBAND9_MON:
2059
+
case AFE_PCM0_INTF_CON1_MASK_MON:
2060
+
case AFE_CONNSYS_I2S_CON_MASK_MON:
2061
+
case AFE_MTKAIF0_CFG0_MASK_MON:
2062
+
case AFE_MTKAIF1_CFG0_MASK_MON:
2063
+
case AFE_ADDA_UL0_SRC_CON0_MASK_MON:
2064
+
case AFE_ASRC_NEW_CON0:
2065
+
case AFE_ASRC_NEW_CON6:
2066
+
case AFE_ASRC_NEW_CON8:
2067
+
case AFE_ASRC_NEW_CON9:
2068
+
case AFE_ASRC_NEW_CON12:
2069
+
case AFE_ASRC_NEW_IP_VERSION:
2070
+
case AFE_GASRC0_NEW_CON0:
2071
+
case AFE_GASRC0_NEW_CON6:
2072
+
case AFE_GASRC0_NEW_CON8:
2073
+
case AFE_GASRC0_NEW_CON9:
2074
+
case AFE_GASRC0_NEW_CON10:
2075
+
case AFE_GASRC0_NEW_CON11:
2076
+
case AFE_GASRC0_NEW_CON12:
2077
+
case AFE_GASRC0_NEW_IP_VERSION:
2078
+
case AFE_GASRC1_NEW_CON0:
2079
+
case AFE_GASRC1_NEW_CON6:
2080
+
case AFE_GASRC1_NEW_CON8:
2081
+
case AFE_GASRC1_NEW_CON9:
2082
+
case AFE_GASRC1_NEW_CON12:
2083
+
case AFE_GASRC1_NEW_IP_VERSION:
2084
+
case AFE_GASRC2_NEW_CON0:
2085
+
case AFE_GASRC2_NEW_CON6:
2086
+
case AFE_GASRC2_NEW_CON8:
2087
+
case AFE_GASRC2_NEW_CON9:
2088
+
case AFE_GASRC2_NEW_CON12:
2089
+
case AFE_GASRC2_NEW_IP_VERSION:
2090
+
case AFE_GAIN0_CUR_L:
2091
+
case AFE_GAIN0_CUR_R:
2092
+
case AFE_GAIN1_CUR_L:
2093
+
case AFE_GAIN1_CUR_R:
2094
+
case AFE_GAIN2_CUR_L:
2095
+
case AFE_GAIN2_CUR_R:
2096
+
case AFE_GAIN3_CUR_L:
2097
+
case AFE_GAIN3_CUR_R:
2098
+
case AFE_IRQ_MCU_EN:
2099
+
case AFE_CUSTOM_IRQ_MCU_EN:
2100
+
case AFE_IRQ_MCU_DSP_EN:
2101
+
case AFE_IRQ_MCU_DSP2_EN:
2102
+
case AFE_DL5_CON0:
2103
+
case AFE_DL6_CON0:
2104
+
case AFE_DL23_CON0:
2105
+
case AFE_DL_24CH_CON0:
2106
+
case AFE_VUL1_CON0:
2107
+
case AFE_VUL3_CON0:
2108
+
case AFE_VUL4_CON0:
2109
+
case AFE_VUL5_CON0:
2110
+
case AFE_VUL9_CON0:
2111
+
case AFE_VUL25_CON0:
2112
+
case AFE_IRQ0_MCU_CFG0:
2113
+
case AFE_IRQ1_MCU_CFG0:
2114
+
case AFE_IRQ2_MCU_CFG0:
2115
+
case AFE_IRQ3_MCU_CFG0:
2116
+
case AFE_IRQ4_MCU_CFG0:
2117
+
case AFE_IRQ5_MCU_CFG0:
2118
+
case AFE_IRQ6_MCU_CFG0:
2119
+
case AFE_IRQ7_MCU_CFG0:
2120
+
case AFE_IRQ8_MCU_CFG0:
2121
+
case AFE_IRQ9_MCU_CFG0:
2122
+
case AFE_IRQ10_MCU_CFG0:
2123
+
case AFE_IRQ11_MCU_CFG0:
2124
+
case AFE_IRQ12_MCU_CFG0:
2125
+
case AFE_IRQ13_MCU_CFG0:
2126
+
case AFE_IRQ14_MCU_CFG0:
2127
+
case AFE_IRQ15_MCU_CFG0:
2128
+
case AFE_IRQ16_MCU_CFG0:
2129
+
case AFE_IRQ17_MCU_CFG0:
2130
+
case AFE_IRQ18_MCU_CFG0:
2131
+
case AFE_IRQ19_MCU_CFG0:
2132
+
case AFE_IRQ20_MCU_CFG0:
2133
+
case AFE_IRQ21_MCU_CFG0:
2134
+
case AFE_IRQ22_MCU_CFG0:
2135
+
case AFE_IRQ23_MCU_CFG0:
2136
+
case AFE_IRQ24_MCU_CFG0:
2137
+
case AFE_IRQ25_MCU_CFG0:
2138
+
case AFE_IRQ26_MCU_CFG0:
2139
+
case AFE_CUSTOM_IRQ0_MCU_CFG0:
2140
+
case AFE_IRQ0_MCU_CFG1:
2141
+
case AFE_IRQ1_MCU_CFG1:
2142
+
case AFE_IRQ2_MCU_CFG1:
2143
+
case AFE_IRQ3_MCU_CFG1:
2144
+
case AFE_IRQ4_MCU_CFG1:
2145
+
case AFE_IRQ5_MCU_CFG1:
2146
+
case AFE_IRQ6_MCU_CFG1:
2147
+
case AFE_IRQ7_MCU_CFG1:
2148
+
case AFE_IRQ8_MCU_CFG1:
2149
+
case AFE_IRQ9_MCU_CFG1:
2150
+
case AFE_IRQ10_MCU_CFG1:
2151
+
case AFE_IRQ11_MCU_CFG1:
2152
+
case AFE_IRQ12_MCU_CFG1:
2153
+
case AFE_IRQ13_MCU_CFG1:
2154
+
case AFE_IRQ14_MCU_CFG1:
2155
+
case AFE_IRQ15_MCU_CFG1:
2156
+
case AFE_IRQ16_MCU_CFG1:
2157
+
case AFE_IRQ17_MCU_CFG1:
2158
+
case AFE_IRQ18_MCU_CFG1:
2159
+
case AFE_IRQ19_MCU_CFG1:
2160
+
case AFE_IRQ20_MCU_CFG1:
2161
+
case AFE_IRQ21_MCU_CFG1:
2162
+
case AFE_IRQ22_MCU_CFG1:
2163
+
case AFE_IRQ23_MCU_CFG1:
2164
+
case AFE_IRQ24_MCU_CFG1:
2165
+
case AFE_IRQ25_MCU_CFG1:
2166
+
case AFE_IRQ26_MCU_CFG1:
2167
+
case AFE_CUSTOM_IRQ0_MCU_CFG1:
2168
+
/* for vow using */
2169
+
case AFE_IRQ_MCU_SCP_EN:
2170
+
case AFE_VUL_CM0_BASE_MSB:
2171
+
case AFE_VUL_CM0_BASE:
2172
+
case AFE_VUL_CM0_END_MSB:
2173
+
case AFE_VUL_CM0_END:
2174
+
case AFE_VUL_CM0_CON0:
2175
+
return true;
2176
+
default:
2177
+
return false;
2178
+
};
2179
+
}
2180
+
2181
+
static const struct regmap_config mt8189_afe_regmap_config = {
2182
+
.reg_bits = 32,
2183
+
.reg_stride = 4,
2184
+
.val_bits = 32,
2185
+
2186
+
.volatile_reg = mt8189_is_volatile_reg,
2187
+
2188
+
.max_register = AFE_MAX_REGISTER,
2189
+
.num_reg_defaults_raw = AFE_MAX_REGISTER,
2190
+
2191
+
.cache_type = REGCACHE_FLAT,
2192
+
};
2193
+
2194
+
static irqreturn_t mt8189_afe_irq_handler(int irq_id, void *dev)
2195
+
{
2196
+
struct mtk_base_afe *afe = dev;
2197
+
struct mtk_base_afe_irq *irq;
2198
+
u32 status;
2199
+
u32 status_mcu;
2200
+
u32 mcu_en;
2201
+
u32 cus_status;
2202
+
u32 cus_status_mcu;
2203
+
u32 cus_mcu_en;
2204
+
u32 tmp_reg;
2205
+
int ret, cus_ret;
2206
+
int i;
2207
+
struct timespec64 ts64;
2208
+
u64 t1, t2;
2209
+
/* one interrupt period = 5ms */
2210
+
const u64 timeout_limit = 5000000;
2211
+
2212
+
/* get irq that is sent to MCU */
2213
+
regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en);
2214
+
regmap_read(afe->regmap, AFE_CUSTOM_IRQ_MCU_EN, &cus_mcu_en);
2215
+
2216
+
ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status);
2217
+
cus_ret = regmap_read(afe->regmap, AFE_CUSTOM_IRQ_MCU_STATUS, &cus_status);
2218
+
/* only care IRQ which is sent to MCU */
2219
+
status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS;
2220
+
cus_status_mcu = cus_status & cus_mcu_en & AFE_IRQ_STATUS_BITS;
2221
+
if ((ret || status_mcu == 0) && (cus_ret || cus_status_mcu == 0)) {
2222
+
dev_err(afe->dev, "%s(), irq status err, ret %d, 0x%x:0x%x:0x%x:0x%x\n",
2223
+
__func__, ret, status, mcu_en, cus_status_mcu, cus_mcu_en);
2224
+
return IRQ_NONE;
2225
+
}
2226
+
2227
+
ktime_get_ts64(&ts64);
2228
+
t1 = ktime_get_ns();
2229
+
2230
+
for (i = 0; i < MT8189_MEMIF_NUM; i++) {
2231
+
struct mtk_base_afe_memif *memif = &afe->memif[i];
2232
+
2233
+
if (!memif->substream)
2234
+
continue;
2235
+
2236
+
if (memif->irq_usage < 0)
2237
+
continue;
2238
+
irq = &afe->irqs[memif->irq_usage];
2239
+
2240
+
if (i == MT8189_MEMIF_HDMI) {
2241
+
if (cus_status_mcu & BIT(irq->irq_data->id))
2242
+
snd_pcm_period_elapsed(memif->substream);
2243
+
} else if (status_mcu & BIT(irq->irq_data->id)) {
2244
+
snd_pcm_period_elapsed(memif->substream);
2245
+
}
2246
+
}
2247
+
2248
+
ktime_get_ts64(&ts64);
2249
+
t2 = ktime_get_ns();
2250
+
t2 = t2 - t1; /* in ns (10^9) */
2251
+
2252
+
if (t2 > timeout_limit)
2253
+
dev_warn(afe->dev, "IRQ handler exceeded time limit by %llu ns\n",
2254
+
t2 - timeout_limit);
2255
+
2256
+
/* clear irq */
2257
+
for (i = 0; i < MT8189_IRQ_NUM; ++i) {
2258
+
if (((cus_status_mcu & BIT(irq_data[i].id)) && i == MT8189_IRQ_31) ||
2259
+
((status_mcu & BIT(irq_data[i].id)) && i != MT8189_IRQ_31)) {
2260
+
regmap_read(afe->regmap, irq_data[i].irq_clr_reg, &tmp_reg);
2261
+
regmap_update_bits(afe->regmap, irq_data[i].irq_clr_reg,
2262
+
AFE_IRQ_CLR_CFG_MASK_SFT |
2263
+
AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT,
2264
+
tmp_reg ^ (AFE_IRQ_CLR_CFG_MASK_SFT |
2265
+
AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT));
2266
+
}
2267
+
}
2268
+
2269
+
return IRQ_HANDLED;
2270
+
}
2271
+
2272
+
static int mt8189_afe_runtime_suspend(struct device *dev)
2273
+
{
2274
+
struct mtk_base_afe *afe = dev_get_drvdata(dev);
2275
+
unsigned int value;
2276
+
unsigned int tmp_reg;
2277
+
int ret, i;
2278
+
2279
+
if (!afe->regmap) {
2280
+
dev_warn(afe->dev, "%s() skip regmap\n", __func__);
2281
+
goto skip_regmap;
2282
+
}
2283
+
2284
+
/* disable AFE */
2285
+
mt8189_afe_disable_main_clock(afe);
2286
+
2287
+
ret = regmap_read_poll_timeout(afe->regmap,
2288
+
AUDIO_ENGEN_CON0_MON,
2289
+
value,
2290
+
(value & AUDIO_ENGEN_MON_SFT) == 0,
2291
+
20,
2292
+
1 * 1000 * 1000);
2293
+
dev_dbg(afe->dev, "%s() read_poll ret %d\n", __func__, ret);
2294
+
if (ret)
2295
+
dev_warn(afe->dev, "%s(), ret %d\n", __func__, ret);
2296
+
2297
+
/* make sure all irq status are cleared */
2298
+
for (i = 0; i < MT8189_IRQ_NUM; i++) {
2299
+
regmap_read(afe->regmap, irq_data[i].irq_clr_reg, &tmp_reg);
2300
+
regmap_update_bits(afe->regmap, irq_data[i].irq_clr_reg,
2301
+
AFE_IRQ_CLR_CFG_MASK_SFT |
2302
+
AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT,
2303
+
tmp_reg ^ (AFE_IRQ_CLR_CFG_MASK_SFT |
2304
+
AFE_IRQ_MISS_FLAG_CLR_CFG_MASK_SFT));
2305
+
}
2306
+
2307
+
/* reset audio 26M request */
2308
+
regmap_update_bits(afe->regmap,
2309
+
AFE_SPM_CONTROL_REQ, 0x1, 0x0);
2310
+
2311
+
/* cache only */
2312
+
regcache_cache_only(afe->regmap, true);
2313
+
regcache_mark_dirty(afe->regmap);
2314
+
2315
+
skip_regmap:
2316
+
mt8189_afe_disable_reg_rw_clk(afe);
2317
+
return 0;
2318
+
}
2319
+
2320
+
static int mt8189_afe_runtime_resume(struct device *dev)
2321
+
{
2322
+
struct mtk_base_afe *afe = dev_get_drvdata(dev);
2323
+
int ret;
2324
+
2325
+
ret = mt8189_afe_enable_reg_rw_clk(afe);
2326
+
if (ret)
2327
+
return ret;
2328
+
2329
+
if (!afe->regmap) {
2330
+
dev_warn(afe->dev, "skip regmap\n");
2331
+
return 0;
2332
+
}
2333
+
2334
+
regcache_cache_only(afe->regmap, false);
2335
+
regcache_sync(afe->regmap);
2336
+
2337
+
/* set audio 26M request */
2338
+
regmap_update_bits(afe->regmap, AFE_SPM_CONTROL_REQ, 0x1, 0x1);
2339
+
regmap_update_bits(afe->regmap, AFE_CBIP_CFG0, 0x1, 0x1);
2340
+
2341
+
/* force cpu use 8_24 format when writing 32bit data */
2342
+
regmap_update_bits(afe->regmap, AFE_MEMIF_CON0,
2343
+
CPU_HD_ALIGN_MASK_SFT, 0 << CPU_HD_ALIGN_SFT);
2344
+
2345
+
/* enable AFE */
2346
+
mt8189_afe_enable_main_clock(afe);
2347
+
2348
+
return 0;
2349
+
}
2350
+
2351
+
static int mt8189_afe_component_probe(struct snd_soc_component *component)
2352
+
{
2353
+
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
2354
+
2355
+
if (component) {
2356
+
/* enable clock for regcache get default value from hw */
2357
+
pm_runtime_get_sync(afe->dev);
2358
+
mtk_afe_add_sub_dai_control(component);
2359
+
pm_runtime_put_sync(afe->dev);
2360
+
}
2361
+
2362
+
return 0;
2363
+
}
2364
+
2365
+
static int mt8189_afe_pcm_open(struct snd_soc_component *component,
2366
+
struct snd_pcm_substream *substream)
2367
+
{
2368
+
/* set the wait_for_avail to 2 sec*/
2369
+
substream->wait_time = msecs_to_jiffies(2 * 1000);
2370
+
2371
+
return 0;
2372
+
}
2373
+
2374
+
static void mt8189_afe_pcm_free(struct snd_soc_component *component,
2375
+
struct snd_pcm *pcm)
2376
+
{
2377
+
snd_pcm_lib_preallocate_free_for_all(pcm);
2378
+
}
2379
+
2380
+
static const struct snd_soc_component_driver mt8189_afe_component = {
2381
+
.name = AFE_PCM_NAME,
2382
+
.probe = mt8189_afe_component_probe,
2383
+
.pcm_construct = mtk_afe_pcm_new,
2384
+
.pcm_destruct = mt8189_afe_pcm_free,
2385
+
.open = mt8189_afe_pcm_open,
2386
+
.pointer = mtk_afe_pcm_pointer,
2387
+
};
2388
+
2389
+
static int mt8189_dai_memif_register(struct mtk_base_afe *afe)
2390
+
{
2391
+
struct mtk_base_afe_dai *dai;
2392
+
2393
+
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
2394
+
if (!dai)
2395
+
return -ENOMEM;
2396
+
2397
+
list_add(&dai->list, &afe->sub_dais);
2398
+
2399
+
dai->dai_drivers = mt8189_memif_dai_driver;
2400
+
dai->num_dai_drivers = ARRAY_SIZE(mt8189_memif_dai_driver);
2401
+
dai->dapm_widgets = mt8189_memif_widgets;
2402
+
dai->num_dapm_widgets = ARRAY_SIZE(mt8189_memif_widgets);
2403
+
dai->dapm_routes = mt8189_memif_routes;
2404
+
dai->num_dapm_routes = ARRAY_SIZE(mt8189_memif_routes);
2405
+
2406
+
return 0;
2407
+
}
2408
+
2409
+
typedef int (*dai_register_cb)(struct mtk_base_afe *);
2410
+
static const dai_register_cb dai_register_cbs[] = {
2411
+
mt8189_dai_adda_register,
2412
+
mt8189_dai_i2s_register,
2413
+
mt8189_dai_pcm_register,
2414
+
mt8189_dai_tdm_register,
2415
+
mt8189_dai_memif_register,
2416
+
};
2417
+
2418
+
static const struct reg_sequence mt8189_cg_patch[] = {
2419
+
{ AUDIO_TOP_CON4, 0x361c },
2420
+
};
2421
+
2422
+
static int mt8189_afe_pcm_dev_probe(struct platform_device *pdev)
2423
+
{
2424
+
int ret, i;
2425
+
unsigned int tmp_reg;
2426
+
int irq_id;
2427
+
struct mtk_base_afe *afe;
2428
+
struct mt8189_afe_private *afe_priv;
2429
+
struct device *dev = &pdev->dev;
2430
+
2431
+
ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(34));
2432
+
if (ret)
2433
+
return ret;
2434
+
2435
+
ret = of_reserved_mem_device_init(dev);
2436
+
if (ret)
2437
+
dev_warn(dev, "failed to assign memory region: %d\n", ret);
2438
+
2439
+
afe = devm_kzalloc(dev, sizeof(*afe), GFP_KERNEL);
2440
+
if (!afe)
2441
+
return -ENOMEM;
2442
+
2443
+
platform_set_drvdata(pdev, afe);
2444
+
2445
+
afe->platform_priv = devm_kzalloc(dev, sizeof(*afe_priv),
2446
+
GFP_KERNEL);
2447
+
if (!afe->platform_priv)
2448
+
return -ENOMEM;
2449
+
2450
+
afe_priv = afe->platform_priv;
2451
+
afe->dev = dev;
2452
+
2453
+
afe->base_addr = devm_platform_ioremap_resource(pdev, 0);
2454
+
if (IS_ERR(afe->base_addr))
2455
+
return dev_err_probe(dev, PTR_ERR(afe->base_addr),
2456
+
"AFE base_addr not found\n");
2457
+
2458
+
/* init audio related clock */
2459
+
ret = mt8189_init_clock(afe);
2460
+
if (ret)
2461
+
return dev_err_probe(dev, ret, "init clock error.\n");
2462
+
2463
+
/* init memif */
2464
+
/* IPM2.0 no need banding */
2465
+
afe->memif_32bit_supported = 1;
2466
+
afe->memif_size = MT8189_MEMIF_NUM;
2467
+
afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
2468
+
GFP_KERNEL);
2469
+
2470
+
if (!afe->memif)
2471
+
return -ENOMEM;
2472
+
2473
+
for (i = 0; i < afe->memif_size; i++) {
2474
+
afe->memif[i].data = &memif_data[i];
2475
+
afe->memif[i].irq_usage = memif_irq_usage[i];
2476
+
afe->memif[i].const_irq = 1;
2477
+
}
2478
+
2479
+
mutex_init(&afe->irq_alloc_lock);
2480
+
2481
+
/* init irq */
2482
+
afe->irqs_size = MT8189_IRQ_NUM;
2483
+
afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
2484
+
GFP_KERNEL);
2485
+
2486
+
if (!afe->irqs)
2487
+
return -ENOMEM;
2488
+
2489
+
for (i = 0; i < afe->irqs_size; i++)
2490
+
afe->irqs[i].irq_data = &irq_data[i];
2491
+
2492
+
/* request irq */
2493
+
irq_id = platform_get_irq(pdev, 0);
2494
+
if (irq_id < 0)
2495
+
return dev_err_probe(dev, irq_id, "no irq found");
2496
+
2497
+
ret = devm_request_irq(dev, irq_id, mt8189_afe_irq_handler,
2498
+
IRQF_TRIGGER_NONE,
2499
+
"Afe_ISR_Handle", afe);
2500
+
if (ret)
2501
+
return dev_err_probe(dev, ret, "could not request_irq for Afe_ISR_Handle\n");
2502
+
2503
+
/* init sub_dais */
2504
+
INIT_LIST_HEAD(&afe->sub_dais);
2505
+
2506
+
for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
2507
+
ret = dai_register_cbs[i](afe);
2508
+
if (ret)
2509
+
return dev_err_probe(dev, ret, "dai register i %d fail\n", i);
2510
+
}
2511
+
2512
+
/* init dai_driver and component_driver */
2513
+
ret = mtk_afe_combine_sub_dai(afe);
2514
+
if (ret)
2515
+
return dev_err_probe(dev, ret, "mtk_afe_combine_sub_dai fail\n");
2516
+
2517
+
/* others */
2518
+
afe->mtk_afe_hardware = &mt8189_afe_hardware;
2519
+
afe->memif_fs = mt8189_memif_fs;
2520
+
afe->irq_fs = mt8189_irq_fs;
2521
+
afe->get_dai_fs = mt8189_get_dai_fs;
2522
+
afe->get_memif_pbuf_size = mt8189_get_memif_pbuf_size;
2523
+
2524
+
afe->runtime_resume = mt8189_afe_runtime_resume;
2525
+
afe->runtime_suspend = mt8189_afe_runtime_suspend;
2526
+
2527
+
ret = devm_pm_runtime_enable(dev);
2528
+
if (ret)
2529
+
return ret;
2530
+
2531
+
/*
2532
+
* Audio device is part of genpd. Registering it as a syscore device
2533
+
* ensure the proper power-on sequence of the AFE device.
2534
+
*/
2535
+
dev_pm_syscore_device(dev, true);
2536
+
2537
+
/* enable clock for regcache get default value from hw */
2538
+
pm_runtime_get_sync(dev);
2539
+
2540
+
afe->regmap = devm_regmap_init_mmio(dev, afe->base_addr,
2541
+
&mt8189_afe_regmap_config);
2542
+
if (IS_ERR(afe->regmap))
2543
+
return PTR_ERR(afe->regmap);
2544
+
2545
+
ret = regmap_register_patch(afe->regmap, mt8189_cg_patch,
2546
+
ARRAY_SIZE(mt8189_cg_patch));
2547
+
if (ret < 0) {
2548
+
dev_err(dev, "Failed to apply cg patch\n");
2549
+
goto err_pm_disable;
2550
+
}
2551
+
2552
+
regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &tmp_reg);
2553
+
regmap_write(afe->regmap, AFE_IRQ_MCU_EN, 0xffffffff);
2554
+
regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &tmp_reg);
2555
+
2556
+
pm_runtime_put_sync(dev);
2557
+
2558
+
regcache_cache_only(afe->regmap, true);
2559
+
regcache_mark_dirty(afe->regmap);
2560
+
2561
+
/* register component */
2562
+
ret = devm_snd_soc_register_component(dev,
2563
+
&mt8189_afe_component,
2564
+
afe->dai_drivers,
2565
+
afe->num_dai_drivers);
2566
+
if (ret) {
2567
+
dev_err(dev, "afe component err: %d\n", ret);
2568
+
goto err_pm_disable;
2569
+
}
2570
+
2571
+
return 0;
2572
+
2573
+
err_pm_disable:
2574
+
pm_runtime_put_sync(dev);
2575
+
return ret;
2576
+
}
2577
+
2578
+
static void mt8189_afe_pcm_dev_remove(struct platform_device *pdev)
2579
+
{
2580
+
struct mtk_base_afe *afe = platform_get_drvdata(pdev);
2581
+
struct device *dev = &pdev->dev;
2582
+
2583
+
pm_runtime_put_sync(dev);
2584
+
if (!pm_runtime_status_suspended(dev))
2585
+
mt8189_afe_runtime_suspend(dev);
2586
+
2587
+
mt8189_afe_disable_main_clock(afe);
2588
+
/* disable afe clock */
2589
+
mt8189_afe_disable_reg_rw_clk(afe);
2590
+
of_reserved_mem_device_release(dev);
2591
+
}
2592
+
2593
+
static const struct of_device_id mt8189_afe_pcm_dt_match[] = {
2594
+
{ .compatible = "mediatek,mt8189-afe-pcm", },
2595
+
{},
2596
+
};
2597
+
MODULE_DEVICE_TABLE(of, mt8189_afe_pcm_dt_match);
2598
+
2599
+
static const struct dev_pm_ops mt8189_afe_pm_ops = {
2600
+
SET_RUNTIME_PM_OPS(mt8189_afe_runtime_suspend,
2601
+
mt8189_afe_runtime_resume, NULL)
2602
+
};
2603
+
2604
+
static struct platform_driver mt8189_afe_pcm_driver = {
2605
+
.driver = {
2606
+
.name = "mt8189-afe-pcm",
2607
+
.of_match_table = mt8189_afe_pcm_dt_match,
2608
+
.pm = &mt8189_afe_pm_ops,
2609
+
},
2610
+
.probe = mt8189_afe_pcm_dev_probe,
2611
+
.remove = mt8189_afe_pcm_dev_remove,
2612
+
};
2613
+
module_platform_driver(mt8189_afe_pcm_driver);
2614
+
2615
+
MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 8189");
2616
+
MODULE_AUTHOR("Darren Ye <darren.ye@mediatek.com>");
2617
+
MODULE_LICENSE("GPL");