net/mlx5e: RX, Drop oversized packets in non-linear mode

Currently the driver has an inconsistent behaviour between modes when it
comes to oversized packets that are not dropped through the physical MTU
check in HW. This can happen for Multi Host configurations where each
port has a different MTU.

Current behavior:

1) Striding RQ in linear mode drops the packet in SW and counts it
with oversize_pkts_sw_drop.

2) Striding RQ in non-linear mode allows it like a normal packet.

3) Legacy RQ can't receive oversized packets by design:
the RX WQE uses MTU sized packet buffers.

This inconsistency is not a violation of the netdev policy [1]
but it is better to be consistent across modes.

This patch aligns (2) with (1) and (3). One exception is added for
LRO: don't drop the oversized packet if it is an LRO packet.

As now rq->hw_mtu always needs to be updated during the MTU change flow,
drop the reset avoidance optimization from mlx5e_change_mtu().

Extract the CQE LRO segments reading into a helper function as it
is used twice now.

[1] Documentation/networking/netdevices.rst#L205

Signed-off-by: Dragos Tatulea <dtatulea@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>
Link: https://patch.msgid.link/20260203072130.1710255-2-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

authored by

Dragos Tatulea and committed by

Jakub Kicinski 3 months ago 7ed7a576 14eb64db

+17 -24

3 changed files

expand all

drivers

net

ethernet

mellanox

mlx5

core

en_main.c

en_rx.c

include

linux

mlx5

device.h

+2 -23

drivers/net/ethernet/mellanox/mlx5/core/en_main.c

··· 4716 4716 struct mlx5e_priv *priv = netdev_priv(netdev); 4717 4717 struct mlx5e_params new_params; 4718 4718 struct mlx5e_params *params; 4719 - bool reset = true; 4720 4719 int err = 0; 4721 4720 4722 4721 mutex_lock(&priv->state_lock); ··· 4741 4742 goto out; 4742 4743 } 4743 4744 4744 - if (params->packet_merge.type == MLX5E_PACKET_MERGE_LRO) 4745 - reset = false; 4746 - 4747 - if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ && 4748 - params->packet_merge.type != MLX5E_PACKET_MERGE_SHAMPO) { 4749 - bool is_linear_old = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, params, NULL); 4750 - bool is_linear_new = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, 4751 - &new_params, NULL); 4752 - u8 sz_old = mlx5e_mpwqe_get_log_rq_size(priv->mdev, params, NULL); 4753 - u8 sz_new = mlx5e_mpwqe_get_log_rq_size(priv->mdev, &new_params, NULL); 4754 - 4755 - /* Always reset in linear mode - hw_mtu is used in data path. 4756 - * Check that the mode was non-linear and didn't change. 4757 - * If XSK is active, XSK RQs are linear. 4758 - * Reset if the RQ size changed, even if it's non-linear. 4759 - */ 4760 - if (!is_linear_old && !is_linear_new && !priv->xsk.refcnt && 4761 - sz_old == sz_new) 4762 - reset = false; 4763 - } 4764 - 4765 - err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, reset); 4745 + err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, 4746 + true); 4766 4747 4767 4748 out: 4768 4749 WRITE_ONCE(netdev->mtu, params->sw_mtu);

+10 -1

drivers/net/ethernet/mellanox/mlx5/core/en_rx.c

··· 1574 1574 struct mlx5e_rq *rq, 1575 1575 struct sk_buff *skb) 1576 1576 { 1577 - u8 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24; 1577 + u8 lro_num_seg = get_cqe_lro_num_seg(cqe); 1578 1578 struct mlx5e_rq_stats *stats = rq->stats; 1579 1579 struct net_device *netdev = rq->netdev; 1580 1580 ··· 2057 2057 u16 linear_data_len; 2058 2058 u16 linear_hr; 2059 2059 void *va; 2060 + 2061 + if (unlikely(cqe_bcnt > rq->hw_mtu)) { 2062 + u8 lro_num_seg = get_cqe_lro_num_seg(cqe); 2063 + 2064 + if (lro_num_seg <= 1) { 2065 + rq->stats->oversize_pkts_sw_drop++; 2066 + return NULL; 2067 + } 2068 + } 2060 2069 2061 2070 prog = rcu_dereference(rq->xdp_prog); 2062 2071

include/linux/mlx5/device.h

··· 962 962 return be32_to_cpu(cqe->sop_drop_qpn) & 0xFFF; 963 963 } 964 964 965 + static inline u8 get_cqe_lro_num_seg(struct mlx5_cqe64 *cqe) 966 + { 967 + return be32_to_cpu(cqe->srqn) >> 24; 968 + } 969 + 965 970 #define MLX5_MPWQE_LOG_NUM_STRIDES_EXT_BASE 3 966 971 #define MLX5_MPWQE_LOG_NUM_STRIDES_BASE 9 967 972 #define MLX5_MPWQE_LOG_NUM_STRIDES_MAX 16

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