Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2025-02-08' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie:
"Just regular drm fixes, amdgpu, xe and i915 mostly, but a few
scattered fixes. I think one of the i915 fixes fixes some build combos
that Guenter was seeing.
amdgpu:
- Add new tiling flag for DCC write compress disable
- Add BO metadata flag for DCC
- Fix potential out of bounds access in display
- Seamless boot fix
- CONFIG_FRAME_WARN fix
- PSR1 fix
xe:
- OA uAPI related fixes
- Fix SRIOV migration initialization
- Restore devcoredump to a sane state
i915:
- Fix the build error with clamp after WARN_ON on gcc 13.x+
- HDCP related fixes
- PMU fix zero delta busyness issue
- Fix page cleanup on DMA remap failure
- Drop 64bpp YUV formats from ICL+ SDR planes
- GuC log related fix
- DisplayPort related fixes
ivpu:
- Fix error handling
komeda:
- add return check
zynqmp:
- fix locking in DP code
ast:
- fix AST DP timeout
cec:
- fix broken CEC adapter check"
* tag 'drm-fixes-2025-02-08' of https://gitlab.freedesktop.org/drm/kernel: (29 commits)
drm/i915/dp: Fix potential infinite loop in 128b/132b SST
Revert "drm/amd/display: Use HW lock mgr for PSR1"
drm/amd/display: Respect user's CONFIG_FRAME_WARN more for dml files
accel/amdxdna: Add MODULE_FIRMWARE() declarations
drm/i915/dp: Iterate DSC BPP from high to low on all platforms
drm/xe: Fix and re-enable xe_print_blob_ascii85()
drm/xe/devcoredump: Move exec queue snapshot to Contexts section
drm/xe/oa: Set stream->pollin in xe_oa_buffer_check_unlocked
drm/xe/pf: Fix migration initialization
drm/xe/oa: Preserve oa_ctrl unused bits
drm/amd/display: Fix seamless boot sequence
drm/amd/display: Fix out-of-bound accesses
drm/amdgpu: add a BO metadata flag to disable write compression for Vulkan
drm/i915/backlight: Return immediately when scale() finds invalid parameters
drm/i915/dp: Return min bpc supported by source instead of 0
drm/i915/dp: fix the Adaptive sync Operation mode for SDP
drm/i915/guc: Debug print LRC state entries only if the context is pinned
drm/i915: Drop 64bpp YUV formats from ICL+ SDR planes
drm/i915: Fix page cleanup on DMA remap failure
drm/i915/pmu: Fix zero delta busyness issue
...
+250
-149
+5
drivers/accel/amdxdna/amdxdna_pci_drv.c
+5
drivers/accel/amdxdna/amdxdna_pci_drv.c
···
21
21
22
22
#define AMDXDNA_AUTOSUSPEND_DELAY 5000 /* milliseconds */
23
23
24
+
MODULE_FIRMWARE("amdnpu/1502_00/npu.sbin");
25
+
MODULE_FIRMWARE("amdnpu/17f0_10/npu.sbin");
26
+
MODULE_FIRMWARE("amdnpu/17f0_11/npu.sbin");
27
+
MODULE_FIRMWARE("amdnpu/17f0_20/npu.sbin");
28
+
24
29
/*
25
30
* Bind the driver base on (vendor_id, device_id) pair and later use the
26
31
* (device_id, rev_id) pair as a key to select the devices. The devices with
+6
-2
drivers/accel/ivpu/ivpu_drv.c
+6
-2
drivers/accel/ivpu/ivpu_drv.c
···
397
397
if (ivpu_fw_is_cold_boot(vdev)) {
398
398
ret = ivpu_pm_dct_init(vdev);
399
399
if (ret)
400
-
goto err_diagnose_failure;
400
+
goto err_disable_ipc;
401
401
402
402
ret = ivpu_hw_sched_init(vdev);
403
403
if (ret)
404
-
goto err_diagnose_failure;
404
+
goto err_disable_ipc;
405
405
}
406
406
407
407
return 0;
408
408
409
+
err_disable_ipc:
410
+
ivpu_ipc_disable(vdev);
411
+
ivpu_hw_irq_disable(vdev);
412
+
disable_irq(vdev->irq);
409
413
err_diagnose_failure:
410
414
ivpu_hw_diagnose_failure(vdev);
411
415
ivpu_mmu_evtq_dump(vdev);
+47
-37
drivers/accel/ivpu/ivpu_pm.c
+47
-37
drivers/accel/ivpu/ivpu_pm.c
···
115
115
return ret;
116
116
}
117
117
118
-
static void ivpu_pm_recovery_work(struct work_struct *work)
118
+
static void ivpu_pm_reset_begin(struct ivpu_device *vdev)
119
119
{
120
-
struct ivpu_pm_info *pm = container_of(work, struct ivpu_pm_info, recovery_work);
121
-
struct ivpu_device *vdev = pm->vdev;
122
-
char *evt[2] = {"IVPU_PM_EVENT=IVPU_RECOVER", NULL};
123
-
int ret;
124
-
125
-
ivpu_err(vdev, "Recovering the NPU (reset #%d)\n", atomic_read(&vdev->pm->reset_counter));
126
-
127
-
ret = pm_runtime_resume_and_get(vdev->drm.dev);
128
-
if (ret)
129
-
ivpu_err(vdev, "Failed to resume NPU: %d\n", ret);
130
-
131
-
ivpu_jsm_state_dump(vdev);
132
-
ivpu_dev_coredump(vdev);
120
+
pm_runtime_disable(vdev->drm.dev);
133
121
134
122
atomic_inc(&vdev->pm->reset_counter);
135
123
atomic_set(&vdev->pm->reset_pending, 1);
136
124
down_write(&vdev->pm->reset_lock);
125
+
}
137
126
138
-
ivpu_suspend(vdev);
127
+
static void ivpu_pm_reset_complete(struct ivpu_device *vdev)
128
+
{
129
+
int ret;
130
+
139
131
ivpu_pm_prepare_cold_boot(vdev);
140
132
ivpu_jobs_abort_all(vdev);
141
133
ivpu_ms_cleanup_all(vdev);
142
134
143
135
ret = ivpu_resume(vdev);
144
-
if (ret)
136
+
if (ret) {
145
137
ivpu_err(vdev, "Failed to resume NPU: %d\n", ret);
138
+
pm_runtime_set_suspended(vdev->drm.dev);
139
+
} else {
140
+
pm_runtime_set_active(vdev->drm.dev);
141
+
}
146
142
147
143
up_write(&vdev->pm->reset_lock);
148
144
atomic_set(&vdev->pm->reset_pending, 0);
149
145
150
-
kobject_uevent_env(&vdev->drm.dev->kobj, KOBJ_CHANGE, evt);
151
146
pm_runtime_mark_last_busy(vdev->drm.dev);
152
-
pm_runtime_put_autosuspend(vdev->drm.dev);
147
+
pm_runtime_enable(vdev->drm.dev);
148
+
}
149
+
150
+
static void ivpu_pm_recovery_work(struct work_struct *work)
151
+
{
152
+
struct ivpu_pm_info *pm = container_of(work, struct ivpu_pm_info, recovery_work);
153
+
struct ivpu_device *vdev = pm->vdev;
154
+
char *evt[2] = {"IVPU_PM_EVENT=IVPU_RECOVER", NULL};
155
+
156
+
ivpu_err(vdev, "Recovering the NPU (reset #%d)\n", atomic_read(&vdev->pm->reset_counter));
157
+
158
+
ivpu_pm_reset_begin(vdev);
159
+
160
+
if (!pm_runtime_status_suspended(vdev->drm.dev)) {
161
+
ivpu_jsm_state_dump(vdev);
162
+
ivpu_dev_coredump(vdev);
163
+
ivpu_suspend(vdev);
164
+
}
165
+
166
+
ivpu_pm_reset_complete(vdev);
167
+
168
+
kobject_uevent_env(&vdev->drm.dev->kobj, KOBJ_CHANGE, evt);
153
169
}
154
170
155
171
void ivpu_pm_trigger_recovery(struct ivpu_device *vdev, const char *reason)
···
325
309
int ret;
326
310
327
311
ret = pm_runtime_resume_and_get(vdev->drm.dev);
328
-
drm_WARN_ON(&vdev->drm, ret < 0);
312
+
if (ret < 0) {
313
+
ivpu_err(vdev, "Failed to resume NPU: %d\n", ret);
314
+
pm_runtime_set_suspended(vdev->drm.dev);
315
+
}
329
316
330
317
return ret;
331
318
}
···
344
325
struct ivpu_device *vdev = pci_get_drvdata(pdev);
345
326
346
327
ivpu_dbg(vdev, PM, "Pre-reset..\n");
347
-
atomic_inc(&vdev->pm->reset_counter);
348
-
atomic_set(&vdev->pm->reset_pending, 1);
349
328
350
-
pm_runtime_get_sync(vdev->drm.dev);
351
-
down_write(&vdev->pm->reset_lock);
352
-
ivpu_prepare_for_reset(vdev);
353
-
ivpu_hw_reset(vdev);
354
-
ivpu_pm_prepare_cold_boot(vdev);
355
-
ivpu_jobs_abort_all(vdev);
356
-
ivpu_ms_cleanup_all(vdev);
329
+
ivpu_pm_reset_begin(vdev);
330
+
331
+
if (!pm_runtime_status_suspended(vdev->drm.dev)) {
332
+
ivpu_prepare_for_reset(vdev);
333
+
ivpu_hw_reset(vdev);
334
+
}
357
335
358
336
ivpu_dbg(vdev, PM, "Pre-reset done.\n");
359
337
}
···
358
342
void ivpu_pm_reset_done_cb(struct pci_dev *pdev)
359
343
{
360
344
struct ivpu_device *vdev = pci_get_drvdata(pdev);
361
-
int ret;
362
345
363
346
ivpu_dbg(vdev, PM, "Post-reset..\n");
364
-
ret = ivpu_resume(vdev);
365
-
if (ret)
366
-
ivpu_err(vdev, "Failed to set RESUME state: %d\n", ret);
367
-
up_write(&vdev->pm->reset_lock);
368
-
atomic_set(&vdev->pm->reset_pending, 0);
369
-
ivpu_dbg(vdev, PM, "Post-reset done.\n");
370
347
371
-
pm_runtime_mark_last_busy(vdev->drm.dev);
372
-
pm_runtime_put_autosuspend(vdev->drm.dev);
348
+
ivpu_pm_reset_complete(vdev);
349
+
350
+
ivpu_dbg(vdev, PM, "Post-reset done.\n");
373
351
}
374
352
375
353
void ivpu_pm_init(struct ivpu_device *vdev)
+2
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+2
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
···
119
119
* - 3.57.0 - Compute tunneling on GFX10+
120
120
* - 3.58.0 - Add GFX12 DCC support
121
121
* - 3.59.0 - Cleared VRAM
122
+
* - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement)
122
123
*/
123
124
#define KMS_DRIVER_MAJOR 3
124
-
#define KMS_DRIVER_MINOR 59
125
+
#define KMS_DRIVER_MINOR 60
125
126
#define KMS_DRIVER_PATCHLEVEL 0
126
127
127
128
/*
+6
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+6
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
···
309
309
mutex_lock(&adev->mman.gtt_window_lock);
310
310
while (src_mm.remaining) {
311
311
uint64_t from, to, cur_size, tiling_flags;
312
-
uint32_t num_type, data_format, max_com;
312
+
uint32_t num_type, data_format, max_com, write_compress_disable;
313
313
struct dma_fence *next;
314
314
315
315
/* Never copy more than 256MiB at once to avoid a timeout */
···
340
340
max_com = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK);
341
341
num_type = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_NUMBER_TYPE);
342
342
data_format = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_DATA_FORMAT);
343
+
write_compress_disable =
344
+
AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_WRITE_COMPRESS_DISABLE);
343
345
copy_flags |= (AMDGPU_COPY_FLAGS_SET(MAX_COMPRESSED, max_com) |
344
346
AMDGPU_COPY_FLAGS_SET(NUMBER_TYPE, num_type) |
345
-
AMDGPU_COPY_FLAGS_SET(DATA_FORMAT, data_format));
347
+
AMDGPU_COPY_FLAGS_SET(DATA_FORMAT, data_format) |
348
+
AMDGPU_COPY_FLAGS_SET(WRITE_COMPRESS_DISABLE,
349
+
write_compress_disable));
346
350
}
347
351
348
352
r = amdgpu_copy_buffer(ring, from, to, cur_size, resv,
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
···
119
119
#define AMDGPU_COPY_FLAGS_NUMBER_TYPE_MASK 0x07
120
120
#define AMDGPU_COPY_FLAGS_DATA_FORMAT_SHIFT 8
121
121
#define AMDGPU_COPY_FLAGS_DATA_FORMAT_MASK 0x3f
122
+
#define AMDGPU_COPY_FLAGS_WRITE_COMPRESS_DISABLE_SHIFT 14
123
+
#define AMDGPU_COPY_FLAGS_WRITE_COMPRESS_DISABLE_MASK 0x1
122
124
123
125
#define AMDGPU_COPY_FLAGS_SET(field, value) \
124
126
(((__u32)(value) & AMDGPU_COPY_FLAGS_##field##_MASK) << AMDGPU_COPY_FLAGS_##field##_SHIFT)
+3
-2
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
+3
-2
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
···
1741
1741
uint32_t byte_count,
1742
1742
uint32_t copy_flags)
1743
1743
{
1744
-
uint32_t num_type, data_format, max_com;
1744
+
uint32_t num_type, data_format, max_com, write_cm;
1745
1745
1746
1746
max_com = AMDGPU_COPY_FLAGS_GET(copy_flags, MAX_COMPRESSED);
1747
1747
data_format = AMDGPU_COPY_FLAGS_GET(copy_flags, DATA_FORMAT);
1748
1748
num_type = AMDGPU_COPY_FLAGS_GET(copy_flags, NUMBER_TYPE);
1749
+
write_cm = AMDGPU_COPY_FLAGS_GET(copy_flags, WRITE_COMPRESS_DISABLE) ? 2 : 1;
1749
1750
1750
1751
ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
1751
1752
SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
···
1763
1762
if ((copy_flags & (AMDGPU_COPY_FLAGS_READ_DECOMPRESSED | AMDGPU_COPY_FLAGS_WRITE_COMPRESSED)))
1764
1763
ib->ptr[ib->length_dw++] = SDMA_DCC_DATA_FORMAT(data_format) | SDMA_DCC_NUM_TYPE(num_type) |
1765
1764
((copy_flags & AMDGPU_COPY_FLAGS_READ_DECOMPRESSED) ? SDMA_DCC_READ_CM(2) : 0) |
1766
-
((copy_flags & AMDGPU_COPY_FLAGS_WRITE_COMPRESSED) ? SDMA_DCC_WRITE_CM(1) : 0) |
1765
+
((copy_flags & AMDGPU_COPY_FLAGS_WRITE_COMPRESSED) ? SDMA_DCC_WRITE_CM(write_cm) : 0) |
1767
1766
SDMA_DCC_MAX_COM(max_com) | SDMA_DCC_MAX_UCOM(1);
1768
1767
else
1769
1768
ib->ptr[ib->length_dw++] = 0;
+1
-1
drivers/gpu/drm/amd/display/dc/core/dc.c
+1
-1
drivers/gpu/drm/amd/display/dc/core/dc.c
···
2133
2133
2134
2134
dc_enable_stereo(dc, context, dc_streams, context->stream_count);
2135
2135
2136
-
if (context->stream_count > get_seamless_boot_stream_count(context) ||
2136
+
if (get_seamless_boot_stream_count(context) == 0 ||
2137
2137
context->stream_count == 0) {
2138
2138
/* Must wait for no flips to be pending before doing optimize bw */
2139
2139
hwss_wait_for_no_pipes_pending(dc, context);
+1
-2
drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
+1
-2
drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
···
63
63
64
64
bool should_use_dmub_lock(struct dc_link *link)
65
65
{
66
-
if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 ||
67
-
link->psr_settings.psr_version == DC_PSR_VERSION_1)
66
+
if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
68
67
return true;
69
68
70
69
if (link->replay_settings.replay_feature_enabled)
+9
-5
drivers/gpu/drm/amd/display/dc/dml/Makefile
+9
-5
drivers/gpu/drm/amd/display/dc/dml/Makefile
···
29
29
dml_rcflags := $(CC_FLAGS_NO_FPU)
30
30
31
31
ifneq ($(CONFIG_FRAME_WARN),0)
32
-
ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y)
33
-
frame_warn_flag := -Wframe-larger-than=3072
34
-
else
35
-
frame_warn_flag := -Wframe-larger-than=2048
36
-
endif
32
+
ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y)
33
+
frame_warn_limit := 3072
34
+
else
35
+
frame_warn_limit := 2048
36
+
endif
37
+
38
+
ifeq ($(call test-lt, $(CONFIG_FRAME_WARN), $(frame_warn_limit)),y)
39
+
frame_warn_flag := -Wframe-larger-than=$(frame_warn_limit)
40
+
endif
37
41
endif
38
42
39
43
CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
+13
-9
drivers/gpu/drm/amd/display/dc/dml2/Makefile
+13
-9
drivers/gpu/drm/amd/display/dc/dml2/Makefile
···
28
28
dml2_rcflags := $(CC_FLAGS_NO_FPU)
29
29
30
30
ifneq ($(CONFIG_FRAME_WARN),0)
31
-
ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y)
32
-
ifeq ($(CONFIG_CC_IS_CLANG)$(CONFIG_COMPILE_TEST),yy)
33
-
frame_warn_flag := -Wframe-larger-than=4096
34
-
else
35
-
frame_warn_flag := -Wframe-larger-than=3072
36
-
endif
37
-
else
38
-
frame_warn_flag := -Wframe-larger-than=2048
39
-
endif
31
+
ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y)
32
+
ifeq ($(CONFIG_CC_IS_CLANG)$(CONFIG_COMPILE_TEST),yy)
33
+
frame_warn_limit := 4096
34
+
else
35
+
frame_warn_limit := 3072
36
+
endif
37
+
else
38
+
frame_warn_limit := 2048
39
+
endif
40
+
41
+
ifeq ($(call test-lt, $(CONFIG_FRAME_WARN), $(frame_warn_limit)),y)
42
+
frame_warn_flag := -Wframe-larger-than=$(frame_warn_limit)
43
+
endif
40
44
endif
41
45
42
46
subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2
+2
-2
drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
+2
-2
drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
···
1017
1017
if (disp_cfg_stream_location < 0)
1018
1018
disp_cfg_stream_location = dml_dispcfg->num_streams++;
1019
1019
1020
-
ASSERT(disp_cfg_stream_location >= 0 && disp_cfg_stream_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__);
1020
+
ASSERT(disp_cfg_stream_location >= 0 && disp_cfg_stream_location < __DML2_WRAPPER_MAX_STREAMS_PLANES__);
1021
1021
populate_dml21_timing_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].timing, context->streams[stream_index], dml_ctx);
1022
1022
adjust_dml21_hblank_timing_config_from_pipe_ctx(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].timing, &context->res_ctx.pipe_ctx[stream_index]);
1023
1023
populate_dml21_output_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].output, context->streams[stream_index], &context->res_ctx.pipe_ctx[stream_index]);
···
1042
1042
if (disp_cfg_plane_location < 0)
1043
1043
disp_cfg_plane_location = dml_dispcfg->num_planes++;
1044
1044
1045
-
ASSERT(disp_cfg_plane_location >= 0 && disp_cfg_plane_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__);
1045
+
ASSERT(disp_cfg_plane_location >= 0 && disp_cfg_plane_location < __DML2_WRAPPER_MAX_STREAMS_PLANES__);
1046
1046
1047
1047
populate_dml21_surface_config_from_plane_state(in_dc, &dml_dispcfg->plane_descriptors[disp_cfg_plane_location].surface, context->stream_status[stream_index].plane_states[plane_index]);
1048
1048
populate_dml21_plane_config_from_plane_state(dml_ctx, &dml_dispcfg->plane_descriptors[disp_cfg_plane_location], context->stream_status[stream_index].plane_states[plane_index], context, stream_index);
+3
-3
drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
+3
-3
drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
···
786
786
case SIGNAL_TYPE_DISPLAY_PORT_MST:
787
787
case SIGNAL_TYPE_DISPLAY_PORT:
788
788
out->OutputEncoder[location] = dml_dp;
789
-
if (dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location] != -1)
789
+
if (location < MAX_HPO_DP2_ENCODERS && dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location] != -1)
790
790
out->OutputEncoder[dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location]] = dml_dp2p0;
791
791
break;
792
792
case SIGNAL_TYPE_EDP:
···
1343
1343
if (disp_cfg_stream_location < 0)
1344
1344
disp_cfg_stream_location = dml_dispcfg->num_timings++;
1345
1345
1346
-
ASSERT(disp_cfg_stream_location >= 0 && disp_cfg_stream_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__);
1346
+
ASSERT(disp_cfg_stream_location >= 0 && disp_cfg_stream_location < __DML2_WRAPPER_MAX_STREAMS_PLANES__);
1347
1347
1348
1348
populate_dml_timing_cfg_from_stream_state(&dml_dispcfg->timing, disp_cfg_stream_location, context->streams[i]);
1349
1349
populate_dml_output_cfg_from_stream_state(&dml_dispcfg->output, disp_cfg_stream_location, context->streams[i], current_pipe_context, dml2);
···
1383
1383
if (disp_cfg_plane_location < 0)
1384
1384
disp_cfg_plane_location = dml_dispcfg->num_surfaces++;
1385
1385
1386
-
ASSERT(disp_cfg_plane_location >= 0 && disp_cfg_plane_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__);
1386
+
ASSERT(disp_cfg_plane_location >= 0 && disp_cfg_plane_location < __DML2_WRAPPER_MAX_STREAMS_PLANES__);
1387
1387
1388
1388
populate_dml_surface_cfg_from_plane_state(dml2->v20.dml_core_ctx.project, &dml_dispcfg->surface, disp_cfg_plane_location, context->stream_status[i].plane_states[j]);
1389
1389
populate_dml_plane_cfg_from_plane_state(
+2
-1
drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
+2
-1
drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
···
129
129
REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
130
130
DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF);
131
131
132
-
hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
132
+
if (safe_to_lower || hubbub->ctx->dc->debug.disable_stutter)
133
+
hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
133
134
134
135
return wm_pending;
135
136
}
+2
-1
drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
+2
-1
drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
···
750
750
REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
751
751
DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF);*/
752
752
753
-
hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
753
+
if (safe_to_lower || hubbub->ctx->dc->debug.disable_stutter)
754
+
hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
754
755
return wm_pending;
755
756
}
756
757
+2
-1
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
+2
-1
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
···
786
786
REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
787
787
DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF);*/
788
788
789
-
hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
789
+
if (safe_to_lower || hubbub->ctx->dc->debug.disable_stutter)
790
+
hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
790
791
791
792
hubbub32_force_usr_retraining_allow(hubbub, hubbub->ctx->dc->debug.force_usr_allow);
792
793
+2
-1
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
+2
-1
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
···
326
326
DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, 0xA);/*hw delta*/
327
327
REG_UPDATE(DCHUBBUB_ARB_HOSTVM_CNTL, DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, 0xF);
328
328
329
-
hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
329
+
if (safe_to_lower || hubbub->ctx->dc->debug.disable_stutter)
330
+
hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
330
331
331
332
hubbub32_force_usr_retraining_allow(hubbub, hubbub->ctx->dc->debug.force_usr_allow);
332
333
+2
drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
+2
drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
+2
drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c
+2
drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c
+2
-1
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+2
-1
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
···
236
236
}
237
237
238
238
hws->funcs.init_pipes(dc, dc->current_state);
239
-
if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
239
+
if (dc->res_pool->hubbub->funcs->allow_self_refresh_control &&
240
+
!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter)
240
241
dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
241
242
!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
242
243
}
+4
drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c
+4
drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c
···
160
160
formats = komeda_get_layer_fourcc_list(&mdev->fmt_tbl,
161
161
kwb_conn->wb_layer->layer_type,
162
162
&n_formats);
163
+
if (!formats) {
164
+
kfree(kwb_conn);
165
+
return -ENOMEM;
166
+
}
163
167
164
168
err = drm_writeback_connector_init(&kms->base, wb_conn,
165
169
&komeda_wb_connector_funcs,
+1
-1
drivers/gpu/drm/ast/ast_dp.c
+1
-1
drivers/gpu/drm/ast/ast_dp.c
+3
-11
drivers/gpu/drm/display/drm_dp_cec.c
+3
-11
drivers/gpu/drm/display/drm_dp_cec.c
···
311
311
if (!aux->transfer)
312
312
return;
313
313
314
-
#ifndef CONFIG_MEDIA_CEC_RC
315
-
/*
316
-
* CEC_CAP_RC is part of CEC_CAP_DEFAULTS, but it is stripped by
317
-
* cec_allocate_adapter() if CONFIG_MEDIA_CEC_RC is undefined.
318
-
*
319
-
* Do this here as well to ensure the tests against cec_caps are
320
-
* correct.
321
-
*/
322
-
cec_caps &= ~CEC_CAP_RC;
323
-
#endif
324
314
cancel_delayed_work_sync(&aux->cec.unregister_work);
325
315
326
316
mutex_lock(&aux->cec.lock);
···
327
337
num_las = CEC_MAX_LOG_ADDRS;
328
338
329
339
if (aux->cec.adap) {
330
-
if (aux->cec.adap->capabilities == cec_caps &&
340
+
/* Check if the adapter properties have changed */
341
+
if ((aux->cec.adap->capabilities & CEC_CAP_MONITOR_ALL) ==
342
+
(cec_caps & CEC_CAP_MONITOR_ALL) &&
331
343
aux->cec.adap->available_log_addrs == num_las) {
332
344
/* Unchanged, so just set the phys addr */
333
345
cec_s_phys_addr(aux->cec.adap, source_physical_address, false);
+3
-2
drivers/gpu/drm/i915/display/intel_backlight.c
+3
-2
drivers/gpu/drm/i915/display/intel_backlight.c
···
41
41
{
42
42
u64 target_val;
43
43
44
-
WARN_ON(source_min > source_max);
45
-
WARN_ON(target_min > target_max);
44
+
if (WARN_ON(source_min >= source_max) ||
45
+
WARN_ON(target_min > target_max))
46
+
return target_min;
46
47
47
48
/* defensive */
48
49
source_val = clamp(source_val, source_min, source_max);
+5
-7
drivers/gpu/drm/i915/display/intel_dp.c
+5
-7
drivers/gpu/drm/i915/display/intel_dp.c
···
1791
1791
if (DISPLAY_VER(display) == 11)
1792
1792
return 10;
1793
1793
1794
-
return 0;
1794
+
return intel_dp_dsc_min_src_input_bpc();
1795
1795
}
1796
1796
1797
1797
int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
···
2072
2072
/* Compressed BPP should be less than the Input DSC bpp */
2073
2073
dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
2074
2074
2075
-
for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) {
2076
-
if (valid_dsc_bpp[i] < dsc_min_bpp)
2075
+
for (i = ARRAY_SIZE(valid_dsc_bpp) - 1; i >= 0; i--) {
2076
+
if (valid_dsc_bpp[i] < dsc_min_bpp ||
2077
+
valid_dsc_bpp[i] > dsc_max_bpp)
2077
2078
continue;
2078
-
if (valid_dsc_bpp[i] > dsc_max_bpp)
2079
-
break;
2080
2079
2081
2080
ret = dsc_compute_link_config(intel_dp,
2082
2081
pipe_config,
···
2828
2829
2829
2830
crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
2830
2831
2831
-
/* Currently only DP_AS_SDP_AVT_FIXED_VTOTAL mode supported */
2832
2832
as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
2833
2833
as_sdp->length = 0x9;
2834
2834
as_sdp->duration_incr_ms = 0;
···
2838
2840
as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
2839
2841
as_sdp->target_rr_divider = true;
2840
2842
} else {
2841
-
as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
2843
+
as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
2842
2844
as_sdp->vtotal = adjusted_mode->vtotal;
2843
2845
as_sdp->target_rr = 0;
2844
2846
}
+4
drivers/gpu/drm/i915/display/intel_dp_mst.c
+4
drivers/gpu/drm/i915/display/intel_dp_mst.c
+14
-1
drivers/gpu/drm/i915/display/intel_hdcp.c
+14
-1
drivers/gpu/drm/i915/display/intel_hdcp.c
···
41
41
u32 rekey_bit = 0;
42
42
43
43
/* Here we assume HDMI is in TMDS mode of operation */
44
-
if (encoder->type != INTEL_OUTPUT_HDMI)
44
+
if (!intel_encoder_is_hdmi(encoder))
45
45
return;
46
46
47
47
if (DISPLAY_VER(display) >= 30) {
···
2188
2188
2189
2189
drm_dbg_kms(display->drm,
2190
2190
"HDCP2.2 Downstream topology change\n");
2191
+
2192
+
ret = hdcp2_authenticate_repeater_topology(connector);
2193
+
if (!ret) {
2194
+
intel_hdcp_update_value(connector,
2195
+
DRM_MODE_CONTENT_PROTECTION_ENABLED,
2196
+
true);
2197
+
goto out;
2198
+
}
2199
+
2200
+
drm_dbg_kms(display->drm,
2201
+
"[CONNECTOR:%d:%s] Repeater topology auth failed.(%d)\n",
2202
+
connector->base.base.id, connector->base.name,
2203
+
ret);
2191
2204
} else {
2192
2205
drm_dbg_kms(display->drm,
2193
2206
"[CONNECTOR:%d:%s] HDCP2.2 link failed, retrying auth\n",
-4
drivers/gpu/drm/i915/display/skl_universal_plane.c
-4
drivers/gpu/drm/i915/display/skl_universal_plane.c
···
106
106
DRM_FORMAT_Y216,
107
107
DRM_FORMAT_XYUV8888,
108
108
DRM_FORMAT_XVYU2101010,
109
-
DRM_FORMAT_XVYU12_16161616,
110
-
DRM_FORMAT_XVYU16161616,
111
109
};
112
110
113
111
static const u32 icl_sdr_uv_plane_formats[] = {
···
132
134
DRM_FORMAT_Y216,
133
135
DRM_FORMAT_XYUV8888,
134
136
DRM_FORMAT_XVYU2101010,
135
-
DRM_FORMAT_XVYU12_16161616,
136
-
DRM_FORMAT_XVYU16161616,
137
137
};
138
138
139
139
static const u32 icl_hdr_plane_formats[] = {
+1
-5
drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+1
-5
drivers/gpu/drm/i915/gem/i915_gem_shmem.c
···
209
209
struct address_space *mapping = obj->base.filp->f_mapping;
210
210
unsigned int max_segment = i915_sg_segment_size(i915->drm.dev);
211
211
struct sg_table *st;
212
-
struct sgt_iter sgt_iter;
213
-
struct page *page;
214
212
int ret;
215
213
216
214
/*
···
237
239
* for PAGE_SIZE chunks instead may be helpful.
238
240
*/
239
241
if (max_segment > PAGE_SIZE) {
240
-
for_each_sgt_page(page, sgt_iter, st)
241
-
put_page(page);
242
-
sg_free_table(st);
242
+
shmem_sg_free_table(st, mapping, false, false);
243
243
kfree(st);
244
244
245
245
max_segment = PAGE_SIZE;
+30
-6
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+30
-6
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
···
1469
1469
spin_unlock_irqrestore(&guc->timestamp.lock, flags);
1470
1470
}
1471
1471
1472
+
static void __update_guc_busyness_running_state(struct intel_guc *guc)
1473
+
{
1474
+
struct intel_gt *gt = guc_to_gt(guc);
1475
+
struct intel_engine_cs *engine;
1476
+
enum intel_engine_id id;
1477
+
unsigned long flags;
1478
+
1479
+
spin_lock_irqsave(&guc->timestamp.lock, flags);
1480
+
for_each_engine(engine, gt, id)
1481
+
engine->stats.guc.running = false;
1482
+
spin_unlock_irqrestore(&guc->timestamp.lock, flags);
1483
+
}
1484
+
1472
1485
static void __update_guc_busyness_stats(struct intel_guc *guc)
1473
1486
{
1474
1487
struct intel_gt *gt = guc_to_gt(guc);
···
1631
1618
1632
1619
if (!guc_submission_initialized(guc))
1633
1620
return;
1621
+
1622
+
/* Assume no engines are running and set running state to false */
1623
+
__update_guc_busyness_running_state(guc);
1634
1624
1635
1625
/*
1636
1626
* There is a race with suspend flow where the worker runs after suspend
···
5535
5519
{
5536
5520
drm_printf(p, "GuC lrc descriptor %u:\n", ce->guc_id.id);
5537
5521
drm_printf(p, "\tHW Context Desc: 0x%08x\n", ce->lrc.lrca);
5538
-
drm_printf(p, "\t\tLRC Head: Internal %u, Memory %u\n",
5539
-
ce->ring->head,
5540
-
ce->lrc_reg_state[CTX_RING_HEAD]);
5541
-
drm_printf(p, "\t\tLRC Tail: Internal %u, Memory %u\n",
5542
-
ce->ring->tail,
5543
-
ce->lrc_reg_state[CTX_RING_TAIL]);
5522
+
if (intel_context_pin_if_active(ce)) {
5523
+
drm_printf(p, "\t\tLRC Head: Internal %u, Memory %u\n",
5524
+
ce->ring->head,
5525
+
ce->lrc_reg_state[CTX_RING_HEAD]);
5526
+
drm_printf(p, "\t\tLRC Tail: Internal %u, Memory %u\n",
5527
+
ce->ring->tail,
5528
+
ce->lrc_reg_state[CTX_RING_TAIL]);
5529
+
intel_context_unpin(ce);
5530
+
} else {
5531
+
drm_printf(p, "\t\tLRC Head: Internal %u, Memory not pinned\n",
5532
+
ce->ring->head);
5533
+
drm_printf(p, "\t\tLRC Tail: Internal %u, Memory not pinned\n",
5534
+
ce->ring->tail);
5535
+
}
5544
5536
drm_printf(p, "\t\tContext Pin Count: %u\n",
5545
5537
atomic_read(&ce->pin_count));
5546
5538
drm_printf(p, "\t\tGuC ID Ref Count: %u\n",
+6
drivers/gpu/drm/xe/regs/xe_oa_regs.h
+6
drivers/gpu/drm/xe/regs/xe_oa_regs.h
···
51
51
/* Common to all OA units */
52
52
#define OA_OACONTROL_REPORT_BC_MASK REG_GENMASK(9, 9)
53
53
#define OA_OACONTROL_COUNTER_SIZE_MASK REG_GENMASK(8, 8)
54
+
#define OAG_OACONTROL_USED_BITS \
55
+
(OAG_OACONTROL_OA_PES_DISAG_EN | OAG_OACONTROL_OA_CCS_SELECT_MASK | \
56
+
OAG_OACONTROL_OA_COUNTER_SEL_MASK | OAG_OACONTROL_OA_COUNTER_ENABLE | \
57
+
OA_OACONTROL_REPORT_BC_MASK | OA_OACONTROL_COUNTER_SIZE_MASK)
54
58
55
59
#define OAG_OA_DEBUG XE_REG(0xdaf8, XE_REG_OPTION_MASKED)
56
60
#define OAG_OA_DEBUG_DISABLE_MMIO_TRG REG_BIT(14)
···
82
78
#define OAM_CONTEXT_CONTROL_OFFSET (0x1bc)
83
79
#define OAM_CONTROL_OFFSET (0x194)
84
80
#define OAM_CONTROL_COUNTER_SEL_MASK REG_GENMASK(3, 1)
81
+
#define OAM_OACONTROL_USED_BITS \
82
+
(OAM_CONTROL_COUNTER_SEL_MASK | OAG_OACONTROL_OA_COUNTER_ENABLE)
85
83
#define OAM_DEBUG_OFFSET (0x198)
86
84
#define OAM_STATUS_OFFSET (0x19c)
87
85
#define OAM_MMIO_TRG_OFFSET (0x1d0)
+15
-27
drivers/gpu/drm/xe/xe_devcoredump.c
+15
-27
drivers/gpu/drm/xe/xe_devcoredump.c
···
119
119
drm_puts(&p, "\n**** GuC CT ****\n");
120
120
xe_guc_ct_snapshot_print(ss->guc.ct, &p);
121
121
122
-
/*
123
-
* Don't add a new section header here because the mesa debug decoder
124
-
* tool expects the context information to be in the 'GuC CT' section.
125
-
*/
126
-
/* drm_puts(&p, "\n**** Contexts ****\n"); */
122
+
drm_puts(&p, "\n**** Contexts ****\n");
127
123
xe_guc_exec_queue_snapshot_print(ss->ge, &p);
128
124
129
125
drm_puts(&p, "\n**** Job ****\n");
···
391
395
/**
392
396
* xe_print_blob_ascii85 - print a BLOB to some useful location in ASCII85
393
397
*
394
-
* The output is split to multiple lines because some print targets, e.g. dmesg
395
-
* cannot handle arbitrarily long lines. Note also that printing to dmesg in
396
-
* piece-meal fashion is not possible, each separate call to drm_puts() has a
397
-
* line-feed automatically added! Therefore, the entire output line must be
398
-
* constructed in a local buffer first, then printed in one atomic output call.
398
+
* The output is split into multiple calls to drm_puts() because some print
399
+
* targets, e.g. dmesg, cannot handle arbitrarily long lines. These targets may
400
+
* add newlines, as is the case with dmesg: each drm_puts() call creates a
401
+
* separate line.
399
402
*
400
403
* There is also a scheduler yield call to prevent the 'task has been stuck for
401
404
* 120s' kernel hang check feature from firing when printing to a slow target
402
405
* such as dmesg over a serial port.
403
406
*
404
-
* TODO: Add compression prior to the ASCII85 encoding to shrink huge buffers down.
405
-
*
406
407
* @p: the printer object to output to
407
408
* @prefix: optional prefix to add to output string
409
+
* @suffix: optional suffix to add at the end. 0 disables it and is
410
+
* not added to the output, which is useful when using multiple calls
411
+
* to dump data to @p
408
412
* @blob: the Binary Large OBject to dump out
409
413
* @offset: offset in bytes to skip from the front of the BLOB, must be a multiple of sizeof(u32)
410
414
* @size: the size in bytes of the BLOB, must be a multiple of sizeof(u32)
411
415
*/
412
-
void xe_print_blob_ascii85(struct drm_printer *p, const char *prefix,
416
+
void xe_print_blob_ascii85(struct drm_printer *p, const char *prefix, char suffix,
413
417
const void *blob, size_t offset, size_t size)
414
418
{
415
419
const u32 *blob32 = (const u32 *)blob;
416
420
char buff[ASCII85_BUFSZ], *line_buff;
417
421
size_t line_pos = 0;
418
422
419
-
/*
420
-
* Splitting blobs across multiple lines is not compatible with the mesa
421
-
* debug decoder tool. Note that even dropping the explicit '\n' below
422
-
* doesn't help because the GuC log is so big some underlying implementation
423
-
* still splits the lines at 512K characters. So just bail completely for
424
-
* the moment.
425
-
*/
426
-
return;
427
-
428
423
#define DMESG_MAX_LINE_LEN 800
429
-
#define MIN_SPACE (ASCII85_BUFSZ + 2) /* 85 + "\n\0" */
424
+
/* Always leave space for the suffix char and the \0 */
425
+
#define MIN_SPACE (ASCII85_BUFSZ + 2) /* 85 + "<suffix>\0" */
430
426
431
427
if (size & 3)
432
428
drm_printf(p, "Size not word aligned: %zu", size);
···
450
462
line_pos += strlen(line_buff + line_pos);
451
463
452
464
if ((line_pos + MIN_SPACE) >= DMESG_MAX_LINE_LEN) {
453
-
line_buff[line_pos++] = '\n';
454
465
line_buff[line_pos++] = 0;
455
466
456
467
drm_puts(p, line_buff);
···
461
474
}
462
475
}
463
476
464
-
if (line_pos) {
465
-
line_buff[line_pos++] = '\n';
466
-
line_buff[line_pos++] = 0;
477
+
if (suffix)
478
+
line_buff[line_pos++] = suffix;
467
479
480
+
if (line_pos) {
481
+
line_buff[line_pos++] = 0;
468
482
drm_puts(p, line_buff);
469
483
}
470
484
+1
-1
drivers/gpu/drm/xe/xe_devcoredump.h
+1
-1
drivers/gpu/drm/xe/xe_devcoredump.h
+3
-1
drivers/gpu/drm/xe/xe_gt.c
+3
-1
drivers/gpu/drm/xe/xe_gt.c
···
532
532
if (IS_SRIOV_PF(gt_to_xe(gt)) && !xe_gt_is_media_type(gt))
533
533
xe_lmtt_init_hw(>_to_tile(gt)->sriov.pf.lmtt);
534
534
535
-
if (IS_SRIOV_PF(gt_to_xe(gt)))
535
+
if (IS_SRIOV_PF(gt_to_xe(gt))) {
536
+
xe_gt_sriov_pf_init(gt);
536
537
xe_gt_sriov_pf_init_hw(gt);
538
+
}
537
539
538
540
xe_force_wake_put(gt_to_fw(gt), fw_ref);
539
541
+13
-1
drivers/gpu/drm/xe/xe_gt_sriov_pf.c
+13
-1
drivers/gpu/drm/xe/xe_gt_sriov_pf.c
···
68
68
return 0;
69
69
}
70
70
71
+
/**
72
+
* xe_gt_sriov_pf_init - Prepare SR-IOV PF data structures on PF.
73
+
* @gt: the &xe_gt to initialize
74
+
*
75
+
* Late one-time initialization of the PF data.
76
+
*
77
+
* Return: 0 on success or a negative error code on failure.
78
+
*/
79
+
int xe_gt_sriov_pf_init(struct xe_gt *gt)
80
+
{
81
+
return xe_gt_sriov_pf_migration_init(gt);
82
+
}
83
+
71
84
static bool pf_needs_enable_ggtt_guest_update(struct xe_device *xe)
72
85
{
73
86
return GRAPHICS_VERx100(xe) == 1200;
···
103
90
pf_enable_ggtt_guest_update(gt);
104
91
105
92
xe_gt_sriov_pf_service_update(gt);
106
-
xe_gt_sriov_pf_migration_init(gt);
107
93
}
108
94
109
95
static u32 pf_get_vf_regs_stride(struct xe_device *xe)
+6
drivers/gpu/drm/xe/xe_gt_sriov_pf.h
+6
drivers/gpu/drm/xe/xe_gt_sriov_pf.h
···
10
10
11
11
#ifdef CONFIG_PCI_IOV
12
12
int xe_gt_sriov_pf_init_early(struct xe_gt *gt);
13
+
int xe_gt_sriov_pf_init(struct xe_gt *gt);
13
14
void xe_gt_sriov_pf_init_hw(struct xe_gt *gt);
14
15
void xe_gt_sriov_pf_sanitize_hw(struct xe_gt *gt, unsigned int vfid);
15
16
void xe_gt_sriov_pf_restart(struct xe_gt *gt);
16
17
#else
17
18
static inline int xe_gt_sriov_pf_init_early(struct xe_gt *gt)
19
+
{
20
+
return 0;
21
+
}
22
+
23
+
static inline int xe_gt_sriov_pf_init(struct xe_gt *gt)
18
24
{
19
25
return 0;
20
26
}
+2
-1
drivers/gpu/drm/xe/xe_guc_ct.c
+2
-1
drivers/gpu/drm/xe/xe_guc_ct.c
···
1724
1724
snapshot->g2h_outstanding);
1725
1725
1726
1726
if (snapshot->ctb)
1727
-
xe_print_blob_ascii85(p, "CTB data", snapshot->ctb, 0, snapshot->ctb_size);
1727
+
xe_print_blob_ascii85(p, "CTB data", '\n',
1728
+
snapshot->ctb, 0, snapshot->ctb_size);
1728
1729
} else {
1729
1730
drm_puts(p, "CT disabled\n");
1730
1731
}
+3
-1
drivers/gpu/drm/xe/xe_guc_log.c
+3
-1
drivers/gpu/drm/xe/xe_guc_log.c
···
211
211
remain = snapshot->size;
212
212
for (i = 0; i < snapshot->num_chunks; i++) {
213
213
size_t size = min(GUC_LOG_CHUNK_SIZE, remain);
214
+
const char *prefix = i ? NULL : "Log data";
215
+
char suffix = i == snapshot->num_chunks - 1 ? '\n' : 0;
214
216
215
-
xe_print_blob_ascii85(p, i ? NULL : "Log data", snapshot->copy[i], 0, size);
217
+
xe_print_blob_ascii85(p, prefix, suffix, snapshot->copy[i], 0, size);
216
218
remain -= size;
217
219
}
218
220
}
+13
-8
drivers/gpu/drm/xe/xe_oa.c
+13
-8
drivers/gpu/drm/xe/xe_oa.c
···
237
237
u32 tail, hw_tail, partial_report_size, available;
238
238
int report_size = stream->oa_buffer.format->size;
239
239
unsigned long flags;
240
-
bool pollin;
241
240
242
241
spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
243
242
···
281
282
stream->oa_buffer.tail = tail;
282
283
283
284
available = xe_oa_circ_diff(stream, stream->oa_buffer.tail, stream->oa_buffer.head);
284
-
pollin = available >= stream->wait_num_reports * report_size;
285
+
stream->pollin = available >= stream->wait_num_reports * report_size;
285
286
286
287
spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
287
288
288
-
return pollin;
289
+
return stream->pollin;
289
290
}
290
291
291
292
static enum hrtimer_restart xe_oa_poll_check_timer_cb(struct hrtimer *hrtimer)
···
293
294
struct xe_oa_stream *stream =
294
295
container_of(hrtimer, typeof(*stream), poll_check_timer);
295
296
296
-
if (xe_oa_buffer_check_unlocked(stream)) {
297
-
stream->pollin = true;
297
+
if (xe_oa_buffer_check_unlocked(stream))
298
298
wake_up(&stream->poll_wq);
299
-
}
300
299
301
300
hrtimer_forward_now(hrtimer, ns_to_ktime(stream->poll_period_ns));
302
301
···
449
452
return val;
450
453
}
451
454
455
+
static u32 __oactrl_used_bits(struct xe_oa_stream *stream)
456
+
{
457
+
return stream->hwe->oa_unit->type == DRM_XE_OA_UNIT_TYPE_OAG ?
458
+
OAG_OACONTROL_USED_BITS : OAM_OACONTROL_USED_BITS;
459
+
}
460
+
452
461
static void xe_oa_enable(struct xe_oa_stream *stream)
453
462
{
454
463
const struct xe_oa_format *format = stream->oa_buffer.format;
···
475
472
stream->hwe->oa_unit->type == DRM_XE_OA_UNIT_TYPE_OAG)
476
473
val |= OAG_OACONTROL_OA_PES_DISAG_EN;
477
474
478
-
xe_mmio_write32(&stream->gt->mmio, regs->oa_ctrl, val);
475
+
xe_mmio_rmw32(&stream->gt->mmio, regs->oa_ctrl, __oactrl_used_bits(stream), val);
479
476
}
480
477
481
478
static void xe_oa_disable(struct xe_oa_stream *stream)
482
479
{
483
480
struct xe_mmio *mmio = &stream->gt->mmio;
484
481
485
-
xe_mmio_write32(mmio, __oa_regs(stream)->oa_ctrl, 0);
482
+
xe_mmio_rmw32(mmio, __oa_regs(stream)->oa_ctrl, __oactrl_used_bits(stream), 0);
486
483
if (xe_mmio_wait32(mmio, __oa_regs(stream)->oa_ctrl,
487
484
OAG_OACONTROL_OA_COUNTER_ENABLE, 0, 50000, NULL, false))
488
485
drm_err(&stream->oa->xe->drm,
···
2536
2533
u->regs = __oam_regs(mtl_oa_base[i]);
2537
2534
u->type = DRM_XE_OA_UNIT_TYPE_OAM;
2538
2535
}
2536
+
2537
+
xe_mmio_write32(>->mmio, u->regs.oa_ctrl, 0);
2539
2538
2540
2539
/* Ensure MMIO trigger remains disabled till there is a stream */
2541
2540
xe_mmio_write32(>->mmio, u->regs.oa_debug,
+1
include/drm/drm_print.h
+1
include/drm/drm_print.h
+8
-1
include/uapi/drm/amdgpu_drm.h
+8
-1
include/uapi/drm/amdgpu_drm.h
···
411
411
/* GFX12 and later: */
412
412
#define AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT 0
413
413
#define AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK 0x7
414
-
/* These are DCC recompression setting for memory management: */
414
+
/* These are DCC recompression settings for memory management: */
415
415
#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3
416
416
#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* 0:64B, 1:128B, 2:256B */
417
417
#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT 5
418
418
#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK 0x7 /* CB_COLOR0_INFO.NUMBER_TYPE */
419
419
#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT 8
420
420
#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK 0x3f /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */
421
+
/* When clearing the buffer or moving it from VRAM to GTT, don't compress and set DCC metadata
422
+
* to uncompressed. Set when parts of an allocation bypass DCC and read raw data. */
423
+
#define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_SHIFT 14
424
+
#define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_MASK 0x1
425
+
/* bit gap */
426
+
#define AMDGPU_TILING_GFX12_SCANOUT_SHIFT 63
427
+
#define AMDGPU_TILING_GFX12_SCANOUT_MASK 0x1
421
428
422
429
/* Set/Get helpers for tiling flags. */
423
430
#define AMDGPU_TILING_SET(field, value) \