Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
crypto: qat - enable RAS support for GEN6 devices
Enable the reporting and handling of errors for QAT GEN6 devices.
Errors are categorized as correctable, non-fatal, or fatal. Error
handling involves reading the error source registers (ERRSOU0 to ERRSOU3)
to determine the source of the error and then decoding the actual source
reading specific registers.
The action taken depends on the error type:
- Correctable and Non-Fatal errors. These error are logged, cleared and
the corresponding counter is incremented.
- Fatal errors. These errors are logged, cleared and a Function Level
Reset (FLR) is scheduled.
This reports and handles the following errors:
- Accelerator engine (AE) correctable errors
- Accelerator engine (AE) uncorrectable errors
- Chassis push-pull (CPP) errors
- Host interface (HI) parity errors
- Internal memory parity errors
- Receive interface (RI) errors
- Transmit interface (TI) errors
- Interface for system-on-chip (SoC) fabric (IOSF) primary command
parity errors
- Shared RAM and slice module (SSM) errors
Signed-off-by: Suman Kumar Chakraborty <suman.kumar.chakraborty@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
authored by
Suman Kumar Chakraborty
and committed by
Herbert Xu
7f3401d0
63935e2e
+1325
+2
drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c
+2
drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c
···
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#include <adf_common_drv.h>
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#include <adf_fw_config.h>
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#include <adf_gen6_pm.h>
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#include <adf_gen6_ras.h>
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#include <adf_gen6_shared.h>
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#include <adf_timer.h>
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#include "adf_6xxx_hw_data.h"
···
835
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adf_gen6_init_hw_csr_ops(&hw_data->csr_ops);
836
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adf_gen6_init_pf_pfvf_ops(&hw_data->pfvf_ops);
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adf_gen6_init_dc_ops(&hw_data->dc_ops);
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adf_gen6_init_ras_ops(&hw_data->ras_ops);
838
838
}
839
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void adf_clean_hw_data_6xxx(struct adf_hw_device_data *hw_data)
+1
drivers/crypto/intel/qat/qat_common/Makefile
+1
drivers/crypto/intel/qat/qat_common/Makefile
+818
drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c
+818
drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2025 Intel Corporation */
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#include <linux/bitfield.h>
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#include <linux/types.h>
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#include "adf_common_drv.h"
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#include "adf_gen6_ras.h"
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#include "adf_sysfs_ras_counters.h"
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static void enable_errsou_reporting(void __iomem *csr)
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{
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/* Enable correctable error reporting in ERRSOU0 */
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ADF_CSR_WR(csr, ADF_GEN6_ERRMSK0, 0);
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+
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/* Enable uncorrectable error reporting in ERRSOU1 */
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ADF_CSR_WR(csr, ADF_GEN6_ERRMSK1, 0);
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+
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/*
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* Enable uncorrectable error reporting in ERRSOU2
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* but disable PM interrupt by default
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*/
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ADF_CSR_WR(csr, ADF_GEN6_ERRMSK2, ADF_GEN6_ERRSOU2_PM_INT_BIT);
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+
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/* Enable uncorrectable error reporting in ERRSOU3 */
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ADF_CSR_WR(csr, ADF_GEN6_ERRMSK3, 0);
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}
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+
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static void enable_ae_error_reporting(struct adf_accel_dev *accel_dev, void __iomem *csr)
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{
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u32 ae_mask = GET_HW_DATA(accel_dev)->ae_mask;
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/* Enable acceleration engine correctable error reporting */
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ADF_CSR_WR(csr, ADF_GEN6_HIAECORERRLOGENABLE_CPP0, ae_mask);
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+
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/* Enable acceleration engine uncorrectable error reporting */
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ADF_CSR_WR(csr, ADF_GEN6_HIAEUNCERRLOGENABLE_CPP0, ae_mask);
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}
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static void enable_cpp_error_reporting(struct adf_accel_dev *accel_dev, void __iomem *csr)
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{
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/* Enable HI CPP agents command parity error reporting */
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ADF_CSR_WR(csr, ADF_GEN6_HICPPAGENTCMDPARERRLOGENABLE,
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ADF_6XXX_HICPPAGENTCMDPARERRLOG_MASK);
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ADF_CSR_WR(csr, ADF_GEN6_CPP_CFC_ERR_CTRL, ADF_GEN6_CPP_CFC_ERR_CTRL_MASK);
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}
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static void enable_ti_ri_error_reporting(void __iomem *csr)
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{
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u32 reg, mask;
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/* Enable RI memory error reporting */
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mask = ADF_GEN6_RIMEM_PARERR_FATAL_MASK | ADF_GEN6_RIMEM_PARERR_CERR_MASK;
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ADF_CSR_WR(csr, ADF_GEN6_RI_MEM_PAR_ERR_EN0, mask);
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+
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/* Enable IOSF primary command parity error reporting */
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ADF_CSR_WR(csr, ADF_GEN6_RIMISCCTL, ADF_GEN6_RIMISCSTS_BIT);
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+
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/* Enable TI internal memory parity error reporting */
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reg = ADF_CSR_RD(csr, ADF_GEN6_TI_CI_PAR_ERR_MASK);
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reg &= ~ADF_GEN6_TI_CI_PAR_STS_MASK;
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ADF_CSR_WR(csr, ADF_GEN6_TI_CI_PAR_ERR_MASK, reg);
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+
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reg = ADF_CSR_RD(csr, ADF_GEN6_TI_PULL0FUB_PAR_ERR_MASK);
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reg &= ~ADF_GEN6_TI_PULL0FUB_PAR_STS_MASK;
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ADF_CSR_WR(csr, ADF_GEN6_TI_PULL0FUB_PAR_ERR_MASK, reg);
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reg = ADF_CSR_RD(csr, ADF_GEN6_TI_PUSHFUB_PAR_ERR_MASK);
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reg &= ~ADF_GEN6_TI_PUSHFUB_PAR_STS_MASK;
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ADF_CSR_WR(csr, ADF_GEN6_TI_PUSHFUB_PAR_ERR_MASK, reg);
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reg = ADF_CSR_RD(csr, ADF_GEN6_TI_CD_PAR_ERR_MASK);
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reg &= ~ADF_GEN6_TI_CD_PAR_STS_MASK;
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ADF_CSR_WR(csr, ADF_GEN6_TI_CD_PAR_ERR_MASK, reg);
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reg = ADF_CSR_RD(csr, ADF_GEN6_TI_TRNSB_PAR_ERR_MASK);
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reg &= ~ADF_GEN6_TI_TRNSB_PAR_STS_MASK;
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ADF_CSR_WR(csr, ADF_GEN6_TI_TRNSB_PAR_ERR_MASK, reg);
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/* Enable error handling in RI, TI CPP interface control registers */
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ADF_CSR_WR(csr, ADF_GEN6_RICPPINTCTL, ADF_GEN6_RICPPINTCTL_MASK);
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ADF_CSR_WR(csr, ADF_GEN6_TICPPINTCTL, ADF_GEN6_TICPPINTCTL_MASK);
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/*
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* Enable error detection and reporting in TIMISCSTS
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* with bits 1, 2 and 30 value preserved
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*/
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reg = ADF_CSR_RD(csr, ADF_GEN6_TIMISCCTL);
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reg &= ADF_GEN6_TIMSCCTL_RELAY_MASK;
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reg |= ADF_GEN6_TIMISCCTL_BIT;
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ADF_CSR_WR(csr, ADF_GEN6_TIMISCCTL, reg);
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}
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static void enable_ssm_error_reporting(struct adf_accel_dev *accel_dev,
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void __iomem *csr)
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{
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/* Enable SSM interrupts */
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ADF_CSR_WR(csr, ADF_GEN6_INTMASKSSM, 0);
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}
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static void adf_gen6_enable_ras(struct adf_accel_dev *accel_dev)
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{
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void __iomem *csr = adf_get_pmisc_base(accel_dev);
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enable_errsou_reporting(csr);
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enable_ae_error_reporting(accel_dev, csr);
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enable_cpp_error_reporting(accel_dev, csr);
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enable_ti_ri_error_reporting(csr);
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enable_ssm_error_reporting(accel_dev, csr);
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}
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static void disable_errsou_reporting(void __iomem *csr)
113
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{
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u32 val;
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/* Disable correctable error reporting in ERRSOU0 */
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ADF_CSR_WR(csr, ADF_GEN6_ERRMSK0, ADF_GEN6_ERRSOU0_MASK);
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/* Disable uncorrectable error reporting in ERRSOU1 */
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ADF_CSR_WR(csr, ADF_GEN6_ERRMSK1, ADF_GEN6_ERRMSK1_MASK);
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/* Disable uncorrectable error reporting in ERRSOU2 */
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val = ADF_CSR_RD(csr, ADF_GEN6_ERRMSK2);
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val |= ADF_GEN6_ERRSOU2_DIS_MASK;
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ADF_CSR_WR(csr, ADF_GEN6_ERRMSK2, val);
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/* Disable uncorrectable error reporting in ERRSOU3 */
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ADF_CSR_WR(csr, ADF_GEN6_ERRMSK3, ADF_GEN6_ERRSOU3_DIS_MASK);
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}
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static void disable_ae_error_reporting(void __iomem *csr)
132
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{
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/* Disable acceleration engine correctable error reporting */
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ADF_CSR_WR(csr, ADF_GEN6_HIAECORERRLOGENABLE_CPP0, 0);
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+
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/* Disable acceleration engine uncorrectable error reporting */
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ADF_CSR_WR(csr, ADF_GEN6_HIAEUNCERRLOGENABLE_CPP0, 0);
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}
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+
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static void disable_cpp_error_reporting(void __iomem *csr)
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{
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/* Disable HI CPP agents command parity error reporting */
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ADF_CSR_WR(csr, ADF_GEN6_HICPPAGENTCMDPARERRLOGENABLE, 0);
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ADF_CSR_WR(csr, ADF_GEN6_CPP_CFC_ERR_CTRL, ADF_GEN6_CPP_CFC_ERR_CTRL_DIS_MASK);
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}
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+
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static void disable_ti_ri_error_reporting(void __iomem *csr)
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{
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u32 reg;
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/* Disable RI memory error reporting */
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ADF_CSR_WR(csr, ADF_GEN6_RI_MEM_PAR_ERR_EN0, 0);
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/* Disable IOSF primary command parity error reporting */
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reg = ADF_CSR_RD(csr, ADF_GEN6_RIMISCCTL);
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reg &= ~ADF_GEN6_RIMISCSTS_BIT;
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ADF_CSR_WR(csr, ADF_GEN6_RIMISCCTL, reg);
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/* Disable TI internal memory parity error reporting */
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ADF_CSR_WR(csr, ADF_GEN6_TI_CI_PAR_ERR_MASK, ADF_GEN6_TI_CI_PAR_STS_MASK);
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ADF_CSR_WR(csr, ADF_GEN6_TI_PULL0FUB_PAR_ERR_MASK, ADF_GEN6_TI_PULL0FUB_PAR_STS_MASK);
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ADF_CSR_WR(csr, ADF_GEN6_TI_PUSHFUB_PAR_ERR_MASK, ADF_GEN6_TI_PUSHFUB_PAR_STS_MASK);
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ADF_CSR_WR(csr, ADF_GEN6_TI_CD_PAR_ERR_MASK, ADF_GEN6_TI_CD_PAR_STS_MASK);
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ADF_CSR_WR(csr, ADF_GEN6_TI_TRNSB_PAR_ERR_MASK, ADF_GEN6_TI_TRNSB_PAR_STS_MASK);
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+
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/* Disable error handling in RI, TI CPP interface control registers */
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reg = ADF_CSR_RD(csr, ADF_GEN6_RICPPINTCTL);
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reg &= ~ADF_GEN6_RICPPINTCTL_MASK;
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ADF_CSR_WR(csr, ADF_GEN6_RICPPINTCTL, reg);
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reg = ADF_CSR_RD(csr, ADF_GEN6_TICPPINTCTL);
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reg &= ~ADF_GEN6_TICPPINTCTL_MASK;
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ADF_CSR_WR(csr, ADF_GEN6_TICPPINTCTL, reg);
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/*
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* Disable error detection and reporting in TIMISCSTS
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* with bits 1, 2 and 30 value preserved
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*/
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reg = ADF_CSR_RD(csr, ADF_GEN6_TIMISCCTL);
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reg &= ADF_GEN6_TIMSCCTL_RELAY_MASK;
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ADF_CSR_WR(csr, ADF_GEN6_TIMISCCTL, reg);
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}
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static void disable_ssm_error_reporting(void __iomem *csr)
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{
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/* Disable SSM interrupts */
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ADF_CSR_WR(csr, ADF_GEN6_INTMASKSSM, ADF_GEN6_INTMASKSSM_MASK);
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}
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static void adf_gen6_disable_ras(struct adf_accel_dev *accel_dev)
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{
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void __iomem *csr = adf_get_pmisc_base(accel_dev);
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disable_errsou_reporting(csr);
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disable_ae_error_reporting(csr);
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disable_cpp_error_reporting(csr);
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disable_ti_ri_error_reporting(csr);
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disable_ssm_error_reporting(csr);
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}
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static void adf_gen6_process_errsou0(struct adf_accel_dev *accel_dev, void __iomem *csr)
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{
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u32 ae, errsou;
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ae = ADF_CSR_RD(csr, ADF_GEN6_HIAECORERRLOG_CPP0);
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ae &= GET_HW_DATA(accel_dev)->ae_mask;
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dev_warn(&GET_DEV(accel_dev), "Correctable error detected: %#x\n", ae);
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ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_CORR);
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/* Clear interrupt from ERRSOU0 */
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ADF_CSR_WR(csr, ADF_GEN6_HIAECORERRLOG_CPP0, ae);
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errsou = ADF_CSR_RD(csr, ADF_GEN6_ERRSOU0);
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if (errsou & ADF_GEN6_ERRSOU0_MASK)
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dev_warn(&GET_DEV(accel_dev), "errsou0 still set: %#x\n", errsou);
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}
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static void adf_handle_cpp_ae_unc(struct adf_accel_dev *accel_dev, void __iomem *csr,
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u32 errsou)
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{
224
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u32 ae;
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if (!(errsou & ADF_GEN6_ERRSOU1_CPP0_MEUNC_BIT))
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return;
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ae = ADF_CSR_RD(csr, ADF_GEN6_HIAEUNCERRLOG_CPP0);
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ae &= GET_HW_DATA(accel_dev)->ae_mask;
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if (ae) {
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dev_err(&GET_DEV(accel_dev), "Uncorrectable error detected: %#x\n", ae);
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ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR);
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ADF_CSR_WR(csr, ADF_GEN6_HIAEUNCERRLOG_CPP0, ae);
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}
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}
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+
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static void adf_handle_cpp_cmd_par_err(struct adf_accel_dev *accel_dev, void __iomem *csr,
239
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u32 errsou)
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{
241
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u32 cmd_par_err;
242
+
243
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if (!(errsou & ADF_GEN6_ERRSOU1_CPP_CMDPARERR_BIT))
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return;
245
+
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cmd_par_err = ADF_CSR_RD(csr, ADF_GEN6_HICPPAGENTCMDPARERRLOG);
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cmd_par_err &= ADF_6XXX_HICPPAGENTCMDPARERRLOG_MASK;
248
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if (cmd_par_err) {
249
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dev_err(&GET_DEV(accel_dev), "HI CPP agent command parity error: %#x\n",
250
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cmd_par_err);
251
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ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL);
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ADF_CSR_WR(csr, ADF_GEN6_HICPPAGENTCMDPARERRLOG, cmd_par_err);
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}
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}
255
+
256
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static void adf_handle_ri_mem_par_err(struct adf_accel_dev *accel_dev, void __iomem *csr,
257
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u32 errsou)
258
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{
259
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u32 rimem_parerr_sts;
260
+
261
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if (!(errsou & ADF_GEN6_ERRSOU1_RIMEM_PARERR_STS_BIT))
262
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return;
263
+
264
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rimem_parerr_sts = ADF_CSR_RD(csr, ADF_GEN6_RIMEM_PARERR_STS);
265
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rimem_parerr_sts &= ADF_GEN6_RIMEM_PARERR_CERR_MASK |
266
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ADF_GEN6_RIMEM_PARERR_FATAL_MASK;
267
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if (rimem_parerr_sts & ADF_GEN6_RIMEM_PARERR_CERR_MASK) {
268
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dev_err(&GET_DEV(accel_dev), "RI memory parity correctable error: %#x\n",
269
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rimem_parerr_sts);
270
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ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_CORR);
271
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}
272
+
273
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if (rimem_parerr_sts & ADF_GEN6_RIMEM_PARERR_FATAL_MASK) {
274
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dev_err(&GET_DEV(accel_dev), "RI memory parity fatal error: %#x\n",
275
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rimem_parerr_sts);
276
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ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL);
277
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}
278
+
279
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ADF_CSR_WR(csr, ADF_GEN6_RIMEM_PARERR_STS, rimem_parerr_sts);
280
+
}
281
+
282
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static void adf_handle_ti_ci_par_sts(struct adf_accel_dev *accel_dev, void __iomem *csr)
283
+
{
284
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u32 ti_ci_par_sts;
285
+
286
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ti_ci_par_sts = ADF_CSR_RD(csr, ADF_GEN6_TI_CI_PAR_STS);
287
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ti_ci_par_sts &= ADF_GEN6_TI_CI_PAR_STS_MASK;
288
+
if (ti_ci_par_sts) {
289
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dev_err(&GET_DEV(accel_dev), "TI memory parity error: %#x\n", ti_ci_par_sts);
290
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ADF_CSR_WR(csr, ADF_GEN6_TI_CI_PAR_STS, ti_ci_par_sts);
291
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ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR);
292
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}
293
+
}
294
+
295
+
static void adf_handle_ti_pullfub_par_sts(struct adf_accel_dev *accel_dev, void __iomem *csr)
296
+
{
297
+
u32 ti_pullfub_par_sts;
298
+
299
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ti_pullfub_par_sts = ADF_CSR_RD(csr, ADF_GEN6_TI_PULL0FUB_PAR_STS);
300
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ti_pullfub_par_sts &= ADF_GEN6_TI_PULL0FUB_PAR_STS_MASK;
301
+
if (ti_pullfub_par_sts) {
302
+
dev_err(&GET_DEV(accel_dev), "TI pull parity error: %#x\n", ti_pullfub_par_sts);
303
+
ADF_CSR_WR(csr, ADF_GEN6_TI_PULL0FUB_PAR_STS, ti_pullfub_par_sts);
304
+
ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR);
305
+
}
306
+
}
307
+
308
+
static void adf_handle_ti_pushfub_par_sts(struct adf_accel_dev *accel_dev, void __iomem *csr)
309
+
{
310
+
u32 ti_pushfub_par_sts;
311
+
312
+
ti_pushfub_par_sts = ADF_CSR_RD(csr, ADF_GEN6_TI_PUSHFUB_PAR_STS);
313
+
ti_pushfub_par_sts &= ADF_GEN6_TI_PUSHFUB_PAR_STS_MASK;
314
+
if (ti_pushfub_par_sts) {
315
+
dev_err(&GET_DEV(accel_dev), "TI push parity error: %#x\n", ti_pushfub_par_sts);
316
+
ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR);
317
+
ADF_CSR_WR(csr, ADF_GEN6_TI_PUSHFUB_PAR_STS, ti_pushfub_par_sts);
318
+
}
319
+
}
320
+
321
+
static void adf_handle_ti_cd_par_sts(struct adf_accel_dev *accel_dev, void __iomem *csr)
322
+
{
323
+
u32 ti_cd_par_sts;
324
+
325
+
ti_cd_par_sts = ADF_CSR_RD(csr, ADF_GEN6_TI_CD_PAR_STS);
326
+
ti_cd_par_sts &= ADF_GEN6_TI_CD_PAR_STS_MASK;
327
+
if (ti_cd_par_sts) {
328
+
dev_err(&GET_DEV(accel_dev), "TI CD parity error: %#x\n", ti_cd_par_sts);
329
+
ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR);
330
+
ADF_CSR_WR(csr, ADF_GEN6_TI_CD_PAR_STS, ti_cd_par_sts);
331
+
}
332
+
}
333
+
334
+
static void adf_handle_ti_trnsb_par_sts(struct adf_accel_dev *accel_dev, void __iomem *csr)
335
+
{
336
+
u32 ti_trnsb_par_sts;
337
+
338
+
ti_trnsb_par_sts = ADF_CSR_RD(csr, ADF_GEN6_TI_TRNSB_PAR_STS);
339
+
ti_trnsb_par_sts &= ADF_GEN6_TI_TRNSB_PAR_STS_MASK;
340
+
if (ti_trnsb_par_sts) {
341
+
dev_err(&GET_DEV(accel_dev), "TI TRNSB parity error: %#x\n", ti_trnsb_par_sts);
342
+
ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR);
343
+
ADF_CSR_WR(csr, ADF_GEN6_TI_TRNSB_PAR_STS, ti_trnsb_par_sts);
344
+
}
345
+
}
346
+
347
+
static void adf_handle_iosfp_cmd_parerr(struct adf_accel_dev *accel_dev, void __iomem *csr)
348
+
{
349
+
u32 rimiscsts;
350
+
351
+
rimiscsts = ADF_CSR_RD(csr, ADF_GEN6_RIMISCSTS);
352
+
rimiscsts &= ADF_GEN6_RIMISCSTS_BIT;
353
+
if (rimiscsts) {
354
+
dev_err(&GET_DEV(accel_dev), "Command parity error detected on IOSFP: %#x\n",
355
+
rimiscsts);
356
+
ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL);
357
+
ADF_CSR_WR(csr, ADF_GEN6_RIMISCSTS, rimiscsts);
358
+
}
359
+
}
360
+
361
+
static void adf_handle_ti_err(struct adf_accel_dev *accel_dev, void __iomem *csr,
362
+
u32 errsou)
363
+
{
364
+
if (!(errsou & ADF_GEN6_ERRSOU1_TIMEM_PARERR_STS_BIT))
365
+
return;
366
+
367
+
adf_handle_ti_ci_par_sts(accel_dev, csr);
368
+
adf_handle_ti_pullfub_par_sts(accel_dev, csr);
369
+
adf_handle_ti_pushfub_par_sts(accel_dev, csr);
370
+
adf_handle_ti_cd_par_sts(accel_dev, csr);
371
+
adf_handle_ti_trnsb_par_sts(accel_dev, csr);
372
+
adf_handle_iosfp_cmd_parerr(accel_dev, csr);
373
+
}
374
+
375
+
static void adf_handle_sfi_cmd_parerr(struct adf_accel_dev *accel_dev, void __iomem *csr,
376
+
u32 errsou)
377
+
{
378
+
if (!(errsou & ADF_GEN6_ERRSOU1_SFICMD_PARERR_BIT))
379
+
return;
380
+
381
+
dev_err(&GET_DEV(accel_dev),
382
+
"Command parity error detected on streaming fabric interface\n");
383
+
384
+
ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL);
385
+
}
386
+
387
+
static void adf_gen6_process_errsou1(struct adf_accel_dev *accel_dev, void __iomem *csr,
388
+
u32 errsou)
389
+
{
390
+
adf_handle_cpp_ae_unc(accel_dev, csr, errsou);
391
+
adf_handle_cpp_cmd_par_err(accel_dev, csr, errsou);
392
+
adf_handle_ri_mem_par_err(accel_dev, csr, errsou);
393
+
adf_handle_ti_err(accel_dev, csr, errsou);
394
+
adf_handle_sfi_cmd_parerr(accel_dev, csr, errsou);
395
+
396
+
errsou = ADF_CSR_RD(csr, ADF_GEN6_ERRSOU1);
397
+
if (errsou & ADF_GEN6_ERRSOU1_MASK)
398
+
dev_warn(&GET_DEV(accel_dev), "errsou1 still set: %#x\n", errsou);
399
+
}
400
+
401
+
static void adf_handle_cerrssmsh(struct adf_accel_dev *accel_dev, void __iomem *csr)
402
+
{
403
+
u32 reg;
404
+
405
+
reg = ADF_CSR_RD(csr, ADF_GEN6_CERRSSMSH);
406
+
reg &= ADF_GEN6_CERRSSMSH_ERROR_BIT;
407
+
if (reg) {
408
+
dev_warn(&GET_DEV(accel_dev),
409
+
"Correctable error on ssm shared memory: %#x\n", reg);
410
+
ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_CORR);
411
+
ADF_CSR_WR(csr, ADF_GEN6_CERRSSMSH, reg);
412
+
}
413
+
}
414
+
415
+
static void adf_handle_uerrssmsh(struct adf_accel_dev *accel_dev, void __iomem *csr,
416
+
u32 iastatssm)
417
+
{
418
+
u32 reg;
419
+
420
+
if (!(iastatssm & ADF_GEN6_IAINTSTATSSM_SH_ERR_BIT))
421
+
return;
422
+
423
+
reg = ADF_CSR_RD(csr, ADF_GEN6_UERRSSMSH);
424
+
reg &= ADF_GEN6_UERRSSMSH_MASK;
425
+
if (reg) {
426
+
dev_err(&GET_DEV(accel_dev),
427
+
"Fatal error on ssm shared memory: %#x\n", reg);
428
+
ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL);
429
+
ADF_CSR_WR(csr, ADF_GEN6_UERRSSMSH, reg);
430
+
}
431
+
}
432
+
433
+
static void adf_handle_pperr_err(struct adf_accel_dev *accel_dev, void __iomem *csr,
434
+
u32 iastatssm)
435
+
{
436
+
u32 reg;
437
+
438
+
if (!(iastatssm & ADF_GEN6_IAINTSTATSSM_PPERR_BIT))
439
+
return;
440
+
441
+
reg = ADF_CSR_RD(csr, ADF_GEN6_PPERR);
442
+
reg &= ADF_GEN6_PPERR_MASK;
443
+
if (reg) {
444
+
dev_err(&GET_DEV(accel_dev),
445
+
"Fatal push or pull data error: %#x\n", reg);
446
+
ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL);
447
+
ADF_CSR_WR(csr, ADF_GEN6_PPERR, reg);
448
+
}
449
+
}
450
+
451
+
static void adf_handle_scmpar_err(struct adf_accel_dev *accel_dev, void __iomem *csr,
452
+
u32 iastatssm)
453
+
{
454
+
u32 reg;
455
+
456
+
if (!(iastatssm & ADF_GEN6_IAINTSTATSSM_SCMPAR_ERR_BIT))
457
+
return;
458
+
459
+
reg = ADF_CSR_RD(csr, ADF_GEN6_SSM_FERR_STATUS);
460
+
reg &= ADF_GEN6_SCM_PAR_ERR_MASK;
461
+
if (reg) {
462
+
dev_err(&GET_DEV(accel_dev), "Fatal error on SCM: %#x\n", reg);
463
+
ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL);
464
+
ADF_CSR_WR(csr, ADF_GEN6_SSM_FERR_STATUS, reg);
465
+
}
466
+
}
467
+
468
+
static void adf_handle_cpppar_err(struct adf_accel_dev *accel_dev, void __iomem *csr,
469
+
u32 iastatssm)
470
+
{
471
+
u32 reg;
472
+
473
+
if (!(iastatssm & ADF_GEN6_IAINTSTATSSM_CPPPAR_ERR_BIT))
474
+
return;
475
+
476
+
reg = ADF_CSR_RD(csr, ADF_GEN6_SSM_FERR_STATUS);
477
+
reg &= ADF_GEN6_CPP_PAR_ERR_MASK;
478
+
if (reg) {
479
+
dev_err(&GET_DEV(accel_dev), "Fatal error on CPP: %#x\n", reg);
480
+
ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL);
481
+
ADF_CSR_WR(csr, ADF_GEN6_SSM_FERR_STATUS, reg);
482
+
}
483
+
}
484
+
485
+
static void adf_handle_rfpar_err(struct adf_accel_dev *accel_dev, void __iomem *csr,
486
+
u32 iastatssm)
487
+
{
488
+
u32 reg;
489
+
490
+
if (!(iastatssm & ADF_GEN6_IAINTSTATSSM_RFPAR_ERR_BIT))
491
+
return;
492
+
493
+
reg = ADF_CSR_RD(csr, ADF_GEN6_SSM_FERR_STATUS);
494
+
reg &= ADF_GEN6_RF_PAR_ERR_MASK;
495
+
if (reg) {
496
+
dev_err(&GET_DEV(accel_dev), "Fatal error on RF Parity: %#x\n", reg);
497
+
ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL);
498
+
ADF_CSR_WR(csr, ADF_GEN6_SSM_FERR_STATUS, reg);
499
+
}
500
+
}
501
+
502
+
static void adf_handle_unexp_cpl_err(struct adf_accel_dev *accel_dev, void __iomem *csr,
503
+
u32 iastatssm)
504
+
{
505
+
u32 reg;
506
+
507
+
if (!(iastatssm & ADF_GEN6_IAINTSTATSSM_UNEXP_CPL_ERR_BIT))
508
+
return;
509
+
510
+
reg = ADF_CSR_RD(csr, ADF_GEN6_SSM_FERR_STATUS);
511
+
reg &= ADF_GEN6_UNEXP_CPL_ERR_MASK;
512
+
if (reg) {
513
+
dev_err(&GET_DEV(accel_dev),
514
+
"Fatal error for AXI unexpected tag/length: %#x\n", reg);
515
+
ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL);
516
+
ADF_CSR_WR(csr, ADF_GEN6_SSM_FERR_STATUS, reg);
517
+
}
518
+
}
519
+
520
+
static void adf_handle_iaintstatssm(struct adf_accel_dev *accel_dev, void __iomem *csr)
521
+
{
522
+
u32 iastatssm = ADF_CSR_RD(csr, ADF_GEN6_IAINTSTATSSM);
523
+
524
+
iastatssm &= ADF_GEN6_IAINTSTATSSM_MASK;
525
+
if (!iastatssm)
526
+
return;
527
+
528
+
adf_handle_uerrssmsh(accel_dev, csr, iastatssm);
529
+
adf_handle_pperr_err(accel_dev, csr, iastatssm);
530
+
adf_handle_scmpar_err(accel_dev, csr, iastatssm);
531
+
adf_handle_cpppar_err(accel_dev, csr, iastatssm);
532
+
adf_handle_rfpar_err(accel_dev, csr, iastatssm);
533
+
adf_handle_unexp_cpl_err(accel_dev, csr, iastatssm);
534
+
535
+
ADF_CSR_WR(csr, ADF_GEN6_IAINTSTATSSM, iastatssm);
536
+
}
537
+
538
+
static void adf_handle_ssm(struct adf_accel_dev *accel_dev, void __iomem *csr, u32 errsou)
539
+
{
540
+
if (!(errsou & ADF_GEN6_ERRSOU2_SSM_ERR_BIT))
541
+
return;
542
+
543
+
adf_handle_cerrssmsh(accel_dev, csr);
544
+
adf_handle_iaintstatssm(accel_dev, csr);
545
+
}
546
+
547
+
static void adf_handle_cpp_cfc_err(struct adf_accel_dev *accel_dev, void __iomem *csr,
548
+
u32 errsou)
549
+
{
550
+
u32 reg;
551
+
552
+
if (!(errsou & ADF_GEN6_ERRSOU2_CPP_CFC_ERR_STATUS_BIT))
553
+
return;
554
+
555
+
reg = ADF_CSR_RD(csr, ADF_GEN6_CPP_CFC_ERR_STATUS);
556
+
if (reg & ADF_GEN6_CPP_CFC_ERR_STATUS_DATAPAR_BIT) {
557
+
dev_err(&GET_DEV(accel_dev), "CPP_CFC_ERR: data parity: %#x", reg);
558
+
ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR);
559
+
}
560
+
561
+
if (reg & ADF_GEN6_CPP_CFC_ERR_STATUS_CMDPAR_BIT) {
562
+
dev_err(&GET_DEV(accel_dev), "CPP_CFC_ERR: command parity: %#x", reg);
563
+
ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL);
564
+
}
565
+
566
+
if (reg & ADF_GEN6_CPP_CFC_FATAL_ERR_BIT) {
567
+
dev_err(&GET_DEV(accel_dev), "CPP_CFC_ERR: errors: %#x", reg);
568
+
ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL);
569
+
}
570
+
571
+
ADF_CSR_WR(csr, ADF_GEN6_CPP_CFC_ERR_STATUS_CLR,
572
+
ADF_GEN6_CPP_CFC_ERR_STATUS_CLR_MASK);
573
+
}
574
+
575
+
static void adf_gen6_process_errsou2(struct adf_accel_dev *accel_dev, void __iomem *csr,
576
+
u32 errsou)
577
+
{
578
+
adf_handle_ssm(accel_dev, csr, errsou);
579
+
adf_handle_cpp_cfc_err(accel_dev, csr, errsou);
580
+
581
+
errsou = ADF_CSR_RD(csr, ADF_GEN6_ERRSOU2);
582
+
if (errsou & ADF_GEN6_ERRSOU2_MASK)
583
+
dev_warn(&GET_DEV(accel_dev), "errsou2 still set: %#x\n", errsou);
584
+
}
585
+
586
+
static void adf_handle_timiscsts(struct adf_accel_dev *accel_dev, void __iomem *csr,
587
+
u32 errsou)
588
+
{
589
+
u32 timiscsts;
590
+
591
+
if (!(errsou & ADF_GEN6_ERRSOU3_TIMISCSTS_BIT))
592
+
return;
593
+
594
+
timiscsts = ADF_CSR_RD(csr, ADF_GEN6_TIMISCSTS);
595
+
if (timiscsts) {
596
+
dev_err(&GET_DEV(accel_dev), "Fatal error in transmit interface: %#x\n",
597
+
timiscsts);
598
+
ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL);
599
+
}
600
+
}
601
+
602
+
static void adf_handle_ricppintsts(struct adf_accel_dev *accel_dev, void __iomem *csr,
603
+
u32 errsou)
604
+
{
605
+
u32 ricppintsts;
606
+
607
+
if (!(errsou & ADF_GEN6_ERRSOU3_RICPPINTSTS_MASK))
608
+
return;
609
+
610
+
ricppintsts = ADF_CSR_RD(csr, ADF_GEN6_RICPPINTSTS);
611
+
ricppintsts &= ADF_GEN6_RICPPINTSTS_MASK;
612
+
if (ricppintsts) {
613
+
dev_err(&GET_DEV(accel_dev), "RI push pull error: %#x\n", ricppintsts);
614
+
ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR);
615
+
ADF_CSR_WR(csr, ADF_GEN6_RICPPINTSTS, ricppintsts);
616
+
}
617
+
}
618
+
619
+
static void adf_handle_ticppintsts(struct adf_accel_dev *accel_dev, void __iomem *csr,
620
+
u32 errsou)
621
+
{
622
+
u32 ticppintsts;
623
+
624
+
if (!(errsou & ADF_GEN6_ERRSOU3_TICPPINTSTS_MASK))
625
+
return;
626
+
627
+
ticppintsts = ADF_CSR_RD(csr, ADF_GEN6_TICPPINTSTS);
628
+
ticppintsts &= ADF_GEN6_TICPPINTSTS_MASK;
629
+
if (ticppintsts) {
630
+
dev_err(&GET_DEV(accel_dev), "TI push pull error: %#x\n", ticppintsts);
631
+
ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL);
632
+
ADF_CSR_WR(csr, ADF_GEN6_TICPPINTSTS, ticppintsts);
633
+
}
634
+
}
635
+
636
+
static void adf_handle_atufaultstatus(struct adf_accel_dev *accel_dev, void __iomem *csr,
637
+
u32 errsou)
638
+
{
639
+
u32 max_rp_num = GET_HW_DATA(accel_dev)->num_banks;
640
+
u32 atufaultstatus;
641
+
u32 i;
642
+
643
+
if (!(errsou & ADF_GEN6_ERRSOU3_ATUFAULTSTATUS_BIT))
644
+
return;
645
+
646
+
for (i = 0; i < max_rp_num; i++) {
647
+
atufaultstatus = ADF_CSR_RD(csr, ADF_GEN6_ATUFAULTSTATUS(i));
648
+
649
+
atufaultstatus &= ADF_GEN6_ATUFAULTSTATUS_BIT;
650
+
if (atufaultstatus) {
651
+
dev_err(&GET_DEV(accel_dev), "Ring pair (%u) ATU detected fault: %#x\n", i,
652
+
atufaultstatus);
653
+
ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR);
654
+
ADF_CSR_WR(csr, ADF_GEN6_ATUFAULTSTATUS(i), atufaultstatus);
655
+
}
656
+
}
657
+
}
658
+
659
+
static void adf_handle_rlterror(struct adf_accel_dev *accel_dev, void __iomem *csr,
660
+
u32 errsou)
661
+
{
662
+
u32 rlterror;
663
+
664
+
if (!(errsou & ADF_GEN6_ERRSOU3_RLTERROR_BIT))
665
+
return;
666
+
667
+
rlterror = ADF_CSR_RD(csr, ADF_GEN6_RLT_ERRLOG);
668
+
rlterror &= ADF_GEN6_RLT_ERRLOG_MASK;
669
+
if (rlterror) {
670
+
dev_err(&GET_DEV(accel_dev), "Error in rate limiting block: %#x\n", rlterror);
671
+
ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR);
672
+
ADF_CSR_WR(csr, ADF_GEN6_RLT_ERRLOG, rlterror);
673
+
}
674
+
}
675
+
676
+
static void adf_handle_vflr(struct adf_accel_dev *accel_dev, void __iomem *csr, u32 errsou)
677
+
{
678
+
if (!(errsou & ADF_GEN6_ERRSOU3_VFLRNOTIFY_BIT))
679
+
return;
680
+
681
+
dev_err(&GET_DEV(accel_dev), "Uncorrectable error in VF\n");
682
+
ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR);
683
+
}
684
+
685
+
static void adf_handle_tc_vc_map_error(struct adf_accel_dev *accel_dev, void __iomem *csr,
686
+
u32 errsou)
687
+
{
688
+
if (!(errsou & ADF_GEN6_ERRSOU3_TC_VC_MAP_ERROR_BIT))
689
+
return;
690
+
691
+
dev_err(&GET_DEV(accel_dev), "Violation of PCIe TC VC mapping\n");
692
+
ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL);
693
+
}
694
+
695
+
static void adf_handle_pcie_devhalt(struct adf_accel_dev *accel_dev, void __iomem *csr,
696
+
u32 errsou)
697
+
{
698
+
if (!(errsou & ADF_GEN6_ERRSOU3_PCIE_DEVHALT_BIT))
699
+
return;
700
+
701
+
dev_err(&GET_DEV(accel_dev),
702
+
"DEVHALT due to an error in an incoming transaction\n");
703
+
ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL);
704
+
}
705
+
706
+
static void adf_handle_pg_req_devhalt(struct adf_accel_dev *accel_dev, void __iomem *csr,
707
+
u32 errsou)
708
+
{
709
+
if (!(errsou & ADF_GEN6_ERRSOU3_PG_REQ_DEVHALT_BIT))
710
+
return;
711
+
712
+
dev_err(&GET_DEV(accel_dev),
713
+
"Error due to response failure in response to a page request\n");
714
+
ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL);
715
+
}
716
+
717
+
static void adf_handle_xlt_cpl_devhalt(struct adf_accel_dev *accel_dev, void __iomem *csr,
718
+
u32 errsou)
719
+
{
720
+
if (!(errsou & ADF_GEN6_ERRSOU3_XLT_CPL_DEVHALT_BIT))
721
+
return;
722
+
723
+
dev_err(&GET_DEV(accel_dev), "Error status for a address translation request\n");
724
+
ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL);
725
+
}
726
+
727
+
static void adf_handle_ti_int_err_devhalt(struct adf_accel_dev *accel_dev, void __iomem *csr,
728
+
u32 errsou)
729
+
{
730
+
if (!(errsou & ADF_GEN6_ERRSOU3_TI_INT_ERR_DEVHALT_BIT))
731
+
return;
732
+
733
+
dev_err(&GET_DEV(accel_dev), "DEVHALT due to a TI internal memory error\n");
734
+
ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL);
735
+
}
736
+
737
+
static void adf_gen6_process_errsou3(struct adf_accel_dev *accel_dev, void __iomem *csr,
738
+
u32 errsou)
739
+
{
740
+
adf_handle_timiscsts(accel_dev, csr, errsou);
741
+
adf_handle_ricppintsts(accel_dev, csr, errsou);
742
+
adf_handle_ticppintsts(accel_dev, csr, errsou);
743
+
adf_handle_atufaultstatus(accel_dev, csr, errsou);
744
+
adf_handle_rlterror(accel_dev, csr, errsou);
745
+
adf_handle_vflr(accel_dev, csr, errsou);
746
+
adf_handle_tc_vc_map_error(accel_dev, csr, errsou);
747
+
adf_handle_pcie_devhalt(accel_dev, csr, errsou);
748
+
adf_handle_pg_req_devhalt(accel_dev, csr, errsou);
749
+
adf_handle_xlt_cpl_devhalt(accel_dev, csr, errsou);
750
+
adf_handle_ti_int_err_devhalt(accel_dev, csr, errsou);
751
+
752
+
errsou = ADF_CSR_RD(csr, ADF_GEN6_ERRSOU3);
753
+
if (errsou & ADF_GEN6_ERRSOU3_MASK)
754
+
dev_warn(&GET_DEV(accel_dev), "errsou3 still set: %#x\n", errsou);
755
+
}
756
+
757
+
static void adf_gen6_is_reset_required(struct adf_accel_dev *accel_dev, void __iomem *csr,
758
+
bool *reset_required)
759
+
{
760
+
u8 reset, dev_state;
761
+
u32 gensts;
762
+
763
+
gensts = ADF_CSR_RD(csr, ADF_GEN6_GENSTS);
764
+
dev_state = FIELD_GET(ADF_GEN6_GENSTS_DEVICE_STATE_MASK, gensts);
765
+
reset = FIELD_GET(ADF_GEN6_GENSTS_RESET_TYPE_MASK, gensts);
766
+
if (dev_state == ADF_GEN6_GENSTS_DEVHALT && reset == ADF_GEN6_GENSTS_PFLR) {
767
+
*reset_required = true;
768
+
return;
769
+
}
770
+
771
+
if (reset == ADF_GEN6_GENSTS_COLD_RESET)
772
+
dev_err(&GET_DEV(accel_dev), "Fatal error, cold reset required\n");
773
+
774
+
*reset_required = false;
775
+
}
776
+
777
+
static bool adf_gen6_handle_interrupt(struct adf_accel_dev *accel_dev, bool *reset_required)
778
+
{
779
+
void __iomem *csr = adf_get_pmisc_base(accel_dev);
780
+
bool handled = false;
781
+
u32 errsou;
782
+
783
+
errsou = ADF_CSR_RD(csr, ADF_GEN6_ERRSOU0);
784
+
if (errsou & ADF_GEN6_ERRSOU0_MASK) {
785
+
adf_gen6_process_errsou0(accel_dev, csr);
786
+
handled = true;
787
+
}
788
+
789
+
errsou = ADF_CSR_RD(csr, ADF_GEN6_ERRSOU1);
790
+
if (errsou & ADF_GEN6_ERRSOU1_MASK) {
791
+
adf_gen6_process_errsou1(accel_dev, csr, errsou);
792
+
handled = true;
793
+
}
794
+
795
+
errsou = ADF_CSR_RD(csr, ADF_GEN6_ERRSOU2);
796
+
if (errsou & ADF_GEN6_ERRSOU2_MASK) {
797
+
adf_gen6_process_errsou2(accel_dev, csr, errsou);
798
+
handled = true;
799
+
}
800
+
801
+
errsou = ADF_CSR_RD(csr, ADF_GEN6_ERRSOU3);
802
+
if (errsou & ADF_GEN6_ERRSOU3_MASK) {
803
+
adf_gen6_process_errsou3(accel_dev, csr, errsou);
804
+
handled = true;
805
+
}
806
+
807
+
adf_gen6_is_reset_required(accel_dev, csr, reset_required);
808
+
809
+
return handled;
810
+
}
811
+
812
+
void adf_gen6_init_ras_ops(struct adf_ras_ops *ras_ops)
813
+
{
814
+
ras_ops->enable_ras_errors = adf_gen6_enable_ras;
815
+
ras_ops->disable_ras_errors = adf_gen6_disable_ras;
816
+
ras_ops->handle_interrupt = adf_gen6_handle_interrupt;
817
+
}
818
+
EXPORT_SYMBOL_GPL(adf_gen6_init_ras_ops);
+504
drivers/crypto/intel/qat/qat_common/adf_gen6_ras.h
+504
drivers/crypto/intel/qat/qat_common/adf_gen6_ras.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/* Copyright(c) 2025 Intel Corporation */
3
+
#ifndef ADF_GEN6_RAS_H_
4
+
#define ADF_GEN6_RAS_H_
5
+
6
+
#include <linux/bits.h>
7
+
8
+
struct adf_ras_ops;
9
+
10
+
/* Error source registers */
11
+
#define ADF_GEN6_ERRSOU0 0x41A200
12
+
#define ADF_GEN6_ERRSOU1 0x41A204
13
+
#define ADF_GEN6_ERRSOU2 0x41A208
14
+
#define ADF_GEN6_ERRSOU3 0x41A20C
15
+
16
+
/* Error source mask registers */
17
+
#define ADF_GEN6_ERRMSK0 0x41A210
18
+
#define ADF_GEN6_ERRMSK1 0x41A214
19
+
#define ADF_GEN6_ERRMSK2 0x41A218
20
+
#define ADF_GEN6_ERRMSK3 0x41A21C
21
+
22
+
/* ERRSOU0 Correctable error mask */
23
+
#define ADF_GEN6_ERRSOU0_MASK BIT(0)
24
+
25
+
#define ADF_GEN6_ERRSOU1_CPP0_MEUNC_BIT BIT(0)
26
+
#define ADF_GEN6_ERRSOU1_CPP_CMDPARERR_BIT BIT(1)
27
+
#define ADF_GEN6_ERRSOU1_RIMEM_PARERR_STS_BIT BIT(2)
28
+
#define ADF_GEN6_ERRSOU1_TIMEM_PARERR_STS_BIT BIT(3)
29
+
#define ADF_GEN6_ERRSOU1_SFICMD_PARERR_BIT BIT(4)
30
+
31
+
#define ADF_GEN6_ERRSOU1_MASK ( \
32
+
(ADF_GEN6_ERRSOU1_CPP0_MEUNC_BIT) | \
33
+
(ADF_GEN6_ERRSOU1_CPP_CMDPARERR_BIT) | \
34
+
(ADF_GEN6_ERRSOU1_RIMEM_PARERR_STS_BIT) | \
35
+
(ADF_GEN6_ERRSOU1_TIMEM_PARERR_STS_BIT) | \
36
+
(ADF_GEN6_ERRSOU1_SFICMD_PARERR_BIT))
37
+
38
+
#define ADF_GEN6_ERRMSK1_CPP0_MEUNC_BIT BIT(0)
39
+
#define ADF_GEN6_ERRMSK1_CPP_CMDPARERR_BIT BIT(1)
40
+
#define ADF_GEN6_ERRMSK1_RIMEM_PARERR_STS_BIT BIT(2)
41
+
#define ADF_GEN6_ERRMSK1_TIMEM_PARERR_STS_BIT BIT(3)
42
+
#define ADF_GEN6_ERRMSK1_IOSFCMD_PARERR_BIT BIT(4)
43
+
44
+
#define ADF_GEN6_ERRMSK1_MASK ( \
45
+
(ADF_GEN6_ERRMSK1_CPP0_MEUNC_BIT) | \
46
+
(ADF_GEN6_ERRMSK1_CPP_CMDPARERR_BIT) | \
47
+
(ADF_GEN6_ERRMSK1_RIMEM_PARERR_STS_BIT) | \
48
+
(ADF_GEN6_ERRMSK1_TIMEM_PARERR_STS_BIT) | \
49
+
(ADF_GEN6_ERRMSK1_IOSFCMD_PARERR_BIT))
50
+
51
+
/* HI AE Uncorrectable error log */
52
+
#define ADF_GEN6_HIAEUNCERRLOG_CPP0 0x41A300
53
+
54
+
/* HI AE Uncorrectable error log enable */
55
+
#define ADF_GEN6_HIAEUNCERRLOGENABLE_CPP0 0x41A320
56
+
57
+
/* HI AE Correctable error log */
58
+
#define ADF_GEN6_HIAECORERRLOG_CPP0 0x41A308
59
+
60
+
/* HI AE Correctable error log enable */
61
+
#define ADF_GEN6_HIAECORERRLOGENABLE_CPP0 0x41A318
62
+
63
+
/* HI CPP Agent Command parity error log */
64
+
#define ADF_GEN6_HICPPAGENTCMDPARERRLOG 0x41A310
65
+
66
+
/* HI CPP Agent command parity error logging enable */
67
+
#define ADF_GEN6_HICPPAGENTCMDPARERRLOGENABLE 0x41A314
68
+
69
+
#define ADF_6XXX_HICPPAGENTCMDPARERRLOG_MASK 0x1B
70
+
71
+
/* RI Memory parity error status register */
72
+
#define ADF_GEN6_RIMEM_PARERR_STS 0x41B128
73
+
74
+
/* RI Memory parity error reporting enable */
75
+
#define ADF_GEN6_RI_MEM_PAR_ERR_EN0 0x41B12C
76
+
77
+
/*
78
+
* RI Memory parity error mask
79
+
* BIT(4) - ri_tlq_phdr parity error
80
+
* BIT(5) - ri_tlq_pdata parity error
81
+
* BIT(6) - ri_tlq_nphdr parity error
82
+
* BIT(7) - ri_tlq_npdata parity error
83
+
* BIT(8) - ri_tlq_cplhdr parity error
84
+
* BIT(10) - BIT(13) - ri_tlq_cpldata[0:3] parity error
85
+
* BIT(19) - ri_cds_cmd_fifo parity error
86
+
* BIT(20) - ri_obc_ricpl_fifo parity error
87
+
* BIT(21) - ri_obc_tiricpl_fifo parity error
88
+
* BIT(22) - ri_obc_cppcpl_fifo parity error
89
+
* BIT(23) - ri_obc_pendcpl_fifo parity error
90
+
* BIT(24) - ri_cpp_cmd_fifo parity error
91
+
* BIT(25) - ri_cds_ticmd_fifo parity error
92
+
* BIT(26) - riti_cmd_fifo parity error
93
+
* BIT(27) - ri_int_msixtbl parity error
94
+
* BIT(28) - ri_int_imstbl parity error
95
+
* BIT(30) - ri_kpt_fuses parity error
96
+
*/
97
+
#define ADF_GEN6_RIMEM_PARERR_FATAL_MASK \
98
+
(BIT(0) | BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(6) | \
99
+
BIT(7) | BIT(8) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | \
100
+
BIT(22) | BIT(23) | BIT(24) | BIT(25) | BIT(26) | BIT(27) | \
101
+
BIT(28) | BIT(30))
102
+
103
+
#define ADF_GEN6_RIMEM_PARERR_CERR_MASK \
104
+
(BIT(10) | BIT(11) | BIT(12) | BIT(13))
105
+
106
+
/* TI CI parity status */
107
+
#define ADF_GEN6_TI_CI_PAR_STS 0x50060C
108
+
109
+
/* TI CI parity reporting mask */
110
+
#define ADF_GEN6_TI_CI_PAR_ERR_MASK 0x500608
111
+
112
+
/*
113
+
* TI CI parity status mask
114
+
* BIT(0) - CdCmdQ_sts patiry error status
115
+
* BIT(1) - CdDataQ_sts parity error status
116
+
* BIT(3) - CPP_SkidQ_sts parity error status
117
+
*/
118
+
#define ADF_GEN6_TI_CI_PAR_STS_MASK \
119
+
(BIT(0) | BIT(1) | BIT(3))
120
+
121
+
/* TI PULLFUB parity status */
122
+
#define ADF_GEN6_TI_PULL0FUB_PAR_STS 0x500618
123
+
124
+
/* TI PULLFUB parity error reporting mask */
125
+
#define ADF_GEN6_TI_PULL0FUB_PAR_ERR_MASK 0x500614
126
+
127
+
/*
128
+
* TI PULLFUB parity status mask
129
+
* BIT(0) - TrnPullReqQ_sts parity status
130
+
* BIT(1) - TrnSharedDataQ_sts parity status
131
+
* BIT(2) - TrnPullReqDataQ_sts parity status
132
+
* BIT(4) - CPP_CiPullReqQ_sts parity status
133
+
* BIT(5) - CPP_TrnPullReqQ_sts parity status
134
+
* BIT(6) - CPP_PullidQ_sts parity status
135
+
* BIT(7) - CPP_WaitDataQ_sts parity status
136
+
* BIT(8) - CPP_CdDataQ_sts parity status
137
+
* BIT(9) - CPP_TrnDataQP0_sts parity status
138
+
* BIT(10) - BIT(11) - CPP_TrnDataQRF[00:01]_sts parity status
139
+
* BIT(12) - CPP_TrnDataQP1_sts parity status
140
+
* BIT(13) - BIT(14) - CPP_TrnDataQRF[10:11]_sts parity status
141
+
*/
142
+
#define ADF_GEN6_TI_PULL0FUB_PAR_STS_MASK \
143
+
(BIT(0) | BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | \
144
+
BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14))
145
+
146
+
/* TI PUSHUB parity status */
147
+
#define ADF_GEN6_TI_PUSHFUB_PAR_STS 0x500630
148
+
149
+
/* TI PUSHFUB parity error reporting mask */
150
+
#define ADF_GEN6_TI_PUSHFUB_PAR_ERR_MASK 0x50062C
151
+
152
+
/*
153
+
* TI PUSHUB parity status mask
154
+
* BIT(0) - SbPushReqQ_sts parity status
155
+
* BIT(1) - BIT(2) - SbPushDataQ[0:1]_sts parity status
156
+
* BIT(4) - CPP_CdPushReqQ_sts parity status
157
+
* BIT(5) - BIT(6) - CPP_CdPushDataQ[0:1]_sts parity status
158
+
* BIT(7) - CPP_SbPushReqQ_sts parity status
159
+
* BIT(8) - CPP_SbPushDataQP_sts parity status
160
+
* BIT(9) - BIT(10) - CPP_SbPushDataQRF[0:1]_sts parity status
161
+
*/
162
+
#define ADF_GEN6_TI_PUSHFUB_PAR_STS_MASK \
163
+
(BIT(0) | BIT(1) | BIT(2) | BIT(4) | BIT(5) | \
164
+
BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10))
165
+
166
+
/* TI CD parity status */
167
+
#define ADF_GEN6_TI_CD_PAR_STS 0x50063C
168
+
169
+
/* TI CD parity error mask */
170
+
#define ADF_GEN6_TI_CD_PAR_ERR_MASK 0x500638
171
+
172
+
/*
173
+
* TI CD parity status mask
174
+
* BIT(0) - BIT(15) - CtxMdRam[0:15]_sts parity status
175
+
* BIT(16) - Leaf2ClusterRam_sts parity status
176
+
* BIT(17) - BIT(18) - Ring2LeafRam[0:1]_sts parity status
177
+
* BIT(19) - VirtualQ_sts parity status
178
+
* BIT(20) - DtRdQ_sts parity status
179
+
* BIT(21) - DtWrQ_sts parity status
180
+
* BIT(22) - RiCmdQ_sts parity status
181
+
* BIT(23) - BypassQ_sts parity status
182
+
* BIT(24) - DtRdQ_sc_sts parity status
183
+
* BIT(25) - DtWrQ_sc_sts parity status
184
+
*/
185
+
#define ADF_GEN6_TI_CD_PAR_STS_MASK \
186
+
(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | \
187
+
BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | \
188
+
BIT(14) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | \
189
+
BIT(21) | BIT(22) | BIT(23) | BIT(24) | BIT(25))
190
+
191
+
/* TI TRNSB parity status */
192
+
#define ADF_GEN6_TI_TRNSB_PAR_STS 0x500648
193
+
194
+
/* TI TRNSB parity error reporting mask */
195
+
#define ADF_GEN6_TI_TRNSB_PAR_ERR_MASK 0x500644
196
+
197
+
/*
198
+
* TI TRNSB parity status mask
199
+
* BIT(0) - TrnPHdrQP_sts parity status
200
+
* BIT(1) - TrnPHdrQRF_sts parity status
201
+
* BIT(2) - TrnPDataQP_sts parity status
202
+
* BIT(3) - BIT(6) - TrnPDataQRF[0:3]_sts parity status
203
+
* BIT(7) - TrnNpHdrQP_sts parity status
204
+
* BIT(8) - BIT(9) - TrnNpHdrQRF[0:1]_sts parity status
205
+
* BIT(10) - TrnCplHdrQ_sts parity status
206
+
* BIT(11) - TrnPutObsReqQ_sts parity status
207
+
* BIT(12) - TrnPushReqQ_sts parity status
208
+
* BIT(13) - SbSplitIdRam_sts parity status
209
+
* BIT(14) - SbReqCountQ_sts parity status
210
+
* BIT(15) - SbCplTrkRam_sts parity status
211
+
* BIT(16) - SbGetObsReqQ_sts parity status
212
+
* BIT(17) - SbEpochIdQ_sts parity status
213
+
* BIT(18) - SbAtCplHdrQ_sts parity status
214
+
* BIT(19) - SbAtCplDataQ_sts parity status
215
+
* BIT(20) - SbReqCountRam_sts parity status
216
+
* BIT(21) - SbAtCplHdrQ_sc_sts parity status
217
+
*/
218
+
#define ADF_GEN6_TI_TRNSB_PAR_STS_MASK \
219
+
(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | \
220
+
BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12) | \
221
+
BIT(13) | BIT(14) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | \
222
+
BIT(19) | BIT(20) | BIT(21))
223
+
224
+
/* Status register to log misc error on RI */
225
+
#define ADF_GEN6_RIMISCSTS 0x41B1B8
226
+
227
+
/* Status control register to log misc RI error */
228
+
#define ADF_GEN6_RIMISCCTL 0x41B1BC
229
+
230
+
/*
231
+
* ERRSOU2 bit mask
232
+
* BIT(0) - SSM Interrupt Mask
233
+
* BIT(1) - CFC on CPP. ORed of CFC Push error and Pull error
234
+
* BIT(2) - BIT(4) - CPP attention interrupts
235
+
* BIT(18) - PM interrupt
236
+
*/
237
+
#define ADF_GEN6_ERRSOU2_SSM_ERR_BIT BIT(0)
238
+
#define ADF_GEN6_ERRSOU2_CPP_CFC_ERR_STATUS_BIT BIT(1)
239
+
#define ADF_GEN6_ERRSOU2_CPP_CFC_ATT_INT_MASK \
240
+
(BIT(2) | BIT(3) | BIT(4))
241
+
242
+
#define ADF_GEN6_ERRSOU2_PM_INT_BIT BIT(18)
243
+
244
+
#define ADF_GEN6_ERRSOU2_MASK \
245
+
(ADF_GEN6_ERRSOU2_SSM_ERR_BIT | \
246
+
ADF_GEN6_ERRSOU2_CPP_CFC_ERR_STATUS_BIT)
247
+
248
+
#define ADF_GEN6_ERRSOU2_DIS_MASK \
249
+
(ADF_GEN6_ERRSOU2_SSM_ERR_BIT | \
250
+
ADF_GEN6_ERRSOU2_CPP_CFC_ERR_STATUS_BIT | \
251
+
ADF_GEN6_ERRSOU2_CPP_CFC_ATT_INT_MASK)
252
+
253
+
#define ADF_GEN6_IAINTSTATSSM 0x28
254
+
255
+
/* IAINTSTATSSM error bit mask definitions */
256
+
#define ADF_GEN6_IAINTSTATSSM_SH_ERR_BIT BIT(0)
257
+
#define ADF_GEN6_IAINTSTATSSM_PPERR_BIT BIT(2)
258
+
#define ADF_GEN6_IAINTSTATSSM_SCMPAR_ERR_BIT BIT(4)
259
+
#define ADF_GEN6_IAINTSTATSSM_CPPPAR_ERR_BIT BIT(5)
260
+
#define ADF_GEN6_IAINTSTATSSM_RFPAR_ERR_BIT BIT(6)
261
+
#define ADF_GEN6_IAINTSTATSSM_UNEXP_CPL_ERR_BIT BIT(7)
262
+
263
+
#define ADF_GEN6_IAINTSTATSSM_MASK \
264
+
(ADF_GEN6_IAINTSTATSSM_SH_ERR_BIT | \
265
+
ADF_GEN6_IAINTSTATSSM_PPERR_BIT | \
266
+
ADF_GEN6_IAINTSTATSSM_SCMPAR_ERR_BIT | \
267
+
ADF_GEN6_IAINTSTATSSM_CPPPAR_ERR_BIT | \
268
+
ADF_GEN6_IAINTSTATSSM_RFPAR_ERR_BIT | \
269
+
ADF_GEN6_IAINTSTATSSM_UNEXP_CPL_ERR_BIT)
270
+
271
+
#define ADF_GEN6_UERRSSMSH 0x18
272
+
273
+
/*
274
+
* UERRSSMSH error bit mask definitions
275
+
*
276
+
* BIT(0) - Indicates one uncorrectable error
277
+
* BIT(15) - Indicates multiple uncorrectable errors
278
+
* in device shared memory
279
+
*/
280
+
#define ADF_GEN6_UERRSSMSH_MASK (BIT(0) | BIT(15))
281
+
282
+
/*
283
+
* CERRSSMSH error bit
284
+
* BIT(0) - Indicates one correctable error
285
+
*/
286
+
#define ADF_GEN6_CERRSSMSH_ERROR_BIT (BIT(0) | BIT(15) | BIT(24))
287
+
#define ADF_GEN6_CERRSSMSH 0x10
288
+
289
+
#define ADF_GEN6_INTMASKSSM 0x0
290
+
291
+
/*
292
+
* Error reporting mask in INTMASKSSM
293
+
* BIT(0) - Shared memory uncorrectable interrupt mask
294
+
* BIT(2) - PPERR interrupt mask
295
+
* BIT(4) - SCM parity error interrupt mask
296
+
* BIT(5) - CPP parity error interrupt mask
297
+
* BIT(6) - SHRAM RF parity error interrupt mask
298
+
* BIT(7) - AXI unexpected completion error mask
299
+
*/
300
+
#define ADF_GEN6_INTMASKSSM_MASK \
301
+
(BIT(0) | BIT(2) | BIT(4) | BIT(5) | BIT(6) | BIT(7))
302
+
303
+
/* CPP push or pull error */
304
+
#define ADF_GEN6_PPERR 0x8
305
+
306
+
#define ADF_GEN6_PPERR_MASK (BIT(0) | BIT(1))
307
+
308
+
/*
309
+
* SSM_FERR_STATUS error bit mask definitions
310
+
*/
311
+
#define ADF_GEN6_SCM_PAR_ERR_MASK BIT(5)
312
+
#define ADF_GEN6_CPP_PAR_ERR_MASK (BIT(0) | BIT(1) | BIT(2))
313
+
#define ADF_GEN6_UNEXP_CPL_ERR_MASK (BIT(3) | BIT(4) | BIT(10) | BIT(11))
314
+
#define ADF_GEN6_RF_PAR_ERR_MASK BIT(16)
315
+
316
+
#define ADF_GEN6_SSM_FERR_STATUS 0x9C
317
+
318
+
#define ADF_GEN6_CPP_CFC_ERR_STATUS 0x640C04
319
+
320
+
/*
321
+
* BIT(0) - Indicates one or more CPP CFC errors
322
+
* BIT(1) - Indicates multiple CPP CFC errors
323
+
* BIT(7) - Indicates CPP CFC command parity error type
324
+
* BIT(8) - Indicates CPP CFC data parity error type
325
+
*/
326
+
#define ADF_GEN6_CPP_CFC_ERR_STATUS_ERR_BIT BIT(0)
327
+
#define ADF_GEN6_CPP_CFC_ERR_STATUS_MERR_BIT BIT(1)
328
+
#define ADF_GEN6_CPP_CFC_ERR_STATUS_CMDPAR_BIT BIT(7)
329
+
#define ADF_GEN6_CPP_CFC_ERR_STATUS_DATAPAR_BIT BIT(8)
330
+
#define ADF_GEN6_CPP_CFC_FATAL_ERR_BIT \
331
+
(ADF_GEN6_CPP_CFC_ERR_STATUS_ERR_BIT | \
332
+
ADF_GEN6_CPP_CFC_ERR_STATUS_MERR_BIT)
333
+
334
+
/*
335
+
* BIT(0) - Enables CFC to detect and log a push/pull data error
336
+
* BIT(1) - Enables CFC to generate interrupt to PCIEP for a CPP error
337
+
* BIT(4) - When 1 parity detection is disabled
338
+
* BIT(5) - When 1 parity detection is disabled on CPP command bus
339
+
* BIT(6) - When 1 parity detection is disabled on CPP push/pull bus
340
+
* BIT(9) - When 1 RF parity error detection is disabled
341
+
*/
342
+
#define ADF_GEN6_CPP_CFC_ERR_CTRL_MASK (BIT(0) | BIT(1))
343
+
344
+
#define ADF_GEN6_CPP_CFC_ERR_CTRL_DIS_MASK \
345
+
(BIT(4) | BIT(5) | BIT(6) | BIT(9) | BIT(10))
346
+
347
+
#define ADF_GEN6_CPP_CFC_ERR_CTRL 0x640C00
348
+
349
+
/*
350
+
* BIT(0) - Clears bit(0) of ADF_GEN6_CPP_CFC_ERR_STATUS
351
+
* when an error is reported on CPP
352
+
* BIT(1) - Clears bit(1) of ADF_GEN6_CPP_CFC_ERR_STATUS
353
+
* when multiple errors are reported on CPP
354
+
* BIT(2) - Clears bit(2) of ADF_GEN6_CPP_CFC_ERR_STATUS
355
+
* when attention interrupt is reported
356
+
*/
357
+
#define ADF_GEN6_CPP_CFC_ERR_STATUS_CLR_MASK (BIT(0) | BIT(1) | BIT(2))
358
+
#define ADF_GEN6_CPP_CFC_ERR_STATUS_CLR 0x640C08
359
+
360
+
/*
361
+
* ERRSOU3 bit masks
362
+
* BIT(0) - indicates error response order overflow and/or BME error
363
+
* BIT(1) - indicates RI push/pull error
364
+
* BIT(2) - indicates TI push/pull error
365
+
* BIT(5) - indicates TI pull parity error
366
+
* BIT(6) - indicates RI push parity error
367
+
* BIT(7) - indicates VFLR interrupt
368
+
* BIT(8) - indicates ring pair interrupts for ATU detected fault
369
+
* BIT(9) - indicates rate limiting error
370
+
*/
371
+
#define ADF_GEN6_ERRSOU3_TIMISCSTS_BIT BIT(0)
372
+
#define ADF_GEN6_ERRSOU3_RICPPINTSTS_MASK (BIT(1) | BIT(6))
373
+
#define ADF_GEN6_ERRSOU3_TICPPINTSTS_MASK (BIT(2) | BIT(5))
374
+
#define ADF_GEN6_ERRSOU3_VFLRNOTIFY_BIT BIT(7)
375
+
#define ADF_GEN6_ERRSOU3_ATUFAULTSTATUS_BIT BIT(8)
376
+
#define ADF_GEN6_ERRSOU3_RLTERROR_BIT BIT(9)
377
+
#define ADF_GEN6_ERRSOU3_TC_VC_MAP_ERROR_BIT BIT(16)
378
+
#define ADF_GEN6_ERRSOU3_PCIE_DEVHALT_BIT BIT(17)
379
+
#define ADF_GEN6_ERRSOU3_PG_REQ_DEVHALT_BIT BIT(18)
380
+
#define ADF_GEN6_ERRSOU3_XLT_CPL_DEVHALT_BIT BIT(19)
381
+
#define ADF_GEN6_ERRSOU3_TI_INT_ERR_DEVHALT_BIT BIT(20)
382
+
383
+
#define ADF_GEN6_ERRSOU3_MASK ( \
384
+
(ADF_GEN6_ERRSOU3_TIMISCSTS_BIT) | \
385
+
(ADF_GEN6_ERRSOU3_RICPPINTSTS_MASK) | \
386
+
(ADF_GEN6_ERRSOU3_TICPPINTSTS_MASK) | \
387
+
(ADF_GEN6_ERRSOU3_VFLRNOTIFY_BIT) | \
388
+
(ADF_GEN6_ERRSOU3_ATUFAULTSTATUS_BIT) | \
389
+
(ADF_GEN6_ERRSOU3_RLTERROR_BIT) | \
390
+
(ADF_GEN6_ERRSOU3_TC_VC_MAP_ERROR_BIT) | \
391
+
(ADF_GEN6_ERRSOU3_PCIE_DEVHALT_BIT) | \
392
+
(ADF_GEN6_ERRSOU3_PG_REQ_DEVHALT_BIT) | \
393
+
(ADF_GEN6_ERRSOU3_XLT_CPL_DEVHALT_BIT) | \
394
+
(ADF_GEN6_ERRSOU3_TI_INT_ERR_DEVHALT_BIT))
395
+
396
+
#define ADF_GEN6_ERRSOU3_DIS_MASK ( \
397
+
(ADF_GEN6_ERRSOU3_TIMISCSTS_BIT) | \
398
+
(ADF_GEN6_ERRSOU3_RICPPINTSTS_MASK) | \
399
+
(ADF_GEN6_ERRSOU3_TICPPINTSTS_MASK) | \
400
+
(ADF_GEN6_ERRSOU3_VFLRNOTIFY_BIT) | \
401
+
(ADF_GEN6_ERRSOU3_ATUFAULTSTATUS_BIT) | \
402
+
(ADF_GEN6_ERRSOU3_RLTERROR_BIT) | \
403
+
(ADF_GEN6_ERRSOU3_TC_VC_MAP_ERROR_BIT))
404
+
405
+
/* Rate limiting error log register */
406
+
#define ADF_GEN6_RLT_ERRLOG 0x508814
407
+
408
+
#define ADF_GEN6_RLT_ERRLOG_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
409
+
410
+
/* TI misc status register */
411
+
#define ADF_GEN6_TIMISCSTS 0x50054C
412
+
413
+
/* TI misc error reporting mask */
414
+
#define ADF_GEN6_TIMISCCTL 0x500548
415
+
416
+
/*
417
+
* TI Misc error reporting control mask
418
+
* BIT(0) - Enables error detection and logging in TIMISCSTS register
419
+
* BIT(1) - It has effect only when SRIOV enabled, this bit is 0 by default
420
+
* BIT(2) - Enables the D-F-x counter within the dispatch arbiter
421
+
* to start based on the command triggered from
422
+
* BIT(30) - Disables VFLR functionality
423
+
* bits 1, 2 and 30 value should be preserved and not meant to be changed
424
+
* within RAS.
425
+
*/
426
+
#define ADF_GEN6_TIMISCCTL_BIT BIT(0)
427
+
#define ADF_GEN6_TIMSCCTL_RELAY_MASK (BIT(1) | BIT(2) | BIT(30))
428
+
429
+
/* RI CPP interface status register */
430
+
#define ADF_GEN6_RICPPINTSTS 0x41A330
431
+
432
+
/*
433
+
* Uncorrectable error mask in RICPPINTSTS register
434
+
* BIT(0) - RI asserted the CPP error signal during a push
435
+
* BIT(1) - RI detected the CPP error signal asserted during a pull
436
+
* BIT(2) - RI detected a push data parity error
437
+
* BIT(3) - RI detected a push valid parity error
438
+
*/
439
+
#define ADF_GEN6_RICPPINTSTS_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
440
+
441
+
/* RI CPP interface register control */
442
+
#define ADF_GEN6_RICPPINTCTL 0x41A32C
443
+
444
+
/*
445
+
* Control bit mask for RICPPINTCTL register
446
+
* BIT(0) - value of 1 enables error detection and reporting
447
+
* on the RI CPP Push interface
448
+
* BIT(1) - value of 1 enables error detection and reporting
449
+
* on the RI CPP Pull interface
450
+
* BIT(2) - value of 1 enables error detection and reporting
451
+
* on the RI Parity
452
+
* BIT(3) - value of 1 enable checking parity on CPP
453
+
*/
454
+
#define ADF_GEN6_RICPPINTCTL_MASK \
455
+
(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4))
456
+
457
+
/* TI CPP interface status register */
458
+
#define ADF_GEN6_TICPPINTSTS 0x50053C
459
+
460
+
/*
461
+
* Uncorrectable error mask in TICPPINTSTS register
462
+
* BIT(0) - value of 1 indicates that the TI asserted
463
+
* the CPP error signal during a push
464
+
* BIT(1) - value of 1 indicates that the TI detected
465
+
* the CPP error signal asserted during a pull
466
+
* BIT(2) - value of 1 indicates that the TI detected
467
+
* a pull data parity error
468
+
*/
469
+
#define ADF_GEN6_TICPPINTSTS_MASK (BIT(0) | BIT(1) | BIT(2))
470
+
471
+
/* TI CPP interface status register control */
472
+
#define ADF_GEN6_TICPPINTCTL 0x500538
473
+
474
+
/*
475
+
* Control bit mask for TICPPINTCTL register
476
+
* BIT(0) - value of 1 enables error detection and reporting on
477
+
* the TI CPP Push interface
478
+
* BIT(1) - value of 1 enables error detection and reporting on
479
+
* the TI CPP Push interface
480
+
* BIT(2) - value of 1 enables parity error detection and logging on
481
+
* the TI CPP Pull interface
482
+
* BIT(3) - value of 1 enables CPP CMD and Pull Data parity checking
483
+
*/
484
+
#define ADF_GEN6_TICPPINTCTL_MASK \
485
+
(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4))
486
+
487
+
/* ATU fault status register */
488
+
#define ADF_GEN6_ATUFAULTSTATUS(i) (0x506000 + ((i) * 0x4))
489
+
490
+
#define ADF_GEN6_ATUFAULTSTATUS_BIT BIT(0)
491
+
492
+
/* Command parity error detected on IOSFP command to QAT */
493
+
#define ADF_GEN6_RIMISCSTS_BIT BIT(0)
494
+
495
+
#define ADF_GEN6_GENSTS 0x41A220
496
+
#define ADF_GEN6_GENSTS_DEVICE_STATE_MASK GENMASK(1, 0)
497
+
#define ADF_GEN6_GENSTS_RESET_TYPE_MASK GENMASK(3, 2)
498
+
#define ADF_GEN6_GENSTS_PFLR 0x1
499
+
#define ADF_GEN6_GENSTS_COLD_RESET 0x3
500
+
#define ADF_GEN6_GENSTS_DEVHALT 0x1
501
+
502
+
void adf_gen6_init_ras_ops(struct adf_ras_ops *ras_ops);
503
+
504
+
#endif /* ADF_GEN6_RAS_H_ */