Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6:
sparc32, leon: bugfix in LEON SMP interrupt init
sparc32, sun4m: bugfix in SMP IPI traphandler
sparc: Remove unnecessary semicolons
Add support for allocating irqs for bootbus devices
Do not skip interrupt sources in sun4d interrupt handler and acknowledge interrupts correctly
Restructure sun4d_build_device_irq so that timer interrupts can be allocated
sparc: PCIC_PCI needs SPARC32 dependency
sparc: Do not select GENERIC_HARDIRQS_NO_DEPRECATED
sparc32,leon: add GRPCI2 PCI Host driver
sparc32,leon: added LEON-common low-level PCI routines
sparc32: added CONFIG_PCIC_PCI Kconfig setting
+1414
-130
+17
-1
arch/sparc/Kconfig
+17
-1
arch/sparc/Kconfig
···
26
26
select HAVE_DMA_API_DEBUG
27
27
select HAVE_ARCH_JUMP_LABEL
28
28
select HAVE_GENERIC_HARDIRQS
29
-
select GENERIC_HARDIRQS_NO_DEPRECATED
30
29
select GENERIC_IRQ_SHOW
31
30
select USE_GENERIC_SMP_HELPERS if SMP
32
31
···
526
527
527
528
config PCI_SYSCALL
528
529
def_bool PCI
530
+
531
+
config PCIC_PCI
532
+
bool
533
+
depends on PCI && SPARC32 && !SPARC_LEON
534
+
default y
535
+
536
+
config LEON_PCI
537
+
bool
538
+
depends on PCI && SPARC_LEON
539
+
default y
540
+
541
+
config GRPCI2
542
+
bool "GRPCI2 Host Bridge Support"
543
+
depends on LEON_PCI
544
+
default y
545
+
help
546
+
Say Y here to include the GRPCI2 Host Bridge Driver.
529
547
530
548
source "drivers/pci/Kconfig"
531
549
+4
-4
arch/sparc/include/asm/floppy_32.h
+4
-4
arch/sparc/include/asm/floppy_32.h
···
138
138
return sun_fdc->data_82072;
139
139
case 7: /* FD_DIR */
140
140
return sun_read_dir();
141
-
};
141
+
}
142
142
panic("sun_82072_fd_inb: How did I get here?");
143
143
}
144
144
···
161
161
case 4: /* FD_STATUS */
162
162
sun_fdc->status_82072 = value;
163
163
break;
164
-
};
164
+
}
165
165
return;
166
166
}
167
167
···
186
186
return sun_fdc->data_82077;
187
187
case 7: /* FD_DIR */
188
188
return sun_read_dir();
189
-
};
189
+
}
190
190
panic("sun_82077_fd_inb: How did I get here?");
191
191
}
192
192
···
212
212
case 3: /* FD_TDR */
213
213
sun_fdc->tapectl_82077 = value;
214
214
break;
215
-
};
215
+
}
216
216
return;
217
217
}
218
218
+2
-2
arch/sparc/include/asm/floppy_64.h
+2
-2
arch/sparc/include/asm/floppy_64.h
···
111
111
case 7: /* FD_DIR */
112
112
/* XXX: Is DCL on 0x80 in sun4m? */
113
113
return sbus_readb(&sun_fdc->dir_82077);
114
-
};
114
+
}
115
115
panic("sun_82072_fd_inb: How did I get here?");
116
116
}
117
117
···
135
135
case 4: /* FD_STATUS */
136
136
sbus_writeb(value, &sun_fdc->status_82077);
137
137
break;
138
-
};
138
+
}
139
139
return;
140
140
}
141
141
+3
arch/sparc/include/asm/leon.h
+3
arch/sparc/include/asm/leon.h
···
318
318
extern unsigned int leon_build_device_irq(unsigned int real_irq,
319
319
irq_flow_handler_t flow_handler,
320
320
const char *name, int do_ack);
321
+
extern void leon_update_virq_handling(unsigned int virq,
322
+
irq_flow_handler_t flow_handler,
323
+
const char *name, int do_ack);
321
324
extern void leon_clear_clock_irq(void);
322
325
extern void leon_load_profile_irq(int cpu, unsigned int limit);
323
326
extern void leon_init_timers(irq_handler_t counter_fn);
+21
arch/sparc/include/asm/leon_pci.h
+21
arch/sparc/include/asm/leon_pci.h
···
1
+
/*
2
+
* asm/leon_pci.h
3
+
*
4
+
* Copyright (C) 2011 Aeroflex Gaisler AB, Daniel Hellstrom
5
+
*/
6
+
7
+
#ifndef _ASM_LEON_PCI_H_
8
+
#define _ASM_LEON_PCI_H_
9
+
10
+
/* PCI related definitions */
11
+
struct leon_pci_info {
12
+
struct pci_ops *ops;
13
+
struct resource io_space;
14
+
struct resource mem_space;
15
+
int (*map_irq)(struct pci_dev *dev, u8 slot, u8 pin);
16
+
};
17
+
18
+
extern void leon_pci_init(struct platform_device *ofdev,
19
+
struct leon_pci_info *info);
20
+
21
+
#endif /* _ASM_LEON_PCI_H_ */
+24
arch/sparc/include/asm/pci_32.h
+24
arch/sparc/include/asm/pci_32.h
···
47
47
48
48
#endif /* __KERNEL__ */
49
49
50
+
#ifndef CONFIG_LEON_PCI
50
51
/* generic pci stuff */
51
52
#include <asm-generic/pci.h>
53
+
#else
54
+
/*
55
+
* On LEON PCI Memory space is mapped 1:1 with physical address space.
56
+
*
57
+
* I/O space is located at low 64Kbytes in PCI I/O space. The I/O addresses
58
+
* are converted into CPU addresses to virtual addresses that are mapped with
59
+
* MMU to the PCI Host PCI I/O space window which are translated to the low
60
+
* 64Kbytes by the Host controller.
61
+
*/
62
+
63
+
extern void
64
+
pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
65
+
struct resource *res);
66
+
67
+
extern void
68
+
pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
69
+
struct pci_bus_region *region);
70
+
71
+
static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
72
+
{
73
+
return PCI_IRQ_NONE;
74
+
}
75
+
#endif
52
76
53
77
#endif /* __SPARC_PCI_H */
+1
-1
arch/sparc/include/asm/pcic.h
+1
-1
arch/sparc/include/asm/pcic.h
+1
-1
arch/sparc/include/asm/system_32.h
+1
-1
arch/sparc/include/asm/system_32.h
+1
-1
arch/sparc/include/asm/system_64.h
+1
-1
arch/sparc/include/asm/system_64.h
+3
-1
arch/sparc/kernel/Makefile
+3
-1
arch/sparc/kernel/Makefile
···
73
73
74
74
obj-y += dma.o
75
75
76
-
obj-$(CONFIG_SPARC32_PCI) += pcic.o
76
+
obj-$(CONFIG_PCIC_PCI) += pcic.o
77
+
obj-$(CONFIG_LEON_PCI) += leon_pci.o
78
+
obj-$(CONFIG_GRPCI2) += leon_pci_grpci2.o
77
79
78
80
obj-$(CONFIG_SMP) += trampoline_$(BITS).o smp_$(BITS).o
79
81
obj-$(CONFIG_SPARC32_SMP) += sun4m_smp.o sun4d_smp.o leon_smp.o
+1
-1
arch/sparc/kernel/apc.c
+1
-1
arch/sparc/kernel/apc.c
+1
-1
arch/sparc/kernel/auxio_32.c
+1
-1
arch/sparc/kernel/auxio_32.c
+1
-1
arch/sparc/kernel/chmc.c
+1
-1
arch/sparc/kernel/chmc.c
+4
-4
arch/sparc/kernel/entry.S
+4
-4
arch/sparc/kernel/entry.S
···
229
229
#ifdef CONFIG_SMP
230
230
.globl patchme_maybe_smp_msg
231
231
232
-
cmp %l7, 12
232
+
cmp %l7, 11
233
233
patchme_maybe_smp_msg:
234
234
bgu maybe_smp4m_msg
235
235
nop
···
293
293
WRITE_PAUSE
294
294
wr %l4, PSR_ET, %psr
295
295
WRITE_PAUSE
296
-
sll %o2, 28, %o2 ! shift for simpler checks below
296
+
sll %o3, 28, %o2 ! shift for simpler checks below
297
297
maybe_smp4m_msg_check_single:
298
298
andcc %o2, 0x1, %g0
299
299
beq,a maybe_smp4m_msg_check_mask
···
1604
1604
retl
1605
1605
nop
1606
1606
1607
-
#ifdef CONFIG_PCI
1607
+
#ifdef CONFIG_PCIC_PCI
1608
1608
#include <asm/pcic.h>
1609
1609
1610
1610
.align 4
···
1650
1650
rd %psr, %l0
1651
1651
.word 0
1652
1652
1653
-
#endif /* CONFIG_PCI */
1653
+
#endif /* CONFIG_PCIC_PCI */
1654
1654
1655
1655
.globl flushw_all
1656
1656
flushw_all:
+31
arch/sparc/kernel/leon_kernel.c
+31
arch/sparc/kernel/leon_kernel.c
···
236
236
return leon_build_device_irq(real_irq, handle_simple_irq, "edge", 0);
237
237
}
238
238
239
+
void leon_update_virq_handling(unsigned int virq,
240
+
irq_flow_handler_t flow_handler,
241
+
const char *name, int do_ack)
242
+
{
243
+
unsigned long mask = (unsigned long)irq_get_chip_data(virq);
244
+
245
+
mask &= ~LEON_DO_ACK_HW;
246
+
if (do_ack)
247
+
mask |= LEON_DO_ACK_HW;
248
+
249
+
irq_set_chip_and_handler_name(virq, &leon_irq,
250
+
flow_handler, name);
251
+
irq_set_chip_data(virq, (void *)mask);
252
+
}
253
+
239
254
void __init leon_init_timers(irq_handler_t counter_fn)
240
255
{
241
256
int irq, eirq;
···
375
360
printk(KERN_ERR "unable to attach timer IRQ%d\n", irq);
376
361
prom_halt();
377
362
}
363
+
364
+
#ifdef CONFIG_SMP
365
+
{
366
+
unsigned long flags;
367
+
368
+
/*
369
+
* In SMP, sun4m adds a IPI handler to IRQ trap handler that
370
+
* LEON never must take, sun4d and LEON overwrites the branch
371
+
* with a NOP.
372
+
*/
373
+
local_irq_save(flags);
374
+
patchme_maybe_smp_msg[0] = 0x01000000; /* NOP out the branch */
375
+
local_flush_cache_all();
376
+
local_irq_restore(flags);
377
+
}
378
+
#endif
378
379
379
380
LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl,
380
381
LEON3_GPTIMER_EN |
+253
arch/sparc/kernel/leon_pci.c
+253
arch/sparc/kernel/leon_pci.c
···
1
+
/*
2
+
* leon_pci.c: LEON Host PCI support
3
+
*
4
+
* Copyright (C) 2011 Aeroflex Gaisler AB, Daniel Hellstrom
5
+
*
6
+
* Code is partially derived from pcic.c
7
+
*/
8
+
9
+
#include <linux/of_device.h>
10
+
#include <linux/kernel.h>
11
+
#include <linux/pci.h>
12
+
#include <asm/leon.h>
13
+
#include <asm/leon_pci.h>
14
+
15
+
/* The LEON architecture does not rely on a BIOS or bootloader to setup
16
+
* PCI for us. The Linux generic routines are used to setup resources,
17
+
* reset values of confuration-space registers settings ae preseved.
18
+
*/
19
+
void leon_pci_init(struct platform_device *ofdev, struct leon_pci_info *info)
20
+
{
21
+
struct pci_bus *root_bus;
22
+
23
+
root_bus = pci_scan_bus_parented(&ofdev->dev, 0, info->ops, info);
24
+
if (root_bus) {
25
+
root_bus->resource[0] = &info->io_space;
26
+
root_bus->resource[1] = &info->mem_space;
27
+
root_bus->resource[2] = NULL;
28
+
29
+
/* Init all PCI devices into PCI tree */
30
+
pci_bus_add_devices(root_bus);
31
+
32
+
/* Setup IRQs of all devices using custom routines */
33
+
pci_fixup_irqs(pci_common_swizzle, info->map_irq);
34
+
35
+
/* Assign devices with resources */
36
+
pci_assign_unassigned_resources();
37
+
}
38
+
}
39
+
40
+
/* PCI Memory and Prefetchable Memory is direct-mapped. However I/O Space is
41
+
* accessed through a Window which is translated to low 64KB in PCI space, the
42
+
* first 4KB is not used so 60KB is available.
43
+
*
44
+
* This function is used by generic code to translate resource addresses into
45
+
* PCI addresses.
46
+
*/
47
+
void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
48
+
struct resource *res)
49
+
{
50
+
struct leon_pci_info *info = dev->bus->sysdata;
51
+
52
+
region->start = res->start;
53
+
region->end = res->end;
54
+
55
+
if (res->flags & IORESOURCE_IO) {
56
+
region->start -= (info->io_space.start - 0x1000);
57
+
region->end -= (info->io_space.start - 0x1000);
58
+
}
59
+
}
60
+
EXPORT_SYMBOL(pcibios_resource_to_bus);
61
+
62
+
/* see pcibios_resource_to_bus() comment */
63
+
void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
64
+
struct pci_bus_region *region)
65
+
{
66
+
struct leon_pci_info *info = dev->bus->sysdata;
67
+
68
+
res->start = region->start;
69
+
res->end = region->end;
70
+
71
+
if (res->flags & IORESOURCE_IO) {
72
+
res->start += (info->io_space.start - 0x1000);
73
+
res->end += (info->io_space.start - 0x1000);
74
+
}
75
+
}
76
+
EXPORT_SYMBOL(pcibios_bus_to_resource);
77
+
78
+
void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
79
+
{
80
+
struct leon_pci_info *info = pbus->sysdata;
81
+
struct pci_dev *dev;
82
+
int i, has_io, has_mem;
83
+
u16 cmd;
84
+
85
+
/* Generic PCI bus probing sets these to point at
86
+
* &io{port,mem}_resouce which is wrong for us.
87
+
*/
88
+
if (pbus->self == NULL) {
89
+
pbus->resource[0] = &info->io_space;
90
+
pbus->resource[1] = &info->mem_space;
91
+
pbus->resource[2] = NULL;
92
+
}
93
+
94
+
list_for_each_entry(dev, &pbus->devices, bus_list) {
95
+
/*
96
+
* We can not rely on that the bootloader has enabled I/O
97
+
* or memory access to PCI devices. Instead we enable it here
98
+
* if the device has BARs of respective type.
99
+
*/
100
+
has_io = has_mem = 0;
101
+
for (i = 0; i < PCI_ROM_RESOURCE; i++) {
102
+
unsigned long f = dev->resource[i].flags;
103
+
if (f & IORESOURCE_IO)
104
+
has_io = 1;
105
+
else if (f & IORESOURCE_MEM)
106
+
has_mem = 1;
107
+
}
108
+
/* ROM BARs are mapped into 32-bit memory space */
109
+
if (dev->resource[PCI_ROM_RESOURCE].end != 0) {
110
+
dev->resource[PCI_ROM_RESOURCE].flags |=
111
+
IORESOURCE_ROM_ENABLE;
112
+
has_mem = 1;
113
+
}
114
+
pci_bus_read_config_word(pbus, dev->devfn, PCI_COMMAND, &cmd);
115
+
if (has_io && !(cmd & PCI_COMMAND_IO)) {
116
+
#ifdef CONFIG_PCI_DEBUG
117
+
printk(KERN_INFO "LEONPCI: Enabling I/O for dev %s\n",
118
+
pci_name(dev));
119
+
#endif
120
+
cmd |= PCI_COMMAND_IO;
121
+
pci_bus_write_config_word(pbus, dev->devfn, PCI_COMMAND,
122
+
cmd);
123
+
}
124
+
if (has_mem && !(cmd & PCI_COMMAND_MEMORY)) {
125
+
#ifdef CONFIG_PCI_DEBUG
126
+
printk(KERN_INFO "LEONPCI: Enabling MEMORY for dev"
127
+
"%s\n", pci_name(dev));
128
+
#endif
129
+
cmd |= PCI_COMMAND_MEMORY;
130
+
pci_bus_write_config_word(pbus, dev->devfn, PCI_COMMAND,
131
+
cmd);
132
+
}
133
+
}
134
+
}
135
+
136
+
/*
137
+
* Other archs parse arguments here.
138
+
*/
139
+
char * __devinit pcibios_setup(char *str)
140
+
{
141
+
return str;
142
+
}
143
+
144
+
resource_size_t pcibios_align_resource(void *data, const struct resource *res,
145
+
resource_size_t size, resource_size_t align)
146
+
{
147
+
return res->start;
148
+
}
149
+
150
+
int pcibios_enable_device(struct pci_dev *dev, int mask)
151
+
{
152
+
return pci_enable_resources(dev, mask);
153
+
}
154
+
155
+
struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
156
+
{
157
+
/*
158
+
* Currently the OpenBoot nodes are not connected with the PCI device,
159
+
* this is because the LEON PROM does not create PCI nodes. Eventually
160
+
* this will change and the same approach as pcic.c can be used to
161
+
* match PROM nodes with pci devices.
162
+
*/
163
+
return NULL;
164
+
}
165
+
EXPORT_SYMBOL(pci_device_to_OF_node);
166
+
167
+
void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
168
+
{
169
+
#ifdef CONFIG_PCI_DEBUG
170
+
printk(KERN_DEBUG "LEONPCI: Assigning IRQ %02d to %s\n", irq,
171
+
pci_name(dev));
172
+
#endif
173
+
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
174
+
}
175
+
176
+
/* in/out routines taken from pcic.c
177
+
*
178
+
* This probably belongs here rather than ioport.c because
179
+
* we do not want this crud linked into SBus kernels.
180
+
* Also, think for a moment about likes of floppy.c that
181
+
* include architecture specific parts. They may want to redefine ins/outs.
182
+
*
183
+
* We do not use horrible macros here because we want to
184
+
* advance pointer by sizeof(size).
185
+
*/
186
+
void outsb(unsigned long addr, const void *src, unsigned long count)
187
+
{
188
+
while (count) {
189
+
count -= 1;
190
+
outb(*(const char *)src, addr);
191
+
src += 1;
192
+
/* addr += 1; */
193
+
}
194
+
}
195
+
EXPORT_SYMBOL(outsb);
196
+
197
+
void outsw(unsigned long addr, const void *src, unsigned long count)
198
+
{
199
+
while (count) {
200
+
count -= 2;
201
+
outw(*(const short *)src, addr);
202
+
src += 2;
203
+
/* addr += 2; */
204
+
}
205
+
}
206
+
EXPORT_SYMBOL(outsw);
207
+
208
+
void outsl(unsigned long addr, const void *src, unsigned long count)
209
+
{
210
+
while (count) {
211
+
count -= 4;
212
+
outl(*(const long *)src, addr);
213
+
src += 4;
214
+
/* addr += 4; */
215
+
}
216
+
}
217
+
EXPORT_SYMBOL(outsl);
218
+
219
+
void insb(unsigned long addr, void *dst, unsigned long count)
220
+
{
221
+
while (count) {
222
+
count -= 1;
223
+
*(unsigned char *)dst = inb(addr);
224
+
dst += 1;
225
+
/* addr += 1; */
226
+
}
227
+
}
228
+
EXPORT_SYMBOL(insb);
229
+
230
+
void insw(unsigned long addr, void *dst, unsigned long count)
231
+
{
232
+
while (count) {
233
+
count -= 2;
234
+
*(unsigned short *)dst = inw(addr);
235
+
dst += 2;
236
+
/* addr += 2; */
237
+
}
238
+
}
239
+
EXPORT_SYMBOL(insw);
240
+
241
+
void insl(unsigned long addr, void *dst, unsigned long count)
242
+
{
243
+
while (count) {
244
+
count -= 4;
245
+
/*
246
+
* XXX I am sure we are in for an unaligned trap here.
247
+
*/
248
+
*(unsigned long *)dst = inl(addr);
249
+
dst += 4;
250
+
/* addr += 4; */
251
+
}
252
+
}
253
+
EXPORT_SYMBOL(insl);
+897
arch/sparc/kernel/leon_pci_grpci2.c
+897
arch/sparc/kernel/leon_pci_grpci2.c
···
1
+
/*
2
+
* leon_pci_grpci2.c: GRPCI2 Host PCI driver
3
+
*
4
+
* Copyright (C) 2011 Aeroflex Gaisler AB, Daniel Hellstrom
5
+
*
6
+
*/
7
+
8
+
#include <linux/of_device.h>
9
+
#include <linux/kernel.h>
10
+
#include <linux/pci.h>
11
+
#include <linux/delay.h>
12
+
#include <linux/module.h>
13
+
#include <asm/io.h>
14
+
#include <asm/leon.h>
15
+
#include <asm/vaddrs.h>
16
+
#include <asm/sections.h>
17
+
#include <asm/leon_pci.h>
18
+
19
+
#include "irq.h"
20
+
21
+
struct grpci2_barcfg {
22
+
unsigned long pciadr; /* PCI Space Address */
23
+
unsigned long ahbadr; /* PCI Base address mapped to this AHB addr */
24
+
};
25
+
26
+
/* Device Node Configuration options:
27
+
* - barcfgs : Custom Configuration of Host's 6 target BARs
28
+
* - irq_mask : Limit which PCI interrupts are enabled
29
+
* - do_reset : Force PCI Reset on startup
30
+
*
31
+
* barcfgs
32
+
* =======
33
+
*
34
+
* Optional custom Target BAR configuration (see struct grpci2_barcfg). All
35
+
* addresses are physical. Array always contains 6 elements (len=2*4*6 bytes)
36
+
*
37
+
* -1 means not configured (let host driver do default setup).
38
+
*
39
+
* [i*2+0] = PCI Address of BAR[i] on target interface
40
+
* [i*2+1] = Accessing PCI address of BAR[i] result in this AMBA address
41
+
*
42
+
*
43
+
* irq_mask
44
+
* ========
45
+
*
46
+
* Limit which PCI interrupts are enabled. 0=Disable, 1=Enable. By default
47
+
* all are enabled. Use this when PCI interrupt pins are floating on PCB.
48
+
* int, len=4.
49
+
* bit0 = PCI INTA#
50
+
* bit1 = PCI INTB#
51
+
* bit2 = PCI INTC#
52
+
* bit3 = PCI INTD#
53
+
*
54
+
*
55
+
* reset
56
+
* =====
57
+
*
58
+
* Force PCI reset on startup. int, len=4
59
+
*/
60
+
61
+
/* Enable Debugging Configuration Space Access */
62
+
#undef GRPCI2_DEBUG_CFGACCESS
63
+
64
+
/*
65
+
* GRPCI2 APB Register MAP
66
+
*/
67
+
struct grpci2_regs {
68
+
unsigned int ctrl; /* 0x00 Control */
69
+
unsigned int sts_cap; /* 0x04 Status / Capabilities */
70
+
int res1; /* 0x08 */
71
+
unsigned int io_map; /* 0x0C I/O Map address */
72
+
unsigned int dma_ctrl; /* 0x10 DMA */
73
+
unsigned int dma_bdbase; /* 0x14 DMA */
74
+
int res2[2]; /* 0x18 */
75
+
unsigned int bars[6]; /* 0x20 read-only PCI BARs */
76
+
int res3[2]; /* 0x38 */
77
+
unsigned int ahbmst_map[16]; /* 0x40 AHB->PCI Map per AHB Master */
78
+
79
+
/* PCI Trace Buffer Registers (OPTIONAL) */
80
+
unsigned int t_ctrl; /* 0x80 */
81
+
unsigned int t_cnt; /* 0x84 */
82
+
unsigned int t_adpat; /* 0x88 */
83
+
unsigned int t_admask; /* 0x8C */
84
+
unsigned int t_sigpat; /* 0x90 */
85
+
unsigned int t_sigmask; /* 0x94 */
86
+
unsigned int t_adstate; /* 0x98 */
87
+
unsigned int t_sigstate; /* 0x9C */
88
+
};
89
+
90
+
#define REGLOAD(a) (be32_to_cpu(__raw_readl(&(a))))
91
+
#define REGSTORE(a, v) (__raw_writel(cpu_to_be32(v), &(a)))
92
+
93
+
#define CTRL_BUS_BIT 16
94
+
95
+
#define CTRL_RESET (1<<31)
96
+
#define CTRL_SI (1<<27)
97
+
#define CTRL_PE (1<<26)
98
+
#define CTRL_EI (1<<25)
99
+
#define CTRL_ER (1<<24)
100
+
#define CTRL_BUS (0xff<<CTRL_BUS_BIT)
101
+
#define CTRL_HOSTINT 0xf
102
+
103
+
#define STS_HOST_BIT 31
104
+
#define STS_MST_BIT 30
105
+
#define STS_TAR_BIT 29
106
+
#define STS_DMA_BIT 28
107
+
#define STS_DI_BIT 27
108
+
#define STS_HI_BIT 26
109
+
#define STS_IRQMODE_BIT 24
110
+
#define STS_TRACE_BIT 23
111
+
#define STS_CFGERRVALID_BIT 20
112
+
#define STS_CFGERR_BIT 19
113
+
#define STS_INTTYPE_BIT 12
114
+
#define STS_INTSTS_BIT 8
115
+
#define STS_FDEPTH_BIT 2
116
+
#define STS_FNUM_BIT 0
117
+
118
+
#define STS_HOST (1<<STS_HOST_BIT)
119
+
#define STS_MST (1<<STS_MST_BIT)
120
+
#define STS_TAR (1<<STS_TAR_BIT)
121
+
#define STS_DMA (1<<STS_DMA_BIT)
122
+
#define STS_DI (1<<STS_DI_BIT)
123
+
#define STS_HI (1<<STS_HI_BIT)
124
+
#define STS_IRQMODE (0x3<<STS_IRQMODE_BIT)
125
+
#define STS_TRACE (1<<STS_TRACE_BIT)
126
+
#define STS_CFGERRVALID (1<<STS_CFGERRVALID_BIT)
127
+
#define STS_CFGERR (1<<STS_CFGERR_BIT)
128
+
#define STS_INTTYPE (0x3f<<STS_INTTYPE_BIT)
129
+
#define STS_INTSTS (0xf<<STS_INTSTS_BIT)
130
+
#define STS_FDEPTH (0x7<<STS_FDEPTH_BIT)
131
+
#define STS_FNUM (0x3<<STS_FNUM_BIT)
132
+
133
+
#define STS_ISYSERR (1<<17)
134
+
#define STS_IDMA (1<<16)
135
+
#define STS_IDMAERR (1<<15)
136
+
#define STS_IMSTABRT (1<<14)
137
+
#define STS_ITGTABRT (1<<13)
138
+
#define STS_IPARERR (1<<12)
139
+
140
+
#define STS_ERR_IRQ (STS_ISYSERR | STS_IMSTABRT | STS_ITGTABRT | STS_IPARERR)
141
+
142
+
struct grpci2_bd_chan {
143
+
unsigned int ctrl; /* 0x00 DMA Control */
144
+
unsigned int nchan; /* 0x04 Next DMA Channel Address */
145
+
unsigned int nbd; /* 0x08 Next Data Descriptor in chan */
146
+
unsigned int res; /* 0x0C Reserved */
147
+
};
148
+
149
+
#define BD_CHAN_EN 0x80000000
150
+
#define BD_CHAN_TYPE 0x00300000
151
+
#define BD_CHAN_BDCNT 0x0000ffff
152
+
#define BD_CHAN_EN_BIT 31
153
+
#define BD_CHAN_TYPE_BIT 20
154
+
#define BD_CHAN_BDCNT_BIT 0
155
+
156
+
struct grpci2_bd_data {
157
+
unsigned int ctrl; /* 0x00 DMA Data Control */
158
+
unsigned int pci_adr; /* 0x04 PCI Start Address */
159
+
unsigned int ahb_adr; /* 0x08 AHB Start address */
160
+
unsigned int next; /* 0x0C Next Data Descriptor in chan */
161
+
};
162
+
163
+
#define BD_DATA_EN 0x80000000
164
+
#define BD_DATA_IE 0x40000000
165
+
#define BD_DATA_DR 0x20000000
166
+
#define BD_DATA_TYPE 0x00300000
167
+
#define BD_DATA_ER 0x00080000
168
+
#define BD_DATA_LEN 0x0000ffff
169
+
#define BD_DATA_EN_BIT 31
170
+
#define BD_DATA_IE_BIT 30
171
+
#define BD_DATA_DR_BIT 29
172
+
#define BD_DATA_TYPE_BIT 20
173
+
#define BD_DATA_ER_BIT 19
174
+
#define BD_DATA_LEN_BIT 0
175
+
176
+
/* GRPCI2 Capability */
177
+
struct grpci2_cap_first {
178
+
unsigned int ctrl;
179
+
unsigned int pci2ahb_map[6];
180
+
unsigned int ext2ahb_map;
181
+
unsigned int io_map;
182
+
unsigned int pcibar_size[6];
183
+
};
184
+
#define CAP9_CTRL_OFS 0
185
+
#define CAP9_BAR_OFS 0x4
186
+
#define CAP9_IOMAP_OFS 0x20
187
+
#define CAP9_BARSIZE_OFS 0x24
188
+
189
+
struct grpci2_priv {
190
+
struct leon_pci_info info; /* must be on top of this structure */
191
+
struct grpci2_regs *regs;
192
+
char irq;
193
+
char irq_mode; /* IRQ Mode from CAPSTS REG */
194
+
char bt_enabled;
195
+
char do_reset;
196
+
char irq_mask;
197
+
u32 pciid; /* PCI ID of Host */
198
+
unsigned char irq_map[4];
199
+
200
+
/* Virtual IRQ numbers */
201
+
unsigned int virq_err;
202
+
unsigned int virq_dma;
203
+
204
+
/* AHB PCI Windows */
205
+
unsigned long pci_area; /* MEMORY */
206
+
unsigned long pci_area_end;
207
+
unsigned long pci_io; /* I/O */
208
+
unsigned long pci_conf; /* CONFIGURATION */
209
+
unsigned long pci_conf_end;
210
+
unsigned long pci_io_va;
211
+
212
+
struct grpci2_barcfg tgtbars[6];
213
+
};
214
+
215
+
DEFINE_SPINLOCK(grpci2_dev_lock);
216
+
struct grpci2_priv *grpci2priv;
217
+
218
+
int grpci2_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
219
+
{
220
+
struct grpci2_priv *priv = dev->bus->sysdata;
221
+
int irq_group;
222
+
223
+
/* Use default IRQ decoding on PCI BUS0 according slot numbering */
224
+
irq_group = slot & 0x3;
225
+
pin = ((pin - 1) + irq_group) & 0x3;
226
+
227
+
return priv->irq_map[pin];
228
+
}
229
+
230
+
static int grpci2_cfg_r32(struct grpci2_priv *priv, unsigned int bus,
231
+
unsigned int devfn, int where, u32 *val)
232
+
{
233
+
unsigned int *pci_conf;
234
+
unsigned long flags;
235
+
u32 tmp;
236
+
237
+
if (where & 0x3)
238
+
return -EINVAL;
239
+
240
+
if (bus == 0 && PCI_SLOT(devfn) != 0)
241
+
devfn += (0x8 * 6);
242
+
243
+
/* Select bus */
244
+
spin_lock_irqsave(&grpci2_dev_lock, flags);
245
+
REGSTORE(priv->regs->ctrl, (REGLOAD(priv->regs->ctrl) & ~(0xff << 16)) |
246
+
(bus << 16));
247
+
spin_unlock_irqrestore(&grpci2_dev_lock, flags);
248
+
249
+
/* clear old status */
250
+
REGSTORE(priv->regs->sts_cap, (STS_CFGERR | STS_CFGERRVALID));
251
+
252
+
pci_conf = (unsigned int *) (priv->pci_conf |
253
+
(devfn << 8) | (where & 0xfc));
254
+
tmp = LEON3_BYPASS_LOAD_PA(pci_conf);
255
+
256
+
/* Wait until GRPCI2 signals that CFG access is done, it should be
257
+
* done instantaneously unless a DMA operation is ongoing...
258
+
*/
259
+
while ((REGLOAD(priv->regs->sts_cap) & STS_CFGERRVALID) == 0)
260
+
;
261
+
262
+
if (REGLOAD(priv->regs->sts_cap) & STS_CFGERR) {
263
+
*val = 0xffffffff;
264
+
} else {
265
+
/* Bus always little endian (unaffected by byte-swapping) */
266
+
*val = flip_dword(tmp);
267
+
}
268
+
269
+
return 0;
270
+
}
271
+
272
+
static int grpci2_cfg_r16(struct grpci2_priv *priv, unsigned int bus,
273
+
unsigned int devfn, int where, u32 *val)
274
+
{
275
+
u32 v;
276
+
int ret;
277
+
278
+
if (where & 0x1)
279
+
return -EINVAL;
280
+
ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
281
+
*val = 0xffff & (v >> (8 * (where & 0x3)));
282
+
return ret;
283
+
}
284
+
285
+
static int grpci2_cfg_r8(struct grpci2_priv *priv, unsigned int bus,
286
+
unsigned int devfn, int where, u32 *val)
287
+
{
288
+
u32 v;
289
+
int ret;
290
+
291
+
ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
292
+
*val = 0xff & (v >> (8 * (where & 3)));
293
+
294
+
return ret;
295
+
}
296
+
297
+
static int grpci2_cfg_w32(struct grpci2_priv *priv, unsigned int bus,
298
+
unsigned int devfn, int where, u32 val)
299
+
{
300
+
unsigned int *pci_conf;
301
+
unsigned long flags;
302
+
303
+
if (where & 0x3)
304
+
return -EINVAL;
305
+
306
+
if (bus == 0 && PCI_SLOT(devfn) != 0)
307
+
devfn += (0x8 * 6);
308
+
309
+
/* Select bus */
310
+
spin_lock_irqsave(&grpci2_dev_lock, flags);
311
+
REGSTORE(priv->regs->ctrl, (REGLOAD(priv->regs->ctrl) & ~(0xff << 16)) |
312
+
(bus << 16));
313
+
spin_unlock_irqrestore(&grpci2_dev_lock, flags);
314
+
315
+
/* clear old status */
316
+
REGSTORE(priv->regs->sts_cap, (STS_CFGERR | STS_CFGERRVALID));
317
+
318
+
pci_conf = (unsigned int *) (priv->pci_conf |
319
+
(devfn << 8) | (where & 0xfc));
320
+
LEON3_BYPASS_STORE_PA(pci_conf, flip_dword(val));
321
+
322
+
/* Wait until GRPCI2 signals that CFG access is done, it should be
323
+
* done instantaneously unless a DMA operation is ongoing...
324
+
*/
325
+
while ((REGLOAD(priv->regs->sts_cap) & STS_CFGERRVALID) == 0)
326
+
;
327
+
328
+
return 0;
329
+
}
330
+
331
+
static int grpci2_cfg_w16(struct grpci2_priv *priv, unsigned int bus,
332
+
unsigned int devfn, int where, u32 val)
333
+
{
334
+
int ret;
335
+
u32 v;
336
+
337
+
if (where & 0x1)
338
+
return -EINVAL;
339
+
ret = grpci2_cfg_r32(priv, bus, devfn, where&~3, &v);
340
+
if (ret)
341
+
return ret;
342
+
v = (v & ~(0xffff << (8 * (where & 0x3)))) |
343
+
((0xffff & val) << (8 * (where & 0x3)));
344
+
return grpci2_cfg_w32(priv, bus, devfn, where & ~0x3, v);
345
+
}
346
+
347
+
static int grpci2_cfg_w8(struct grpci2_priv *priv, unsigned int bus,
348
+
unsigned int devfn, int where, u32 val)
349
+
{
350
+
int ret;
351
+
u32 v;
352
+
353
+
ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
354
+
if (ret != 0)
355
+
return ret;
356
+
v = (v & ~(0xff << (8 * (where & 0x3)))) |
357
+
((0xff & val) << (8 * (where & 0x3)));
358
+
return grpci2_cfg_w32(priv, bus, devfn, where & ~0x3, v);
359
+
}
360
+
361
+
/* Read from Configuration Space. When entering here the PCI layer has taken
362
+
* the pci_lock spinlock and IRQ is off.
363
+
*/
364
+
static int grpci2_read_config(struct pci_bus *bus, unsigned int devfn,
365
+
int where, int size, u32 *val)
366
+
{
367
+
struct grpci2_priv *priv = grpci2priv;
368
+
unsigned int busno = bus->number;
369
+
int ret;
370
+
371
+
if (PCI_SLOT(devfn) > 15 || (PCI_SLOT(devfn) == 0 && busno == 0)) {
372
+
*val = ~0;
373
+
return 0;
374
+
}
375
+
376
+
switch (size) {
377
+
case 1:
378
+
ret = grpci2_cfg_r8(priv, busno, devfn, where, val);
379
+
break;
380
+
case 2:
381
+
ret = grpci2_cfg_r16(priv, busno, devfn, where, val);
382
+
break;
383
+
case 4:
384
+
ret = grpci2_cfg_r32(priv, busno, devfn, where, val);
385
+
break;
386
+
default:
387
+
ret = -EINVAL;
388
+
break;
389
+
}
390
+
391
+
#ifdef GRPCI2_DEBUG_CFGACCESS
392
+
printk(KERN_INFO "grpci2_read_config: [%02x:%02x:%x] ofs=%d val=%x "
393
+
"size=%d\n", busno, PCI_SLOT(devfn), PCI_FUNC(devfn), where,
394
+
*val, size);
395
+
#endif
396
+
397
+
return ret;
398
+
}
399
+
400
+
/* Write to Configuration Space. When entering here the PCI layer has taken
401
+
* the pci_lock spinlock and IRQ is off.
402
+
*/
403
+
static int grpci2_write_config(struct pci_bus *bus, unsigned int devfn,
404
+
int where, int size, u32 val)
405
+
{
406
+
struct grpci2_priv *priv = grpci2priv;
407
+
unsigned int busno = bus->number;
408
+
409
+
if (PCI_SLOT(devfn) > 15 || (PCI_SLOT(devfn) == 0 && busno == 0))
410
+
return 0;
411
+
412
+
#ifdef GRPCI2_DEBUG_CFGACCESS
413
+
printk(KERN_INFO "grpci2_write_config: [%02x:%02x:%x] ofs=%d size=%d "
414
+
"val=%x\n", busno, PCI_SLOT(devfn), PCI_FUNC(devfn),
415
+
where, size, val);
416
+
#endif
417
+
418
+
switch (size) {
419
+
default:
420
+
return -EINVAL;
421
+
case 1:
422
+
return grpci2_cfg_w8(priv, busno, devfn, where, val);
423
+
case 2:
424
+
return grpci2_cfg_w16(priv, busno, devfn, where, val);
425
+
case 4:
426
+
return grpci2_cfg_w32(priv, busno, devfn, where, val);
427
+
}
428
+
}
429
+
430
+
static struct pci_ops grpci2_ops = {
431
+
.read = grpci2_read_config,
432
+
.write = grpci2_write_config,
433
+
};
434
+
435
+
/* GENIRQ IRQ chip implementation for GRPCI2 irqmode=0..2. In configuration
436
+
* 3 where all PCI Interrupts has a separate IRQ on the system IRQ controller
437
+
* this is not needed and the standard IRQ controller can be used.
438
+
*/
439
+
440
+
static void grpci2_mask_irq(struct irq_data *data)
441
+
{
442
+
unsigned long flags;
443
+
unsigned int irqidx;
444
+
struct grpci2_priv *priv = grpci2priv;
445
+
446
+
irqidx = (unsigned int)data->chip_data - 1;
447
+
if (irqidx > 3) /* only mask PCI interrupts here */
448
+
return;
449
+
450
+
spin_lock_irqsave(&grpci2_dev_lock, flags);
451
+
REGSTORE(priv->regs->ctrl, REGLOAD(priv->regs->ctrl) & ~(1 << irqidx));
452
+
spin_unlock_irqrestore(&grpci2_dev_lock, flags);
453
+
}
454
+
455
+
static void grpci2_unmask_irq(struct irq_data *data)
456
+
{
457
+
unsigned long flags;
458
+
unsigned int irqidx;
459
+
struct grpci2_priv *priv = grpci2priv;
460
+
461
+
irqidx = (unsigned int)data->chip_data - 1;
462
+
if (irqidx > 3) /* only unmask PCI interrupts here */
463
+
return;
464
+
465
+
spin_lock_irqsave(&grpci2_dev_lock, flags);
466
+
REGSTORE(priv->regs->ctrl, REGLOAD(priv->regs->ctrl) | (1 << irqidx));
467
+
spin_unlock_irqrestore(&grpci2_dev_lock, flags);
468
+
}
469
+
470
+
static unsigned int grpci2_startup_irq(struct irq_data *data)
471
+
{
472
+
grpci2_unmask_irq(data);
473
+
return 0;
474
+
}
475
+
476
+
static void grpci2_shutdown_irq(struct irq_data *data)
477
+
{
478
+
grpci2_mask_irq(data);
479
+
}
480
+
481
+
static struct irq_chip grpci2_irq = {
482
+
.name = "grpci2",
483
+
.irq_startup = grpci2_startup_irq,
484
+
.irq_shutdown = grpci2_shutdown_irq,
485
+
.irq_mask = grpci2_mask_irq,
486
+
.irq_unmask = grpci2_unmask_irq,
487
+
};
488
+
489
+
/* Handle one or multiple IRQs from the PCI core */
490
+
static void grpci2_pci_flow_irq(unsigned int irq, struct irq_desc *desc)
491
+
{
492
+
struct grpci2_priv *priv = grpci2priv;
493
+
int i, ack = 0;
494
+
unsigned int ctrl, sts_cap, pci_ints;
495
+
496
+
ctrl = REGLOAD(priv->regs->ctrl);
497
+
sts_cap = REGLOAD(priv->regs->sts_cap);
498
+
499
+
/* Error Interrupt? */
500
+
if (sts_cap & STS_ERR_IRQ) {
501
+
generic_handle_irq(priv->virq_err);
502
+
ack = 1;
503
+
}
504
+
505
+
/* PCI Interrupt? */
506
+
pci_ints = ((~sts_cap) >> STS_INTSTS_BIT) & ctrl & CTRL_HOSTINT;
507
+
if (pci_ints) {
508
+
/* Call respective PCI Interrupt handler */
509
+
for (i = 0; i < 4; i++) {
510
+
if (pci_ints & (1 << i))
511
+
generic_handle_irq(priv->irq_map[i]);
512
+
}
513
+
ack = 1;
514
+
}
515
+
516
+
/*
517
+
* Decode DMA Interrupt only when shared with Err and PCI INTX#, when
518
+
* the DMA is a unique IRQ the DMA interrupts doesn't end up here, they
519
+
* goes directly to DMA ISR.
520
+
*/
521
+
if ((priv->irq_mode == 0) && (sts_cap & (STS_IDMA | STS_IDMAERR))) {
522
+
generic_handle_irq(priv->virq_dma);
523
+
ack = 1;
524
+
}
525
+
526
+
/*
527
+
* Call "first level" IRQ chip end-of-irq handler. It will ACK LEON IRQ
528
+
* Controller, this must be done after IRQ sources have been handled to
529
+
* avoid double IRQ generation
530
+
*/
531
+
if (ack)
532
+
desc->irq_data.chip->irq_eoi(&desc->irq_data);
533
+
}
534
+
535
+
/* Create a virtual IRQ */
536
+
static unsigned int grpci2_build_device_irq(unsigned int irq)
537
+
{
538
+
unsigned int virq = 0, pil;
539
+
540
+
pil = 1 << 8;
541
+
virq = irq_alloc(irq, pil);
542
+
if (virq == 0)
543
+
goto out;
544
+
545
+
irq_set_chip_and_handler_name(virq, &grpci2_irq, handle_simple_irq,
546
+
"pcilvl");
547
+
irq_set_chip_data(virq, (void *)irq);
548
+
549
+
out:
550
+
return virq;
551
+
}
552
+
553
+
void grpci2_hw_init(struct grpci2_priv *priv)
554
+
{
555
+
u32 ahbadr, pciadr, bar_sz, capptr, io_map, data;
556
+
struct grpci2_regs *regs = priv->regs;
557
+
int i;
558
+
struct grpci2_barcfg *barcfg = priv->tgtbars;
559
+
560
+
/* Reset any earlier setup */
561
+
if (priv->do_reset) {
562
+
printk(KERN_INFO "GRPCI2: Resetting PCI bus\n");
563
+
REGSTORE(regs->ctrl, CTRL_RESET);
564
+
ssleep(1); /* Wait for boards to settle */
565
+
}
566
+
REGSTORE(regs->ctrl, 0);
567
+
REGSTORE(regs->sts_cap, ~0); /* Clear Status */
568
+
REGSTORE(regs->dma_ctrl, 0);
569
+
REGSTORE(regs->dma_bdbase, 0);
570
+
571
+
/* Translate I/O accesses to 0, I/O Space always @ PCI low 64Kbytes */
572
+
REGSTORE(regs->io_map, REGLOAD(regs->io_map) & 0x0000ffff);
573
+
574
+
/* set 1:1 mapping between AHB -> PCI memory space, for all Masters
575
+
* Each AHB master has it's own mapping registers. Max 16 AHB masters.
576
+
*/
577
+
for (i = 0; i < 16; i++)
578
+
REGSTORE(regs->ahbmst_map[i], priv->pci_area);
579
+
580
+
/* Get the GRPCI2 Host PCI ID */
581
+
grpci2_cfg_r32(priv, 0, 0, PCI_VENDOR_ID, &priv->pciid);
582
+
583
+
/* Get address to first (always defined) capability structure */
584
+
grpci2_cfg_r8(priv, 0, 0, PCI_CAPABILITY_LIST, &capptr);
585
+
586
+
/* Enable/Disable Byte twisting */
587
+
grpci2_cfg_r32(priv, 0, 0, capptr+CAP9_IOMAP_OFS, &io_map);
588
+
io_map = (io_map & ~0x1) | (priv->bt_enabled ? 1 : 0);
589
+
grpci2_cfg_w32(priv, 0, 0, capptr+CAP9_IOMAP_OFS, io_map);
590
+
591
+
/* Setup the Host's PCI Target BARs for other peripherals to access,
592
+
* and do DMA to the host's memory. The target BARs can be sized and
593
+
* enabled individually.
594
+
*
595
+
* User may set custom target BARs, but default is:
596
+
* The first BARs is used to map kernel low (DMA is part of normal
597
+
* region on sparc which is SRMMU_MAXMEM big) main memory 1:1 to the
598
+
* PCI bus, the other BARs are disabled. We assume that the first BAR
599
+
* is always available.
600
+
*/
601
+
for (i = 0; i < 6; i++) {
602
+
if (barcfg[i].pciadr != ~0 && barcfg[i].ahbadr != ~0) {
603
+
/* Target BARs must have the proper alignment */
604
+
ahbadr = barcfg[i].ahbadr;
605
+
pciadr = barcfg[i].pciadr;
606
+
bar_sz = ((pciadr - 1) & ~pciadr) + 1;
607
+
} else {
608
+
if (i == 0) {
609
+
/* Map main memory */
610
+
bar_sz = 0xf0000008; /* 256MB prefetchable */
611
+
ahbadr = 0xf0000000 & (u32)__pa(PAGE_ALIGN(
612
+
(unsigned long) &_end));
613
+
pciadr = ahbadr;
614
+
} else {
615
+
bar_sz = 0;
616
+
ahbadr = 0;
617
+
pciadr = 0;
618
+
}
619
+
}
620
+
grpci2_cfg_w32(priv, 0, 0, capptr+CAP9_BARSIZE_OFS+i*4, bar_sz);
621
+
grpci2_cfg_w32(priv, 0, 0, PCI_BASE_ADDRESS_0+i*4, pciadr);
622
+
grpci2_cfg_w32(priv, 0, 0, capptr+CAP9_BAR_OFS+i*4, ahbadr);
623
+
printk(KERN_INFO " TGT BAR[%d]: 0x%08x (PCI)-> 0x%08x\n",
624
+
i, pciadr, ahbadr);
625
+
}
626
+
627
+
/* set as bus master and enable pci memory responses */
628
+
grpci2_cfg_r32(priv, 0, 0, PCI_COMMAND, &data);
629
+
data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
630
+
grpci2_cfg_w32(priv, 0, 0, PCI_COMMAND, data);
631
+
632
+
/* Enable Error respone (CPU-TRAP) on illegal memory access. */
633
+
REGSTORE(regs->ctrl, CTRL_ER | CTRL_PE);
634
+
}
635
+
636
+
static irqreturn_t grpci2_jump_interrupt(int irq, void *arg)
637
+
{
638
+
printk(KERN_ERR "GRPCI2: Jump IRQ happened\n");
639
+
return IRQ_NONE;
640
+
}
641
+
642
+
/* Handle GRPCI2 Error Interrupt */
643
+
static irqreturn_t grpci2_err_interrupt(int irq, void *arg)
644
+
{
645
+
struct grpci2_priv *priv = arg;
646
+
struct grpci2_regs *regs = priv->regs;
647
+
unsigned int status;
648
+
649
+
status = REGLOAD(regs->sts_cap);
650
+
if ((status & STS_ERR_IRQ) == 0)
651
+
return IRQ_NONE;
652
+
653
+
if (status & STS_IPARERR)
654
+
printk(KERN_ERR "GRPCI2: Parity Error\n");
655
+
656
+
if (status & STS_ITGTABRT)
657
+
printk(KERN_ERR "GRPCI2: Target Abort\n");
658
+
659
+
if (status & STS_IMSTABRT)
660
+
printk(KERN_ERR "GRPCI2: Master Abort\n");
661
+
662
+
if (status & STS_ISYSERR)
663
+
printk(KERN_ERR "GRPCI2: System Error\n");
664
+
665
+
/* Clear handled INT TYPE IRQs */
666
+
REGSTORE(regs->sts_cap, status & STS_ERR_IRQ);
667
+
668
+
return IRQ_HANDLED;
669
+
}
670
+
671
+
static int __devinit grpci2_of_probe(struct platform_device *ofdev)
672
+
{
673
+
struct grpci2_regs *regs;
674
+
struct grpci2_priv *priv;
675
+
int err, i, len;
676
+
const int *tmp;
677
+
unsigned int capability;
678
+
679
+
if (grpci2priv) {
680
+
printk(KERN_ERR "GRPCI2: only one GRPCI2 core supported\n");
681
+
return -ENODEV;
682
+
}
683
+
684
+
if (ofdev->num_resources < 3) {
685
+
printk(KERN_ERR "GRPCI2: not enough APB/AHB resources\n");
686
+
return -EIO;
687
+
}
688
+
689
+
/* Find Device Address */
690
+
regs = of_ioremap(&ofdev->resource[0], 0,
691
+
resource_size(&ofdev->resource[0]),
692
+
"grlib-grpci2 regs");
693
+
if (regs == NULL) {
694
+
printk(KERN_ERR "GRPCI2: ioremap failed\n");
695
+
return -EIO;
696
+
}
697
+
698
+
/*
699
+
* Check that we're in Host Slot and that we can act as a Host Bridge
700
+
* and not only as target.
701
+
*/
702
+
capability = REGLOAD(regs->sts_cap);
703
+
if ((capability & STS_HOST) || !(capability & STS_MST)) {
704
+
printk(KERN_INFO "GRPCI2: not in host system slot\n");
705
+
err = -EIO;
706
+
goto err1;
707
+
}
708
+
709
+
priv = grpci2priv = kzalloc(sizeof(struct grpci2_priv), GFP_KERNEL);
710
+
if (grpci2priv == NULL) {
711
+
err = -ENOMEM;
712
+
goto err1;
713
+
}
714
+
memset(grpci2priv, 0, sizeof(*grpci2priv));
715
+
priv->regs = regs;
716
+
priv->irq = ofdev->archdata.irqs[0]; /* BASE IRQ */
717
+
priv->irq_mode = (capability & STS_IRQMODE) >> STS_IRQMODE_BIT;
718
+
719
+
printk(KERN_INFO "GRPCI2: host found at %p, irq%d\n", regs, priv->irq);
720
+
721
+
/* Byte twisting should be made configurable from kernel command line */
722
+
priv->bt_enabled = 1;
723
+
724
+
/* Let user do custom Target BAR assignment */
725
+
tmp = of_get_property(ofdev->dev.of_node, "barcfg", &len);
726
+
if (tmp && (len == 2*4*6))
727
+
memcpy(priv->tgtbars, tmp, 2*4*6);
728
+
else
729
+
memset(priv->tgtbars, -1, 2*4*6);
730
+
731
+
/* Limit IRQ unmasking in irq_mode 2 and 3 */
732
+
tmp = of_get_property(ofdev->dev.of_node, "irq_mask", &len);
733
+
if (tmp && (len == 4))
734
+
priv->do_reset = *tmp;
735
+
else
736
+
priv->irq_mask = 0xf;
737
+
738
+
/* Optional PCI reset. Force PCI reset on startup */
739
+
tmp = of_get_property(ofdev->dev.of_node, "reset", &len);
740
+
if (tmp && (len == 4))
741
+
priv->do_reset = *tmp;
742
+
else
743
+
priv->do_reset = 0;
744
+
745
+
/* Find PCI Memory, I/O and Configuration Space Windows */
746
+
priv->pci_area = ofdev->resource[1].start;
747
+
priv->pci_area_end = ofdev->resource[1].end+1;
748
+
priv->pci_io = ofdev->resource[2].start;
749
+
priv->pci_conf = ofdev->resource[2].start + 0x10000;
750
+
priv->pci_conf_end = priv->pci_conf + 0x10000;
751
+
priv->pci_io_va = (unsigned long)ioremap(priv->pci_io, 0x10000);
752
+
if (!priv->pci_io_va) {
753
+
err = -EIO;
754
+
goto err2;
755
+
}
756
+
757
+
printk(KERN_INFO
758
+
"GRPCI2: MEMORY SPACE [0x%08lx - 0x%08lx]\n"
759
+
" I/O SPACE [0x%08lx - 0x%08lx]\n"
760
+
" CONFIG SPACE [0x%08lx - 0x%08lx]\n",
761
+
priv->pci_area, priv->pci_area_end-1,
762
+
priv->pci_io, priv->pci_conf-1,
763
+
priv->pci_conf, priv->pci_conf_end-1);
764
+
765
+
/*
766
+
* I/O Space resources in I/O Window mapped into Virtual Adr Space
767
+
* We never use low 4KB because some devices seem have problems using
768
+
* address 0.
769
+
*/
770
+
memset(&priv->info.io_space, 0, sizeof(struct resource));
771
+
priv->info.io_space.name = "GRPCI2 PCI I/O Space";
772
+
priv->info.io_space.start = priv->pci_io_va + 0x1000;
773
+
priv->info.io_space.end = priv->pci_io_va + 0x10000 - 1;
774
+
priv->info.io_space.flags = IORESOURCE_IO;
775
+
776
+
/*
777
+
* GRPCI2 has no prefetchable memory, map everything as
778
+
* non-prefetchable memory
779
+
*/
780
+
memset(&priv->info.mem_space, 0, sizeof(struct resource));
781
+
priv->info.mem_space.name = "GRPCI2 PCI MEM Space";
782
+
priv->info.mem_space.start = priv->pci_area;
783
+
priv->info.mem_space.end = priv->pci_area_end - 1;
784
+
priv->info.mem_space.flags = IORESOURCE_MEM;
785
+
786
+
if (request_resource(&iomem_resource, &priv->info.mem_space) < 0)
787
+
goto err3;
788
+
if (request_resource(&ioport_resource, &priv->info.io_space) < 0)
789
+
goto err4;
790
+
791
+
grpci2_hw_init(priv);
792
+
793
+
/*
794
+
* Get PCI Interrupt to System IRQ mapping and setup IRQ handling
795
+
* Error IRQ always on PCI INTA.
796
+
*/
797
+
if (priv->irq_mode < 2) {
798
+
/* All PCI interrupts are shared using the same system IRQ */
799
+
leon_update_virq_handling(priv->irq, grpci2_pci_flow_irq,
800
+
"pcilvl", 0);
801
+
802
+
priv->irq_map[0] = grpci2_build_device_irq(1);
803
+
priv->irq_map[1] = grpci2_build_device_irq(2);
804
+
priv->irq_map[2] = grpci2_build_device_irq(3);
805
+
priv->irq_map[3] = grpci2_build_device_irq(4);
806
+
807
+
priv->virq_err = grpci2_build_device_irq(5);
808
+
if (priv->irq_mode & 1)
809
+
priv->virq_dma = ofdev->archdata.irqs[1];
810
+
else
811
+
priv->virq_dma = grpci2_build_device_irq(6);
812
+
813
+
/* Enable IRQs on LEON IRQ controller */
814
+
err = request_irq(priv->irq, grpci2_jump_interrupt, 0,
815
+
"GRPCI2_JUMP", priv);
816
+
if (err)
817
+
printk(KERN_ERR "GRPCI2: ERR IRQ request failed\n");
818
+
} else {
819
+
/* All PCI interrupts have an unique IRQ interrupt */
820
+
for (i = 0; i < 4; i++) {
821
+
/* Make LEON IRQ layer handle level IRQ by acking */
822
+
leon_update_virq_handling(ofdev->archdata.irqs[i],
823
+
handle_fasteoi_irq, "pcilvl",
824
+
1);
825
+
priv->irq_map[i] = ofdev->archdata.irqs[i];
826
+
}
827
+
priv->virq_err = priv->irq_map[0];
828
+
if (priv->irq_mode & 1)
829
+
priv->virq_dma = ofdev->archdata.irqs[4];
830
+
else
831
+
priv->virq_dma = priv->irq_map[0];
832
+
833
+
/* Unmask all PCI interrupts, request_irq will not do that */
834
+
REGSTORE(regs->ctrl, REGLOAD(regs->ctrl)|(priv->irq_mask&0xf));
835
+
}
836
+
837
+
/* Setup IRQ handler for non-configuration space access errors */
838
+
err = request_irq(priv->virq_err, grpci2_err_interrupt, IRQF_SHARED,
839
+
"GRPCI2_ERR", priv);
840
+
if (err) {
841
+
printk(KERN_DEBUG "GRPCI2: ERR VIRQ request failed: %d\n", err);
842
+
goto err5;
843
+
}
844
+
845
+
/*
846
+
* Enable Error Interrupts. PCI interrupts are unmasked once request_irq
847
+
* is called by the PCI Device drivers
848
+
*/
849
+
REGSTORE(regs->ctrl, REGLOAD(regs->ctrl) | CTRL_EI | CTRL_SI);
850
+
851
+
/* Init common layer and scan buses */
852
+
priv->info.ops = &grpci2_ops;
853
+
priv->info.map_irq = grpci2_map_irq;
854
+
leon_pci_init(ofdev, &priv->info);
855
+
856
+
return 0;
857
+
858
+
err5:
859
+
release_resource(&priv->info.io_space);
860
+
err4:
861
+
release_resource(&priv->info.mem_space);
862
+
err3:
863
+
err = -ENOMEM;
864
+
iounmap((void *)priv->pci_io_va);
865
+
err2:
866
+
kfree(priv);
867
+
err1:
868
+
of_iounmap(&ofdev->resource[0], regs,
869
+
resource_size(&ofdev->resource[0]));
870
+
return err;
871
+
}
872
+
873
+
static struct of_device_id grpci2_of_match[] = {
874
+
{
875
+
.name = "GAISLER_GRPCI2",
876
+
},
877
+
{
878
+
.name = "01_07c",
879
+
},
880
+
{},
881
+
};
882
+
883
+
static struct platform_driver grpci2_of_driver = {
884
+
.driver = {
885
+
.name = "grpci2",
886
+
.owner = THIS_MODULE,
887
+
.of_match_table = grpci2_of_match,
888
+
},
889
+
.probe = grpci2_of_probe,
890
+
};
891
+
892
+
static int __init grpci2_init(void)
893
+
{
894
+
return platform_driver_register(&grpci2_of_driver);
895
+
}
896
+
897
+
subsys_initcall(grpci2_init);
+1
-1
arch/sparc/kernel/module.c
+1
-1
arch/sparc/kernel/module.c
+2
-2
arch/sparc/kernel/pci_common.c
+2
-2
arch/sparc/kernel/pci_common.c
+3
-3
arch/sparc/kernel/pci_schizo.c
+3
-3
arch/sparc/kernel/pci_schizo.c
···
264
264
default:
265
265
type_string = "ECC Error";
266
266
break;
267
-
};
267
+
}
268
268
printk("%s: IOMMU Error, type[%s]\n",
269
269
pbm->name, type_string);
270
270
···
319
319
default:
320
320
type_string = "ECC Error";
321
321
break;
322
-
};
322
+
}
323
323
printk("%s: IOMMU TAG(%d)[error(%s) ctx(%x) wr(%d) str(%d) "
324
324
"sz(%dK) vpg(%08lx)]\n",
325
325
pbm->name, i, type_string,
···
1328
1328
default:
1329
1329
chipset_name = "SCHIZO";
1330
1330
break;
1331
-
};
1331
+
}
1332
1332
1333
1333
/* For SCHIZO, three OBP regs:
1334
1334
* 1) PBM controller regs
+1
-1
arch/sparc/kernel/prom_irqtrans.c
+1
-1
arch/sparc/kernel/prom_irqtrans.c
+1
-1
arch/sparc/kernel/psycho_common.c
+1
-1
arch/sparc/kernel/psycho_common.c
+2
-2
arch/sparc/kernel/sbus.c
+2
-2
arch/sparc/kernel/sbus.c
···
97
97
98
98
default:
99
99
return;
100
-
};
100
+
}
101
101
102
102
val = upa_readq(cfg_reg);
103
103
if (val & (1UL << 14UL)) {
···
244
244
case 3:
245
245
iclr = reg_base + SYSIO_ICLR_SLOT3;
246
246
break;
247
-
};
247
+
}
248
248
249
249
iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
250
250
}
+1
-1
arch/sparc/kernel/setup_32.c
+1
-1
arch/sparc/kernel/setup_32.c
+1
-1
arch/sparc/kernel/setup_64.c
+1
-1
arch/sparc/kernel/setup_64.c
+3
-3
arch/sparc/kernel/smp_32.c
+3
-3
arch/sparc/kernel/smp_32.c
···
114
114
printk("UNKNOWN!\n");
115
115
BUG();
116
116
break;
117
-
};
117
+
}
118
118
}
119
119
120
120
void cpu_panic(void)
···
374
374
printk("UNKNOWN!\n");
375
375
BUG();
376
376
break;
377
-
};
377
+
}
378
378
}
379
379
380
380
/* Set this up early so that things like the scheduler can init
···
447
447
printk("UNKNOWN!\n");
448
448
BUG();
449
449
break;
450
-
};
450
+
}
451
451
452
452
if (!ret) {
453
453
cpumask_set_cpu(cpu, &smp_commenced_mask);
+94
-58
arch/sparc/kernel/sun4d_irq.c
+94
-58
arch/sparc/kernel/sun4d_irq.c
···
103
103
104
104
sbil = (sbusl << 2);
105
105
/* Loop for each pending SBI */
106
-
for (sbino = 0; bus_mask; sbino++) {
106
+
for (sbino = 0; bus_mask; sbino++, bus_mask >>= 1) {
107
107
unsigned int idx, mask;
108
108
109
-
bus_mask >>= 1;
110
109
if (!(bus_mask & 1))
111
110
continue;
112
111
/* XXX This seems to ACK the irq twice. acquire_sbi()
···
117
118
mask &= (0xf << sbil);
118
119
119
120
/* Loop for each pending SBI slot */
120
-
idx = 0;
121
121
slot = (1 << sbil);
122
-
while (mask != 0) {
122
+
for (idx = 0; mask != 0; idx++, slot <<= 1) {
123
123
unsigned int pil;
124
124
struct irq_bucket *p;
125
125
126
-
idx++;
127
-
slot <<= 1;
128
126
if (!(mask & slot))
129
127
continue;
130
128
131
129
mask &= ~slot;
132
-
pil = sun4d_encode_irq(sbino, sbil, idx);
130
+
pil = sun4d_encode_irq(sbino, sbusl, idx);
133
131
134
132
p = irq_map[pil];
135
133
while (p) {
···
214
218
215
219
#ifdef CONFIG_SMP
216
220
spin_lock_irqsave(&sun4d_imsk_lock, flags);
217
-
cc_set_imsk_other(cpuid, cc_get_imsk_other(cpuid) | ~(1 << real_irq));
221
+
cc_set_imsk_other(cpuid, cc_get_imsk_other(cpuid) & ~(1 << real_irq));
218
222
spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
219
223
#else
220
-
cc_set_imsk(cc_get_imsk() | ~(1 << real_irq));
224
+
cc_set_imsk(cc_get_imsk() & ~(1 << real_irq));
221
225
#endif
222
226
}
223
227
···
295
299
}
296
300
}
297
301
298
-
unsigned int sun4d_build_device_irq(struct platform_device *op,
299
-
unsigned int real_irq)
302
+
unsigned int _sun4d_build_device_irq(unsigned int real_irq,
303
+
unsigned int pil,
304
+
unsigned int board)
300
305
{
301
-
struct device_node *dp = op->dev.of_node;
302
-
struct device_node *io_unit, *sbi = dp->parent;
303
-
const struct linux_prom_registers *regs;
304
306
struct sun4d_handler_data *handler_data;
305
-
unsigned int pil;
306
307
unsigned int irq;
307
-
int board, slot;
308
-
int sbusl;
309
-
310
-
irq = 0;
311
-
while (sbi) {
312
-
if (!strcmp(sbi->name, "sbi"))
313
-
break;
314
-
315
-
sbi = sbi->parent;
316
-
}
317
-
if (!sbi)
318
-
goto err_out;
319
-
320
-
regs = of_get_property(dp, "reg", NULL);
321
-
if (!regs)
322
-
goto err_out;
323
-
324
-
slot = regs->which_io;
325
-
326
-
/*
327
-
* If SBI's parent is not io-unit or the io-unit lacks
328
-
* a "board#" property, something is very wrong.
329
-
*/
330
-
if (!sbi->parent || strcmp(sbi->parent->name, "io-unit")) {
331
-
printk("%s: Error, parent is not io-unit.\n", sbi->full_name);
332
-
goto err_out;
333
-
}
334
-
io_unit = sbi->parent;
335
-
board = of_getintprop_default(io_unit, "board#", -1);
336
-
if (board == -1) {
337
-
printk("%s: Error, lacks board# property.\n", io_unit->full_name);
338
-
goto err_out;
339
-
}
340
-
341
-
sbusl = pil_to_sbus[real_irq];
342
-
if (sbusl)
343
-
pil = sun4d_encode_irq(board, sbusl, slot);
344
-
else
345
-
pil = real_irq;
346
308
347
309
irq = irq_alloc(real_irq, pil);
348
-
if (irq == 0)
310
+
if (irq == 0) {
311
+
prom_printf("IRQ: allocate for %d %d %d failed\n",
312
+
real_irq, pil, board);
349
313
goto err_out;
314
+
}
350
315
351
316
handler_data = irq_get_handler_data(irq);
352
317
if (unlikely(handler_data))
···
325
368
irq_set_handler_data(irq, handler_data);
326
369
327
370
err_out:
328
-
return real_irq;
371
+
return irq;
329
372
}
373
+
374
+
375
+
376
+
unsigned int sun4d_build_device_irq(struct platform_device *op,
377
+
unsigned int real_irq)
378
+
{
379
+
struct device_node *dp = op->dev.of_node;
380
+
struct device_node *board_parent, *bus = dp->parent;
381
+
char *bus_connection;
382
+
const struct linux_prom_registers *regs;
383
+
unsigned int pil;
384
+
unsigned int irq;
385
+
int board, slot;
386
+
int sbusl;
387
+
388
+
irq = real_irq;
389
+
while (bus) {
390
+
if (!strcmp(bus->name, "sbi")) {
391
+
bus_connection = "io-unit";
392
+
break;
393
+
}
394
+
395
+
if (!strcmp(bus->name, "bootbus")) {
396
+
bus_connection = "cpu-unit";
397
+
break;
398
+
}
399
+
400
+
bus = bus->parent;
401
+
}
402
+
if (!bus)
403
+
goto err_out;
404
+
405
+
regs = of_get_property(dp, "reg", NULL);
406
+
if (!regs)
407
+
goto err_out;
408
+
409
+
slot = regs->which_io;
410
+
411
+
/*
412
+
* If Bus nodes parent is not io-unit/cpu-unit or the io-unit/cpu-unit
413
+
* lacks a "board#" property, something is very wrong.
414
+
*/
415
+
if (!bus->parent || strcmp(bus->parent->name, bus_connection)) {
416
+
printk(KERN_ERR "%s: Error, parent is not %s.\n",
417
+
bus->full_name, bus_connection);
418
+
goto err_out;
419
+
}
420
+
board_parent = bus->parent;
421
+
board = of_getintprop_default(board_parent, "board#", -1);
422
+
if (board == -1) {
423
+
printk(KERN_ERR "%s: Error, lacks board# property.\n",
424
+
board_parent->full_name);
425
+
goto err_out;
426
+
}
427
+
428
+
sbusl = pil_to_sbus[real_irq];
429
+
if (sbusl)
430
+
pil = sun4d_encode_irq(board, sbusl, slot);
431
+
else
432
+
pil = real_irq;
433
+
434
+
irq = _sun4d_build_device_irq(real_irq, pil, board);
435
+
err_out:
436
+
return irq;
437
+
}
438
+
439
+
unsigned int sun4d_build_timer_irq(unsigned int board, unsigned int real_irq)
440
+
{
441
+
return _sun4d_build_device_irq(real_irq, real_irq, board);
442
+
}
443
+
330
444
331
445
static void __init sun4d_fixup_trap_table(void)
332
446
{
···
430
402
unsigned int irq;
431
403
const u32 *reg;
432
404
int err;
405
+
int board;
433
406
434
407
dp = of_find_node_by_name(NULL, "cpu-unit");
435
408
if (!dp) {
···
443
414
* bootbus.
444
415
*/
445
416
reg = of_get_property(dp, "reg", NULL);
446
-
of_node_put(dp);
447
417
if (!reg) {
448
418
prom_printf("sun4d_init_timers: No reg property\n");
449
419
prom_halt();
450
420
}
421
+
422
+
board = of_getintprop_default(dp, "board#", -1);
423
+
if (board == -1) {
424
+
prom_printf("sun4d_init_timers: No board# property on cpu-unit\n");
425
+
prom_halt();
426
+
}
427
+
428
+
of_node_put(dp);
451
429
452
430
res.start = reg[1];
453
431
res.end = reg[2] - 1;
···
470
434
471
435
master_l10_counter = &sun4d_timers->l10_cur_count;
472
436
473
-
irq = sun4d_build_device_irq(NULL, SUN4D_TIMER_IRQ);
437
+
irq = sun4d_build_timer_irq(board, SUN4D_TIMER_IRQ);
474
438
err = request_irq(irq, counter_fn, IRQF_TIMER, "timer", NULL);
475
439
if (err) {
476
440
prom_printf("sun4d_init_timers: request_irq() failed with %d\n",
+1
-1
arch/sparc/kernel/sys_sparc32.c
+1
-1
arch/sparc/kernel/sys_sparc32.c
+3
-3
arch/sparc/kernel/sys_sparc_64.c
+3
-3
arch/sparc/kernel/sys_sparc_64.c
···
460
460
default:
461
461
err = -ENOSYS;
462
462
goto out;
463
-
};
463
+
}
464
464
}
465
465
if (call <= MSGCTL) {
466
466
switch (call) {
···
481
481
default:
482
482
err = -ENOSYS;
483
483
goto out;
484
-
};
484
+
}
485
485
}
486
486
if (call <= SHMCTL) {
487
487
switch (call) {
···
507
507
default:
508
508
err = -ENOSYS;
509
509
goto out;
510
-
};
510
+
}
511
511
} else {
512
512
err = -ENOSYS;
513
513
}
+1
-1
arch/sparc/kernel/time_64.c
+1
-1
arch/sparc/kernel/time_64.c
+1
-1
arch/sparc/kernel/traps_64.c
+1
-1
arch/sparc/kernel/traps_64.c
+3
-3
arch/sparc/kernel/unaligned_64.c
+3
-3
arch/sparc/kernel/unaligned_64.c
···
211
211
default:
212
212
BUG();
213
213
break;
214
-
};
214
+
}
215
215
}
216
216
return __do_int_store(dst_addr, size, src_val, asi);
217
217
}
···
328
328
case ASI_SNFL:
329
329
asi &= ~0x08;
330
330
break;
331
-
};
331
+
}
332
332
switch (dir) {
333
333
case load:
334
334
reg_addr = fetch_reg_addr(((insn>>25)&0x1f), regs);
···
351
351
default:
352
352
BUG();
353
353
break;
354
-
};
354
+
}
355
355
*reg_addr = val_in;
356
356
}
357
357
break;
+3
-3
arch/sparc/kernel/us2e_cpufreq.c
+3
-3
arch/sparc/kernel/us2e_cpufreq.c
···
176
176
177
177
default:
178
178
BUG();
179
-
};
179
+
}
180
180
}
181
181
182
182
static unsigned long index_to_divisor(unsigned int index)
···
199
199
200
200
default:
201
201
BUG();
202
-
};
202
+
}
203
203
}
204
204
205
205
static unsigned long estar_to_divisor(unsigned long estar)
···
224
224
break;
225
225
default:
226
226
BUG();
227
-
};
227
+
}
228
228
229
229
return ret;
230
230
}
+2
-2
arch/sparc/kernel/us3_cpufreq.c
+2
-2
arch/sparc/kernel/us3_cpufreq.c
+1
-1
arch/sparc/kernel/viohs.c
+1
-1
arch/sparc/kernel/viohs.c
+7
-7
arch/sparc/kernel/visemul.c
+7
-7
arch/sparc/kernel/visemul.c
···
334
334
left = edge32_tab_l[(rs1 >> 2) & 0x1].left;
335
335
right = edge32_tab_l[(rs2 >> 2) & 0x1].right;
336
336
break;
337
-
};
337
+
}
338
338
339
339
if ((rs1 & ~0x7UL) == (rs2 & ~0x7UL))
340
340
rd_val = right & left;
···
360
360
tstate = regs->tstate & ~(TSTATE_XCC | TSTATE_ICC);
361
361
regs->tstate = tstate | (ccr << 32UL);
362
362
}
363
-
};
363
+
}
364
364
}
365
365
366
366
static void array(struct pt_regs *regs, unsigned int insn, unsigned int opf)
···
392
392
393
393
case ARRAY32_OPF:
394
394
rd_val <<= 2;
395
-
};
395
+
}
396
396
397
397
store_reg(regs, rd_val, RD(insn));
398
398
}
···
577
577
*fpd_regaddr(f, RD(insn)) = rd_val;
578
578
break;
579
579
}
580
-
};
580
+
}
581
581
}
582
582
583
583
static void pmul(struct pt_regs *regs, unsigned int insn, unsigned int opf)
···
693
693
*fpd_regaddr(f, RD(insn)) = rd_val;
694
694
break;
695
695
}
696
-
};
696
+
}
697
697
}
698
698
699
699
static void pcmp(struct pt_regs *regs, unsigned int insn, unsigned int opf)
···
786
786
rd_val |= 1 << i;
787
787
}
788
788
break;
789
-
};
789
+
}
790
790
791
791
maybe_flush_windows(0, 0, RD(insn), 0);
792
792
store_reg(regs, rd_val, RD(insn));
···
885
885
case BSHUFFLE_OPF:
886
886
bshuffle(regs, insn);
887
887
break;
888
-
};
888
+
}
889
889
890
890
regs->tpc = regs->tnpc;
891
891
regs->tnpc += 4;
+1
-1
arch/sparc/mm/fault_32.c
+1
-1
arch/sparc/mm/fault_32.c
+1
-1
arch/sparc/mm/init_32.c
+1
-1
arch/sparc/mm/init_32.c
···
340
340
prom_printf("paging_init: sparc_cpu_model = %d\n", sparc_cpu_model);
341
341
prom_printf("paging_init: Halting...\n");
342
342
prom_halt();
343
-
};
343
+
}
344
344
345
345
/* Initialize the protection map with non-constant, MMU dependent values. */
346
346
protection_map[0] = PAGE_NONE;
+3
-3
arch/sparc/mm/init_64.c
+3
-3
arch/sparc/mm/init_64.c
···
1625
1625
ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1626
1626
ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1627
1627
break;
1628
-
};
1628
+
}
1629
1629
1630
1630
ktsb_descr[0].assoc = 1;
1631
1631
ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
···
2266
2266
return _PAGE_SZ512K_4V;
2267
2267
case 4 * 1024 * 1024:
2268
2268
return _PAGE_SZ4MB_4V;
2269
-
};
2269
+
}
2270
2270
} else {
2271
2271
switch (sz) {
2272
2272
case 8 * 1024:
···
2278
2278
return _PAGE_SZ512K_4U;
2279
2279
case 4 * 1024 * 1024:
2280
2280
return _PAGE_SZ4MB_4U;
2281
-
};
2281
+
}
2282
2282
}
2283
2283
}
2284
2284
+2
-2
arch/sparc/mm/srmmu.c
+2
-2
arch/sparc/mm/srmmu.c
···
1665
1665
default:
1666
1666
srmmu_modtype = Swift_ok;
1667
1667
break;
1668
-
};
1668
+
}
1669
1669
1670
1670
BTFIXUPSET_CALL(flush_cache_all, swift_flush_cache_all, BTFIXUPCALL_NORM);
1671
1671
BTFIXUPSET_CALL(flush_cache_mm, swift_flush_cache_mm, BTFIXUPCALL_NORM);
···
2069
2069
/* Some other Cypress revision, assume a 605. */
2070
2070
init_cypress_605(mod_rev);
2071
2071
break;
2072
-
};
2072
+
}
2073
2073
return;
2074
2074
}
2075
2075
+4
-4
arch/sparc/mm/sun4c.c
+4
-4
arch/sparc/mm/sun4c.c
···
318
318
prom_printf("probe_vac: Didn't expect vac-linesize of %d, halting\n",
319
319
sun4c_vacinfo.linesize);
320
320
prom_halt();
321
-
};
321
+
}
322
322
323
323
sun4c_flush_all();
324
324
sun4c_enable_vac();
···
364
364
prom_printf("Unhandled number of segmaps: %d\n",
365
365
num_segmaps);
366
366
prom_halt();
367
-
};
367
+
}
368
368
switch (num_contexts) {
369
369
case 8:
370
370
/* Default, nothing to do. */
···
377
377
prom_printf("Unhandled number of contexts: %d\n",
378
378
num_contexts);
379
379
prom_halt();
380
-
};
380
+
}
381
381
382
382
if (sun4c_vacinfo.do_hwflushes != 0) {
383
383
PATCH_INSN(vac_hwflush_patch1_on, vac_hwflush_patch1);
···
394
394
prom_printf("Impossible VAC linesize %d, halting...\n",
395
395
sun4c_vacinfo.linesize);
396
396
prom_halt();
397
-
};
397
+
}
398
398
}
399
399
}
400
400
+3
-3
arch/sparc/mm/tsb.c
+3
-3
arch/sparc/mm/tsb.c
···
180
180
printk(KERN_ERR "TSB[%s:%d]: Impossible TSB size %lu, killing process.\n",
181
181
current->comm, current->pid, tsb_bytes);
182
182
do_exit(SIGSEGV);
183
-
};
183
+
}
184
184
tte |= pte_sz_bits(page_sz);
185
185
186
186
if (tlb_type == cheetah_plus || tlb_type == hypervisor) {
···
215
215
#endif
216
216
default:
217
217
BUG();
218
-
};
218
+
}
219
219
hp->assoc = 1;
220
220
hp->num_ttes = tsb_bytes / 16;
221
221
hp->ctx_idx = 0;
···
230
230
#endif
231
231
default:
232
232
BUG();
233
-
};
233
+
}
234
234
hp->tsb_base = tsb_paddr;
235
235
hp->resv = 0;
236
236
}
+1
-1
arch/sparc/prom/console_32.c
+1
-1
arch/sparc/prom/console_32.c
+1
-1
arch/sparc/prom/init_32.c
+1
-1
arch/sparc/prom/init_32.c
+1
-1
arch/sparc/prom/mp.c
+1
-1
arch/sparc/prom/mp.c