Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes
Add USB host controller and PHY nodes.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230119004533.1869870-2-abel.vesa@linaro.org
authored by
Abel Vesa
and committed by
Bjorn Andersson
7f7e5c1b
e5988fd6
+91
-1
+91
-1
arch/arm64/boot/dts/qcom/sm8550.dtsi
+91
-1
arch/arm64/boot/dts/qcom/sm8550.dtsi
···
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#include <dt-bindings/mailbox/qcom-ipcc.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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+
#include <dt-bindings/phy/phy-qcom-qmp.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
···
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<&ufs_mem_phy 0>,
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<&ufs_mem_phy 1>,
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<&ufs_mem_phy 2>,
750
-
<0>;
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<&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
751
750
};
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751
753
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ipcc: mailbox@408000 {
···
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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status = "disabled";
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+
};
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+
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+
usb_1_hsphy: phy@88e3000 {
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compatible = "qcom,sm8550-snps-eusb2-phy";
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+
reg = <0x0 0x088e3000 0x0 0x154>;
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+
#phy-cells = <0>;
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+
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clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
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+
clock-names = "ref";
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+
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+
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
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+
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+
status = "disabled";
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+
};
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+
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+
usb_dp_qmpphy: phy@88e8000 {
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+
compatible = "qcom,sm8550-qmp-usb3-dp-phy";
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+
reg = <0x0 0x088e8000 0x0 0x3000>;
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+
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+
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
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<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
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clock-names = "aux", "ref", "com_aux", "usb3_pipe";
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+
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+
power-domains = <&gcc USB3_PHY_GDSC>;
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+
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+
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
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<&gcc GCC_USB3_PHY_PRIM_BCR>;
2399
+
reset-names = "phy", "common";
2400
+
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+
#clock-cells = <1>;
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+
#phy-cells = <1>;
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+
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status = "disabled";
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+
};
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+
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usb_1: usb@a6f8800 {
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compatible = "qcom,sm8550-dwc3", "qcom,dwc3";
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+
reg = <0x0 0x0a6f8800 0x0 0x400>;
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+
#address-cells = <2>;
2411
+
#size-cells = <2>;
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ranges;
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+
2414
+
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
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+
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
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<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
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+
<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
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<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&tcsr TCSR_USB3_CLKREF_EN>;
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+
clock-names = "cfg_noc",
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"core",
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+
"iface",
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+
"sleep",
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"mock_utmi",
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"xo";
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+
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+
assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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+
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
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+
assigned-clock-rates = <19200000>, <200000000>;
2430
+
2431
+
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2432
+
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
2433
+
<&pdc 15 IRQ_TYPE_EDGE_RISING>,
2434
+
<&pdc 14 IRQ_TYPE_EDGE_RISING>;
2435
+
interrupt-names = "hs_phy_irq",
2436
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"ss_phy_irq",
2437
+
"dm_hs_phy_irq",
2438
+
"dp_hs_phy_irq";
2439
+
2440
+
power-domains = <&gcc USB30_PRIM_GDSC>;
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+
required-opps = <&rpmhpd_opp_nom>;
2442
+
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+
resets = <&gcc GCC_USB30_PRIM_BCR>;
2444
+
2445
+
status = "disabled";
2446
+
2447
+
usb_1_dwc3: usb@a600000 {
2448
+
compatible = "snps,dwc3";
2449
+
reg = <0x0 0x0a600000 0x0 0xcd00>;
2450
+
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2451
+
iommus = <&apps_smmu 0x40 0x0>;
2452
+
snps,dis_u2_susphy_quirk;
2453
+
snps,dis_enblslpm_quirk;
2454
+
snps,usb3_lpm_capable;
2455
+
phys = <&usb_1_hsphy>,
2456
+
<&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
2457
+
phy-names = "usb2-phy", "usb3-phy";
2458
+
};
2371
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};
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2373
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pdc: interrupt-controller@b220000 {