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Merge branch 'fix-missing-phy-to-mac-rx-clock'
Romain Gantois says:
====================
Fix missing PHY-to-MAC RX clock
There is an issue with some stmmac/PHY combinations that has been reported
some time ago in a couple of different series:
Clark Wang's report:
https://lore.kernel.org/all/20230202081559.3553637-1-xiaoning.wang@nxp.com/
Clément Léger's report:
https://lore.kernel.org/linux-arm-kernel/20230116103926.276869-4-clement.leger@bootlin.com/
Stmmac controllers require an RX clock signal from the MII bus to perform
their hardware initialization successfully. This causes issues with some
PHY/PCS devices. If these devices do not bring the clock signal up before
the MAC driver initializes its hardware, then said initialization will
fail. This can happen at probe time or when the system wakes up from a
suspended state.
This series introduces new flags for phy_device and phylink_pcs. These
flags allow MAC drivers to signal to PHY/PCS drivers that the RX clock
signal should be enabled as soon as possible, and that it should always
stay enabled.
I have included specific uses of these flags that fix the RZN1 GMAC1 stmmac
driver that I am currently working on and that is not yet upstream. I have
also included changes to the at803x PHY driver that should fix the issue
that Clark Wang was having.
====================
Link: https://lore.kernel.org/r/20240326-rxc_bugfix-v6-0-24a74e5c761f@bootlin.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+111
-13
+1
-1
drivers/net/ethernet/stmicro/stmmac/common.h
+1
-1
drivers/net/ethernet/stmicro/stmmac/common.h
···
593
593
const struct stmmac_mmc_ops *mmc;
594
594
const struct stmmac_est_ops *est;
595
595
struct dw_xpcs *xpcs;
596
-
struct phylink_pcs *lynx_pcs; /* Lynx external PCS */
596
+
struct phylink_pcs *phylink_pcs;
597
597
struct mii_regs mii; /* MII register Addresses */
598
598
struct mac_link link;
599
599
void __iomem *pcsr; /* vpointer to device CSRs */
+4
-4
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
+4
-4
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
···
479
479
goto err_dvr_remove;
480
480
}
481
481
482
-
stpriv->hw->lynx_pcs = lynx_pcs_create_mdiodev(pcs_bus, 0);
483
-
if (IS_ERR(stpriv->hw->lynx_pcs)) {
484
-
ret = PTR_ERR(stpriv->hw->lynx_pcs);
482
+
stpriv->hw->phylink_pcs = lynx_pcs_create_mdiodev(pcs_bus, 0);
483
+
if (IS_ERR(stpriv->hw->phylink_pcs)) {
484
+
ret = PTR_ERR(stpriv->hw->phylink_pcs);
485
485
goto err_dvr_remove;
486
486
}
487
487
}
···
498
498
{
499
499
struct net_device *ndev = platform_get_drvdata(pdev);
500
500
struct stmmac_priv *priv = netdev_priv(ndev);
501
-
struct phylink_pcs *pcs = priv->hw->lynx_pcs;
501
+
struct phylink_pcs *pcs = priv->hw->phylink_pcs;
502
502
503
503
stmmac_pltfr_remove(pdev);
504
504
+9
-6
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+9
-6
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
···
944
944
if (priv->hw->xpcs)
945
945
return &priv->hw->xpcs->pcs;
946
946
947
-
if (priv->hw->lynx_pcs)
948
-
return priv->hw->lynx_pcs;
949
-
950
-
return NULL;
947
+
return priv->hw->phylink_pcs;
951
948
}
952
949
953
950
static void stmmac_mac_config(struct phylink_config *config, unsigned int mode,
···
1217
1220
priv->phylink_config.dev = &priv->dev->dev;
1218
1221
priv->phylink_config.type = PHYLINK_NETDEV;
1219
1222
priv->phylink_config.mac_managed_pm = true;
1223
+
1224
+
/* Stmmac always requires an RX clock for hardware initialization */
1225
+
priv->phylink_config.mac_requires_rxc = true;
1220
1226
1221
1227
mdio_bus_data = priv->plat->mdio_bus_data;
1222
1228
if (mdio_bus_data)
···
3411
3411
u32 chan;
3412
3412
int ret;
3413
3413
3414
+
/* Make sure RX clock is enabled */
3415
+
if (priv->hw->phylink_pcs)
3416
+
phylink_pcs_pre_init(priv->phylink, priv->hw->phylink_pcs);
3417
+
3414
3418
/* DMA initialization and SW reset */
3415
3419
ret = stmmac_init_dma_engine(priv);
3416
3420
if (ret < 0) {
···
3964
3960
if (priv->hw->pcs != STMMAC_PCS_TBI &&
3965
3961
priv->hw->pcs != STMMAC_PCS_RTBI &&
3966
3962
(!priv->hw->xpcs ||
3967
-
xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73) &&
3968
-
!priv->hw->lynx_pcs) {
3963
+
xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73)) {
3969
3964
ret = stmmac_init_phy(dev);
3970
3965
if (ret) {
3971
3966
netdev_err(priv->dev,
+28
drivers/net/pcs/pcs-rzn1-miic.c
+28
drivers/net/pcs/pcs-rzn1-miic.c
···
279
279
return -EINVAL;
280
280
}
281
281
282
+
static int miic_pre_init(struct phylink_pcs *pcs)
283
+
{
284
+
struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs);
285
+
struct miic *miic = miic_port->miic;
286
+
u32 val, mask;
287
+
288
+
/* Start RX clock if required */
289
+
if (pcs->rxc_always_on) {
290
+
/* In MII through mode, the clock signals will be driven by the
291
+
* external PHY, which might not be initialized yet. Set RMII
292
+
* as default mode to ensure that a reference clock signal is
293
+
* generated.
294
+
*/
295
+
miic_port->interface = PHY_INTERFACE_MODE_RMII;
296
+
297
+
val = FIELD_PREP(MIIC_CONVCTRL_CONV_MODE, CONV_MODE_RMII) |
298
+
FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, CONV_MODE_100MBPS);
299
+
mask = MIIC_CONVCTRL_CONV_MODE | MIIC_CONVCTRL_CONV_SPEED;
300
+
301
+
miic_reg_rmw(miic, MIIC_CONVCTRL(miic_port->port), mask, val);
302
+
303
+
miic_converter_enable(miic, miic_port->port, 1);
304
+
}
305
+
306
+
return 0;
307
+
}
308
+
282
309
static const struct phylink_pcs_ops miic_phylink_ops = {
283
310
.pcs_validate = miic_validate,
284
311
.pcs_config = miic_config,
285
312
.pcs_link_up = miic_link_up,
313
+
.pcs_pre_init = miic_pre_init,
286
314
};
287
315
288
316
struct phylink_pcs *miic_create(struct device *dev, struct device_node *np)
+24
-1
drivers/net/phy/phylink.c
+24
-1
drivers/net/phy/phylink.c
···
1042
1042
mod_timer(&pl->link_poll, jiffies + HZ);
1043
1043
}
1044
1044
1045
+
int phylink_pcs_pre_init(struct phylink *pl, struct phylink_pcs *pcs)
1046
+
{
1047
+
int ret = 0;
1048
+
1049
+
/* Signal to PCS driver that MAC requires RX clock for init */
1050
+
if (pl->config->mac_requires_rxc)
1051
+
pcs->rxc_always_on = true;
1052
+
1053
+
if (pcs->ops->pcs_pre_init)
1054
+
ret = pcs->ops->pcs_pre_init(pcs);
1055
+
1056
+
return ret;
1057
+
}
1058
+
EXPORT_SYMBOL_GPL(phylink_pcs_pre_init);
1059
+
1045
1060
static void phylink_mac_config(struct phylink *pl,
1046
1061
const struct phylink_link_state *state)
1047
1062
{
···
1938
1923
static int phylink_attach_phy(struct phylink *pl, struct phy_device *phy,
1939
1924
phy_interface_t interface)
1940
1925
{
1926
+
u32 flags = 0;
1927
+
1941
1928
if (WARN_ON(pl->cfg_link_an_mode == MLO_AN_FIXED ||
1942
1929
(pl->cfg_link_an_mode == MLO_AN_INBAND &&
1943
1930
phy_interface_mode_is_8023z(interface) && !pl->sfp_bus)))
···
1948
1931
if (pl->phydev)
1949
1932
return -EBUSY;
1950
1933
1951
-
return phy_attach_direct(pl->netdev, phy, 0, interface);
1934
+
if (pl->config->mac_requires_rxc)
1935
+
flags |= PHY_F_RXC_ALWAYS_ON;
1936
+
1937
+
return phy_attach_direct(pl->netdev, phy, flags, interface);
1952
1938
}
1953
1939
1954
1940
/**
···
2053
2033
pl->link_interface = phy_dev->interface;
2054
2034
pl->link_config.interface = pl->link_interface;
2055
2035
}
2036
+
2037
+
if (pl->config->mac_requires_rxc)
2038
+
flags |= PHY_F_RXC_ALWAYS_ON;
2056
2039
2057
2040
ret = phy_attach_direct(pl->netdev, phy_dev, flags,
2058
2041
pl->link_interface);
+2
-1
drivers/net/phy/qcom/at803x.c
+2
-1
drivers/net/phy/qcom/at803x.c
···
426
426
/* The default after hardware reset is hibernation mode enabled. After
427
427
* software reset, the value is retained.
428
428
*/
429
-
if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE))
429
+
if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE) &&
430
+
!(phydev->dev_flags & PHY_F_RXC_ALWAYS_ON))
430
431
return 0;
431
432
432
433
return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
+1
include/linux/phy.h
+1
include/linux/phy.h
+42
include/linux/phylink.h
+42
include/linux/phylink.h
···
138
138
* @poll_fixed_state: if true, starts link_poll,
139
139
* if MAC link is at %MLO_AN_FIXED mode.
140
140
* @mac_managed_pm: if true, indicate the MAC driver is responsible for PHY PM.
141
+
* @mac_requires_rxc: if true, the MAC always requires a receive clock from PHY.
142
+
* The PHY driver should start the clock signal as soon as
143
+
* possible and avoid stopping it during suspend events.
141
144
* @ovr_an_inband: if true, override PCS to MLO_AN_INBAND
142
145
* @get_fixed_state: callback to execute to determine the fixed link state,
143
146
* if MAC link is at %MLO_AN_FIXED mode.
···
153
150
enum phylink_op_type type;
154
151
bool poll_fixed_state;
155
152
bool mac_managed_pm;
153
+
bool mac_requires_rxc;
156
154
bool ovr_an_inband;
157
155
void (*get_fixed_state)(struct phylink_config *config,
158
156
struct phylink_link_state *state);
···
396
392
* @phylink: pointer to &struct phylink_config
397
393
* @neg_mode: provide PCS neg mode via "mode" argument
398
394
* @poll: poll the PCS for link changes
395
+
* @rxc_always_on: The MAC driver requires the reference clock
396
+
* to always be on. Standalone PCS drivers which
397
+
* do not have access to a PHY device can check
398
+
* this instead of PHY_F_RXC_ALWAYS_ON.
399
399
*
400
400
* This structure is designed to be embedded within the PCS private data,
401
401
* and will be passed between phylink and the PCS.
···
412
404
struct phylink *phylink;
413
405
bool neg_mode;
414
406
bool poll;
407
+
bool rxc_always_on;
415
408
};
416
409
417
410
/**
···
427
418
* @pcs_an_restart: restart 802.3z BaseX autonegotiation.
428
419
* @pcs_link_up: program the PCS for the resolved link configuration
429
420
* (where necessary).
421
+
* @pcs_pre_init: configure PCS components necessary for MAC hardware
422
+
* initialization e.g. RX clock for stmmac.
430
423
*/
431
424
struct phylink_pcs_ops {
432
425
int (*pcs_validate)(struct phylink_pcs *pcs, unsigned long *supported,
···
448
437
void (*pcs_an_restart)(struct phylink_pcs *pcs);
449
438
void (*pcs_link_up)(struct phylink_pcs *pcs, unsigned int neg_mode,
450
439
phy_interface_t interface, int speed, int duplex);
440
+
int (*pcs_pre_init)(struct phylink_pcs *pcs);
451
441
};
452
442
453
443
#if 0 /* For kernel-doc purposes only. */
···
554
542
*/
555
543
void pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
556
544
phy_interface_t interface, int speed, int duplex);
545
+
546
+
/**
547
+
* pcs_pre_init() - Configure PCS components necessary for MAC initialization
548
+
* @pcs: a pointer to a &struct phylink_pcs.
549
+
*
550
+
* This function can be called by MAC drivers through the
551
+
* phylink_pcs_pre_init() wrapper, before their hardware is initialized. It
552
+
* should not be called after the link is brought up, as reconfiguring the PCS
553
+
* at this point could break the link.
554
+
*
555
+
* Some MAC devices require specific hardware initialization to be performed by
556
+
* their associated PCS device before they can properly initialize their own
557
+
* hardware. An example of this is the initialization of stmmac controllers,
558
+
* which requires an active REF_CLK signal to be provided by the PHY/PCS.
559
+
*
560
+
* By calling phylink_pcs_pre_init(), MAC drivers can ensure that the PCS is
561
+
* setup in a way that allows for successful hardware initialization.
562
+
*
563
+
* The specific configuration performed by pcs_pre_init() is dependent on the
564
+
* model of PCS and the requirements of the MAC device attached to it. PCS
565
+
* driver authors should consider whether their target device is to be used in
566
+
* conjunction with a MAC device whose driver calls phylink_pcs_pre_init(). MAC
567
+
* driver authors should document their requirements for the PCS
568
+
* pre-initialization.
569
+
*
570
+
*/
571
+
int pcs_pre_init(struct phylink_pcs *pcs);
572
+
557
573
#endif
558
574
559
575
struct phylink *phylink_create(struct phylink_config *,
···
600
560
601
561
void phylink_mac_change(struct phylink *, bool up);
602
562
void phylink_pcs_change(struct phylink_pcs *, bool up);
563
+
564
+
int phylink_pcs_pre_init(struct phylink *pl, struct phylink_pcs *pcs);
603
565
604
566
void phylink_start(struct phylink *);
605
567
void phylink_stop(struct phylink *);