Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'cris-for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/jesper/cris
Pull arch/cris updates from Jesper Nilsson:
"Some much needed love for the CRIS-port.
There's a bunch of changes this time, giving the CRISv32 port a bit of
modern makeover with device-tree, irq domain and gpiolib support, and
more switchover to generic frameworks.
Some small fixes and removal of the theoretical SMP support brings up
the rear"
* tag 'cris-for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/jesper/cris:
cris: fix integer overflow in ELF_ET_DYN_BASE
CRISv32: use GENERIC_SCHED_CLOCK
CRISv32: use MMIO clocksource
CRISv32: use generic clockevents
CRIS: use generic headers via Kbuild
CRIS: use generic cmpxchg.h
CRIS: use generic atomic.h
CRIS: use generic atomic bitops
CRISv10: remove redundant macros from system.h
CRIS: remove SMP code
CRISv32: don't enable irqs in INIT_THREAD
CRISv32: handle multiple signals
CRISv32: prevent bogus restarts on sigreturn
CRISv32: don't attempt syscall restart on irq exit
Add binding documentation for CRIS
CRIS: add Axis 88 board device tree
CRISv32: add device tree support
CRISv32: add irq domains support
CRIS: enable GPIOLIB
+326
-1146
+9
Documentation/devicetree/bindings/cris/axis.txt
+9
Documentation/devicetree/bindings/cris/axis.txt
+8
Documentation/devicetree/bindings/cris/boards.txt
+8
Documentation/devicetree/bindings/cris/boards.txt
+23
Documentation/devicetree/bindings/cris/interrupts.txt
+23
Documentation/devicetree/bindings/cris/interrupts.txt
···
1
+
* CRISv32 Interrupt Controller
2
+
3
+
Interrupt controller for the CRISv32 SoCs.
4
+
5
+
Main node required properties:
6
+
7
+
- compatible : should be:
8
+
"axis,crisv32-intc"
9
+
- interrupt-controller : Identifies the node as an interrupt controller
10
+
- #interrupt-cells : Specifies the number of cells needed to encode an
11
+
interrupt source. The type shall be a <u32> and the value shall be 1.
12
+
- reg: physical base address and size of the intc registers map.
13
+
14
+
Example:
15
+
16
+
intc: interrupt-controller {
17
+
compatible = "axis,crisv32-intc";
18
+
reg = <0xb001c000 0x1000>;
19
+
interrupt-controller;
20
+
#interrupt-cells = <1>;
21
+
};
22
+
23
+
+11
-1
arch/cris/Kconfig
+11
-1
arch/cris/Kconfig
···
46
46
select ARCH_WANT_IPC_PARSE_VERSION
47
47
select GENERIC_IRQ_SHOW
48
48
select GENERIC_IOMAP
49
-
select GENERIC_SMP_IDLE_THREAD if ETRAX_ARCH_V32
50
49
select GENERIC_CMOS_UPDATE
51
50
select MODULES_USE_ELF_RELA
52
51
select CLONE_BACKWARDS2
53
52
select OLD_SIGSUSPEND
54
53
select OLD_SIGACTION
54
+
select ARCH_REQUIRE_GPIOLIB
55
+
select IRQ_DOMAIN if ETRAX_ARCH_V32
56
+
select OF if ETRAX_ARCH_V32
57
+
select OF_EARLY_FLATTREE if ETRAX_ARCH_V32
58
+
select CLKSRC_MMIO if ETRAX_ARCH_V32
59
+
select GENERIC_CLOCKEVENTS if ETRAX_ARCH_V32
60
+
select GENERIC_SCHED_CLOCK if ETRAX_ARCH_V32
55
61
56
62
config HZ
57
63
int
···
66
60
config NR_CPUS
67
61
int
68
62
default "1"
63
+
64
+
config BUILTIN_DTB
65
+
string "DTB to build into the kernel image"
66
+
depends on OF
69
67
70
68
source "init/Kconfig"
71
69
+4
arch/cris/Makefile
+4
arch/cris/Makefile
-1
arch/cris/arch-v32/kernel/Makefile
-1
arch/cris/arch-v32/kernel/Makefile
+8
-34
arch/cris/arch-v32/kernel/entry.S
+8
-34
arch/cris/arch-v32/kernel/entry.S
···
99
99
100
100
.type ret_from_intr,@function
101
101
ret_from_intr:
102
+
moveq 0, $r9 ; not a syscall
103
+
102
104
;; Check for resched if preemptive kernel, or if we're going back to
103
105
;; user-mode. This test matches the user_regs(regs) macro. Don't simply
104
106
;; test CCS since that doesn't necessarily reflect what mode we'll
···
147
145
;; Stack-frame similar to the irq heads, which is reversed in
148
146
;; ret_from_sys_call.
149
147
150
-
sub.d 92, $sp ; Skip EXS and EDA.
148
+
sub.d 92, $sp ; Skip EDA.
151
149
movem $r13, [$sp]
152
150
move.d $sp, $r8
153
151
addq 14*4, $r8
···
158
156
move $ccs, $r4
159
157
move $srp, $r5
160
158
move $erp, $r6
159
+
move.d $r9, $r7 ; Store syscall number in EXS
161
160
subq 4, $sp
162
-
movem $r6, [$r8]
161
+
movem $r7, [$r8]
163
162
ei ; Enable interrupts while processing syscalls.
164
163
move.d $r10, [$sp]
165
164
···
281
278
.type _work_pending,@function
282
279
_work_pending:
283
280
addoq +TI_flags, $r0, $acr
284
-
move.d [$acr], $r10
285
-
btstq TIF_NEED_RESCHED, $r10 ; Need resched?
286
-
bpl _work_notifysig ; No, must be signal/notify.
287
-
nop
288
-
.size _work_pending, . - _work_pending
289
-
290
-
.type _work_resched,@function
291
-
_work_resched:
292
-
move.d $r9, $r1 ; Preserve R9.
293
-
jsr schedule
294
-
nop
295
-
move.d $r1, $r9
296
-
di
297
-
298
-
addoq +TI_flags, $r0, $acr
299
-
move.d [$acr], $r1
300
-
and.d _TIF_WORK_MASK, $r1 ; Ignore sycall trace counter.
301
-
beq _Rexit
302
-
nop
303
-
btstq TIF_NEED_RESCHED, $r1
304
-
bmi _work_resched ; current->work.need_resched.
305
-
nop
306
-
.size _work_resched, . - _work_resched
307
-
308
-
.type _work_notifysig,@function
309
-
_work_notifysig:
310
-
;; Deal with pending signals and notify-resume requests.
311
-
312
-
addoq +TI_flags, $r0, $acr
313
281
move.d [$acr], $r12 ; The thread_info_flags parameter.
314
282
move.d $sp, $r11 ; The regs param.
315
-
jsr do_notify_resume
316
-
move.d $r9, $r10 ; do_notify_resume syscall/irq param.
283
+
jsr do_work_pending
284
+
move.d $r9, $r10 ; The syscall/irq param.
317
285
318
286
ba _Rexit
319
287
nop
320
-
.size _work_notifysig, . - _work_notifysig
288
+
.size _work_pending, . - _work_pending
321
289
322
290
;; We get here as a sidetrack when we've entered a syscall with the
323
291
;; trace-bit set. We need to call do_syscall_trace and then continue
-32
arch/cris/arch-v32/kernel/head.S
-32
arch/cris/arch-v32/kernel/head.S
···
52
52
53
53
GIO_INIT
54
54
55
-
#ifdef CONFIG_SMP
56
-
secondary_cpu_entry: /* Entry point for secondary CPUs */
57
-
di
58
-
#endif
59
-
60
55
;; Setup and enable the MMU. Use same configuration for both the data
61
56
;; and the instruction MMU.
62
57
;;
···
159
164
nop
160
165
nop
161
166
162
-
#ifdef CONFIG_SMP
163
-
;; Read CPU ID
164
-
move 0, $srs
165
-
nop
166
-
nop
167
-
nop
168
-
move $s12, $r0
169
-
cmpq 0, $r0
170
-
beq master_cpu
171
-
nop
172
-
slave_cpu:
173
-
; Time to boot-up. Get stack location provided by master CPU.
174
-
move.d smp_init_current_idle_thread, $r1
175
-
move.d [$r1], $sp
176
-
add.d 8192, $sp
177
-
move.d ebp_start, $r0 ; Defined in linker-script.
178
-
move $r0, $ebp
179
-
jsr smp_callin
180
-
nop
181
-
master_cpu:
182
-
/* Set up entry point for secondary CPUs. The boot ROM has set up
183
-
* EBP at start of internal memory. The CPU will get there
184
-
* later when we issue an IPI to them... */
185
-
move.d MEM_INTMEM_START + IPI_INTR_VECT * 4, $r0
186
-
move.d secondary_cpu_entry, $r1
187
-
move.d $r1, [$r0]
188
-
#endif
189
167
; Check if starting from DRAM (network->RAM boot or unpacked
190
168
; compressed kernel), or directly from flash.
191
169
lapcq ., $r0
+25
-6
arch/cris/arch-v32/kernel/irq.c
+25
-6
arch/cris/arch-v32/kernel/irq.c
···
10
10
#include <linux/errno.h>
11
11
#include <linux/init.h>
12
12
#include <linux/profile.h>
13
+
#include <linux/of.h>
14
+
#include <linux/of_irq.h>
13
15
#include <linux/proc_fs.h>
14
16
#include <linux/seq_file.h>
15
17
#include <linux/threads.h>
···
58
56
static unsigned long irq_regs[NR_CPUS] =
59
57
{
60
58
regi_irq,
61
-
#ifdef CONFIG_SMP
62
-
regi_irq2,
63
-
#endif
64
59
};
65
60
66
61
#if NR_REAL_IRQS > 32
···
430
431
irq_exit();
431
432
}
432
433
434
+
static int crisv32_irq_map(struct irq_domain *h, unsigned int virq,
435
+
irq_hw_number_t hw_irq_num)
436
+
{
437
+
irq_set_chip_and_handler(virq, &crisv32_irq_type, handle_simple_irq);
438
+
439
+
return 0;
440
+
}
441
+
442
+
static struct irq_domain_ops crisv32_irq_ops = {
443
+
.map = crisv32_irq_map,
444
+
.xlate = irq_domain_xlate_onecell,
445
+
};
446
+
433
447
/*
434
448
* This is called by start_kernel. It fixes the IRQ masks and setup the
435
449
* interrupt vector table to point to bad_interrupt pointers.
···
453
441
int i;
454
442
int j;
455
443
reg_intr_vect_rw_mask vect_mask = {0};
444
+
struct device_node *np;
445
+
struct irq_domain *domain;
456
446
457
447
/* Clear all interrupts masks. */
458
448
for (i = 0; i < NBR_REGS; i++)
···
463
449
for (i = 0; i < 256; i++)
464
450
etrax_irv->v[i] = weird_irq;
465
451
466
-
/* Point all IRQ's to bad handlers. */
452
+
np = of_find_compatible_node(NULL, NULL, "axis,crisv32-intc");
453
+
domain = irq_domain_add_legacy(np, NR_IRQS - FIRST_IRQ,
454
+
FIRST_IRQ, FIRST_IRQ,
455
+
&crisv32_irq_ops, NULL);
456
+
BUG_ON(!domain);
457
+
irq_set_default_host(domain);
458
+
of_node_put(np);
459
+
467
460
for (i = FIRST_IRQ, j = 0; j < NR_IRQS; i++, j++) {
468
-
irq_set_chip_and_handler(j, &crisv32_irq_type,
469
-
handle_simple_irq);
470
461
set_exception_vector(i, interrupt[j]);
471
462
}
472
463
-5
arch/cris/arch-v32/kernel/setup.c
-5
arch/cris/arch-v32/kernel/setup.c
+5
arch/cris/arch-v32/kernel/signal.c
+5
arch/cris/arch-v32/kernel/signal.c
···
72
72
/* Make that the user-mode flag is set. */
73
73
regs->ccs |= (1 << (U_CCS_BITNR + CCS_SHIFT));
74
74
75
+
/* Don't perform syscall restarting */
76
+
regs->exs = -1;
77
+
75
78
/* Restore the old USP. */
76
79
err |= __get_user(old_usp, &sc->usp);
77
80
wrusp(old_usp);
···
427
424
do_signal(int canrestart, struct pt_regs *regs)
428
425
{
429
426
struct ksignal ksig;
427
+
428
+
canrestart = canrestart && ((int)regs->exs >= 0);
430
429
431
430
/*
432
431
* The common case should go fast, which is why this point is
-358
arch/cris/arch-v32/kernel/smp.c
-358
arch/cris/arch-v32/kernel/smp.c
···
1
-
#include <linux/types.h>
2
-
#include <asm/delay.h>
3
-
#include <irq.h>
4
-
#include <hwregs/intr_vect.h>
5
-
#include <hwregs/intr_vect_defs.h>
6
-
#include <asm/tlbflush.h>
7
-
#include <asm/mmu_context.h>
8
-
#include <hwregs/asm/mmu_defs_asm.h>
9
-
#include <hwregs/supp_reg.h>
10
-
#include <linux/atomic.h>
11
-
12
-
#include <linux/err.h>
13
-
#include <linux/init.h>
14
-
#include <linux/timex.h>
15
-
#include <linux/sched.h>
16
-
#include <linux/kernel.h>
17
-
#include <linux/cpumask.h>
18
-
#include <linux/interrupt.h>
19
-
#include <linux/module.h>
20
-
21
-
#define IPI_SCHEDULE 1
22
-
#define IPI_CALL 2
23
-
#define IPI_FLUSH_TLB 4
24
-
#define IPI_BOOT 8
25
-
26
-
#define FLUSH_ALL (void*)0xffffffff
27
-
28
-
/* Vector of locks used for various atomic operations */
29
-
spinlock_t cris_atomic_locks[] = {
30
-
[0 ... LOCK_COUNT - 1] = __SPIN_LOCK_UNLOCKED(cris_atomic_locks)
31
-
};
32
-
33
-
/* CPU masks */
34
-
cpumask_t phys_cpu_present_map = CPU_MASK_NONE;
35
-
EXPORT_SYMBOL(phys_cpu_present_map);
36
-
37
-
/* Variables used during SMP boot */
38
-
volatile int cpu_now_booting = 0;
39
-
volatile struct thread_info *smp_init_current_idle_thread;
40
-
41
-
/* Variables used during IPI */
42
-
static DEFINE_SPINLOCK(call_lock);
43
-
static DEFINE_SPINLOCK(tlbstate_lock);
44
-
45
-
struct call_data_struct {
46
-
void (*func) (void *info);
47
-
void *info;
48
-
int wait;
49
-
};
50
-
51
-
static struct call_data_struct * call_data;
52
-
53
-
static struct mm_struct* flush_mm;
54
-
static struct vm_area_struct* flush_vma;
55
-
static unsigned long flush_addr;
56
-
57
-
/* Mode registers */
58
-
static unsigned long irq_regs[NR_CPUS] = {
59
-
regi_irq,
60
-
regi_irq2
61
-
};
62
-
63
-
static irqreturn_t crisv32_ipi_interrupt(int irq, void *dev_id);
64
-
static int send_ipi(int vector, int wait, cpumask_t cpu_mask);
65
-
static struct irqaction irq_ipi = {
66
-
.handler = crisv32_ipi_interrupt,
67
-
.flags = 0,
68
-
.name = "ipi",
69
-
};
70
-
71
-
extern void cris_mmu_init(void);
72
-
extern void cris_timer_init(void);
73
-
74
-
/* SMP initialization */
75
-
void __init smp_prepare_cpus(unsigned int max_cpus)
76
-
{
77
-
int i;
78
-
79
-
/* From now on we can expect IPIs so set them up */
80
-
setup_irq(IPI_INTR_VECT, &irq_ipi);
81
-
82
-
/* Mark all possible CPUs as present */
83
-
for (i = 0; i < max_cpus; i++)
84
-
cpumask_set_cpu(i, &phys_cpu_present_map);
85
-
}
86
-
87
-
void smp_prepare_boot_cpu(void)
88
-
{
89
-
/* PGD pointer has moved after per_cpu initialization so
90
-
* update the MMU.
91
-
*/
92
-
pgd_t **pgd;
93
-
pgd = (pgd_t**)&per_cpu(current_pgd, smp_processor_id());
94
-
95
-
SUPP_BANK_SEL(1);
96
-
SUPP_REG_WR(RW_MM_TLB_PGD, pgd);
97
-
SUPP_BANK_SEL(2);
98
-
SUPP_REG_WR(RW_MM_TLB_PGD, pgd);
99
-
100
-
set_cpu_online(0, true);
101
-
cpumask_set_cpu(0, &phys_cpu_present_map);
102
-
set_cpu_possible(0, true);
103
-
}
104
-
105
-
void __init smp_cpus_done(unsigned int max_cpus)
106
-
{
107
-
}
108
-
109
-
/* Bring one cpu online.*/
110
-
static int __init
111
-
smp_boot_one_cpu(int cpuid, struct task_struct idle)
112
-
{
113
-
unsigned timeout;
114
-
cpumask_t cpu_mask;
115
-
116
-
cpumask_clear(&cpu_mask);
117
-
task_thread_info(idle)->cpu = cpuid;
118
-
119
-
/* Information to the CPU that is about to boot */
120
-
smp_init_current_idle_thread = task_thread_info(idle);
121
-
cpu_now_booting = cpuid;
122
-
123
-
/* Kick it */
124
-
set_cpu_online(cpuid, true);
125
-
cpumask_set_cpu(cpuid, &cpu_mask);
126
-
send_ipi(IPI_BOOT, 0, cpu_mask);
127
-
set_cpu_online(cpuid, false);
128
-
129
-
/* Wait for CPU to come online */
130
-
for (timeout = 0; timeout < 10000; timeout++) {
131
-
if(cpu_online(cpuid)) {
132
-
cpu_now_booting = 0;
133
-
smp_init_current_idle_thread = NULL;
134
-
return 0; /* CPU online */
135
-
}
136
-
udelay(100);
137
-
barrier();
138
-
}
139
-
140
-
printk(KERN_CRIT "SMP: CPU:%d is stuck.\n", cpuid);
141
-
return -1;
142
-
}
143
-
144
-
/* Secondary CPUs starts using C here. Here we need to setup CPU
145
-
* specific stuff such as the local timer and the MMU. */
146
-
void __init smp_callin(void)
147
-
{
148
-
int cpu = cpu_now_booting;
149
-
reg_intr_vect_rw_mask vect_mask = {0};
150
-
151
-
/* Initialise the idle task for this CPU */
152
-
atomic_inc(&init_mm.mm_count);
153
-
current->active_mm = &init_mm;
154
-
155
-
/* Set up MMU */
156
-
cris_mmu_init();
157
-
__flush_tlb_all();
158
-
159
-
/* Setup local timer. */
160
-
cris_timer_init();
161
-
162
-
/* Enable IRQ and idle */
163
-
REG_WR(intr_vect, irq_regs[cpu], rw_mask, vect_mask);
164
-
crisv32_unmask_irq(IPI_INTR_VECT);
165
-
crisv32_unmask_irq(TIMER0_INTR_VECT);
166
-
preempt_disable();
167
-
notify_cpu_starting(cpu);
168
-
local_irq_enable();
169
-
170
-
set_cpu_online(cpu, true);
171
-
cpu_startup_entry(CPUHP_ONLINE);
172
-
}
173
-
174
-
/* Stop execution on this CPU.*/
175
-
void stop_this_cpu(void* dummy)
176
-
{
177
-
local_irq_disable();
178
-
asm volatile("halt");
179
-
}
180
-
181
-
/* Other calls */
182
-
void smp_send_stop(void)
183
-
{
184
-
smp_call_function(stop_this_cpu, NULL, 0);
185
-
}
186
-
187
-
int setup_profiling_timer(unsigned int multiplier)
188
-
{
189
-
return -EINVAL;
190
-
}
191
-
192
-
193
-
/* cache_decay_ticks is used by the scheduler to decide if a process
194
-
* is "hot" on one CPU. A higher value means a higher penalty to move
195
-
* a process to another CPU. Our cache is rather small so we report
196
-
* 1 tick.
197
-
*/
198
-
unsigned long cache_decay_ticks = 1;
199
-
200
-
int __cpu_up(unsigned int cpu, struct task_struct *tidle)
201
-
{
202
-
smp_boot_one_cpu(cpu, tidle);
203
-
return cpu_online(cpu) ? 0 : -ENOSYS;
204
-
}
205
-
206
-
void smp_send_reschedule(int cpu)
207
-
{
208
-
cpumask_t cpu_mask;
209
-
cpumask_clear(&cpu_mask);
210
-
cpumask_set_cpu(cpu, &cpu_mask);
211
-
send_ipi(IPI_SCHEDULE, 0, cpu_mask);
212
-
}
213
-
214
-
/* TLB flushing
215
-
*
216
-
* Flush needs to be done on the local CPU and on any other CPU that
217
-
* may have the same mapping. The mm->cpu_vm_mask is used to keep track
218
-
* of which CPUs that a specific process has been executed on.
219
-
*/
220
-
void flush_tlb_common(struct mm_struct* mm, struct vm_area_struct* vma, unsigned long addr)
221
-
{
222
-
unsigned long flags;
223
-
cpumask_t cpu_mask;
224
-
225
-
spin_lock_irqsave(&tlbstate_lock, flags);
226
-
cpu_mask = (mm == FLUSH_ALL ? cpu_all_mask : *mm_cpumask(mm));
227
-
cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
228
-
flush_mm = mm;
229
-
flush_vma = vma;
230
-
flush_addr = addr;
231
-
send_ipi(IPI_FLUSH_TLB, 1, cpu_mask);
232
-
spin_unlock_irqrestore(&tlbstate_lock, flags);
233
-
}
234
-
235
-
void flush_tlb_all(void)
236
-
{
237
-
__flush_tlb_all();
238
-
flush_tlb_common(FLUSH_ALL, FLUSH_ALL, 0);
239
-
}
240
-
241
-
void flush_tlb_mm(struct mm_struct *mm)
242
-
{
243
-
__flush_tlb_mm(mm);
244
-
flush_tlb_common(mm, FLUSH_ALL, 0);
245
-
/* No more mappings in other CPUs */
246
-
cpumask_clear(mm_cpumask(mm));
247
-
cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
248
-
}
249
-
250
-
void flush_tlb_page(struct vm_area_struct *vma,
251
-
unsigned long addr)
252
-
{
253
-
__flush_tlb_page(vma, addr);
254
-
flush_tlb_common(vma->vm_mm, vma, addr);
255
-
}
256
-
257
-
/* Inter processor interrupts
258
-
*
259
-
* The IPIs are used for:
260
-
* * Force a schedule on a CPU
261
-
* * FLush TLB on other CPUs
262
-
* * Call a function on other CPUs
263
-
*/
264
-
265
-
int send_ipi(int vector, int wait, cpumask_t cpu_mask)
266
-
{
267
-
int i = 0;
268
-
reg_intr_vect_rw_ipi ipi = REG_RD(intr_vect, irq_regs[i], rw_ipi);
269
-
int ret = 0;
270
-
271
-
/* Calculate CPUs to send to. */
272
-
cpumask_and(&cpu_mask, &cpu_mask, cpu_online_mask);
273
-
274
-
/* Send the IPI. */
275
-
for_each_cpu(i, &cpu_mask)
276
-
{
277
-
ipi.vector |= vector;
278
-
REG_WR(intr_vect, irq_regs[i], rw_ipi, ipi);
279
-
}
280
-
281
-
/* Wait for IPI to finish on other CPUS */
282
-
if (wait) {
283
-
for_each_cpu(i, &cpu_mask) {
284
-
int j;
285
-
for (j = 0 ; j < 1000; j++) {
286
-
ipi = REG_RD(intr_vect, irq_regs[i], rw_ipi);
287
-
if (!ipi.vector)
288
-
break;
289
-
udelay(100);
290
-
}
291
-
292
-
/* Timeout? */
293
-
if (ipi.vector) {
294
-
printk("SMP call timeout from %d to %d\n", smp_processor_id(), i);
295
-
ret = -ETIMEDOUT;
296
-
dump_stack();
297
-
}
298
-
}
299
-
}
300
-
return ret;
301
-
}
302
-
303
-
/*
304
-
* You must not call this function with disabled interrupts or from a
305
-
* hardware interrupt handler or from a bottom half handler.
306
-
*/
307
-
int smp_call_function(void (*func)(void *info), void *info, int wait)
308
-
{
309
-
cpumask_t cpu_mask;
310
-
struct call_data_struct data;
311
-
int ret;
312
-
313
-
cpumask_setall(&cpu_mask);
314
-
cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
315
-
316
-
WARN_ON(irqs_disabled());
317
-
318
-
data.func = func;
319
-
data.info = info;
320
-
data.wait = wait;
321
-
322
-
spin_lock(&call_lock);
323
-
call_data = &data;
324
-
ret = send_ipi(IPI_CALL, wait, cpu_mask);
325
-
spin_unlock(&call_lock);
326
-
327
-
return ret;
328
-
}
329
-
330
-
irqreturn_t crisv32_ipi_interrupt(int irq, void *dev_id)
331
-
{
332
-
void (*func) (void *info) = call_data->func;
333
-
void *info = call_data->info;
334
-
reg_intr_vect_rw_ipi ipi;
335
-
336
-
ipi = REG_RD(intr_vect, irq_regs[smp_processor_id()], rw_ipi);
337
-
338
-
if (ipi.vector & IPI_SCHEDULE) {
339
-
scheduler_ipi();
340
-
}
341
-
if (ipi.vector & IPI_CALL) {
342
-
func(info);
343
-
}
344
-
if (ipi.vector & IPI_FLUSH_TLB) {
345
-
if (flush_mm == FLUSH_ALL)
346
-
__flush_tlb_all();
347
-
else if (flush_vma == FLUSH_ALL)
348
-
__flush_tlb_mm(flush_mm);
349
-
else
350
-
__flush_tlb_page(flush_vma, flush_addr);
351
-
}
352
-
353
-
ipi.vector = 0;
354
-
REG_WR(intr_vect, irq_regs[smp_processor_id()], rw_ipi, ipi);
355
-
356
-
return IRQ_HANDLED;
357
-
}
358
-
+98
-84
arch/cris/arch-v32/kernel/time.c
+98
-84
arch/cris/arch-v32/kernel/time.c
···
8
8
#include <linux/timex.h>
9
9
#include <linux/time.h>
10
10
#include <linux/clocksource.h>
11
+
#include <linux/clockchips.h>
11
12
#include <linux/interrupt.h>
12
13
#include <linux/swap.h>
13
14
#include <linux/sched.h>
14
15
#include <linux/init.h>
15
16
#include <linux/threads.h>
16
17
#include <linux/cpufreq.h>
18
+
#include <linux/sched_clock.h>
17
19
#include <linux/mm.h>
18
20
#include <asm/types.h>
19
21
#include <asm/signal.h>
···
38
36
/* Number of 763 counts before watchdog bites */
39
37
#define ETRAX_WD_CNT ((2*ETRAX_WD_HZ)/HZ + 1)
40
38
41
-
/* Register the continuos readonly timer available in FS and ARTPEC-3. */
42
-
static cycle_t read_cont_rotime(struct clocksource *cs)
43
-
{
44
-
return (u32)REG_RD(timer, regi_timer0, r_time);
45
-
}
46
-
47
-
static struct clocksource cont_rotime = {
48
-
.name = "crisv32_rotime",
49
-
.rating = 300,
50
-
.read = read_cont_rotime,
51
-
.mask = CLOCKSOURCE_MASK(32),
52
-
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
53
-
};
54
-
55
-
static int __init etrax_init_cont_rotime(void)
56
-
{
57
-
clocksource_register_khz(&cont_rotime, 100000);
58
-
return 0;
59
-
}
60
-
arch_initcall(etrax_init_cont_rotime);
39
+
#define CRISV32_TIMER_FREQ (100000000lu)
61
40
62
41
unsigned long timer_regs[NR_CPUS] =
63
42
{
64
43
regi_timer0,
65
-
#ifdef CONFIG_SMP
66
-
regi_timer2
67
-
#endif
68
44
};
69
45
70
46
extern int set_rtc_mmss(unsigned long nowtime);
···
169
189
#endif
170
190
}
171
191
172
-
/*
173
-
* timer_interrupt() needs to keep up the real-time clock,
174
-
* as well as call the "xtime_update()" routine every clocktick.
175
-
*/
176
-
extern void cris_do_profile(struct pt_regs *regs);
192
+
extern void cris_profile_sample(struct pt_regs *regs);
193
+
static void __iomem *timer_base;
177
194
178
-
static inline irqreturn_t timer_interrupt(int irq, void *dev_id)
195
+
static void crisv32_clkevt_mode(enum clock_event_mode mode,
196
+
struct clock_event_device *dev)
179
197
{
180
-
struct pt_regs *regs = get_irq_regs();
181
-
int cpu = smp_processor_id();
182
-
reg_timer_r_masked_intr masked_intr;
183
-
reg_timer_rw_ack_intr ack_intr = { 0 };
198
+
reg_timer_rw_tmr0_ctrl ctrl = {
199
+
.op = regk_timer_hold,
200
+
.freq = regk_timer_f100,
201
+
};
184
202
185
-
/* Check if the timer interrupt is for us (a tmr0 int) */
186
-
masked_intr = REG_RD(timer, timer_regs[cpu], r_masked_intr);
187
-
if (!masked_intr.tmr0)
203
+
REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
204
+
}
205
+
206
+
static int crisv32_clkevt_next_event(unsigned long evt,
207
+
struct clock_event_device *dev)
208
+
{
209
+
reg_timer_rw_tmr0_ctrl ctrl = {
210
+
.op = regk_timer_ld,
211
+
.freq = regk_timer_f100,
212
+
};
213
+
214
+
REG_WR(timer, timer_base, rw_tmr0_div, evt);
215
+
REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
216
+
217
+
ctrl.op = regk_timer_run;
218
+
REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
219
+
220
+
return 0;
221
+
}
222
+
223
+
static irqreturn_t crisv32_timer_interrupt(int irq, void *dev_id)
224
+
{
225
+
struct clock_event_device *evt = dev_id;
226
+
reg_timer_rw_tmr0_ctrl ctrl = {
227
+
.op = regk_timer_hold,
228
+
.freq = regk_timer_f100,
229
+
};
230
+
reg_timer_rw_ack_intr ack = { .tmr0 = 1 };
231
+
reg_timer_r_masked_intr intr;
232
+
233
+
intr = REG_RD(timer, timer_base, r_masked_intr);
234
+
if (!intr.tmr0)
188
235
return IRQ_NONE;
189
236
190
-
/* Acknowledge the timer irq. */
191
-
ack_intr.tmr0 = 1;
192
-
REG_WR(timer, timer_regs[cpu], rw_ack_intr, ack_intr);
237
+
REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
238
+
REG_WR(timer, timer_base, rw_ack_intr, ack);
193
239
194
-
/* Reset watchdog otherwise it resets us! */
195
240
reset_watchdog();
241
+
#ifdef CONFIG_SYSTEM_PROFILER
242
+
cris_profile_sample(get_irq_regs());
243
+
#endif
196
244
197
-
/* Update statistics. */
198
-
update_process_times(user_mode(regs));
245
+
evt->event_handler(evt);
199
246
200
-
cris_do_profile(regs); /* Save profiling information */
201
-
202
-
/* The master CPU is responsible for the time keeping. */
203
-
if (cpu != 0)
204
-
return IRQ_HANDLED;
205
-
206
-
/* Call the real timer interrupt handler */
207
-
xtime_update(1);
208
247
return IRQ_HANDLED;
209
248
}
210
249
211
-
/* Timer is IRQF_SHARED so drivers can add stuff to the timer irq chain. */
212
-
static struct irqaction irq_timer = {
213
-
.handler = timer_interrupt,
214
-
.flags = IRQF_SHARED,
215
-
.name = "timer"
250
+
static struct clock_event_device crisv32_clockevent = {
251
+
.name = "crisv32-timer",
252
+
.rating = 300,
253
+
.features = CLOCK_EVT_FEAT_ONESHOT,
254
+
.set_mode = crisv32_clkevt_mode,
255
+
.set_next_event = crisv32_clkevt_next_event,
216
256
};
217
257
218
-
void __init cris_timer_init(void)
258
+
/* Timer is IRQF_SHARED so drivers can add stuff to the timer irq chain. */
259
+
static struct irqaction irq_timer = {
260
+
.handler = crisv32_timer_interrupt,
261
+
.flags = IRQF_TIMER | IRQF_SHARED,
262
+
.name = "crisv32-timer",
263
+
.dev_id = &crisv32_clockevent,
264
+
};
265
+
266
+
static u64 notrace crisv32_timer_sched_clock(void)
219
267
{
220
-
int cpu = smp_processor_id();
221
-
reg_timer_rw_tmr0_ctrl tmr0_ctrl = { 0 };
222
-
reg_timer_rw_tmr0_div tmr0_div = TIMER0_DIV;
268
+
return REG_RD(timer, timer_base, r_time);
269
+
}
270
+
271
+
static void __init crisv32_timer_init(void)
272
+
{
223
273
reg_timer_rw_intr_mask timer_intr_mask;
274
+
reg_timer_rw_tmr0_ctrl ctrl = {
275
+
.op = regk_timer_hold,
276
+
.freq = regk_timer_f100,
277
+
};
224
278
225
-
/* Setup the etrax timers.
226
-
* Base frequency is 100MHz, divider 1000000 -> 100 HZ
227
-
* We use timer0, so timer1 is free.
228
-
* The trig timer is used by the fasttimer API if enabled.
229
-
*/
279
+
REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
230
280
231
-
tmr0_ctrl.op = regk_timer_ld;
232
-
tmr0_ctrl.freq = regk_timer_f100;
233
-
REG_WR(timer, timer_regs[cpu], rw_tmr0_div, tmr0_div);
234
-
REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Load */
235
-
tmr0_ctrl.op = regk_timer_run;
236
-
REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Start */
237
-
238
-
/* Enable the timer irq. */
239
-
timer_intr_mask = REG_RD(timer, timer_regs[cpu], rw_intr_mask);
281
+
timer_intr_mask = REG_RD(timer, timer_base, rw_intr_mask);
240
282
timer_intr_mask.tmr0 = 1;
241
-
REG_WR(timer, timer_regs[cpu], rw_intr_mask, timer_intr_mask);
283
+
REG_WR(timer, timer_base, rw_intr_mask, timer_intr_mask);
242
284
}
243
285
244
286
void __init time_init(void)
245
287
{
246
-
reg_intr_vect_rw_mask intr_mask;
288
+
int irq;
289
+
int ret;
247
290
248
291
/* Probe for the RTC and read it if it exists.
249
292
* Before the RTC can be probed the loops_per_usec variable needs
···
276
273
*/
277
274
loops_per_usec = 50;
278
275
279
-
/* Start CPU local timer. */
280
-
cris_timer_init();
276
+
irq = TIMER0_INTR_VECT;
277
+
timer_base = (void __iomem *) regi_timer0;
281
278
282
-
/* Enable the timer irq in global config. */
283
-
intr_mask = REG_RD_VECT(intr_vect, regi_irq, rw_mask, 1);
284
-
intr_mask.timer0 = 1;
285
-
REG_WR_VECT(intr_vect, regi_irq, rw_mask, 1, intr_mask);
279
+
crisv32_timer_init();
286
280
287
-
/* Now actually register the timer irq handler that calls
288
-
* timer_interrupt(). */
289
-
setup_irq(TIMER0_INTR_VECT, &irq_timer);
281
+
sched_clock_register(crisv32_timer_sched_clock, 32,
282
+
CRISV32_TIMER_FREQ);
283
+
284
+
clocksource_mmio_init(timer_base + REG_RD_ADDR_timer_r_time,
285
+
"crisv32-timer", CRISV32_TIMER_FREQ,
286
+
300, 32, clocksource_mmio_readl_up);
287
+
288
+
crisv32_clockevent.cpumask = cpu_possible_mask;
289
+
crisv32_clockevent.irq = irq;
290
+
291
+
ret = setup_irq(irq, &irq_timer);
292
+
if (ret)
293
+
pr_warn("failed to setup irq %d\n", irq);
294
+
295
+
clockevents_config_and_register(&crisv32_clockevent,
296
+
CRISV32_TIMER_FREQ,
297
+
2, 0xffffffff);
290
298
291
299
/* Enable watchdog if we should use one. */
292
300
+1
-1
arch/cris/arch-v32/lib/Makefile
+1
-1
arch/cris/arch-v32/lib/Makefile
-40
arch/cris/arch-v32/lib/spinlock.S
-40
arch/cris/arch-v32/lib/spinlock.S
···
1
-
;; Core of the spinlock implementation
2
-
;;
3
-
;; Copyright (C) 2004 Axis Communications AB.
4
-
;;
5
-
;; Author: Mikael Starvik
6
-
7
-
8
-
.global cris_spin_lock
9
-
.type cris_spin_lock,@function
10
-
.global cris_spin_trylock
11
-
.type cris_spin_trylock,@function
12
-
13
-
.text
14
-
15
-
cris_spin_lock:
16
-
clearf p
17
-
1: test.b [$r10]
18
-
beq 1b
19
-
clearf p
20
-
ax
21
-
clear.b [$r10]
22
-
bcs 1b
23
-
clearf p
24
-
ret
25
-
nop
26
-
27
-
.size cris_spin_lock, . - cris_spin_lock
28
-
29
-
cris_spin_trylock:
30
-
clearf p
31
-
1: move.b [$r10], $r11
32
-
ax
33
-
clear.b [$r10]
34
-
bcs 1b
35
-
clearf p
36
-
ret
37
-
movu.b $r11,$r10
38
-
39
-
.size cris_spin_trylock, . - cris_spin_trylock
40
-
-11
arch/cris/arch-v32/mm/init.c
-11
arch/cris/arch-v32/mm/init.c
···
40
40
*/
41
41
per_cpu(current_pgd, smp_processor_id()) = init_mm.pgd;
42
42
43
-
#ifdef CONFIG_SMP
44
-
{
45
-
pgd_t **pgd;
46
-
pgd = (pgd_t**)&per_cpu(current_pgd, smp_processor_id());
47
-
SUPP_BANK_SEL(1);
48
-
SUPP_REG_WR(RW_MM_TLB_PGD, pgd);
49
-
SUPP_BANK_SEL(2);
50
-
SUPP_REG_WR(RW_MM_TLB_PGD, pgd);
51
-
}
52
-
#endif
53
-
54
43
/* Initialise the TLB. Function found in tlb.c. */
55
44
tlb_init();
56
45
-4
arch/cris/arch-v32/mm/mmu.S
-4
arch/cris/arch-v32/mm/mmu.S
···
115
115
move.d $r0, [$r1] ; last_refill_cause = rw_mm_cause
116
116
117
117
3: ; Probably not in a loop, continue normal processing
118
-
#ifdef CONFIG_SMP
119
-
move $s7, $acr ; PGD
120
-
#else
121
118
move.d current_pgd, $acr ; PGD
122
-
#endif
123
119
; Look up PMD in PGD
124
120
lsrq 24, $r0 ; Get PMD index into PGD (bit 24-31)
125
121
move.d [$acr], $acr ; PGD for the current process
+6
arch/cris/boot/dts/Makefile
+6
arch/cris/boot/dts/Makefile
+18
arch/cris/boot/dts/dev88.dts
+18
arch/cris/boot/dts/dev88.dts
+38
arch/cris/boot/dts/etraxfs.dtsi
+38
arch/cris/boot/dts/etraxfs.dtsi
···
1
+
/ {
2
+
#address-cells = <1>;
3
+
#size-cells = <1>;
4
+
interrupt-parent = <&intc>;
5
+
6
+
cpus {
7
+
#address-cells = <1>;
8
+
#size-cells = <0>;
9
+
10
+
cpu@0 {
11
+
device_type = "cpu";
12
+
model = "axis,crisv32";
13
+
reg = <0>;
14
+
};
15
+
};
16
+
17
+
soc {
18
+
compatible = "simple-bus";
19
+
model = "etraxfs";
20
+
#address-cells = <1>;
21
+
#size-cells = <1>;
22
+
ranges;
23
+
24
+
intc: interrupt-controller {
25
+
compatible = "axis,crisv32-intc";
26
+
reg = <0xb001c000 0x1000>;
27
+
interrupt-controller;
28
+
#interrupt-cells = <1>;
29
+
};
30
+
31
+
serial@b00260000 {
32
+
compatible = "axis,etraxfs-uart";
33
+
reg = <0xb0026000 0x1000>;
34
+
interrupts = <68>;
35
+
status = "disabled";
36
+
};
37
+
};
38
+
};
-7
arch/cris/include/arch-v10/arch/atomic.h
-7
arch/cris/include/arch-v10/arch/atomic.h
-8
arch/cris/include/arch-v10/arch/system.h
-8
arch/cris/include/arch-v10/arch/system.h
···
36
36
return 0;
37
37
}
38
38
39
-
#define nop() __asm__ __volatile__ ("nop");
40
-
41
-
#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
42
-
#define tas(ptr) (xchg((ptr),1))
43
-
44
-
struct __xchg_dummy { unsigned long a[100]; };
45
-
#define __xg(x) ((struct __xchg_dummy *)(x))
46
-
47
39
#endif
-36
arch/cris/include/arch-v32/arch/atomic.h
-36
arch/cris/include/arch-v32/arch/atomic.h
···
1
-
#ifndef __ASM_CRIS_ARCH_ATOMIC__
2
-
#define __ASM_CRIS_ARCH_ATOMIC__
3
-
4
-
#include <linux/spinlock_types.h>
5
-
6
-
extern void cris_spin_unlock(void *l, int val);
7
-
extern void cris_spin_lock(void *l);
8
-
extern int cris_spin_trylock(void* l);
9
-
10
-
#ifndef CONFIG_SMP
11
-
#define cris_atomic_save(addr, flags) local_irq_save(flags);
12
-
#define cris_atomic_restore(addr, flags) local_irq_restore(flags);
13
-
#else
14
-
15
-
extern spinlock_t cris_atomic_locks[];
16
-
#define LOCK_COUNT 128
17
-
#define HASH_ADDR(a) (((int)a) & 127)
18
-
19
-
#define cris_atomic_save(addr, flags) \
20
-
local_irq_save(flags); \
21
-
cris_spin_lock((void *)&cris_atomic_locks[HASH_ADDR(addr)].raw_lock.slock);
22
-
23
-
#define cris_atomic_restore(addr, flags) \
24
-
{ \
25
-
spinlock_t *lock = (void*)&cris_atomic_locks[HASH_ADDR(addr)]; \
26
-
__asm__ volatile ("move.d %1,%0" \
27
-
: "=m" (lock->raw_lock.slock) \
28
-
: "r" (1) \
29
-
: "memory"); \
30
-
local_irq_restore(flags); \
31
-
}
32
-
33
-
#endif
34
-
35
-
#endif
36
-
+1
-2
arch/cris/include/arch-v32/arch/processor.h
+1
-2
arch/cris/include/arch-v32/arch/processor.h
-131
arch/cris/include/arch-v32/arch/spinlock.h
-131
arch/cris/include/arch-v32/arch/spinlock.h
···
1
-
#ifndef __ASM_ARCH_SPINLOCK_H
2
-
#define __ASM_ARCH_SPINLOCK_H
3
-
4
-
#include <linux/spinlock_types.h>
5
-
6
-
#define RW_LOCK_BIAS 0x01000000
7
-
8
-
extern void cris_spin_unlock(void *l, int val);
9
-
extern void cris_spin_lock(void *l);
10
-
extern int cris_spin_trylock(void *l);
11
-
12
-
static inline int arch_spin_is_locked(arch_spinlock_t *x)
13
-
{
14
-
return *(volatile signed char *)(&(x)->slock) <= 0;
15
-
}
16
-
17
-
static inline void arch_spin_unlock(arch_spinlock_t *lock)
18
-
{
19
-
__asm__ volatile ("move.d %1,%0" \
20
-
: "=m" (lock->slock) \
21
-
: "r" (1) \
22
-
: "memory");
23
-
}
24
-
25
-
static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
26
-
{
27
-
while (arch_spin_is_locked(lock))
28
-
cpu_relax();
29
-
}
30
-
31
-
static inline int arch_spin_trylock(arch_spinlock_t *lock)
32
-
{
33
-
return cris_spin_trylock((void *)&lock->slock);
34
-
}
35
-
36
-
static inline void arch_spin_lock(arch_spinlock_t *lock)
37
-
{
38
-
cris_spin_lock((void *)&lock->slock);
39
-
}
40
-
41
-
static inline void
42
-
arch_spin_lock_flags(arch_spinlock_t *lock, unsigned long flags)
43
-
{
44
-
arch_spin_lock(lock);
45
-
}
46
-
47
-
/*
48
-
* Read-write spinlocks, allowing multiple readers
49
-
* but only one writer.
50
-
*
51
-
* NOTE! it is quite common to have readers in interrupts
52
-
* but no interrupt writers. For those circumstances we
53
-
* can "mix" irq-safe locks - any writer needs to get a
54
-
* irq-safe write-lock, but readers can get non-irqsafe
55
-
* read-locks.
56
-
*
57
-
*/
58
-
59
-
static inline int arch_read_can_lock(arch_rwlock_t *x)
60
-
{
61
-
return (int)(x)->lock > 0;
62
-
}
63
-
64
-
static inline int arch_write_can_lock(arch_rwlock_t *x)
65
-
{
66
-
return (x)->lock == RW_LOCK_BIAS;
67
-
}
68
-
69
-
static inline void arch_read_lock(arch_rwlock_t *rw)
70
-
{
71
-
arch_spin_lock(&rw->slock);
72
-
while (rw->lock == 0);
73
-
rw->lock--;
74
-
arch_spin_unlock(&rw->slock);
75
-
}
76
-
77
-
static inline void arch_write_lock(arch_rwlock_t *rw)
78
-
{
79
-
arch_spin_lock(&rw->slock);
80
-
while (rw->lock != RW_LOCK_BIAS);
81
-
rw->lock = 0;
82
-
arch_spin_unlock(&rw->slock);
83
-
}
84
-
85
-
static inline void arch_read_unlock(arch_rwlock_t *rw)
86
-
{
87
-
arch_spin_lock(&rw->slock);
88
-
rw->lock++;
89
-
arch_spin_unlock(&rw->slock);
90
-
}
91
-
92
-
static inline void arch_write_unlock(arch_rwlock_t *rw)
93
-
{
94
-
arch_spin_lock(&rw->slock);
95
-
while (rw->lock != RW_LOCK_BIAS);
96
-
rw->lock = RW_LOCK_BIAS;
97
-
arch_spin_unlock(&rw->slock);
98
-
}
99
-
100
-
static inline int arch_read_trylock(arch_rwlock_t *rw)
101
-
{
102
-
int ret = 0;
103
-
arch_spin_lock(&rw->slock);
104
-
if (rw->lock != 0) {
105
-
rw->lock--;
106
-
ret = 1;
107
-
}
108
-
arch_spin_unlock(&rw->slock);
109
-
return ret;
110
-
}
111
-
112
-
static inline int arch_write_trylock(arch_rwlock_t *rw)
113
-
{
114
-
int ret = 0;
115
-
arch_spin_lock(&rw->slock);
116
-
if (rw->lock == RW_LOCK_BIAS) {
117
-
rw->lock = 0;
118
-
ret = 1;
119
-
}
120
-
arch_spin_unlock(&rw->slock);
121
-
return ret;
122
-
}
123
-
124
-
#define _raw_read_lock_flags(lock, flags) _raw_read_lock(lock)
125
-
#define _raw_write_lock_flags(lock, flags) _raw_write_lock(lock)
126
-
127
-
#define arch_spin_relax(lock) cpu_relax()
128
-
#define arch_read_relax(lock) cpu_relax()
129
-
#define arch_write_relax(lock) cpu_relax()
130
-
131
-
#endif /* __ASM_ARCH_SPINLOCK_H */
+14
-1
arch/cris/include/asm/Kbuild
+14
-1
arch/cris/include/asm/Kbuild
···
1
-
1
+
generic-y += atomic.h
2
2
generic-y += barrier.h
3
3
generic-y += clkdev.h
4
+
generic-y += cmpxchg.h
4
5
generic-y += cputime.h
6
+
generic-y += device.h
7
+
generic-y += div64.h
5
8
generic-y += exec.h
9
+
generic-y += emergency-restart.h
10
+
generic-y += futex.h
11
+
generic-y += hardirq.h
12
+
generic-y += irq_regs.h
6
13
generic-y += irq_work.h
14
+
generic-y += kdebug.h
15
+
generic-y += kmap_types.h
7
16
generic-y += kvm_para.h
8
17
generic-y += linkage.h
18
+
generic-y += local.h
19
+
generic-y += local64.h
9
20
generic-y += mcs_spinlock.h
10
21
generic-y += module.h
22
+
generic-y += percpu.h
11
23
generic-y += preempt.h
12
24
generic-y += scatterlist.h
13
25
generic-y += sections.h
26
+
generic-y += topology.h
14
27
generic-y += trace_clock.h
15
28
generic-y += vga.h
16
29
generic-y += xor.h
-149
arch/cris/include/asm/atomic.h
-149
arch/cris/include/asm/atomic.h
···
1
-
/* $Id: atomic.h,v 1.3 2001/07/25 16:15:19 bjornw Exp $ */
2
-
3
-
#ifndef __ASM_CRIS_ATOMIC__
4
-
#define __ASM_CRIS_ATOMIC__
5
-
6
-
#include <linux/compiler.h>
7
-
#include <linux/types.h>
8
-
#include <asm/cmpxchg.h>
9
-
#include <arch/atomic.h>
10
-
#include <arch/system.h>
11
-
#include <asm/barrier.h>
12
-
13
-
/*
14
-
* Atomic operations that C can't guarantee us. Useful for
15
-
* resource counting etc..
16
-
*/
17
-
18
-
#define ATOMIC_INIT(i) { (i) }
19
-
20
-
#define atomic_read(v) ACCESS_ONCE((v)->counter)
21
-
#define atomic_set(v,i) (((v)->counter) = (i))
22
-
23
-
/* These should be written in asm but we do it in C for now. */
24
-
25
-
#define ATOMIC_OP(op, c_op) \
26
-
static inline void atomic_##op(int i, volatile atomic_t *v) \
27
-
{ \
28
-
unsigned long flags; \
29
-
cris_atomic_save(v, flags); \
30
-
v->counter c_op i; \
31
-
cris_atomic_restore(v, flags); \
32
-
} \
33
-
34
-
#define ATOMIC_OP_RETURN(op, c_op) \
35
-
static inline int atomic_##op##_return(int i, volatile atomic_t *v) \
36
-
{ \
37
-
unsigned long flags; \
38
-
int retval; \
39
-
cris_atomic_save(v, flags); \
40
-
retval = (v->counter c_op i); \
41
-
cris_atomic_restore(v, flags); \
42
-
return retval; \
43
-
}
44
-
45
-
#define ATOMIC_OPS(op, c_op) ATOMIC_OP(op, c_op) ATOMIC_OP_RETURN(op, c_op)
46
-
47
-
ATOMIC_OPS(add, +=)
48
-
ATOMIC_OPS(sub, -=)
49
-
50
-
#undef ATOMIC_OPS
51
-
#undef ATOMIC_OP_RETURN
52
-
#undef ATOMIC_OP
53
-
54
-
#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
55
-
56
-
static inline int atomic_sub_and_test(int i, volatile atomic_t *v)
57
-
{
58
-
int retval;
59
-
unsigned long flags;
60
-
cris_atomic_save(v, flags);
61
-
retval = (v->counter -= i) == 0;
62
-
cris_atomic_restore(v, flags);
63
-
return retval;
64
-
}
65
-
66
-
static inline void atomic_inc(volatile atomic_t *v)
67
-
{
68
-
unsigned long flags;
69
-
cris_atomic_save(v, flags);
70
-
(v->counter)++;
71
-
cris_atomic_restore(v, flags);
72
-
}
73
-
74
-
static inline void atomic_dec(volatile atomic_t *v)
75
-
{
76
-
unsigned long flags;
77
-
cris_atomic_save(v, flags);
78
-
(v->counter)--;
79
-
cris_atomic_restore(v, flags);
80
-
}
81
-
82
-
static inline int atomic_inc_return(volatile atomic_t *v)
83
-
{
84
-
unsigned long flags;
85
-
int retval;
86
-
cris_atomic_save(v, flags);
87
-
retval = ++(v->counter);
88
-
cris_atomic_restore(v, flags);
89
-
return retval;
90
-
}
91
-
92
-
static inline int atomic_dec_return(volatile atomic_t *v)
93
-
{
94
-
unsigned long flags;
95
-
int retval;
96
-
cris_atomic_save(v, flags);
97
-
retval = --(v->counter);
98
-
cris_atomic_restore(v, flags);
99
-
return retval;
100
-
}
101
-
static inline int atomic_dec_and_test(volatile atomic_t *v)
102
-
{
103
-
int retval;
104
-
unsigned long flags;
105
-
cris_atomic_save(v, flags);
106
-
retval = --(v->counter) == 0;
107
-
cris_atomic_restore(v, flags);
108
-
return retval;
109
-
}
110
-
111
-
static inline int atomic_inc_and_test(volatile atomic_t *v)
112
-
{
113
-
int retval;
114
-
unsigned long flags;
115
-
cris_atomic_save(v, flags);
116
-
retval = ++(v->counter) == 0;
117
-
cris_atomic_restore(v, flags);
118
-
return retval;
119
-
}
120
-
121
-
static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
122
-
{
123
-
int ret;
124
-
unsigned long flags;
125
-
126
-
cris_atomic_save(v, flags);
127
-
ret = v->counter;
128
-
if (likely(ret == old))
129
-
v->counter = new;
130
-
cris_atomic_restore(v, flags);
131
-
return ret;
132
-
}
133
-
134
-
#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
135
-
136
-
static inline int __atomic_add_unless(atomic_t *v, int a, int u)
137
-
{
138
-
int ret;
139
-
unsigned long flags;
140
-
141
-
cris_atomic_save(v, flags);
142
-
ret = v->counter;
143
-
if (ret != u)
144
-
v->counter += a;
145
-
cris_atomic_restore(v, flags);
146
-
return ret;
147
-
}
148
-
149
-
#endif
+1
-110
arch/cris/include/asm/bitops.h
+1
-110
arch/cris/include/asm/bitops.h
···
19
19
#endif
20
20
21
21
#include <arch/bitops.h>
22
-
#include <linux/atomic.h>
23
22
#include <linux/compiler.h>
24
23
#include <asm/barrier.h>
25
24
26
-
/*
27
-
* set_bit - Atomically set a bit in memory
28
-
* @nr: the bit to set
29
-
* @addr: the address to start counting from
30
-
*
31
-
* This function is atomic and may not be reordered. See __set_bit()
32
-
* if you do not require the atomic guarantees.
33
-
* Note that @nr may be almost arbitrarily large; this function is not
34
-
* restricted to acting on a single-word quantity.
35
-
*/
36
-
37
-
#define set_bit(nr, addr) (void)test_and_set_bit(nr, addr)
38
-
39
-
/*
40
-
* clear_bit - Clears a bit in memory
41
-
* @nr: Bit to clear
42
-
* @addr: Address to start counting from
43
-
*
44
-
* clear_bit() is atomic and may not be reordered. However, it does
45
-
* not contain a memory barrier, so if it is used for locking purposes,
46
-
* you should call smp_mb__before_atomic() and/or smp_mb__after_atomic()
47
-
* in order to ensure changes are visible on other processors.
48
-
*/
49
-
50
-
#define clear_bit(nr, addr) (void)test_and_clear_bit(nr, addr)
51
-
52
-
/*
53
-
* change_bit - Toggle a bit in memory
54
-
* @nr: Bit to change
55
-
* @addr: Address to start counting from
56
-
*
57
-
* change_bit() is atomic and may not be reordered.
58
-
* Note that @nr may be almost arbitrarily large; this function is not
59
-
* restricted to acting on a single-word quantity.
60
-
*/
61
-
62
-
#define change_bit(nr, addr) (void)test_and_change_bit(nr, addr)
63
-
64
-
/**
65
-
* test_and_set_bit - Set a bit and return its old value
66
-
* @nr: Bit to set
67
-
* @addr: Address to count from
68
-
*
69
-
* This operation is atomic and cannot be reordered.
70
-
* It also implies a memory barrier.
71
-
*/
72
-
73
-
static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
74
-
{
75
-
unsigned int mask, retval;
76
-
unsigned long flags;
77
-
unsigned int *adr = (unsigned int *)addr;
78
-
79
-
adr += nr >> 5;
80
-
mask = 1 << (nr & 0x1f);
81
-
cris_atomic_save(addr, flags);
82
-
retval = (mask & *adr) != 0;
83
-
*adr |= mask;
84
-
cris_atomic_restore(addr, flags);
85
-
return retval;
86
-
}
87
-
88
-
/**
89
-
* test_and_clear_bit - Clear a bit and return its old value
90
-
* @nr: Bit to clear
91
-
* @addr: Address to count from
92
-
*
93
-
* This operation is atomic and cannot be reordered.
94
-
* It also implies a memory barrier.
95
-
*/
96
-
97
-
static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
98
-
{
99
-
unsigned int mask, retval;
100
-
unsigned long flags;
101
-
unsigned int *adr = (unsigned int *)addr;
102
-
103
-
adr += nr >> 5;
104
-
mask = 1 << (nr & 0x1f);
105
-
cris_atomic_save(addr, flags);
106
-
retval = (mask & *adr) != 0;
107
-
*adr &= ~mask;
108
-
cris_atomic_restore(addr, flags);
109
-
return retval;
110
-
}
111
-
112
-
/**
113
-
* test_and_change_bit - Change a bit and return its old value
114
-
* @nr: Bit to change
115
-
* @addr: Address to count from
116
-
*
117
-
* This operation is atomic and cannot be reordered.
118
-
* It also implies a memory barrier.
119
-
*/
120
-
121
-
static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
122
-
{
123
-
unsigned int mask, retval;
124
-
unsigned long flags;
125
-
unsigned int *adr = (unsigned int *)addr;
126
-
adr += nr >> 5;
127
-
mask = 1 << (nr & 0x1f);
128
-
cris_atomic_save(addr, flags);
129
-
retval = (mask & *adr) != 0;
130
-
*adr ^= mask;
131
-
cris_atomic_restore(addr, flags);
132
-
return retval;
133
-
}
134
-
25
+
#include <asm-generic/bitops/atomic.h>
135
26
#include <asm-generic/bitops/non-atomic.h>
136
27
137
28
/*
-53
arch/cris/include/asm/cmpxchg.h
-53
arch/cris/include/asm/cmpxchg.h
···
1
-
#ifndef __ASM_CRIS_CMPXCHG__
2
-
#define __ASM_CRIS_CMPXCHG__
3
-
4
-
#include <linux/irqflags.h>
5
-
6
-
static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
7
-
{
8
-
/* since Etrax doesn't have any atomic xchg instructions, we need to disable
9
-
irq's (if enabled) and do it with move.d's */
10
-
unsigned long flags,temp;
11
-
local_irq_save(flags); /* save flags, including irq enable bit and shut off irqs */
12
-
switch (size) {
13
-
case 1:
14
-
*((unsigned char *)&temp) = x;
15
-
x = *(unsigned char *)ptr;
16
-
*(unsigned char *)ptr = *((unsigned char *)&temp);
17
-
break;
18
-
case 2:
19
-
*((unsigned short *)&temp) = x;
20
-
x = *(unsigned short *)ptr;
21
-
*(unsigned short *)ptr = *((unsigned short *)&temp);
22
-
break;
23
-
case 4:
24
-
temp = x;
25
-
x = *(unsigned long *)ptr;
26
-
*(unsigned long *)ptr = temp;
27
-
break;
28
-
}
29
-
local_irq_restore(flags); /* restore irq enable bit */
30
-
return x;
31
-
}
32
-
33
-
#define xchg(ptr,x) \
34
-
((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
35
-
36
-
#define tas(ptr) (xchg((ptr),1))
37
-
38
-
#include <asm-generic/cmpxchg-local.h>
39
-
40
-
/*
41
-
* cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
42
-
* them available.
43
-
*/
44
-
#define cmpxchg_local(ptr, o, n) \
45
-
((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
46
-
(unsigned long)(n), sizeof(*(ptr))))
47
-
#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
48
-
49
-
#ifndef CONFIG_SMP
50
-
#include <asm-generic/cmpxchg.h>
51
-
#endif
52
-
53
-
#endif /* __ASM_CRIS_CMPXCHG__ */
-7
arch/cris/include/asm/device.h
-7
arch/cris/include/asm/device.h
-1
arch/cris/include/asm/div64.h
-1
arch/cris/include/asm/div64.h
···
1
-
#include <asm-generic/div64.h>
+1
-1
arch/cris/include/asm/elf.h
+1
-1
arch/cris/include/asm/elf.h
···
71
71
the loader. We need to make sure that it is out of the way of the program
72
72
that it will "exec", and that there is sufficient room for the brk. */
73
73
74
-
#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
74
+
#define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2)
75
75
76
76
/* This yields a mask that user programs can use to figure out what
77
77
instruction set this CPU supports. This could be done in user space,
-6
arch/cris/include/asm/emergency-restart.h
-6
arch/cris/include/asm/emergency-restart.h
-6
arch/cris/include/asm/futex.h
-6
arch/cris/include/asm/futex.h
-7
arch/cris/include/asm/hardirq.h
-7
arch/cris/include/asm/hardirq.h
-1
arch/cris/include/asm/irq_regs.h
-1
arch/cris/include/asm/irq_regs.h
···
1
-
#include <asm-generic/irq_regs.h>
-1
arch/cris/include/asm/kdebug.h
-1
arch/cris/include/asm/kdebug.h
···
1
-
#include <asm-generic/kdebug.h>
-10
arch/cris/include/asm/kmap_types.h
-10
arch/cris/include/asm/kmap_types.h
-1
arch/cris/include/asm/local.h
-1
arch/cris/include/asm/local.h
···
1
-
#include <asm-generic/local.h>
-1
arch/cris/include/asm/local64.h
-1
arch/cris/include/asm/local64.h
···
1
-
#include <asm-generic/local64.h>
-6
arch/cris/include/asm/percpu.h
-6
arch/cris/include/asm/percpu.h
-10
arch/cris/include/asm/smp.h
-10
arch/cris/include/asm/smp.h
-1
arch/cris/include/asm/spinlock.h
-1
arch/cris/include/asm/spinlock.h
···
1
-
#include <arch/spinlock.h>
-7
arch/cris/include/asm/tlbflush.h
-7
arch/cris/include/asm/tlbflush.h
···
22
22
extern void __flush_tlb_page(struct vm_area_struct *vma,
23
23
unsigned long addr);
24
24
25
-
#ifdef CONFIG_SMP
26
-
extern void flush_tlb_all(void);
27
-
extern void flush_tlb_mm(struct mm_struct *mm);
28
-
extern void flush_tlb_page(struct vm_area_struct *vma,
29
-
unsigned long addr);
30
-
#else
31
25
#define flush_tlb_all __flush_tlb_all
32
26
#define flush_tlb_mm __flush_tlb_mm
33
27
#define flush_tlb_page __flush_tlb_page
34
-
#endif
35
28
36
29
static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end)
37
30
{
-6
arch/cris/include/asm/topology.h
-6
arch/cris/include/asm/topology.h
+1
arch/cris/kernel/Makefile
+1
arch/cris/kernel/Makefile
+14
arch/cris/kernel/devicetree.c
+14
arch/cris/kernel/devicetree.c
···
1
+
#include <linux/init.h>
2
+
#include <linux/bootmem.h>
3
+
#include <linux/printk.h>
4
+
5
+
void __init early_init_dt_add_memory_arch(u64 base, u64 size)
6
+
{
7
+
pr_err("%s(%llx, %llx)\n",
8
+
__func__, base, size);
9
+
}
10
+
11
+
void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
12
+
{
13
+
return alloc_bootmem_align(size, align);
14
+
}
+23
arch/cris/kernel/ptrace.c
+23
arch/cris/kernel/ptrace.c
···
42
42
tracehook_notify_resume(regs);
43
43
}
44
44
}
45
+
46
+
void do_work_pending(int syscall, struct pt_regs *regs,
47
+
unsigned int thread_flags)
48
+
{
49
+
do {
50
+
if (likely(thread_flags & _TIF_NEED_RESCHED)) {
51
+
schedule();
52
+
} else {
53
+
if (unlikely(!user_mode(regs)))
54
+
return;
55
+
local_irq_enable();
56
+
if (thread_flags & _TIF_SIGPENDING) {
57
+
do_signal(syscall, regs);
58
+
syscall = 0;
59
+
} else {
60
+
clear_thread_flag(TIF_NOTIFY_RESUME);
61
+
tracehook_notify_resume(regs);
62
+
}
63
+
}
64
+
local_irq_disable();
65
+
thread_flags = current_thread_info()->flags;
66
+
} while (thread_flags & _TIF_WORK_MASK);
67
+
}
+15
arch/cris/kernel/setup.c
+15
arch/cris/kernel/setup.c
···
19
19
#include <linux/utsname.h>
20
20
#include <linux/pfn.h>
21
21
#include <linux/cpu.h>
22
+
#include <linux/of.h>
23
+
#include <linux/of_fdt.h>
24
+
#include <linux/of_platform.h>
22
25
#include <asm/setup.h>
23
26
#include <arch/system.h>
24
27
···
66
63
unsigned long bootmap_size;
67
64
unsigned long start_pfn, max_pfn;
68
65
unsigned long memory_start;
66
+
67
+
#ifdef CONFIG_OF
68
+
early_init_dt_scan(__dtb_start);
69
+
#endif
69
70
70
71
/* register an initial console printing routine for printk's */
71
72
···
148
141
149
142
reserve_bootmem(PFN_PHYS(start_pfn), bootmap_size, BOOTMEM_DEFAULT);
150
143
144
+
unflatten_and_copy_device_tree();
145
+
151
146
/* paging_init() sets up the MMU and marks all pages as reserved */
152
147
153
148
paging_init();
···
213
204
214
205
subsys_initcall(topology_init);
215
206
207
+
static int __init cris_of_init(void)
208
+
{
209
+
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
210
+
return 0;
211
+
}
212
+
core_initcall(cris_of_init);
+2
arch/cris/kernel/time.c
+2
arch/cris/kernel/time.c