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dt-bindings: clock: exynos990: Add CMU_PERIS block

Add CMU_PERIS block compatible, and clock definitions.

CMU_PERIS requires one bus clock dependency, and it's used for i.e the MCT.

Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250104-exynos990-cmu-v1-1-9f54d69286d6@mentallysanemainliners.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

authored by

Igor Belwon and committed by
Krzysztof Kozlowski 7fa119f5 2014c95a

+40
+19
Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml
··· 31 31 compatible: 32 32 enum: 33 33 - samsung,exynos990-cmu-hsi0 34 + - samsung,exynos990-cmu-peris 34 35 - samsung,exynos990-cmu-top 35 36 36 37 clocks: ··· 79 78 - const: usb31drd 80 79 - const: usbdp_debug 81 80 - const: dpgtc 81 + 82 + - if: 83 + properties: 84 + compatible: 85 + contains: 86 + const: samsung,exynos990-cmu-peris 87 + 88 + then: 89 + properties: 90 + clocks: 91 + items: 92 + - description: External reference clock (26 MHz) 93 + - description: CMU_PERIS BUS clock (from CMU_TOP) 94 + 95 + clock-names: 96 + items: 97 + - const: oscclk 98 + - const: bus 82 99 83 100 - if: 84 101 properties:
+21
include/dt-bindings/clock/samsung,exynos990.h
··· 233 233 #define CLK_GOUT_HSI0_CMU_HSI0_PCLK 21 234 234 #define CLK_GOUT_HSI0_XIU_D_HSI0_ACLK 22 235 235 236 + /* CMU_PERIS */ 237 + #define CLK_MOUT_PERIS_BUS_USER 1 238 + #define CLK_MOUT_PERIS_CLK_PERIS_GIC 2 239 + #define CLK_GOUT_PERIS_SYSREG_PERIS_PCLK 3 240 + #define CLK_GOUT_PERIS_WDT_CLUSTER2_PCLK 4 241 + #define CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK 5 242 + #define CLK_CLK_PERIS_PERIS_CMU_PERIS_PCLK 6 243 + #define CLK_GOUT_PERIS_CLK_PERIS_BUSP_CLK 7 244 + #define CLK_GOUT_PERIS_CLK_PERIS_OSCCLK_CLK 8 245 + #define CLK_GOUT_PERIS_CLK_PERIS_GIC_CLK 9 246 + #define CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKM 10 247 + #define CLK_GOUT_PERIS_OTP_CON_BIRA_PCLK 11 248 + #define CLK_GOUT_PERIS_GIC_CLK 12 249 + #define CLK_GOUT_PERIS_LHM_AXI_P_PERIS_CLK 13 250 + #define CLK_GOUT_PERIS_MCT_PCLK 14 251 + #define CLK_GOUT_PERIS_OTP_CON_TOP_PCLK 15 252 + #define CLK_GOUT_PERIS_D_TZPC_PERIS_PCLK 16 253 + #define CLK_GOUT_PERIS_TMU_TOP_PCLK 17 254 + #define CLK_GOUT_PERIS_OTP_CON_BIRA_OSCCLK 18 255 + #define CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK 19 256 + 236 257 #endif