Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm
Pull ARM fixes from Russell King:
"Some small fixes for this merge window, most of them quite self
explanatory - the biggest thing here is a fix for the ARMv7 LPAE
suspend/resume support"
* 'fixes' of git://git.linaro.org/people/rmk/linux-arm:
ARM: 7894/1: kconfig: select GENERIC_CLOCKEVENTS if HAVE_ARM_ARCH_TIMER
ARM: 7893/1: bitops: only emit .arch_extension mp if CONFIG_SMP
ARM: 7892/1: Fix warning for V7M builds
ARM: 7888/1: seccomp: not compatible with ARM OABI
ARM: 7886/1: make OABI default to off
ARM: 7885/1: Save/Restore 64-bit TTBR registers on LPAE suspend/resume
ARM: 7884/1: mm: Fix ECC mem policy printk
ARM: 7883/1: fix mov to mvn conversion in case of 64 bit phys_addr_t and BE
ARM: 7882/1: mm: fix __phys_to_virt to work with 64 bit phys_addr_t in BE case
ARM: 7881/1: __fixup_smp read of SCU config should do byteswap in BE case
ARM: Fix nommu.c build warning
+39
-14
+8
-3
arch/arm/Kconfig
+8
-3
arch/arm/Kconfig
···
25
25
select HARDIRQS_SW_RESEND
26
26
select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
27
27
select HAVE_ARCH_KGDB
28
-
select HAVE_ARCH_SECCOMP_FILTER
28
+
select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
29
29
select HAVE_ARCH_TRACEHOOK
30
30
select HAVE_BPF_JIT
31
31
select HAVE_CONTEXT_TRACKING
···
1496
1496
bool "Architected timer support"
1497
1497
depends on CPU_V7
1498
1498
select ARM_ARCH_TIMER
1499
+
select GENERIC_CLOCKEVENTS
1499
1500
help
1500
1501
This option enables support for the ARM architected timer
1501
1502
···
1720
1719
config OABI_COMPAT
1721
1720
bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1722
1721
depends on AEABI && !THUMB2_KERNEL
1723
-
default y
1724
1722
help
1725
1723
This option preserves the old syscall interface along with the
1726
1724
new (ARM EABI) one. It also provides a compatibility layer to
···
1727
1727
in memory differs between the legacy ABI and the new ARM EABI
1728
1728
(only for non "thumb" binaries). This option adds a tiny
1729
1729
overhead to all syscalls and produces a slightly larger kernel.
1730
+
1731
+
The seccomp filter system will not be available when this is
1732
+
selected, since there is no way yet to sensibly distinguish
1733
+
between calling conventions during filtering.
1734
+
1730
1735
If you know you'll be using only pure EABI user space then you
1731
1736
can say N here. If this option is not selected and you attempt
1732
1737
to execute a legacy ABI binary then the result will be
1733
1738
UNPREDICTABLE (in fact it can be predicted that it won't work
1734
-
at all). If in doubt say Y.
1739
+
at all). If in doubt say N.
1735
1740
1736
1741
config ARCH_HAS_HOLES_MEMORYMODEL
1737
1742
bool
+8
-1
arch/arm/include/asm/memory.h
+8
-1
arch/arm/include/asm/memory.h
···
226
226
static inline unsigned long __phys_to_virt(phys_addr_t x)
227
227
{
228
228
unsigned long t;
229
-
__pv_stub(x, t, "sub", __PV_BITS_31_24);
229
+
230
+
/*
231
+
* 'unsigned long' cast discard upper word when
232
+
* phys_addr_t is 64 bit, and makes sure that inline
233
+
* assembler expression receives 32 bit argument
234
+
* in place where 'r' 32 bit operand is expected.
235
+
*/
236
+
__pv_stub((unsigned long) x, t, "sub", __PV_BITS_31_24);
230
237
return t;
231
238
}
232
239
+6
-1
arch/arm/kernel/head.S
+6
-1
arch/arm/kernel/head.S
···
508
508
teq r0, #0x0 @ '0' on actual UP A9 hardware
509
509
beq __fixup_smp_on_up @ So its an A9 UP
510
510
ldr r0, [r0, #4] @ read SCU Config
511
+
ARM_BE8(rev r0, r0) @ byteswap if big endian
511
512
and r0, r0, #0x3 @ number of CPUs
512
513
teq r0, #0x0 @ is 1?
513
514
movne pc, lr
···
645
644
bcc 1b
646
645
bx lr
647
646
#else
647
+
#ifdef CONFIG_CPU_ENDIAN_BE8
648
+
moveq r0, #0x00004000 @ set bit 22, mov to mvn instruction
649
+
#else
648
650
moveq r0, #0x400000 @ set bit 22, mov to mvn instruction
651
+
#endif
649
652
b 2f
650
653
1: ldr ip, [r7, r3]
651
654
#ifdef CONFIG_CPU_ENDIAN_BE8
···
658
653
tst ip, #0x000f0000 @ check the rotation field
659
654
orrne ip, ip, r6, lsl #24 @ mask in offset bits 31-24
660
655
biceq ip, ip, #0x00004000 @ clear bit 22
661
-
orreq ip, ip, r0, lsl #24 @ mask in offset bits 7-0
656
+
orreq ip, ip, r0 @ mask in offset bits 7-0
662
657
#else
663
658
bic ip, ip, #0x000000ff
664
659
tst ip, #0xf00 @ check the rotation field
+1
-1
arch/arm/kernel/traps.c
+1
-1
arch/arm/kernel/traps.c
+1
-1
arch/arm/lib/bitops.h
+1
-1
arch/arm/lib/bitops.h
+2
-2
arch/arm/mm/mmu.c
+2
-2
arch/arm/mm/mmu.c
···
558
558
mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
559
559
break;
560
560
}
561
-
printk("Memory policy: ECC %sabled, Data cache %s\n",
562
-
ecc_mask ? "en" : "dis", cp->policy);
561
+
pr_info("Memory policy: %sData cache %s\n",
562
+
ecc_mask ? "ECC enabled, " : "", cp->policy);
563
563
564
564
for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
565
565
struct mem_type *t = &mem_types[i];
+1
arch/arm/mm/nommu.c
+1
arch/arm/mm/nommu.c
+12
-5
arch/arm/mm/proc-v7.S
+12
-5
arch/arm/mm/proc-v7.S
···
92
92
93
93
/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
94
94
.globl cpu_v7_suspend_size
95
-
.equ cpu_v7_suspend_size, 4 * 8
95
+
.equ cpu_v7_suspend_size, 4 * 9
96
96
#ifdef CONFIG_ARM_CPU_SUSPEND
97
97
ENTRY(cpu_v7_do_suspend)
98
98
stmfd sp!, {r4 - r10, lr}
···
101
101
stmia r0!, {r4 - r5}
102
102
#ifdef CONFIG_MMU
103
103
mrc p15, 0, r6, c3, c0, 0 @ Domain ID
104
+
#ifdef CONFIG_ARM_LPAE
105
+
mrrc p15, 1, r5, r7, c2 @ TTB 1
106
+
#else
104
107
mrc p15, 0, r7, c2, c0, 1 @ TTB 1
108
+
#endif
105
109
mrc p15, 0, r11, c2, c0, 2 @ TTB control register
106
110
#endif
107
111
mrc p15, 0, r8, c1, c0, 0 @ Control register
108
112
mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
109
113
mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
110
-
stmia r0, {r6 - r11}
114
+
stmia r0, {r5 - r11}
111
115
ldmfd sp!, {r4 - r10, pc}
112
116
ENDPROC(cpu_v7_do_suspend)
113
117
···
122
118
ldmia r0!, {r4 - r5}
123
119
mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
124
120
mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
125
-
ldmia r0, {r6 - r11}
121
+
ldmia r0, {r5 - r11}
126
122
#ifdef CONFIG_MMU
127
123
mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
128
124
mcr p15, 0, r6, c3, c0, 0 @ Domain ID
129
-
#ifndef CONFIG_ARM_LPAE
125
+
#ifdef CONFIG_ARM_LPAE
126
+
mcrr p15, 0, r1, ip, c2 @ TTB 0
127
+
mcrr p15, 1, r5, r7, c2 @ TTB 1
128
+
#else
130
129
ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
131
130
ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
132
-
#endif
133
131
mcr p15, 0, r1, c2, c0, 0 @ TTB 0
134
132
mcr p15, 0, r7, c2, c0, 1 @ TTB 1
133
+
#endif
135
134
mcr p15, 0, r11, c2, c0, 2 @ TTB control register
136
135
ldr r4, =PRRR @ PRRR
137
136
ldr r5, =NMRR @ NMRR