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drm/msm/a6xx: Enable Preemption on X2-85

Add the save-restore register lists and set the necessary quirk flags
in the catalog to enable the Preemption feature on Adreno X2-85 GPU.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/714684/
Message-ID: <20260327-a8xx-gpu-batch2-v2-16-2b53c38d2101@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

authored by

Akhil P Oommen and committed by
Rob Clark 7fad3309 a693602e

+42
+42
drivers/gpu/drm/msm/adreno/a6xx_catalog.c
··· 1761 1761 1762 1762 DECLARE_ADRENO_PROTECT(x285_protect, 15); 1763 1763 1764 + static const struct adreno_reglist_pipe x285_dyn_pwrup_reglist_regs[] = { 1765 + { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 1766 + { REG_A8XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 1767 + { REG_A8XX_GRAS_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 1768 + { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 1769 + { REG_A8XX_PC_CHICKEN_BITS_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 1770 + { REG_A8XX_PC_CHICKEN_BITS_2, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 1771 + { REG_A8XX_PC_CHICKEN_BITS_3, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 1772 + { REG_A8XX_PC_CHICKEN_BITS_4, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 1773 + { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 1774 + { REG_A8XX_PC_VIS_STREAM_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 1775 + { REG_A7XX_RB_CCU_CNTL, 0, BIT(PIPE_BR) }, 1776 + { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0, BIT(PIPE_BR)}, 1777 + { REG_A8XX_RB_CCU_NC_MODE_CNTL, 0, BIT(PIPE_BR) }, 1778 + { REG_A8XX_RB_CMP_NC_MODE_CNTL, 0, BIT(PIPE_BR) }, 1779 + { REG_A6XX_RB_RBP_CNTL, 0, BIT(PIPE_BR) }, 1780 + { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0, BIT(PIPE_BR) }, 1781 + { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0, BIT(PIPE_BR) }, 1782 + { REG_A7XX_VFD_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 1783 + { REG_A8XX_VFD_CB_BV_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 1784 + { REG_A8XX_VFD_CB_BR_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 1785 + { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 1786 + { REG_A8XX_VFD_CB_LP_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 1787 + { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, 1788 + { REG_A8XX_CP_HW_FAULT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) | 1789 + BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) | 1790 + BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) }, 1791 + { REG_A8XX_CP_INTERRUPT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) | 1792 + BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) | 1793 + BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) }, 1794 + { REG_A8XX_CP_PROTECT_CNTL_PIPE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIPE_LPAC)}, 1795 + { REG_A8XX_CP_PROTECT_PIPE(15), 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIPE_LPAC) }, 1796 + { REG_A8XX_RB_GC_GMEM_PROTECT, 0, BIT(PIPE_BR) }, 1797 + { REG_A8XX_RB_LPAC_GMEM_PROTECT, 0, BIT(PIPE_BR) }, 1798 + { REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0, BIT(PIPE_BR) }, 1799 + }; 1800 + DECLARE_ADRENO_REGLIST_PIPE_LIST(x285_dyn_pwrup_reglist); 1801 + 1764 1802 static const struct adreno_reglist_pipe a840_nonctxt_regs[] = { 1765 1803 { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) }, 1766 1804 { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) }, ··· 2120 2082 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 2121 2083 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 2122 2084 ADRENO_QUIRK_HAS_HW_APRIV | 2085 + ADRENO_QUIRK_PREEMPTION | 2123 2086 ADRENO_QUIRK_SOFTFUSE, 2124 2087 .funcs = &a8xx_gpu_funcs, 2125 2088 .a6xx = &(const struct a6xx_info) { 2126 2089 .protect = &x285_protect, 2127 2090 .nonctxt_reglist = x285_nonctxt_regs, 2091 + .pwrup_reglist = &a840_pwrup_reglist, 2092 + .dyn_pwrup_reglist = &x285_dyn_pwrup_reglist, 2093 + .ifpc_reglist = &a840_ifpc_reglist, 2128 2094 .gbif_cx = a840_gbif, 2129 2095 .max_slices = 4, 2130 2096 .gmu_chipid = 0x8010100,