Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'i2c/for-current-fixed' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
Pull i2c fixes from Wolfram Sang:
"Three driver bugfixes and one leak fix for the core"
* 'i2c/for-current-fixed' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux:
i2c: mlxcpld: Modify register setting for 400KHz frequency
i2c: mlxcpld: Fix criteria for frequency setting
i2c: mediatek: Add OFFSET_EXT_CONF setting back
i2c: acpi: fix resource leak in reconfiguration device addition
+13
-3
+2
-2
drivers/i2c/busses/i2c-mlxcpld.c
+2
-2
drivers/i2c/busses/i2c-mlxcpld.c
···
49
49
#define MLXCPLD_LPCI2C_NACK_IND 2
50
50
51
51
#define MLXCPLD_I2C_FREQ_1000KHZ_SET 0x04
52
-
#define MLXCPLD_I2C_FREQ_400KHZ_SET 0x0f
52
+
#define MLXCPLD_I2C_FREQ_400KHZ_SET 0x0c
53
53
#define MLXCPLD_I2C_FREQ_100KHZ_SET 0x42
54
54
55
55
enum mlxcpld_i2c_frequency {
···
495
495
return err;
496
496
497
497
/* Set frequency only if it is not 100KHz, which is default. */
498
-
switch ((data->reg & data->mask) >> data->bit) {
498
+
switch ((regval & data->mask) >> data->bit) {
499
499
case MLXCPLD_I2C_FREQ_1000KHZ:
500
500
freq = MLXCPLD_I2C_FREQ_1000KHZ_SET;
501
501
break;
+10
-1
drivers/i2c/busses/i2c-mt65xx.c
+10
-1
drivers/i2c/busses/i2c-mt65xx.c
···
41
41
#define I2C_HANDSHAKE_RST 0x0020
42
42
#define I2C_FIFO_ADDR_CLR 0x0001
43
43
#define I2C_DELAY_LEN 0x0002
44
+
#define I2C_ST_START_CON 0x8001
45
+
#define I2C_FS_START_CON 0x1800
44
46
#define I2C_TIME_CLR_VALUE 0x0000
45
47
#define I2C_TIME_DEFAULT_VALUE 0x0003
46
48
#define I2C_WRRD_TRANAC_VALUE 0x0002
···
482
480
{
483
481
u16 control_reg;
484
482
u16 intr_stat_reg;
483
+
u16 ext_conf_val;
485
484
486
485
mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_START);
487
486
intr_stat_reg = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
···
521
518
if (i2c->dev_comp->ltiming_adjust)
522
519
mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING);
523
520
521
+
if (i2c->speed_hz <= I2C_MAX_STANDARD_MODE_FREQ)
522
+
ext_conf_val = I2C_ST_START_CON;
523
+
else
524
+
ext_conf_val = I2C_FS_START_CON;
525
+
524
526
if (i2c->dev_comp->timing_adjust) {
525
-
mtk_i2c_writew(i2c, i2c->ac_timing.ext, OFFSET_EXT_CONF);
527
+
ext_conf_val = i2c->ac_timing.ext;
526
528
mtk_i2c_writew(i2c, i2c->ac_timing.inter_clk_div,
527
529
OFFSET_CLOCK_DIV);
528
530
mtk_i2c_writew(i2c, I2C_SCL_MIS_COMP_VALUE,
···
552
544
OFFSET_HS_STA_STO_AC_TIMING);
553
545
}
554
546
}
547
+
mtk_i2c_writew(i2c, ext_conf_val, OFFSET_EXT_CONF);
555
548
556
549
/* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
557
550
if (i2c->have_pmic)