tjh.dev / kernel
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drm/amd/display: prevent hang on link training fail

[Why]
When link training fails, the phy clock will be disabled. However, in
enable_streams, it is assumed that link training succeeded and the
mux selects the phy clock, causing a hang when a register write is made.

[How]
When enable_stream is hit, check if link training failed. If it did, fall
back to the ref clock to avoid a hang and keep the system in a recoverable
state.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Brendan Tam <Brendan.Tam@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

authored by

Brendan Tam and committed by
Alex Deucher 8058061e 0389f2a3

+10 -3
+5 -1
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
··· 3033 3033 dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst); 3034 3034 3035 3035 phyd32clk = get_phyd32clk_src(link); 3036 - dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk); 3036 + if (link->cur_link_settings.link_rate == LINK_RATE_UNKNOWN) { 3037 + dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst); 3038 + } else { 3039 + dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk); 3040 + } 3037 3041 } else { 3038 3042 if (dccg->funcs->enable_symclk_se) 3039 3043 dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst,
+5 -2
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
··· 936 936 if (dc_is_dp_signal(pipe_ctx->stream->signal) || dc_is_virtual_signal(pipe_ctx->stream->signal)) { 937 937 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 938 938 dccg->funcs->set_dpstreamclk(dccg, DPREFCLK, tg->inst, dp_hpo_inst); 939 - 940 - dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk); 939 + if (link->cur_link_settings.link_rate == LINK_RATE_UNKNOWN) { 940 + dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst); 941 + } else { 942 + dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk); 943 + } 941 944 } else { 942 945 dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst, 943 946 link_enc->transmitter - TRANSMITTER_UNIPHY_A);