+2 -1

drivers/net/wireless/realtek/rtw88/usb.c

reviewed

··· 965 965 struct sk_buff *rx_skb; 966 966 int i; 967 967 968 968 - rtwusb->rxwq = alloc_workqueue("rtw88_usb: rx wq", WQ_BH, 0); 968 968 + rtwusb->rxwq = alloc_workqueue("rtw88_usb: rx wq", WQ_BH | WQ_PERCPU, 969 969 + 0); 969 970 if (!rtwusb->rxwq) { 970 971 rtw_err(rtwdev, "failed to create RX work queue\n"); 971 972 return -ENOMEM;

+27 -4

drivers/net/wireless/realtek/rtw89/chan.c

reviewed

··· 60 60 } 61 61 } 62 62 63 63 + static enum rtw89_tx_comp_band rtw89_get_tx_comp_band(enum rtw89_band band, 64 64 + u8 center_chan) 65 65 + { 66 66 + switch (band) { 67 67 + default: 68 68 + case RTW89_BAND_2G: 69 69 + return RTW89_TX_COMP_BAND_2GHZ; 70 70 + case RTW89_BAND_5G: 71 71 + if (center_chan < 149) 72 72 + return RTW89_TX_COMP_BAND_5GHZ_L; 73 73 + else 74 74 + return RTW89_TX_COMP_BAND_5GHZ_H; 75 75 + case RTW89_BAND_6G: 76 76 + if (center_chan < 65) 77 77 + return RTW89_TX_COMP_BAND_5GHZ_H; 78 78 + else if (center_chan < 193) 79 79 + return RTW89_TX_COMP_BAND_6GHZ_M; 80 80 + else 81 81 + return RTW89_TX_COMP_BAND_6GHZ_UH; 82 82 + } 83 83 + } 84 84 + 63 85 static enum rtw89_sc_offset rtw89_get_primary_chan_idx(enum rtw89_bandwidth bw, 64 86 u32 center_freq, 65 87 u32 primary_freq) ··· 145 123 146 124 chan->freq = center_freq; 147 125 chan->subband_type = rtw89_get_subband_type(band, center_chan); 126 126 + chan->tx_comp_band = rtw89_get_tx_comp_band(band, center_chan); 148 127 chan->pri_ch_idx = rtw89_get_primary_chan_idx(bandwidth, center_freq, 149 128 primary_freq); 150 129 chan->pri_sb_idx = rtw89_get_primary_sb_idx(center_chan, primary_chan, ··· 372 349 if (unlikely(!rtwvif_link->chanctx_assigned)) 373 350 return; 374 351 375 375 - cur = rtw89_vif_get_link_inst(rtwvif, 0); 376 376 - if (!cur || !cur->chanctx_assigned) 352 352 + cur = rtw89_get_designated_link(rtwvif); 353 353 + if (unlikely(!cur) || !cur->chanctx_assigned) 377 354 return; 378 355 379 356 if (cur == rtwvif_link) ··· 522 499 } 523 500 524 501 /* To be consistent with legacy behavior, expect the first active role 525 525 - * which uses RTW89_CHANCTX_0 to put at position 0, and make its first 526 526 - * link instance take RTW89_CHANCTX_0. (normalizing) 502 502 + * which uses RTW89_CHANCTX_0 to put at position 0 and its designated 503 503 + * link take RTW89_CHANCTX_0. (normalizing) 527 504 */ 528 505 list_for_each_entry(role, &mgnt->active_list, mgnt_entry) { 529 506 for (i = 0; i < role->links_inst_valid_num; i++) {

+39 -1

drivers/net/wireless/realtek/rtw89/core.h

reviewed

··· 23 23 struct rtw89_h2c_rf_tssi; 24 24 struct rtw89_fw_txpwr_track_cfg; 25 25 struct rtw89_phy_rfk_log_fmt; 26 26 + struct rtw89_phy_calc_efuse_gain; 26 27 struct rtw89_debugfs; 27 28 struct rtw89_regd_data; 28 29 struct rtw89_wow_cam_info; ··· 113 112 114 113 RTW89_SUBBAND_NR, 115 114 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 115 115 + }; 116 116 + 117 117 + enum rtw89_tx_comp_band { 118 118 + RTW89_TX_COMP_BAND_2GHZ, 119 119 + RTW89_TX_COMP_BAND_5GHZ_L, 120 120 + RTW89_TX_COMP_BAND_5GHZ_H, 121 121 + RTW89_TX_COMP_BAND_6GHZ_M, 122 122 + RTW89_TX_COMP_BAND_6GHZ_UH, 123 123 + 124 124 + RTW89_TX_COMP_BAND_NR, 116 125 }; 117 126 118 127 enum rtw89_gain_offset { ··· 1001 990 */ 1002 991 u32 freq; 1003 992 enum rtw89_subband subband_type; 993 993 + enum rtw89_tx_comp_band tx_comp_band; 1004 994 enum rtw89_sc_offset pri_ch_idx; 1005 995 u8 pri_sb_idx; 1006 996 }; ··· 3834 3822 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 3835 3823 void (*digital_pwr_comp)(struct rtw89_dev *rtwdev, 3836 3824 enum rtw89_phy_idx phy_idx); 3825 3825 + void (*calc_rx_gain_normal)(struct rtw89_dev *rtwdev, 3826 3826 + const struct rtw89_chan *chan, 3827 3827 + enum rtw89_rf_path path, 3828 3828 + enum rtw89_phy_idx phy_idx, 3829 3829 + struct rtw89_phy_calc_efuse_gain *calc); 3837 3830 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 3838 3831 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 3839 3832 void (*query_rxdesc)(struct rtw89_dev *rtwdev, ··· 4778 4761 RTW89_FW_FEATURE_ADDR_CAM_V0, 4779 4762 RTW89_FW_FEATURE_SER_L1_BY_EVENT, 4780 4763 RTW89_FW_FEATURE_SIM_SER_L0L1_BY_HALT_H2C, 4764 4764 + RTW89_FW_FEATURE_LPS_ML_INFO_V1, 4781 4765 4782 4766 NUM_OF_RTW89_FW_FEATURES, 4783 4767 }; ··· 4842 4824 const struct rtw89_regd_data *regd; 4843 4825 const struct rtw89_fw_element_hdr *afe; 4844 4826 const struct rtw89_fw_element_hdr *diag_mac; 4827 4827 + const struct rtw89_fw_element_hdr *tx_comp; 4845 4828 }; 4846 4829 4847 4830 enum rtw89_fw_mss_dev_type { ··· 5705 5686 u16 ifs_clm_cckfa; 5706 5687 u16 ifs_clm_cckcca_excl_fa; 5707 5688 u16 ifs_clm_total_ifs; 5708 5708 - u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 5689 5689 + u16 ifs_clm_his[RTW89_IFS_CLM_NUM]; 5709 5690 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 5710 5691 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 5711 5692 u8 ifs_clm_tx_ratio; ··· 5904 5885 s8 offset_base[RTW89_PHY_NUM]; /* S(8, 4) */ 5905 5886 s8 rssi_base[RTW89_PHY_NUM]; /* S(8, 4) */ 5906 5887 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 5888 5888 + }; 5889 5889 + 5890 5890 + struct rtw89_phy_calc_efuse_gain { 5891 5891 + s8 cck_mean_gain_bias; 5892 5892 + s8 cck_rpl_ofst; 5893 5893 + s8 rssi_ofst; 5907 5894 }; 5908 5895 5909 5896 #define RTW89_MAX_PATTERN_NUM 18 ··· 7364 7339 7365 7340 if (chip->ops->digital_pwr_comp) 7366 7341 chip->ops->digital_pwr_comp(rtwdev, phy_idx); 7342 7342 + } 7343 7343 + 7344 7344 + static inline 7345 7345 + void rtw89_chip_calc_rx_gain_normal(struct rtw89_dev *rtwdev, 7346 7346 + const struct rtw89_chan *chan, 7347 7347 + enum rtw89_rf_path path, 7348 7348 + enum rtw89_phy_idx phy_idx, 7349 7349 + struct rtw89_phy_calc_efuse_gain *calc) 7350 7350 + { 7351 7351 + const struct rtw89_chip_info *chip = rtwdev->chip; 7352 7352 + 7353 7353 + if (chip->ops->calc_rx_gain_normal) 7354 7354 + chip->ops->calc_rx_gain_normal(rtwdev, chan, path, phy_idx, calc); 7367 7355 } 7368 7356 7369 7357 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev,

+73 -26

drivers/net/wireless/realtek/rtw89/debug.c

reviewed

··· 826 826 s8 *bufp, tmp; 827 827 int ret; 828 828 829 829 - bufp = vzalloc(map->addr_to - map->addr_from + 4); 830 830 - if (!bufp) 831 831 - return -ENOMEM; 832 832 - 833 829 if (path_num == 1) 834 830 max_valid_addr = map->addr_to_1ss; 835 831 else ··· 833 837 834 838 if (max_valid_addr == 0) 835 839 return -EOPNOTSUPP; 840 840 + 841 841 + bufp = vzalloc(map->addr_to - map->addr_from + 4); 842 842 + if (!bufp) 843 843 + return -ENOMEM; 836 844 837 845 for (addr = map->addr_from; addr <= max_valid_addr; addr += 4) { 838 846 ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val); ··· 3538 3538 return count; 3539 3539 } 3540 3540 3541 3541 - static int rtw89_dbg_trigger_ctrl_error_by_halt_h2c(struct rtw89_dev *rtwdev) 3541 3541 + static int rtw89_dbg_trigger_l1_error_by_halt_h2c_ax(struct rtw89_dev *rtwdev) 3542 3542 { 3543 3543 if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 3544 3544 return -EBUSY; ··· 3546 3546 return rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L1_RESET_FORCE); 3547 3547 } 3548 3548 3549 3549 - static int rtw89_dbg_trigger_ctrl_error(struct rtw89_dev *rtwdev) 3549 3549 + static int rtw89_dbg_trigger_l1_error_by_halt_h2c_be(struct rtw89_dev *rtwdev) 3550 3550 + { 3551 3551 + if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 3552 3552 + return -EBUSY; 3553 3553 + 3554 3554 + rtw89_write32_set(rtwdev, R_BE_FW_TRIGGER_IDCT_ISR, 3555 3555 + B_BE_DMAC_FW_TRIG_IDCT | B_BE_DMAC_FW_ERR_IDCT_IMR); 3556 3556 + 3557 3557 + return 0; 3558 3558 + } 3559 3559 + 3560 3560 + static int rtw89_dbg_trigger_l1_error_by_halt_h2c(struct rtw89_dev *rtwdev) 3561 3561 + { 3562 3562 + const struct rtw89_chip_info *chip = rtwdev->chip; 3563 3563 + 3564 3564 + switch (chip->chip_gen) { 3565 3565 + case RTW89_CHIP_AX: 3566 3566 + return rtw89_dbg_trigger_l1_error_by_halt_h2c_ax(rtwdev); 3567 3567 + case RTW89_CHIP_BE: 3568 3568 + return rtw89_dbg_trigger_l1_error_by_halt_h2c_be(rtwdev); 3569 3569 + default: 3570 3570 + return -EOPNOTSUPP; 3571 3571 + } 3572 3572 + } 3573 3573 + 3574 3574 + static int rtw89_dbg_trigger_l1_error(struct rtw89_dev *rtwdev) 3550 3575 { 3551 3576 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3552 3577 struct rtw89_cpuio_ctrl ctrl_para = {0}; ··· 3579 3554 int ret; 3580 3555 3581 3556 if (RTW89_CHK_FW_FEATURE(SIM_SER_L0L1_BY_HALT_H2C, &rtwdev->fw)) 3582 3582 - return rtw89_dbg_trigger_ctrl_error_by_halt_h2c(rtwdev); 3557 3557 + return rtw89_dbg_trigger_l1_error_by_halt_h2c(rtwdev); 3583 3558 3584 3559 rtw89_leave_ps_mode(rtwdev); 3585 3560 ··· 3601 3576 return 0; 3602 3577 } 3603 3578 3604 3604 - static int rtw89_dbg_trigger_mac_error_ax(struct rtw89_dev *rtwdev) 3579 3579 + static int rtw89_dbg_trigger_l0_error_ax(struct rtw89_dev *rtwdev) 3605 3580 { 3606 3581 u16 val16; 3607 3582 u8 val8; ··· 3623 3598 return 0; 3624 3599 } 3625 3600 3626 3626 - static int rtw89_dbg_trigger_mac_error_be(struct rtw89_dev *rtwdev) 3601 3601 + static int rtw89_dbg_trigger_l0_error_be(struct rtw89_dev *rtwdev) 3627 3602 { 3603 3603 + u8 val8; 3628 3604 int ret; 3629 3605 3630 3606 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3631 3607 if (ret) 3632 3608 return ret; 3633 3609 3634 3634 - rtw89_write32_set(rtwdev, R_BE_CMAC_FW_TRIGGER_IDCT_ISR, 3635 3635 - B_BE_CMAC_FW_TRIG_IDCT | B_BE_CMAC_FW_ERR_IDCT_IMR); 3610 3610 + val8 = rtw89_read8(rtwdev, R_BE_CMAC_FUNC_EN); 3611 3611 + rtw89_write8(rtwdev, R_BE_CMAC_FUNC_EN, val8 & ~B_BE_TMAC_EN); 3612 3612 + mdelay(1); 3613 3613 + rtw89_write8(rtwdev, R_BE_CMAC_FUNC_EN, val8); 3636 3614 3637 3615 return 0; 3638 3616 } 3639 3617 3640 3640 - static int rtw89_dbg_trigger_mac_error_by_halt_h2c(struct rtw89_dev *rtwdev) 3618 3618 + static int rtw89_dbg_trigger_l0_error_by_halt_h2c_ax(struct rtw89_dev *rtwdev) 3641 3619 { 3642 3620 if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 3643 3621 return -EBUSY; ··· 3648 3620 return rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L0_RESET_FORCE); 3649 3621 } 3650 3622 3651 3651 - static int rtw89_dbg_trigger_mac_error(struct rtw89_dev *rtwdev) 3623 3623 + static int rtw89_dbg_trigger_l0_error_by_halt_h2c_be(struct rtw89_dev *rtwdev) 3624 3624 + { 3625 3625 + if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 3626 3626 + return -EBUSY; 3627 3627 + 3628 3628 + rtw89_write32_set(rtwdev, R_BE_CMAC_FW_TRIGGER_IDCT_ISR, 3629 3629 + B_BE_CMAC_FW_TRIG_IDCT | B_BE_CMAC_FW_ERR_IDCT_IMR); 3630 3630 + 3631 3631 + return 0; 3632 3632 + } 3633 3633 + 3634 3634 + static int rtw89_dbg_trigger_l0_error(struct rtw89_dev *rtwdev) 3652 3635 { 3653 3636 const struct rtw89_chip_info *chip = rtwdev->chip; 3654 3654 - 3655 3655 - if (RTW89_CHK_FW_FEATURE(SIM_SER_L0L1_BY_HALT_H2C, &rtwdev->fw)) 3656 3656 - return rtw89_dbg_trigger_mac_error_by_halt_h2c(rtwdev); 3657 3657 - 3658 3658 - rtw89_leave_ps_mode(rtwdev); 3637 3637 + int (*sim_l0_by_halt_h2c)(struct rtw89_dev *rtwdev); 3638 3638 + int (*sim_l0)(struct rtw89_dev *rtwdev); 3659 3639 3660 3640 switch (chip->chip_gen) { 3661 3641 case RTW89_CHIP_AX: 3662 3662 - return rtw89_dbg_trigger_mac_error_ax(rtwdev); 3642 3642 + sim_l0_by_halt_h2c = rtw89_dbg_trigger_l0_error_by_halt_h2c_ax; 3643 3643 + sim_l0 = rtw89_dbg_trigger_l0_error_ax; 3644 3644 + break; 3663 3645 case RTW89_CHIP_BE: 3664 3664 - return rtw89_dbg_trigger_mac_error_be(rtwdev); 3646 3646 + sim_l0_by_halt_h2c = rtw89_dbg_trigger_l0_error_by_halt_h2c_be; 3647 3647 + sim_l0 = rtw89_dbg_trigger_l0_error_be; 3648 3648 + break; 3665 3649 default: 3666 3650 return -EOPNOTSUPP; 3667 3651 } 3652 3652 + 3653 3653 + if (RTW89_CHK_FW_FEATURE(SIM_SER_L0L1_BY_HALT_H2C, &rtwdev->fw)) 3654 3654 + return sim_l0_by_halt_h2c(rtwdev); 3655 3655 + 3656 3656 + rtw89_leave_ps_mode(rtwdev); 3657 3657 + 3658 3658 + return sim_l0(rtwdev); 3668 3659 } 3669 3660 3670 3661 static ssize_t ··· 3700 3653 3701 3654 enum rtw89_dbg_crash_simulation_type { 3702 3655 RTW89_DBG_SIM_CPU_EXCEPTION = 1, 3703 3703 - RTW89_DBG_SIM_CTRL_ERROR = 2, 3704 3704 - RTW89_DBG_SIM_MAC_ERROR = 3, 3656 3656 + RTW89_DBG_SIM_L1_ERROR = 2, 3657 3657 + RTW89_DBG_SIM_L0_ERROR = 3, 3705 3658 }; 3706 3659 3707 3660 static ssize_t ··· 3726 3679 return -EOPNOTSUPP; 3727 3680 sim = rtw89_fw_h2c_trigger_cpu_exception; 3728 3681 break; 3729 3729 - case RTW89_DBG_SIM_CTRL_ERROR: 3730 3730 - sim = rtw89_dbg_trigger_ctrl_error; 3682 3682 + case RTW89_DBG_SIM_L1_ERROR: 3683 3683 + sim = rtw89_dbg_trigger_l1_error; 3731 3684 break; 3732 3732 - case RTW89_DBG_SIM_MAC_ERROR: 3733 3733 - sim = rtw89_dbg_trigger_mac_error; 3685 3685 + case RTW89_DBG_SIM_L0_ERROR: 3686 3686 + sim = rtw89_dbg_trigger_l0_error; 3734 3687 3735 3688 /* Driver SER flow won't get involved; only FW will. */ 3736 3689 announce = false;

+1

drivers/net/wireless/realtek/rtw89/debug.h

reviewed

··· 31 31 RTW89_DBG_CHAN = BIT(20), 32 32 RTW89_DBG_ACPI = BIT(21), 33 33 RTW89_DBG_EDCCA = BIT(22), 34 34 + RTW89_DBG_PS = BIT(23), 34 35 35 36 RTW89_DBG_UNEXP = BIT(31), 36 37 };

+288 -9

drivers/net/wireless/realtek/rtw89/fw.c

reviewed

··· 922 922 __DIS_FW_FEAT(RTL8922A, ge, 0, 35, 84, 0, WITH_RFK_PRE_NOTIFY, G), 923 923 __CFG_FW_FEAT(RTL8922A, ge, 0, 35, 84, 0, RFK_PRE_NOTIFY_MCC_V1), 924 924 __CFG_FW_FEAT(RTL8922A, lt, 0, 35, 84, 0, ADDR_CAM_V0), 925 925 + __CFG_FW_FEAT(RTL8922A, ge, 0, 35, 97, 0, SIM_SER_L0L1_BY_HALT_H2C), 925 926 }; 926 927 927 928 static void rtw89_fw_iterate_feature_cfg(struct rtw89_fw_info *fw, ··· 1383 1382 return 0; 1384 1383 } 1385 1384 1385 1385 + static 1386 1386 + int rtw89_build_tx_comp_from_elm(struct rtw89_dev *rtwdev, 1387 1387 + const struct rtw89_fw_element_hdr *elm, 1388 1388 + const union rtw89_fw_element_arg arg) 1389 1389 + { 1390 1390 + struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 1391 1391 + struct rtw89_hal *hal = &rtwdev->hal; 1392 1392 + u16 aid; 1393 1393 + 1394 1394 + aid = le16_to_cpu(elm->aid); 1395 1395 + if (aid && aid != hal->aid) 1396 1396 + return 1; /* ignore if aid not matched */ 1397 1397 + else if (elm_info->tx_comp) 1398 1398 + return 1; /* ignore if an element is existing */ 1399 1399 + 1400 1400 + elm_info->tx_comp = elm; 1401 1401 + 1402 1402 + return 0; 1403 1403 + } 1404 1404 + 1386 1405 static const struct rtw89_fw_element_handler __fw_element_handlers[] = { 1387 1406 [RTW89_FW_ELEMENT_ID_BBMCU0] = {__rtw89_fw_recognize_from_elm, 1388 1407 { .fw_type = RTW89_FW_BBMCU0 }, NULL}, ··· 1493 1472 }, 1494 1473 [RTW89_FW_ELEMENT_ID_DIAG_MAC] = { 1495 1474 rtw89_recognize_diag_mac_from_elm, {}, NULL, 1475 1475 + }, 1476 1476 + [RTW89_FW_ELEMENT_ID_TX_COMP] = { 1477 1477 + rtw89_build_tx_comp_from_elm, {}, NULL, 1496 1478 }, 1497 1479 }; 1498 1480 ··· 3278 3254 3279 3255 ret = read_poll_timeout(rtw89_phy_read32_mask, done, done, 50, 5000, 3280 3256 true, rtwdev, R_CHK_LPS_STAT, B_CHK_LPS_STAT); 3257 3257 + if (ret) 3258 3258 + rtw89_warn(rtwdev, "h2c_lps_ml_cmn_info done polling timeout\n"); 3259 3259 + 3260 3260 + return 0; 3261 3261 + fail: 3262 3262 + dev_kfree_skb_any(skb); 3263 3263 + 3264 3264 + return ret; 3265 3265 + } 3266 3266 + 3267 3267 + void rtw89_bb_lps_cmn_info_rx_gain_fill(struct rtw89_dev *rtwdev, 3268 3268 + struct rtw89_bb_link_info_rx_gain *h2c_gain, 3269 3269 + const struct rtw89_chan *chan, u8 phy_idx) 3270 3270 + { 3271 3271 + const struct rtw89_phy_bb_gain_info_be *gain = &rtwdev->bb_gain.be; 3272 3272 + enum rtw89_bb_link_rx_gain_table_type tab_idx; 3273 3273 + struct rtw89_chan chan_bcn; 3274 3274 + u8 bw = chan->band_width; 3275 3275 + u8 gain_band; 3276 3276 + u8 bw_idx; 3277 3277 + u8 path; 3278 3278 + int i; 3279 3279 + 3280 3280 + rtw89_chan_create(&chan_bcn, chan->primary_channel, chan->primary_channel, 3281 3281 + chan->band_type, RTW89_CHANNEL_WIDTH_20); 3282 3282 + 3283 3283 + for (tab_idx = RTW89_BB_PS_LINK_RX_GAIN_TAB_BCN_PATH_A; 3284 3284 + tab_idx < RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX; tab_idx++) { 3285 3285 + struct rtw89_phy_calc_efuse_gain calc = {}; 3286 3286 + 3287 3287 + path = (tab_idx & BIT(0)) ? (RF_PATH_B) : (RF_PATH_A); 3288 3288 + if (tab_idx & BIT(1)) { 3289 3289 + rtw89_chip_calc_rx_gain_normal(rtwdev, chan, path, phy_idx, 3290 3290 + &calc); 3291 3291 + gain_band = rtw89_subband_to_gain_band_be(chan->subband_type); 3292 3292 + if (bw > RTW89_CHANNEL_WIDTH_40) 3293 3293 + bw_idx = RTW89_BB_BW_80_160_320; 3294 3294 + else 3295 3295 + bw_idx = RTW89_BB_BW_20_40; 3296 3296 + } else { 3297 3297 + rtw89_chip_calc_rx_gain_normal(rtwdev, &chan_bcn, path, phy_idx, 3298 3298 + &calc); 3299 3299 + gain_band = rtw89_subband_to_gain_band_be(chan_bcn.subband_type); 3300 3300 + bw_idx = RTW89_BB_BW_20_40; 3301 3301 + } 3302 3302 + 3303 3303 + /* efuse ofst and comp */ 3304 3304 + h2c_gain->gain_ofst[tab_idx] = calc.rssi_ofst; 3305 3305 + h2c_gain->cck_gain_ofst[tab_idx] = calc.cck_rpl_ofst; 3306 3306 + h2c_gain->cck_rpl_bias_comp[tab_idx][0] = calc.cck_mean_gain_bias; 3307 3307 + h2c_gain->cck_rpl_bias_comp[tab_idx][1] = calc.cck_mean_gain_bias; 3308 3308 + 3309 3309 + for (i = 0; i < TIA_GAIN_NUM; i++) { 3310 3310 + h2c_gain->gain_err_tia[tab_idx][i] = 3311 3311 + cpu_to_le16(gain->tia_gain[gain_band][bw_idx][path][i]); 3312 3312 + } 3313 3313 + memcpy(h2c_gain->gain_err_lna[tab_idx], 3314 3314 + gain->lna_gain[gain_band][bw_idx][path], 3315 3315 + LNA_GAIN_NUM); 3316 3316 + memcpy(h2c_gain->op1db_lna[tab_idx], 3317 3317 + gain->lna_op1db[gain_band][bw_idx][path], 3318 3318 + LNA_GAIN_NUM); 3319 3319 + memcpy(h2c_gain->op1db_tia[tab_idx], 3320 3320 + gain->tia_lna_op1db[gain_band][bw_idx][path], 3321 3321 + LNA_GAIN_NUM + 1); 3322 3322 + 3323 3323 + memcpy(h2c_gain->rpl_bias_comp_bw[tab_idx]._20M, 3324 3324 + gain->rpl_ofst_20[gain_band][path], 3325 3325 + RTW89_BW20_SC_20M); 3326 3326 + memcpy(h2c_gain->rpl_bias_comp_bw[tab_idx]._40M, 3327 3327 + gain->rpl_ofst_40[gain_band][path], 3328 3328 + RTW89_BW20_SC_40M); 3329 3329 + memcpy(h2c_gain->rpl_bias_comp_bw[tab_idx]._80M, 3330 3330 + gain->rpl_ofst_80[gain_band][path], 3331 3331 + RTW89_BW20_SC_80M); 3332 3332 + memcpy(h2c_gain->rpl_bias_comp_bw[tab_idx]._160M, 3333 3333 + gain->rpl_ofst_160[gain_band][path], 3334 3334 + RTW89_BW20_SC_160M); 3335 3335 + } 3336 3336 + } 3337 3337 + 3338 3338 + int rtw89_fw_h2c_lps_ml_cmn_info_v1(struct rtw89_dev *rtwdev, 3339 3339 + struct rtw89_vif *rtwvif) 3340 3340 + { 3341 3341 + static const u8 bcn_bw_ofst[] = {0, 0, 0, 3, 6, 9, 0, 12}; 3342 3342 + const struct rtw89_chip_info *chip = rtwdev->chip; 3343 3343 + struct rtw89_efuse *efuse = &rtwdev->efuse; 3344 3344 + struct rtw89_h2c_lps_ml_cmn_info_v1 *h2c; 3345 3345 + struct rtw89_vif_link *rtwvif_link; 3346 3346 + const struct rtw89_chan *chan; 3347 3347 + struct rtw89_bb_ctx *bb; 3348 3348 + u32 len = sizeof(*h2c); 3349 3349 + unsigned int link_id; 3350 3350 + struct sk_buff *skb; 3351 3351 + u8 beacon_bw_ofst; 3352 3352 + u32 done; 3353 3353 + int ret; 3354 3354 + 3355 3355 + if (chip->chip_gen != RTW89_CHIP_BE) 3356 3356 + return 0; 3357 3357 + 3358 3358 + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len); 3359 3359 + if (!skb) { 3360 3360 + rtw89_err(rtwdev, "failed to alloc skb for h2c lps_ml_cmn_info_v1\n"); 3361 3361 + return -ENOMEM; 3362 3362 + } 3363 3363 + skb_put(skb, len); 3364 3364 + h2c = (struct rtw89_h2c_lps_ml_cmn_info_v1 *)skb->data; 3365 3365 + 3366 3366 + h2c->fmt_id = 0x20; 3367 3367 + 3368 3368 + h2c->mlo_dbcc_mode = cpu_to_le32(rtwdev->mlo_dbcc_mode); 3369 3369 + h2c->rfe_type = efuse->rfe_type; 3370 3370 + h2c->rssi_main = U8_MAX; 3371 3371 + 3372 3372 + memset(h2c->link_id, 0xfe, RTW89_BB_PS_LINK_BUF_MAX); 3373 3373 + 3374 3374 + rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) { 3375 3375 + u8 phy_idx = rtwvif_link->phy_idx; 3376 3376 + 3377 3377 + bb = rtw89_get_bb_ctx(rtwdev, phy_idx); 3378 3378 + chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 3379 3379 + 3380 3380 + h2c->link_id[phy_idx] = phy_idx; 3381 3381 + h2c->central_ch[phy_idx] = chan->channel; 3382 3382 + h2c->pri_ch[phy_idx] = chan->primary_channel; 3383 3383 + h2c->band[phy_idx] = chan->band_type; 3384 3384 + h2c->bw[phy_idx] = chan->band_width; 3385 3385 + 3386 3386 + if (rtwvif_link->bcn_bw_idx < ARRAY_SIZE(bcn_bw_ofst)) { 3387 3387 + beacon_bw_ofst = bcn_bw_ofst[rtwvif_link->bcn_bw_idx]; 3388 3388 + h2c->dup_bcn_ofst[phy_idx] = beacon_bw_ofst; 3389 3389 + } 3390 3390 + 3391 3391 + if (h2c->rssi_main > bb->ch_info.rssi_min) 3392 3392 + h2c->rssi_main = bb->ch_info.rssi_min; 3393 3393 + 3394 3394 + rtw89_bb_lps_cmn_info_rx_gain_fill(rtwdev, 3395 3395 + &h2c->rx_gain[phy_idx], 3396 3396 + chan, phy_idx); 3397 3397 + } 3398 3398 + 3399 3399 + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, 3400 3400 + H2C_CAT_OUTSRC, H2C_CL_OUTSRC_DM, 3401 3401 + H2C_FUNC_FW_LPS_ML_CMN_INFO, 0, 0, len); 3402 3402 + 3403 3403 + rtw89_phy_write32_mask(rtwdev, R_CHK_LPS_STAT_BE4, B_CHK_LPS_STAT, 0); 3404 3404 + ret = rtw89_h2c_tx(rtwdev, skb, false); 3405 3405 + if (ret) { 3406 3406 + rtw89_err(rtwdev, "failed to send h2c\n"); 3407 3407 + goto fail; 3408 3408 + } 3409 3409 + 3410 3410 + ret = read_poll_timeout(rtw89_phy_read32_mask, done, done, 50, 5000, 3411 3411 + true, rtwdev, R_CHK_LPS_STAT_BE4, B_CHK_LPS_STAT); 3281 3412 if (ret) 3282 3413 rtw89_warn(rtwdev, "h2c_lps_ml_cmn_info done polling timeout\n"); 3283 3414 ··· 7292 7113 int rtw89_fw_h2c_rf_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, 7293 7114 const struct rtw89_chan *chan, enum rtw89_tssi_mode tssi_mode) 7294 7115 { 7116 7116 + const struct rtw89_chip_info *chip = rtwdev->chip; 7295 7117 struct rtw89_efuse *efuse = &rtwdev->efuse; 7296 7118 struct rtw89_hal *hal = &rtwdev->hal; 7297 7119 struct rtw89_h2c_rf_tssi *h2c; ··· 7313 7133 h2c->ch = chan->channel; 7314 7134 h2c->bw = chan->band_width; 7315 7135 h2c->band = chan->band_type; 7316 7316 - h2c->hwtx_en = true; 7317 7136 h2c->cv = hal->cv; 7318 7137 h2c->tssi_mode = tssi_mode; 7319 7138 h2c->rfe_type = efuse->rfe_type; 7139 7139 + 7140 7140 + if (chip->chip_id == RTL8922A) 7141 7141 + h2c->hwtx_en = true; 7142 7142 + else 7143 7143 + h2c->hwtx_en = false; 7320 7144 7321 7145 rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(rtwdev, phy_idx, chan, h2c); 7322 7146 rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(rtwdev, phy_idx, chan, h2c); ··· 7504 7320 skb_put(skb, len); 7505 7321 h2c = (struct rtw89_h2c_rf_dack *)skb->data; 7506 7322 7507 7507 - h2c->len = cpu_to_le32(len); 7508 7508 - h2c->phy = cpu_to_le32(phy_idx); 7509 7509 - h2c->type = cpu_to_le32(0); 7323 7323 + h2c->len = len; 7324 7324 + h2c->phy = phy_idx; 7325 7325 + h2c->type = 0; 7510 7326 7511 7327 rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, 7512 7328 H2C_CAT_OUTSRC, H2C_CL_OUTSRC_RF_FW_RFK, ··· 7615 7431 return ret; 7616 7432 } 7617 7433 7434 7434 + int rtw89_fw_h2c_rf_txiqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, 7435 7435 + const struct rtw89_chan *chan) 7436 7436 + { 7437 7437 + struct rtw89_h2c_rf_txiqk *h2c; 7438 7438 + u32 len = sizeof(*h2c); 7439 7439 + struct sk_buff *skb; 7440 7440 + int ret; 7441 7441 + 7442 7442 + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len); 7443 7443 + if (!skb) { 7444 7444 + rtw89_err(rtwdev, "failed to alloc skb for h2c RF TXIQK\n"); 7445 7445 + return -ENOMEM; 7446 7446 + } 7447 7447 + skb_put(skb, len); 7448 7448 + h2c = (struct rtw89_h2c_rf_txiqk *)skb->data; 7449 7449 + 7450 7450 + h2c->len = len; 7451 7451 + h2c->phy = phy_idx; 7452 7452 + h2c->txiqk_enable = true; 7453 7453 + h2c->is_wb_txiqk = true; 7454 7454 + h2c->kpath = RF_AB; 7455 7455 + h2c->cur_band = chan->band_type; 7456 7456 + h2c->cur_bw = chan->band_width; 7457 7457 + h2c->cur_ch = chan->channel; 7458 7458 + h2c->txiqk_dbg_en = rtw89_debug_is_enabled(rtwdev, RTW89_DBG_RFK); 7459 7459 + 7460 7460 + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, 7461 7461 + H2C_CAT_OUTSRC, H2C_CL_OUTSRC_RF_FW_RFK, 7462 7462 + H2C_FUNC_RFK_TXIQK_OFFOAD, 0, 0, len); 7463 7463 + 7464 7464 + ret = rtw89_h2c_tx(rtwdev, skb, false); 7465 7465 + if (ret) { 7466 7466 + rtw89_err(rtwdev, "failed to send h2c\n"); 7467 7467 + goto fail; 7468 7468 + } 7469 7469 + 7470 7470 + return 0; 7471 7471 + fail: 7472 7472 + dev_kfree_skb_any(skb); 7473 7473 + 7474 7474 + return ret; 7475 7475 + } 7476 7476 + 7477 7477 + int rtw89_fw_h2c_rf_cim3k(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, 7478 7478 + const struct rtw89_chan *chan) 7479 7479 + { 7480 7480 + struct rtw89_h2c_rf_cim3k *h2c; 7481 7481 + u32 len = sizeof(*h2c); 7482 7482 + struct sk_buff *skb; 7483 7483 + int ret; 7484 7484 + 7485 7485 + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len); 7486 7486 + if (!skb) { 7487 7487 + rtw89_err(rtwdev, "failed to alloc skb for h2c RF CIM3K\n"); 7488 7488 + return -ENOMEM; 7489 7489 + } 7490 7490 + skb_put(skb, len); 7491 7491 + h2c = (struct rtw89_h2c_rf_cim3k *)skb->data; 7492 7492 + 7493 7493 + h2c->len = len; 7494 7494 + h2c->phy = phy_idx; 7495 7495 + h2c->kpath = RF_AB; 7496 7496 + h2c->cur_band = chan->band_type; 7497 7497 + h2c->cur_bw = chan->band_width; 7498 7498 + h2c->cur_ch = chan->channel; 7499 7499 + h2c->cim3k_dbg_en = rtw89_debug_is_enabled(rtwdev, RTW89_DBG_RFK); 7500 7500 + 7501 7501 + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, 7502 7502 + H2C_CAT_OUTSRC, H2C_CL_OUTSRC_RF_FW_RFK, 7503 7503 + H2C_FUNC_RFK_CIM3K_OFFOAD, 0, 0, len); 7504 7504 + 7505 7505 + ret = rtw89_h2c_tx(rtwdev, skb, false); 7506 7506 + if (ret) { 7507 7507 + rtw89_err(rtwdev, "failed to send h2c\n"); 7508 7508 + goto fail; 7509 7509 + } 7510 7510 + 7511 7511 + return 0; 7512 7512 + fail: 7513 7513 + dev_kfree_skb_any(skb); 7514 7514 + 7515 7515 + return ret; 7516 7516 + } 7517 7517 + 7618 7518 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev, 7619 7519 u8 h2c_class, u8 h2c_func, u8 *buf, u16 len, 7620 7520 bool rack, bool dack) ··· 7782 7514 lockdep_assert_wiphy(rtwdev->hw->wiphy); 7783 7515 7784 7516 __rtw89_fw_free_all_early_h2c(rtwdev); 7517 7517 + } 7518 7518 + 7519 7519 + void rtw89_fw_c2h_dummy_handler(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 7520 7520 + { 7521 7521 + struct rtw89_fw_c2h_attr *attr = RTW89_SKB_C2H_CB(c2h); 7522 7522 + u8 category = attr->category; 7523 7523 + u8 class = attr->class; 7524 7524 + u8 func = attr->func; 7525 7525 + 7526 7526 + rtw89_debug(rtwdev, RTW89_DBG_FW, 7527 7527 + "C2H cate=%u cls=%u func=%u is dummy\n", category, class, func); 7785 7528 } 7786 7529 7787 7530 static void rtw89_fw_c2h_parse_attr(struct sk_buff *c2h) ··· 9027 8748 if (tmp == scan_rtwvif) 9028 8749 continue; 9029 8750 9030 9030 - tmp_link = rtw89_vif_get_link_inst(tmp, 0); 9031 9031 - if (unlikely(!tmp_link)) { 9032 9032 - rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 9033 9033 - "hw scan: no HW-0 link for extra op\n"); 8751 8751 + tmp_link = rtw89_get_designated_link(tmp); 8752 8752 + if (unlikely(!tmp_link)) 9034 8753 continue; 9035 9035 - } 9036 8754 9037 8755 tmp_chan = rtw89_chan_get(rtwdev, tmp_link->chanctx_idx); 9038 8756 *ext = (struct rtw89_hw_scan_extra_op){ ··· 9055 8779 struct cfg80211_scan_request *req = &scan_req->req; 9056 8780 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 9057 8781 rtwvif_link->chanctx_idx); 8782 8782 + struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 9058 8783 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 9059 8784 struct rtw89_chanctx_pause_parm pause_parm = { 9060 8785 .rsn = RTW89_CHANCTX_PAUSE_REASON_HW_SCAN, ··· 9084 8807 if (req->flags & NL80211_SCAN_FLAG_RANDOM_ADDR) 9085 8808 get_random_mask_addr(mac_addr, req->mac_addr, 9086 8809 req->mac_addr_mask); 8810 8810 + else if (ieee80211_vif_is_mld(vif)) 8811 8811 + ether_addr_copy(mac_addr, vif->addr); 9087 8812 else 9088 8813 ether_addr_copy(mac_addr, rtwvif_link->mac_addr); 9089 8814

+180 -8

drivers/net/wireless/realtek/rtw89/fw.h

reviewed

··· 2017 2017 u8 dup_bcn_ofst[RTW89_PHY_NUM]; 2018 2018 } __packed; 2019 2019 2020 2020 + #define BB_RX_GAIN_TB_RSSI_COMP_NUM 3 2021 2021 + #define BB_RX_GAIN_CCK_RPL_BIAS_COMP_NUM 2 2022 2022 + #define BB_GT2_GS_IDX_NUM 11 2023 2023 + #define BB_GT2_WB_GIDX_ELNA_NUM 16 2024 2024 + #define BB_GT2_G_ELNA_NUM 2 2025 2025 + 2026 2026 + enum rtw89_bb_link_rx_gain_table_type { 2027 2027 + RTW89_BB_PS_LINK_RX_GAIN_TAB_BCN_PATH_A = 0x00, 2028 2028 + RTW89_BB_PS_LINK_RX_GAIN_TAB_BCN_PATH_B = 0x01, 2029 2029 + RTW89_BB_PS_LINK_RX_GAIN_TAB_NOR_PATH_A = 0x02, 2030 2030 + RTW89_BB_PS_LINK_RX_GAIN_TAB_NOR_PATH_B = 0x03, 2031 2031 + RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX, 2032 2032 + }; 2033 2033 + 2034 2034 + enum rtw89_bb_ps_link_buf_id { 2035 2035 + RTW89_BB_PS_LINK_BUF_0 = 0x00, 2036 2036 + RTW89_BB_PS_LINK_BUF_1 = 0x01, 2037 2037 + RTW89_BB_PS_LINK_BUF_2 = 0x02, 2038 2038 + RTW89_BB_PS_LINK_BUF_MAX, 2039 2039 + }; 2040 2040 + 2041 2041 + struct rtw89_bb_link_info_rx_gain { 2042 2042 + u8 gain_ofst[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX]; 2043 2043 + __le16 rpl_bias_comp[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX]; 2044 2044 + u8 tb_rssi_m_bias_comp[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX] 2045 2045 + [BB_RX_GAIN_TB_RSSI_COMP_NUM]; 2046 2046 + u8 cck_gain_ofst[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX]; 2047 2047 + u8 cck_rpl_bias_comp[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX] 2048 2048 + [BB_RX_GAIN_CCK_RPL_BIAS_COMP_NUM]; 2049 2049 + u8 gain_err_lna[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][LNA_GAIN_NUM]; 2050 2050 + __le16 gain_err_tia[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][TIA_GAIN_NUM]; 2051 2051 + u8 op1db_lna[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][LNA_GAIN_NUM]; 2052 2052 + u8 op1db_tia[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][TIA_LNA_OP1DB_NUM]; 2053 2053 + struct { 2054 2054 + u8 _20M[RTW89_BW20_SC_20M]; 2055 2055 + u8 _40M[RTW89_BW20_SC_40M]; 2056 2056 + u8 _80M[RTW89_BW20_SC_80M]; 2057 2057 + u8 _160M[RTW89_BW20_SC_160M]; 2058 2058 + } rpl_bias_comp_bw[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX]; 2059 2059 + u8 wb_gs[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][BB_GT2_GS_IDX_NUM]; 2060 2060 + u8 bypass_lna[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][LNA_GAIN_NUM]; 2061 2061 + u8 wb_lna_tia[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][BB_GT2_WB_GIDX_ELNA_NUM]; 2062 2062 + u8 wb_g_elna[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][BB_GT2_G_ELNA_NUM]; 2063 2063 + } __packed; 2064 2064 + 2065 2065 + struct rtw89_h2c_lps_ml_cmn_info_v1 { 2066 2066 + u8 fmt_id; 2067 2067 + u8 rfe_type; 2068 2068 + u8 rssi_main; 2069 2069 + u8 rsvd0; 2070 2070 + __le32 mlo_dbcc_mode; 2071 2071 + u8 link_id[RTW89_BB_PS_LINK_BUF_MAX]; 2072 2072 + u8 central_ch[RTW89_BB_PS_LINK_BUF_MAX]; 2073 2073 + u8 pri_ch[RTW89_BB_PS_LINK_BUF_MAX]; 2074 2074 + u8 bw[RTW89_BB_PS_LINK_BUF_MAX]; 2075 2075 + u8 band[RTW89_BB_PS_LINK_BUF_MAX]; 2076 2076 + u8 dup_bcn_ofst[RTW89_BB_PS_LINK_BUF_MAX]; 2077 2077 + struct rtw89_bb_link_info_rx_gain rx_gain[RTW89_BB_PS_LINK_BUF_MAX]; 2078 2078 + } __packed; 2079 2079 + 2020 2080 struct rtw89_h2c_trig_cpu_except { 2021 2081 __le32 w0; 2022 2082 } __packed; ··· 3889 3829 #define RTW89_C2H_RA_RPT_W3_MD_SEL_B2 BIT(15) 3890 3830 #define RTW89_C2H_RA_RPT_W3_BW_B2 BIT(16) 3891 3831 3832 3832 + struct rtw89_c2h_lps_rpt { 3833 3833 + struct rtw89_c2h_hdr hdr; 3834 3834 + u8 type; 3835 3835 + u8 cnt_bbcr; 3836 3836 + u8 cnt_bbmcucr; 3837 3837 + u8 cnt_rfcr; 3838 3838 + u8 data[]; 3839 3839 + /* 3840 3840 + * The layout of data: 3841 3841 + * u8 info[][4], size = total_len - size of below fields 3842 3842 + * __le16 bbcr_addr[], size = cnt_bbcr 3843 3843 + * __le32 bbcr_data[], size = cnt_bbcr 3844 3844 + * __le16 bbmcucr_addr[], size = cnt_bbmcucr 3845 3845 + * __le32 bbmcucr_data[], size = cnt_bbmcucr 3846 3846 + * __le16 rfcr_addr[], size = cnt_rfcr 3847 3847 + * __le32 rfcr_data_a[], size = cnt_rfcr 3848 3848 + * __le32 rfcr_data_b[], size = cnt_rfcr 3849 3849 + */ 3850 3850 + } __packed; 3851 3851 + 3892 3852 struct rtw89_c2h_fw_scan_rpt { 3893 3853 struct rtw89_c2h_hdr hdr; 3894 3854 u8 phy_idx; ··· 4262 4182 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_RU_6GHZ = 26, 4263 4183 RTW89_FW_ELEMENT_ID_AFE_PWR_SEQ = 27, 4264 4184 RTW89_FW_ELEMENT_ID_DIAG_MAC = 28, 4185 4185 + RTW89_FW_ELEMENT_ID_TX_COMP = 29, 4265 4186 4266 4187 RTW89_FW_ELEMENT_ID_NUM, 4267 4188 }; ··· 4718 4637 H2C_FUNC_RFK_RXDCK_OFFLOAD = 0x6, 4719 4638 H2C_FUNC_RFK_PRE_NOTIFY = 0x8, 4720 4639 H2C_FUNC_RFK_TAS_OFFLOAD = 0x9, 4640 4640 + H2C_FUNC_RFK_TXIQK_OFFOAD = 0xc, 4641 4641 + H2C_FUNC_RFK_CIM3K_OFFOAD = 0xe, 4721 4642 }; 4722 4643 4723 4644 struct rtw89_fw_h2c_rf_get_mccch { ··· 4912 4829 } __packed; 4913 4830 4914 4831 struct rtw89_h2c_rf_dack { 4915 4915 - __le32 len; 4916 4916 - __le32 phy; 4917 4917 - __le32 type; 4832 4832 + u8 len; 4833 4833 + u8 phy; 4834 4834 + u8 type; 4918 4835 } __packed; 4919 4836 4920 4837 struct rtw89_h2c_rf_rxdck_v0 { ··· 4935 4852 struct rtw89_h2c_rf_rxdck { 4936 4853 struct rtw89_h2c_rf_rxdck_v0 v0; 4937 4854 u8 is_chl_k; 4855 4855 + } __packed; 4856 4856 + 4857 4857 + struct rtw89_h2c_rf_txiqk { 4858 4858 + u8 len; 4859 4859 + u8 phy; 4860 4860 + u8 txiqk_enable; 4861 4861 + u8 is_wb_txiqk; 4862 4862 + u8 kpath; 4863 4863 + u8 cur_band; 4864 4864 + u8 cur_bw; 4865 4865 + u8 cur_ch; 4866 4866 + u8 txiqk_dbg_en; 4867 4867 + } __packed; 4868 4868 + 4869 4869 + struct rtw89_h2c_rf_cim3k { 4870 4870 + u8 len; 4871 4871 + u8 phy; 4872 4872 + u8 su_cim3k_enable[2]; 4873 4873 + u8 ru_cim3k_enable[2]; 4874 4874 + u8 kpath; 4875 4875 + u8 cur_band; 4876 4876 + u8 cur_bw; 4877 4877 + u8 cur_ch; 4878 4878 + u8 cim3k_dbg_en; 4938 4879 } __packed; 4939 4880 4940 4881 enum rtw89_rf_log_type { ··· 5005 4898 u8 rsvd; 5006 4899 __le32 reload_cnt; 5007 4900 __le32 iqk_fail_cnt; 4901 4901 + __le32 rf_0x18[2]; 5008 4902 __le32 lok_idac[2]; 5009 4903 __le32 lok_vbuf[2]; 5010 5010 - __le32 rftxgain[2][4]; 5011 5011 - __le32 rfrxgain[2][4]; 5012 5012 - __le32 tx_xym[2][4]; 5013 5013 - __le32 rx_xym[2][4]; 4904 4904 + __le32 rftxgain[2][6]; 4905 4905 + __le32 rfrxgain[2][6]; 4906 4906 + __le32 tx_xym[2][6]; 4907 4907 + __le32 rx_xym[2][6]; 4908 4908 + __le32 rx_wb_xym[2][32]; 4909 4909 + bool is_radar; 4910 4910 + u8 rsvd1[3]; 5014 4911 } __packed; 5015 4912 5016 4913 struct rtw89_c2h_rf_dpk_rpt_log { ··· 5057 4946 u8 dack_fail; 5058 4947 u8 wbdck_d[2]; 5059 4948 u8 rck_d; 4949 4949 + u8 adgaink_ex_d; 5060 4950 } __packed; 5061 4951 5062 4952 struct rtw89_c2h_rf_rxdck_rpt_log { ··· 5084 4972 u8 is_txgapk_ok; 5085 4973 u8 chk_id; 5086 4974 u8 ver; 5087 5087 - u8 rsv1; 4975 4975 + u8 d_bnd_ok; 4976 4976 + __le32 stage[2]; 4977 4977 + __le16 failcode[2]; 4978 4978 + u8 rsvd[4]; 4979 4979 + } __packed; 4980 4980 + 4981 4981 + struct rtw89_c2h_rf_txiqk_rpt_log { 4982 4982 + u8 fw_txiqk_ver; 4983 4983 + u8 iqk_band[2]; 4984 4984 + u8 iqk_ch[2]; 4985 4985 + u8 iqk_bw[2]; 4986 4986 + bool tx_iqk_fail[2]; 4987 4987 + bool is_iqk_init; 4988 4988 + bool txiqk_en; 4989 4989 + bool lok_en; 4990 4990 + bool lok_fail[2]; 4991 4991 + u8 rsvd[2]; 4992 4992 + __le32 iqk_times; 4993 4993 + bool txiqk_nctldone[2]; 4994 4994 + u8 rsvd2[2]; 4995 4995 + __le32 txgain[2][6]; 4996 4996 + __le32 tx_iqc[2][6]; 4997 4997 + __le32 tx_xym[2][6][14]; 4998 4998 + __le32 kidx[2]; 4999 4999 + } __packed; 5000 5000 + 5001 5001 + struct rtw89_c2h_rf_cim3k_rpt_log { 5002 5002 + u8 cim3k_band[2]; 5003 5003 + u8 cim3k_ch[2]; 5004 5004 + u8 cim3k_bw[2]; 5005 5005 + u8 su_path_ok[2]; 5006 5006 + u8 ru_path_ok[2]; 5007 5007 + u8 txagc_cim3k[2]; 5008 5008 + u8 ther_cim3k[2]; 5009 5009 + u8 cim3k_gs[2]; 5010 5010 + __le16 cim3k_pwsf[2]; 5011 5011 + bool cim3k_nctldone[2]; 5012 5012 + u8 rsvd[2]; 5013 5013 + __le32 cim3k_rxiqc[2]; 5014 5014 + __le32 cim3k_su_coef[2][3]; 5015 5015 + __le16 dc_i[2]; 5016 5016 + __le16 dc_q[2]; 5017 5017 + u8 corr_val[2]; 5018 5018 + u8 corr_idx[2]; 5019 5019 + u8 rxbb_ov[2]; 5020 5020 + u8 cim3k_txiqc[2]; 5021 5021 + u8 kidx[2]; 5022 5022 + u8 fw_cim3k_ver; 5023 5023 + bool su_cim3k_en[2]; 5024 5024 + bool ru_cim3k_en[2]; 5025 5025 + u8 rsvd1; 5088 5026 } __packed; 5089 5027 5090 5028 struct rtw89_c2h_rfk_report { ··· 5249 5087 void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h); 5250 5088 void rtw89_fw_c2h_work(struct wiphy *wiphy, struct wiphy_work *work); 5251 5089 void rtw89_fw_c2h_purge_obsoleted_scan_events(struct rtw89_dev *rtwdev); 5090 5090 + void rtw89_fw_c2h_dummy_handler(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len); 5252 5091 int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev, 5253 5092 struct rtw89_vif_link *rtwvif_link, 5254 5093 struct rtw89_sta_link *rtwsta_link, ··· 5317 5154 int rtw89_fw_h2c_rf_rxdck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, 5318 5155 const struct rtw89_chan *chan, bool is_chl_k); 5319 5156 int rtw89_fw_h2c_rf_tas_trigger(struct rtw89_dev *rtwdev, bool enable); 5157 5157 + int rtw89_fw_h2c_rf_txiqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, 5158 5158 + const struct rtw89_chan *chan); 5159 5159 + int rtw89_fw_h2c_rf_cim3k(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, 5160 5160 + const struct rtw89_chan *chan); 5320 5161 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev, 5321 5162 u8 h2c_class, u8 h2c_func, u8 *buf, u16 len, 5322 5163 bool rack, bool dack); ··· 5351 5184 int rtw89_fw_h2c_lps_ch_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 5352 5185 int rtw89_fw_h2c_lps_ml_cmn_info(struct rtw89_dev *rtwdev, 5353 5186 struct rtw89_vif *rtwvif); 5187 5187 + void rtw89_bb_lps_cmn_info_rx_gain_fill(struct rtw89_dev *rtwdev, 5188 5188 + struct rtw89_bb_link_info_rx_gain *h2c_gain, 5189 5189 + const struct rtw89_chan *chan, u8 phy_idx); 5190 5190 + int rtw89_fw_h2c_lps_ml_cmn_info_v1(struct rtw89_dev *rtwdev, 5191 5191 + struct rtw89_vif *rtwvif); 5354 5192 int rtw89_fw_h2c_fwips(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 5355 5193 bool enable); 5356 5194 struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len);

+17 -6

drivers/net/wireless/realtek/rtw89/mac.c

reviewed

··· 1554 1554 set_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1555 1555 1556 1556 rtw89_mac_update_scoreboard(rtwdev, MAC_AX_NOTIFY_TP_MAJOR); 1557 1557 + rtw89_mac_clr_aon_intr(rtwdev); 1557 1558 } else { 1558 1559 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1559 1560 clear_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); ··· 4374 4373 R_AX_PORT_HGQ_WINDOW_CFG + 3}, 4375 4374 }; 4376 4375 4376 4376 + static const struct rtw89_mac_mu_gid_addr rtw89_mac_mu_gid_addr_ax = { 4377 4377 + .position_en = {R_AX_GID_POSITION_EN0, R_AX_GID_POSITION_EN1}, 4378 4378 + .position = {R_AX_GID_POSITION0, R_AX_GID_POSITION1, 4379 4379 + R_AX_GID_POSITION2, R_AX_GID_POSITION3}, 4380 4380 + }; 4381 4381 + 4377 4382 static void rtw89_mac_check_packet_ctrl(struct rtw89_dev *rtwdev, 4378 4383 struct rtw89_vif_link *rtwvif_link, u8 type) 4379 4384 { ··· 6776 6769 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 6777 6770 struct ieee80211_bss_conf *conf) 6778 6771 { 6772 6772 + const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6773 6773 + const struct rtw89_mac_mu_gid_addr *addr = mac->mu_gid; 6779 6774 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 6780 6775 struct rtw89_vif_link *rtwvif_link; 6781 6776 u8 mac_idx; ··· 6797 6788 6798 6789 p = (__le32 *)conf->mu_group.membership; 6799 6790 rtw89_write32(rtwdev, 6800 6800 - rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN0, mac_idx), 6791 6791 + rtw89_mac_reg_by_idx(rtwdev, addr->position_en[0], mac_idx), 6801 6792 le32_to_cpu(p[0])); 6802 6793 rtw89_write32(rtwdev, 6803 6803 - rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN1, mac_idx), 6794 6794 + rtw89_mac_reg_by_idx(rtwdev, addr->position_en[1], mac_idx), 6804 6795 le32_to_cpu(p[1])); 6805 6796 6806 6797 p = (__le32 *)conf->mu_group.position; 6807 6807 - rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION0, mac_idx), 6798 6798 + rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, addr->position[0], mac_idx), 6808 6799 le32_to_cpu(p[0])); 6809 6809 - rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION1, mac_idx), 6800 6800 + rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, addr->position[1], mac_idx), 6810 6801 le32_to_cpu(p[1])); 6811 6811 - rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION2, mac_idx), 6802 6802 + rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, addr->position[2], mac_idx), 6812 6803 le32_to_cpu(p[2])); 6813 6813 - rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION3, mac_idx), 6804 6804 + rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, addr->position[3], mac_idx), 6814 6805 le32_to_cpu(p[3])); 6815 6806 } 6816 6807 ··· 7290 7281 .port_base = &rtw89_port_base_ax, 7291 7282 .agg_len_ht = R_AX_AGG_LEN_HT_0, 7292 7283 .ps_status = R_AX_PPWRBIT_SETTING, 7284 7284 + .mu_gid = &rtw89_mac_mu_gid_addr_ax, 7293 7285 7294 7286 .muedca_ctrl = { 7295 7287 .addr = R_AX_MUEDCA_EN, ··· 7313 7303 .sys_init = sys_init_ax, 7314 7304 .trx_init = trx_init_ax, 7315 7305 .preload_init = preload_init_set_ax, 7306 7306 + .clr_aon_intr = NULL, 7316 7307 .err_imr_ctrl = err_imr_ctrl_ax, 7317 7308 .mac_func_en = NULL, 7318 7309 .hci_func_en = rtw89_mac_hci_func_en_ax,

+23

drivers/net/wireless/realtek/rtw89/mac.h

reviewed

··· 1015 1015 1016 1016 extern const struct rtw89_mac_size_set rtw89_mac_size; 1017 1017 1018 1018 + struct rtw89_mac_mu_gid_addr { 1019 1019 + u32 position_en[2]; 1020 1020 + u32 position[4]; 1021 1021 + }; 1022 1022 + 1018 1023 struct rtw89_mac_gen_def { 1019 1024 u32 band1_offset; 1020 1025 u32 filter_model_addr; ··· 1030 1025 const struct rtw89_port_reg *port_base; 1031 1026 u32 agg_len_ht; 1032 1027 u32 ps_status; 1028 1028 + const struct rtw89_mac_mu_gid_addr *mu_gid; 1033 1029 1034 1030 struct rtw89_reg_def muedca_ctrl; 1035 1031 struct rtw89_reg_def bfee_ctrl; ··· 1045 1039 int (*trx_init)(struct rtw89_dev *rtwdev); 1046 1040 int (*preload_init)(struct rtw89_dev *rtwdev, u8 mac_idx, 1047 1041 enum rtw89_qta_mode mode); 1042 1042 + void (*clr_aon_intr)(struct rtw89_dev *rtwdev); 1048 1043 void (*err_imr_ctrl)(struct rtw89_dev *rtwdev, bool en); 1049 1044 int (*mac_func_en)(struct rtw89_dev *rtwdev); 1050 1045 void (*hci_func_en)(struct rtw89_dev *rtwdev); ··· 1143 1136 addr = rtw89_mac_reg_by_idx(rtwdev, addr, band); 1144 1137 1145 1138 rtw89_write16(rtwdev, addr, data); 1139 1139 + } 1140 1140 + 1141 1141 + static inline void 1142 1142 + rtw89_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data, u8 band) 1143 1143 + { 1144 1144 + addr = rtw89_mac_reg_by_idx(rtwdev, addr, band); 1145 1145 + 1146 1146 + rtw89_write32_mask(rtwdev, addr, mask, data); 1146 1147 } 1147 1148 1148 1149 static inline ··· 1264 1249 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1265 1250 1266 1251 return mac->check_mac_en(rtwdev, band, sel); 1252 1252 + } 1253 1253 + 1254 1254 + static inline void rtw89_mac_clr_aon_intr(struct rtw89_dev *rtwdev) 1255 1255 + { 1256 1256 + const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1257 1257 + 1258 1258 + if (mac->clr_aon_intr) 1259 1259 + mac->clr_aon_intr(rtwdev); 1267 1260 } 1268 1261 1269 1262 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val);

+2 -2

drivers/net/wireless/realtek/rtw89/mac80211.c

reviewed

··· 1438 1438 1439 1439 BUILD_BUG_ON(RTW89_MLD_NON_STA_LINK_NUM != 1); 1440 1440 1441 1441 - rtwvif_link = rtw89_vif_get_link_inst(rtwvif, 0); 1441 1441 + rtwvif_link = rtw89_get_designated_link(rtwvif); 1442 1442 if (unlikely(!rtwvif_link)) { 1443 1443 - rtw89_err(rtwdev, "chsw bcn: find no link on HW-0\n"); 1443 1443 + rtw89_err(rtwdev, "chsw bcn: find no designated link\n"); 1444 1444 return; 1445 1445 } 1446 1446

+22 -1

drivers/net/wireless/realtek/rtw89/mac_be.c

reviewed

··· 62 62 R_BE_PORT_HGQ_WINDOW_CFG + 3}, 63 63 }; 64 64 65 65 + static const struct rtw89_mac_mu_gid_addr rtw89_mac_mu_gid_addr_be = { 66 66 + .position_en = {R_BE_GID_POSITION_EN0, R_BE_GID_POSITION_EN1}, 67 67 + .position = {R_BE_GID_POSITION0, R_BE_GID_POSITION1, 68 68 + R_BE_GID_POSITION2, R_BE_GID_POSITION3}, 69 69 + }; 70 70 + 65 71 static int rtw89_mac_check_mac_en_be(struct rtw89_dev *rtwdev, u8 mac_idx, 66 72 enum rtw89_mac_hwmod_sel sel) 67 73 { ··· 1334 1328 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_SPECIAL_TX_SETTING, mac_idx); 1335 1329 rtw89_write32_clr(rtwdev, reg, B_BE_BMC_NAV_PROTECT); 1336 1330 1331 1331 + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_0, mac_idx); 1332 1332 + rtw89_write32_set(rtwdev, reg, B_BE_WMAC_MBA_DUR_FORCE); 1333 1333 + 1337 1334 return 0; 1338 1335 } 1339 1336 ··· 1361 1352 static int tmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) 1362 1353 { 1363 1354 const struct rtw89_chip_info *chip = rtwdev->chip; 1355 1355 + struct rtw89_hal *hal = &rtwdev->hal; 1364 1356 u32 reg; 1365 1357 1366 1358 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TB_PPDU_CTRL, mac_idx); ··· 1373 1363 rtw89_write32_mask(rtwdev, reg, B_BE_EHT_HE_PPDU_2XLTF_ZLD_USTIMER_MASK, 0xe); 1374 1364 } 1375 1365 1376 1376 - if (chip->chip_id == RTL8922D) { 1366 1366 + if (chip->chip_id == RTL8922D && hal->cid != RTL8922D_CID7090) { 1377 1367 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_COMMON_PHYINTF_CTRL_0, mac_idx); 1378 1368 rtw89_write32_clr(rtwdev, reg, CLEAR_DTOP_DIS); 1379 1369 } ··· 1998 1988 rtw89_write32(rtwdev, reg, val32); 1999 1989 2000 1990 return 0; 1991 1991 + } 1992 1992 + 1993 1993 + static void clr_aon_intr_be(struct rtw89_dev *rtwdev) 1994 1994 + { 1995 1995 + if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE) 1996 1996 + return; 1997 1997 + 1998 1998 + rtw89_write32_clr(rtwdev, R_BE_FWS0IMR, B_BE_FS_GPIOA_INT_EN); 1999 1999 + rtw89_write32_set(rtwdev, R_BE_FWS0ISR, B_BE_FS_GPIOA_INT); 2001 2000 } 2002 2001 2003 2002 static int dbcc_bb_ctrl_be(struct rtw89_dev *rtwdev, bool bb1_en) ··· 3176 3157 .port_base = &rtw89_port_base_be, 3177 3158 .agg_len_ht = R_BE_AGG_LEN_HT_0, 3178 3159 .ps_status = R_BE_WMTX_POWER_BE_BIT_CTL, 3160 3160 + .mu_gid = &rtw89_mac_mu_gid_addr_be, 3179 3161 3180 3162 .muedca_ctrl = { 3181 3163 .addr = R_BE_MUEDCA_EN, ··· 3199 3179 .sys_init = sys_init_be, 3200 3180 .trx_init = trx_init_be, 3201 3181 .preload_init = preload_init_be, 3182 3182 + .clr_aon_intr = clr_aon_intr_be, 3202 3183 .err_imr_ctrl = err_imr_ctrl_be, 3203 3184 .mac_func_en = mac_func_en_be, 3204 3185 .hci_func_en = rtw89_mac_hci_func_en_be,

+13 -4

drivers/net/wireless/realtek/rtw89/pci.c

reviewed

··· 604 604 605 605 info->parse_rpp(rtwdev, rpp, &rpp_info); 606 606 607 607 - if (unlikely(rpp_info.txch == RTW89_TXCH_CH12)) { 608 608 - rtw89_warn(rtwdev, "should no fwcmd release report\n"); 607 607 + if (unlikely(rpp_info.txch >= RTW89_TXCH_NUM || 608 608 + info->tx_dma_ch_mask & BIT(rpp_info.txch))) { 609 609 + rtw89_warn(rtwdev, "should no release report on txch %d\n", 610 610 + rpp_info.txch); 609 611 return; 610 612 } 611 613 ··· 969 967 970 968 if (unlikely(isrs.halt_c2h_isrs & isr_def->isr_wdt_timeout)) 971 969 rtw89_ser_notify(rtwdev, MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT); 970 970 + 971 971 + if (unlikely(isrs.halt_c2h_isrs & isr_def->isr_sps_ocp)) 972 972 + rtw89_warn(rtwdev, "SPS OCP alarm 0x%x\n", isrs.halt_c2h_isrs); 972 973 973 974 if (unlikely(rtwpci->under_recovery)) 974 975 goto enable_intr; ··· 4008 4003 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 4009 4004 4010 4005 rtwpci->ind_intrs = B_BE_HS0_IND_INT_EN0; 4011 4011 - rtwpci->halt_c2h_intrs = B_BE_HALT_C2H_INT_EN | B_BE_WDT_TIMEOUT_INT_EN; 4006 4006 + rtwpci->halt_c2h_intrs = B_BE_HALT_C2H_INT_EN | B_BE_WDT_TIMEOUT_INT_EN | 4007 4007 + B_BE_SPSANA_OCP_INT_EN | B_BE_SPS_OCP_INT_EN; 4012 4008 rtwpci->intrs[0] = 0; 4013 4009 rtwpci->intrs[1] = 0; 4014 4010 } ··· 4019 4013 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 4020 4014 4021 4015 rtwpci->ind_intrs = B_BE_HS0_IND_INT_EN0; 4022 4022 - rtwpci->halt_c2h_intrs = B_BE_HALT_C2H_INT_EN | B_BE_WDT_TIMEOUT_INT_EN; 4016 4016 + rtwpci->halt_c2h_intrs = B_BE_HALT_C2H_INT_EN | B_BE_WDT_TIMEOUT_INT_EN | 4017 4017 + B_BE_SPSANA_OCP_INT_EN | B_BE_SPS_OCP_INT_EN; 4023 4018 rtwpci->intrs[0] = 0; 4024 4019 rtwpci->intrs[1] = B_BE_PCIE_RDU_CH1_IMR | 4025 4020 B_BE_PCIE_RDU_CH0_IMR | ··· 4610 4603 rtw89_write32_clr(rtwdev, R_AX_PCIE_PS_CTRL_V1, 4611 4604 B_AX_SEL_REQ_ENTR_L1); 4612 4605 } 4606 4606 + rtw89_pci_hci_ldo(rtwdev); 4613 4607 rtw89_pci_l2_hci_ldo(rtwdev); 4614 4608 4615 4609 rtw89_pci_basic_cfg(rtwdev, true); ··· 4662 4654 .isr_rdu = B_AX_RDU_INT, 4663 4655 .isr_halt_c2h = B_AX_HALT_C2H_INT_EN, 4664 4656 .isr_wdt_timeout = B_AX_WDT_TIMEOUT_INT_EN, 4657 4657 + .isr_sps_ocp = 0, 4665 4658 .isr_clear_rpq = {R_AX_PCIE_HISR00, B_AX_RPQDMA_INT | B_AX_RPQBD_FULL_INT}, 4666 4659 .isr_clear_rxq = {R_AX_PCIE_HISR00, B_AX_RXP1DMA_INT | B_AX_RXDMA_INT | 4667 4660 B_AX_RDU_INT},

+1

drivers/net/wireless/realtek/rtw89/pci.h

reviewed

··· 1331 1331 u32 isr_rdu; 1332 1332 u32 isr_halt_c2h; 1333 1333 u32 isr_wdt_timeout; 1334 1334 + u32 isr_sps_ocp; 1334 1335 struct rtw89_reg2_def isr_clear_rpq; 1335 1336 struct rtw89_reg2_def isr_clear_rxq; 1336 1337 };

+2

drivers/net/wireless/realtek/rtw89/pci_be.c

reviewed

··· 763 763 .isr_rdu = B_BE_RDU_CH1_INT_V1 | B_BE_RDU_CH0_INT_V1, 764 764 .isr_halt_c2h = B_BE_HALT_C2H_INT, 765 765 .isr_wdt_timeout = B_BE_WDT_TIMEOUT_INT, 766 766 + .isr_sps_ocp = 0, 766 767 .isr_clear_rpq = {R_BE_PCIE_DMA_ISR, B_BE_PCIE_RX_RPQ0_ISR_V1}, 767 768 .isr_clear_rxq = {R_BE_PCIE_DMA_ISR, B_BE_PCIE_RX_RX0P2_ISR_V1}, 768 769 }; ··· 773 772 .isr_rdu = B_BE_PCIE_RDU_CH1_INT | B_BE_PCIE_RDU_CH0_INT, 774 773 .isr_halt_c2h = B_BE_HALT_C2H_INT, 775 774 .isr_wdt_timeout = B_BE_WDT_TIMEOUT_INT, 775 775 + .isr_sps_ocp = B_BE_SPS_OCP_INT | B_BE_SPSANA_OCP_INT, 776 776 .isr_clear_rpq = {R_BE_PCIE_DMA_ISR, B_BE_PCIE_RX_RPQ0_ISR_V1}, 777 777 .isr_clear_rxq = {R_BE_PCIE_DMA_ISR, B_BE_PCIE_RX_RX0P2_ISR_V1}, 778 778 };

+346 -35

drivers/net/wireless/realtek/rtw89/phy.c

reviewed

··· 1036 1036 } 1037 1037 EXPORT_SYMBOL(rtw89_phy_read_rf_v2); 1038 1038 1039 1039 + static u32 rtw89_phy_read_full_rf_v3_a(struct rtw89_dev *rtwdev, 1040 1040 + enum rtw89_rf_path rf_path, u32 addr) 1041 1041 + { 1042 1042 + bool done; 1043 1043 + u32 busy; 1044 1044 + int ret; 1045 1045 + u32 val; 1046 1046 + 1047 1047 + ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, busy, !busy, 1048 1048 + 1, 30, false, 1049 1049 + rtwdev, R_SW_SI_DATA_BE4, 1050 1050 + B_SW_SI_W_BUSY_BE4 | B_SW_SI_R_BUSY_BE4); 1051 1051 + if (ret) { 1052 1052 + rtw89_warn(rtwdev, "poll HWSI is busy\n"); 1053 1053 + return INV_RF_DATA; 1054 1054 + } 1055 1055 + 1056 1056 + val = u32_encode_bits(rf_path, GENMASK(10, 8)) | 1057 1057 + u32_encode_bits(addr, GENMASK(7, 0)); 1058 1058 + 1059 1059 + rtw89_phy_write32_mask(rtwdev, R_SW_SI_READ_ADDR_BE4, B_SW_SI_READ_ADDR_BE4, val); 1060 1060 + 1061 1061 + ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 1062 1062 + 1, 30, false, 1063 1063 + rtwdev, R_SW_SI_DATA_BE4, B_SW_SI_READ_DATA_DONE_BE4); 1064 1064 + if (ret) { 1065 1065 + rtw89_warn(rtwdev, "read HWSI is busy\n"); 1066 1066 + return INV_RF_DATA; 1067 1067 + } 1068 1068 + 1069 1069 + val = rtw89_phy_read32_mask(rtwdev, R_SW_SI_DATA_BE4, B_SW_SI_READ_DATA_BE4); 1070 1070 + 1071 1071 + return val; 1072 1072 + } 1073 1073 + 1074 1074 + static u32 rtw89_phy_read_rf_v3_a(struct rtw89_dev *rtwdev, 1075 1075 + enum rtw89_rf_path rf_path, u32 addr, u32 mask) 1076 1076 + { 1077 1077 + u32 val; 1078 1078 + 1079 1079 + val = rtw89_phy_read_full_rf_v3_a(rtwdev, rf_path, addr); 1080 1080 + 1081 1081 + return (val & mask) >> __ffs(mask); 1082 1082 + } 1083 1083 + 1084 1084 + u32 rtw89_phy_read_rf_v3(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 1085 1085 + u32 addr, u32 mask) 1086 1086 + { 1087 1087 + bool ad_sel = u32_get_bits(addr, RTW89_RF_ADDR_ADSEL_MASK); 1088 1088 + 1089 1089 + if (rf_path >= rtwdev->chip->rf_path_num) { 1090 1090 + rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 1091 1091 + return INV_RF_DATA; 1092 1092 + } 1093 1093 + 1094 1094 + if (ad_sel) 1095 1095 + return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask); 1096 1096 + else 1097 1097 + return rtw89_phy_read_rf_v3_a(rtwdev, rf_path, addr, mask); 1098 1098 + } 1099 1099 + EXPORT_SYMBOL(rtw89_phy_read_rf_v3); 1100 1100 + 1039 1101 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 1040 1102 u32 addr, u32 mask, u32 data) 1041 1103 { ··· 1236 1174 return rtw89_phy_write_rf_a_v2(rtwdev, rf_path, addr, mask, data); 1237 1175 } 1238 1176 EXPORT_SYMBOL(rtw89_phy_write_rf_v2); 1177 1177 + 1178 1178 + static 1179 1179 + bool rtw89_phy_write_full_rf_v3_a(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 1180 1180 + u32 addr, u32 data) 1181 1181 + { 1182 1182 + u32 busy; 1183 1183 + u32 val; 1184 1184 + int ret; 1185 1185 + 1186 1186 + ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, busy, !busy, 1187 1187 + 1, 30, false, 1188 1188 + rtwdev, R_SW_SI_DATA_BE4, 1189 1189 + B_SW_SI_W_BUSY_BE4 | B_SW_SI_R_BUSY_BE4); 1190 1190 + if (ret) { 1191 1191 + rtw89_warn(rtwdev, "[%s] HWSI is busy\n", __func__); 1192 1192 + return false; 1193 1193 + } 1194 1194 + 1195 1195 + val = u32_encode_bits(rf_path, B_SW_SI_DATA_PATH_BE4) | 1196 1196 + u32_encode_bits(addr, B_SW_SI_DATA_ADR_BE4) | 1197 1197 + u32_encode_bits(data, B_SW_SI_DATA_DAT_BE4); 1198 1198 + 1199 1199 + rtw89_phy_write32(rtwdev, R_SW_SI_WDATA_BE4, val); 1200 1200 + 1201 1201 + return true; 1202 1202 + } 1203 1203 + 1204 1204 + static 1205 1205 + bool rtw89_phy_write_rf_a_v3(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 1206 1206 + u32 addr, u32 mask, u32 data) 1207 1207 + { 1208 1208 + u32 val; 1209 1209 + 1210 1210 + if (mask == RFREG_MASK) { 1211 1211 + val = data; 1212 1212 + } else { 1213 1213 + val = rtw89_phy_read_full_rf_v3_a(rtwdev, rf_path, addr); 1214 1214 + val &= ~mask; 1215 1215 + val |= (data << __ffs(mask)) & mask; 1216 1216 + } 1217 1217 + 1218 1218 + return rtw89_phy_write_full_rf_v3_a(rtwdev, rf_path, addr, val); 1219 1219 + } 1220 1220 + 1221 1221 + bool rtw89_phy_write_rf_v3(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 1222 1222 + u32 addr, u32 mask, u32 data) 1223 1223 + { 1224 1224 + bool ad_sel = u32_get_bits(addr, RTW89_RF_ADDR_ADSEL_MASK); 1225 1225 + 1226 1226 + if (rf_path >= rtwdev->chip->rf_path_num) { 1227 1227 + rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 1228 1228 + return INV_RF_DATA; 1229 1229 + } 1230 1230 + 1231 1231 + if (ad_sel) 1232 1232 + return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data); 1233 1233 + else 1234 1234 + return rtw89_phy_write_rf_a_v3(rtwdev, rf_path, addr, mask, data); 1235 1235 + } 1236 1236 + EXPORT_SYMBOL(rtw89_phy_write_rf_v3); 1239 1237 1240 1238 static bool rtw89_chip_rf_v1(struct rtw89_dev *rtwdev) 1241 1239 { ··· 3332 3210 [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt, 3333 3211 [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL, 3334 3212 [RTW89_PHY_C2H_FUNC_TXSTS] = NULL, 3213 3213 + [RTW89_PHY_C2H_FUNC_ACCELERATE_EN] = rtw89_fw_c2h_dummy_handler, 3335 3214 }; 3336 3215 3337 3216 static void 3338 3217 rtw89_phy_c2h_lowrt_rty(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3339 3218 { 3219 3219 + } 3220 3220 + 3221 3221 + static void 3222 3222 + rtw89_phy_c2h_lps_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3223 3223 + { 3224 3224 + const struct rtw89_c2h_lps_rpt *c2h_rpt = (const void *)c2h->data; 3225 3225 + const __le32 *data_a, *data_b; 3226 3226 + u16 len_info, cr_len, idx; 3227 3227 + const __le16 *addr; 3228 3228 + const u8 *info; 3229 3229 + 3230 3230 + /* elements size of BBCR/BBMCUCR/RFCR are 6/6/10 bytes respectively */ 3231 3231 + cr_len = c2h_rpt->cnt_bbcr * 6 + 3232 3232 + c2h_rpt->cnt_bbmcucr * 6 + 3233 3233 + c2h_rpt->cnt_rfcr * 10; 3234 3234 + len_info = len - (sizeof(*c2h_rpt) + cr_len); 3235 3235 + 3236 3236 + if (len < sizeof(*c2h_rpt) + cr_len || len_info % 4 != 0) { 3237 3237 + rtw89_debug(rtwdev, RTW89_DBG_PS, 3238 3238 + "Invalid LPS RPT len(%d) TYPE(%d) CRCNT: BB(%d) MCU(%d) RF(%d)\n", 3239 3239 + len, c2h_rpt->type, c2h_rpt->cnt_bbcr, 3240 3240 + c2h_rpt->cnt_bbmcucr, c2h_rpt->cnt_rfcr); 3241 3241 + return; 3242 3242 + } 3243 3243 + 3244 3244 + rtw89_debug(rtwdev, RTW89_DBG_PS, 3245 3245 + "LPS RPT TYPE(%d), CRCNT: BB(%d) MCU(%d) RF(%d)\n", 3246 3246 + c2h_rpt->type, c2h_rpt->cnt_bbcr, 3247 3247 + c2h_rpt->cnt_bbmcucr, c2h_rpt->cnt_rfcr); 3248 3248 + 3249 3249 + info = &c2h_rpt->data[0]; 3250 3250 + for (idx = 0; idx < len_info; idx += 4, info += 4) 3251 3251 + rtw89_debug(rtwdev, RTW89_DBG_PS, 3252 3252 + "BB LPS INFO (%02d) - 0x%02x,0x%02x,0x%02x,0x%02x\n", 3253 3253 + idx, info[3], info[2], info[1], info[0]); 3254 3254 + 3255 3255 + addr = (const void *)(info); 3256 3256 + data_a = (const void *)(addr + c2h_rpt->cnt_bbcr); 3257 3257 + for (idx = 0; idx < c2h_rpt->cnt_bbcr; idx++, addr++, data_a++) 3258 3258 + rtw89_debug(rtwdev, RTW89_DBG_PS, 3259 3259 + "LPS BB CR - 0x%04x=0x%08x\n", 3260 3260 + le16_to_cpu(*addr), le32_to_cpu(*data_a)); 3261 3261 + 3262 3262 + addr = (const void *)data_a; 3263 3263 + data_a = (const void *)(addr + c2h_rpt->cnt_bbmcucr); 3264 3264 + for (idx = 0; idx < c2h_rpt->cnt_bbmcucr; idx++, addr++, data_a++) 3265 3265 + rtw89_debug(rtwdev, RTW89_DBG_PS, 3266 3266 + "LPS BBMCU - 0x%04x=0x%08x\n", 3267 3267 + le16_to_cpu(*addr), le32_to_cpu(*data_a)); 3268 3268 + 3269 3269 + addr = (const void *)data_a; 3270 3270 + data_a = (const void *)(addr + c2h_rpt->cnt_rfcr); 3271 3271 + data_b = (const void *)(data_a + c2h_rpt->cnt_rfcr); 3272 3272 + for (idx = 0; idx < c2h_rpt->cnt_rfcr; idx++, addr++, data_a++, data_b++) 3273 3273 + rtw89_debug(rtwdev, RTW89_DBG_PS, 3274 3274 + "LPS RFCR - 0x%04x=0x%05x,0x%05x\n", 3275 3275 + le16_to_cpu(*addr), le32_to_cpu(*data_a), 3276 3276 + le32_to_cpu(*data_b)); 3340 3277 } 3341 3278 3342 3279 static void ··· 3419 3238 [RTW89_PHY_C2H_DM_FUNC_SIGB] = NULL, 3420 3239 [RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY] = rtw89_phy_c2h_lowrt_rty, 3421 3240 [RTW89_PHY_C2H_DM_FUNC_MCC_DIG] = NULL, 3241 3241 + [RTW89_PHY_C2H_DM_FUNC_LPS] = rtw89_phy_c2h_lps_rpt, 3242 3242 + [RTW89_PHY_C2H_DM_FUNC_ENV_MNTR] = rtw89_fw_c2h_dummy_handler, 3422 3243 [RTW89_PHY_C2H_DM_FUNC_FW_SCAN] = rtw89_phy_c2h_fw_scan_rpt, 3423 3244 }; 3424 3245 ··· 3458 3275 { 3459 3276 struct rtw89_c2h_rf_txgapk_rpt_log *txgapk; 3460 3277 struct rtw89_c2h_rf_rxdck_rpt_log *rxdck; 3278 3278 + struct rtw89_c2h_rf_txiqk_rpt_log *txiqk; 3279 3279 + struct rtw89_c2h_rf_cim3k_rpt_log *cim3k; 3461 3280 struct rtw89_c2h_rf_dack_rpt_log *dack; 3462 3281 struct rtw89_c2h_rf_tssi_rpt_log *tssi; 3463 3282 struct rtw89_c2h_rf_dpk_rpt_log *dpk; ··· 3514 3329 i, iqk->iqk_ch[i]); 3515 3330 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_bw[%d] = %x\n", 3516 3331 i, iqk->iqk_bw[i]); 3332 3332 + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->rf_0x18[%d] = %x\n", 3333 3333 + i, le32_to_cpu(iqk->rf_0x18[i])); 3517 3334 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->lok_idac[%d] = %x\n", 3518 3335 i, le32_to_cpu(iqk->lok_idac[i])); 3519 3336 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->lok_vbuf[%d] = %x\n", ··· 3524 3337 i, iqk->iqk_tx_fail[i]); 3525 3338 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_rx_fail[%d] = %x\n", 3526 3339 i, iqk->iqk_rx_fail[i]); 3527 3527 - for (j = 0; j < 4; j++) 3340 3340 + for (j = 0; j < 6; j++) 3528 3341 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3529 3342 "[IQK] iqk->rftxgain[%d][%d] = %x\n", 3530 3343 i, j, le32_to_cpu(iqk->rftxgain[i][j])); 3531 3531 - for (j = 0; j < 4; j++) 3344 3344 + for (j = 0; j < 6; j++) 3532 3345 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3533 3346 "[IQK] iqk->tx_xym[%d][%d] = %x\n", 3534 3347 i, j, le32_to_cpu(iqk->tx_xym[i][j])); 3535 3535 - for (j = 0; j < 4; j++) 3348 3348 + for (j = 0; j < 6; j++) 3536 3349 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3537 3350 "[IQK] iqk->rfrxgain[%d][%d] = %x\n", 3538 3351 i, j, le32_to_cpu(iqk->rfrxgain[i][j])); 3539 3539 - for (j = 0; j < 4; j++) 3352 3352 + for (j = 0; j < 6; j++) 3540 3353 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3541 3354 "[IQK] iqk->rx_xym[%d][%d] = %x\n", 3542 3355 i, j, le32_to_cpu(iqk->rx_xym[i][j])); 3356 3356 + 3357 3357 + if (!iqk->iqk_xym_en) 3358 3358 + continue; 3359 3359 + 3360 3360 + for (j = 0; j < 32; j++) 3361 3361 + rtw89_debug(rtwdev, RTW89_DBG_RFK, 3362 3362 + "[IQK] iqk->rx_wb_xym[%d][%d] = %x\n", 3363 3363 + i, j, iqk->rx_wb_xym[i][j]); 3543 3364 } 3544 3365 return; 3545 3366 case RTW89_PHY_C2H_RFK_LOG_FUNC_DPK: ··· 3703 3508 le32_to_cpu(txgapk->chk_cnt)); 3704 3509 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt ver = 0x%x\n", 3705 3510 txgapk->ver); 3706 3706 - rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt rsv1 = %d\n", 3707 3707 - txgapk->rsv1); 3511 3511 + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt d_bnd_ok = %d\n", 3512 3512 + txgapk->d_bnd_ok); 3513 3513 + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt stage[0] = 0x%x\n", 3514 3514 + le32_to_cpu(txgapk->stage[0])); 3515 3515 + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt stage[1] = 0x%x\n", 3516 3516 + le32_to_cpu(txgapk->stage[1])); 3517 3517 + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]failcode[0] = 0x%x\n", 3518 3518 + le16_to_cpu(txgapk->failcode[0])); 3519 3519 + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]failcode[1] = 0x%x\n", 3520 3520 + le16_to_cpu(txgapk->failcode[1])); 3708 3521 3709 3522 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt track_d[0] = %*ph\n", 3710 3523 (int)sizeof(txgapk->track_d[0]), txgapk->track_d[0]); ··· 3728 3525 goto out; 3729 3526 3730 3527 rtw89_phy_c2h_rfk_tas_pwr(rtwdev, content); 3731 3731 - 3528 3528 + return; 3529 3529 + case RTW89_PHY_C2H_RFK_LOG_FUNC_TXIQK: 3530 3530 + if (len != sizeof(*txiqk)) 3531 3531 + goto out; 3532 3532 + return; 3533 3533 + case RTW89_PHY_C2H_RFK_LOG_FUNC_CIM3K: 3534 3534 + if (len != sizeof(*cim3k)) 3535 3535 + goto out; 3732 3536 return; 3733 3537 default: 3734 3538 break; ··· 3872 3662 RTW89_PHY_C2H_RFK_LOG_FUNC_TAS_PWR, "TAS"); 3873 3663 } 3874 3664 3665 3665 + static void 3666 3666 + rtw89_phy_c2h_rfk_log_txiqk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3667 3667 + { 3668 3668 + rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 3669 3669 + RTW89_PHY_C2H_RFK_LOG_FUNC_TXIQK, "TXIQK"); 3670 3670 + } 3671 3671 + 3672 3672 + static void 3673 3673 + rtw89_phy_c2h_rfk_log_cim3k(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3674 3674 + { 3675 3675 + rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 3676 3676 + RTW89_PHY_C2H_RFK_LOG_FUNC_CIM3K, "CIM3K"); 3677 3677 + } 3678 3678 + 3875 3679 static 3876 3680 void (* const rtw89_phy_c2h_rfk_log_handler[])(struct rtw89_dev *rtwdev, 3877 3681 struct sk_buff *c2h, u32 len) = { ··· 3896 3672 [RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI] = rtw89_phy_c2h_rfk_log_tssi, 3897 3673 [RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK] = rtw89_phy_c2h_rfk_log_txgapk, 3898 3674 [RTW89_PHY_C2H_RFK_LOG_FUNC_TAS_PWR] = rtw89_phy_c2h_rfk_log_tas_pwr, 3675 3675 + [RTW89_PHY_C2H_RFK_LOG_FUNC_TXIQK] = rtw89_phy_c2h_rfk_log_txiqk, 3676 3676 + [RTW89_PHY_C2H_RFK_LOG_FUNC_CIM3K] = rtw89_phy_c2h_rfk_log_cim3k, 3899 3677 }; 3900 3678 3901 3679 static ··· 3986 3760 case RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK: 3987 3761 case RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI: 3988 3762 case RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK: 3763 3763 + case RTW89_PHY_C2H_RFK_LOG_FUNC_TXIQK: 3989 3764 return true; 3990 3765 default: 3991 3766 return false; ··· 4011 3784 4012 3785 switch (class) { 4013 3786 case RTW89_PHY_C2H_CLASS_RA: 4014 4014 - if (func < RTW89_PHY_C2H_FUNC_RA_MAX) 3787 3787 + if (func < ARRAY_SIZE(rtw89_phy_c2h_ra_handler)) 4015 3788 handler = rtw89_phy_c2h_ra_handler[func]; 4016 3789 break; 4017 3790 case RTW89_PHY_C2H_RFK_LOG: ··· 4164 3937 return rtw89_phy_rfk_report_wait(rtwdev, "RX_DCK", ms); 4165 3938 } 4166 3939 EXPORT_SYMBOL(rtw89_phy_rfk_rxdck_and_wait); 3940 3940 + 3941 3941 + int rtw89_phy_rfk_txiqk_and_wait(struct rtw89_dev *rtwdev, 3942 3942 + enum rtw89_phy_idx phy_idx, 3943 3943 + const struct rtw89_chan *chan, 3944 3944 + unsigned int ms) 3945 3945 + { 3946 3946 + int ret; 3947 3947 + 3948 3948 + rtw89_phy_rfk_report_prep(rtwdev); 3949 3949 + 3950 3950 + ret = rtw89_fw_h2c_rf_txiqk(rtwdev, phy_idx, chan); 3951 3951 + if (ret) 3952 3952 + return ret; 3953 3953 + 3954 3954 + return rtw89_phy_rfk_report_wait(rtwdev, "TX_IQK", ms); 3955 3955 + } 3956 3956 + EXPORT_SYMBOL(rtw89_phy_rfk_txiqk_and_wait); 3957 3957 + 3958 3958 + int rtw89_phy_rfk_cim3k_and_wait(struct rtw89_dev *rtwdev, 3959 3959 + enum rtw89_phy_idx phy_idx, 3960 3960 + const struct rtw89_chan *chan, 3961 3961 + unsigned int ms) 3962 3962 + { 3963 3963 + int ret; 3964 3964 + 3965 3965 + rtw89_phy_rfk_report_prep(rtwdev); 3966 3966 + 3967 3967 + ret = rtw89_fw_h2c_rf_cim3k(rtwdev, phy_idx, chan); 3968 3968 + if (ret) 3969 3969 + return ret; 3970 3970 + 3971 3971 + return rtw89_phy_rfk_report_wait(rtwdev, "CIM3k", ms); 3972 3972 + } 3973 3973 + EXPORT_SYMBOL(rtw89_phy_rfk_cim3k_and_wait); 4167 3974 4168 3975 static u32 phy_tssi_get_cck_group(u8 ch) 4169 3976 { ··· 4646 4385 const struct rtw89_chan *chan, 4647 4386 struct rtw89_h2c_rf_tssi *h2c) 4648 4387 { 4388 4388 + const struct rtw89_chip_info *chip = rtwdev->chip; 4649 4389 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; 4650 4390 u8 ch = chan->channel; 4651 4391 s8 trim_de; ··· 4670 4408 cck_de = tssi_info->tssi_cck[i][gidx]; 4671 4409 val = u32_get_bits(cck_de + trim_de, 0xff); 4672 4410 4673 4673 - h2c->curr_tssi_cck_de[i] = 0x0; 4674 4674 - h2c->curr_tssi_cck_de_20m[i] = val; 4675 4675 - h2c->curr_tssi_cck_de_40m[i] = val; 4411 4411 + if (chip->chip_id == RTL8922A) { 4412 4412 + h2c->curr_tssi_cck_de[i] = 0x0; 4413 4413 + h2c->curr_tssi_cck_de_20m[i] = val; 4414 4414 + h2c->curr_tssi_cck_de_40m[i] = val; 4415 4415 + } else { 4416 4416 + h2c->curr_tssi_cck_de[i] = val; 4417 4417 + } 4418 4418 + 4676 4419 h2c->curr_tssi_efuse_cck_de[i] = cck_de; 4677 4420 4678 4421 rtw89_debug(rtwdev, RTW89_DBG_TSSI, ··· 4686 4419 ofdm_de = phy_tssi_get_ofdm_de(rtwdev, phy, chan, i); 4687 4420 val = u32_get_bits(ofdm_de + trim_de, 0xff); 4688 4421 4689 4689 - h2c->curr_tssi_ofdm_de[i] = 0x0; 4690 4690 - h2c->curr_tssi_ofdm_de_20m[i] = val; 4691 4691 - h2c->curr_tssi_ofdm_de_40m[i] = val; 4692 4692 - h2c->curr_tssi_ofdm_de_80m[i] = val; 4693 4693 - h2c->curr_tssi_ofdm_de_160m[i] = val; 4694 4694 - h2c->curr_tssi_ofdm_de_320m[i] = val; 4422 4422 + if (chip->chip_id == RTL8922A) { 4423 4423 + h2c->curr_tssi_ofdm_de[i] = 0x0; 4424 4424 + h2c->curr_tssi_ofdm_de_20m[i] = val; 4425 4425 + h2c->curr_tssi_ofdm_de_40m[i] = val; 4426 4426 + h2c->curr_tssi_ofdm_de_80m[i] = val; 4427 4427 + h2c->curr_tssi_ofdm_de_160m[i] = val; 4428 4428 + h2c->curr_tssi_ofdm_de_320m[i] = val; 4429 4429 + } else { 4430 4430 + h2c->curr_tssi_ofdm_de[i] = val; 4431 4431 + } 4432 4432 + 4695 4433 h2c->curr_tssi_efuse_ofdm_de[i] = ofdm_de; 4696 4434 4697 4435 rtw89_debug(rtwdev, RTW89_DBG_TSSI, ··· 4711 4439 { 4712 4440 struct rtw89_fw_txpwr_track_cfg *trk = rtwdev->fw.elm_info.txpwr_trk; 4713 4441 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; 4442 4442 + const struct rtw89_chip_info *chip = rtwdev->chip; 4714 4443 const s8 *thm_up[RF_PATH_B + 1] = {}; 4715 4444 const s8 *thm_down[RF_PATH_B + 1] = {}; 4716 4445 u8 subband = chan->subband_type; 4717 4717 - s8 thm_ofst[128] = {0}; 4446 4446 + s8 thm_ofst[128] = {}; 4447 4447 + int multiplier; 4718 4448 u8 thermal; 4719 4449 u8 path; 4720 4450 u8 i, j; ··· 4780 4506 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4781 4507 "[TSSI] tmeter tbl on subband: %u\n", subband); 4782 4508 4509 4509 + if (chip->chip_id == RTL8922A) 4510 4510 + multiplier = 1; 4511 4511 + else 4512 4512 + multiplier = -1; 4513 4513 + 4783 4514 for (path = RF_PATH_A; path <= RF_PATH_B; path++) { 4784 4515 thermal = tssi_info->thermal[path]; 4785 4516 rtw89_debug(rtwdev, RTW89_DBG_TSSI, ··· 4799 4520 h2c->pg_thermal[path] = thermal; 4800 4521 4801 4522 i = 0; 4802 4802 - for (j = 0; j < 64; j++) 4523 4523 + for (j = 0; j < 64; j++) { 4803 4524 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ? 4804 4525 thm_up[path][i++] : 4805 4526 thm_up[path][DELTA_SWINGIDX_SIZE - 1]; 4527 4527 + thm_ofst[j] *= multiplier; 4528 4528 + } 4806 4529 4807 4530 i = 1; 4808 4808 - for (j = 127; j >= 64; j--) 4531 4531 + for (j = 127; j >= 64; j--) { 4809 4532 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ? 4810 4533 -thm_down[path][i++] : 4811 4534 -thm_down[path][DELTA_SWINGIDX_SIZE - 1]; 4535 4535 + thm_ofst[j] *= multiplier; 4536 4536 + } 4812 4537 4813 4538 for (i = 0; i < 128; i += 4) { 4814 4539 h2c->ftable[path][i + 0] = thm_ofst[i + 3]; ··· 6301 6018 env->ifs_clm_his[1] = 6302 6019 rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr, 6303 6020 ccx->ifs_t2_his_mask, bb->phy_idx); 6021 6021 + 6304 6022 env->ifs_clm_his[2] = 6305 6305 - rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr, 6023 6023 + rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr2, 6306 6024 ccx->ifs_t3_his_mask, bb->phy_idx); 6307 6025 env->ifs_clm_his[3] = 6308 6308 - rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr, 6026 6026 + rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr2, 6309 6027 ccx->ifs_t4_his_mask, bb->phy_idx); 6310 6028 6311 6029 env->ifs_clm_avg[0] = ··· 6569 6285 return true; 6570 6286 } 6571 6287 6572 6572 - static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page) 6288 6288 + static u32 rtw89_phy_get_ie_bitmap_addr(struct rtw89_dev *rtwdev, 6289 6289 + enum rtw89_phy_status_bitmap ie_page) 6573 6290 { 6291 6291 + const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 6574 6292 static const u8 ie_page_shift = 2; 6575 6293 6576 6294 if (ie_page == RTW89_EHT_PKT) 6577 6577 - return R_PHY_STS_BITMAP_EHT; 6295 6295 + return phy->physt_bmp_eht; 6578 6296 6579 6579 - return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift); 6297 6297 + return phy->physt_bmp_start + (ie_page << ie_page_shift); 6580 6298 } 6581 6299 6582 6300 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev, ··· 6590 6304 if (!rtw89_physts_ie_page_valid(rtwdev, &ie_page)) 6591 6305 return 0; 6592 6306 6593 6593 - addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 6307 6307 + addr = rtw89_phy_get_ie_bitmap_addr(rtwdev, ie_page); 6594 6308 6595 6309 return rtw89_phy_read32_idx(rtwdev, addr, MASKDWORD, phy_idx); 6596 6310 } ··· 6608 6322 if (chip->chip_id == RTL8852A) 6609 6323 val &= B_PHY_STS_BITMAP_MSK_52A; 6610 6324 6611 6611 - addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 6325 6325 + addr = rtw89_phy_get_ie_bitmap_addr(rtwdev, ie_page); 6612 6326 rtw89_phy_write32_idx(rtwdev, addr, MASKDWORD, val, phy_idx); 6613 6327 } 6614 6328 ··· 6632 6346 } 6633 6347 } 6634 6348 6349 6349 + static void rtw89_physts_enable_hdr_2(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 6350 6350 + { 6351 6351 + const struct rtw89_chip_info *chip = rtwdev->chip; 6352 6352 + 6353 6353 + if (chip->chip_gen == RTW89_CHIP_AX || chip->chip_id == RTL8922A) 6354 6354 + return; 6355 6355 + 6356 6356 + rtw89_phy_write32_idx_set(rtwdev, R_STS_HDR2_PARSING_BE4, 6357 6357 + B_STS_HDR2_PARSING_BE4, phy_idx); 6358 6358 + } 6359 6359 + 6635 6360 static void __rtw89_physts_parsing_init(struct rtw89_dev *rtwdev, 6636 6361 enum rtw89_phy_idx phy_idx) 6637 6362 { ··· 6651 6354 u8 i; 6652 6355 6653 6356 rtw89_physts_enable_fail_report(rtwdev, false, phy_idx); 6357 6357 + 6358 6358 + /* enable hdr_2 for 8922D (PHYSTS_BE_GEN2 above) */ 6359 6359 + rtw89_physts_enable_hdr_2(rtwdev, phy_idx); 6654 6360 6655 6361 for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) { 6656 6362 if (i == RTW89_RSVD_9 || ··· 7019 6719 bool enable) 7020 6720 { 7021 6721 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 6722 6722 + 6723 6723 + if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 6724 6724 + return; 7022 6725 7023 6726 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_p20_pagcugc_en.addr, 7024 6727 dig_regs->p0_p20_pagcugc_en.mask, enable, bb->phy_idx); ··· 8082 7779 bool flag_fb, flag_p20, flag_s20, flag_s40, flag_s80; 8083 7780 s8 pwdb_fb, pwdb_p20, pwdb_s20, pwdb_s40, pwdb_s80; 8084 7781 u8 path, per20_bitmap = 0; 7782 7782 + u8 pwdb_sel = 5; 8085 7783 u8 pwdb[8]; 8086 7784 u32 tmp; 8087 7785 ··· 8094 7790 else 8095 7791 edcca_p_regs = &edcca_regs->p[RTW89_PHY_0]; 8096 7792 8097 8097 - if (rtwdev->chip->chip_id == RTL8922A) 8098 8098 - rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be, 8099 8099 - edcca_regs->rpt_sel_be_mask, 0); 8100 8100 - 8101 7793 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel, 8102 7794 edcca_p_regs->rpt_sel_mask, 0); 7795 7795 + if (rtwdev->chip->chip_id == RTL8922A || rtwdev->chip->chip_id == RTL8922D) { 7796 7796 + rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be, 7797 7797 + edcca_regs->rpt_sel_be_mask, 0); 7798 7798 + per20_bitmap = rtw89_phy_read32_mask(rtwdev, edcca_p_regs->rpt_a, 7799 7799 + MASKBYTE0); 7800 7800 + } 8103 7801 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b); 8104 7802 path = u32_get_bits(tmp, B_EDCCA_RPT_B_PATH_MASK); 8105 7803 flag_s80 = u32_get_bits(tmp, B_EDCCA_RPT_B_S80); ··· 8113 7807 pwdb_p20 = u32_get_bits(tmp, MASKBYTE2); 8114 7808 pwdb_fb = u32_get_bits(tmp, MASKBYTE3); 8115 7809 7810 7810 + if (rtwdev->chip->chip_id == RTL8922D) 7811 7811 + pwdb_sel = 2; 7812 7812 + 8116 7813 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel, 8117 8117 - edcca_p_regs->rpt_sel_mask, 5); 7814 7814 + edcca_p_regs->rpt_sel_mask, pwdb_sel); 8118 7815 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b); 8119 7816 pwdb_s80 = u32_get_bits(tmp, MASKBYTE1); 8120 7817 pwdb_s40 = u32_get_bits(tmp, MASKBYTE2); 8121 7818 8122 8122 - if (rtwdev->chip->chip_id == RTL8922A) { 7819 7819 + if (rtwdev->chip->chip_id == RTL8922A || rtwdev->chip->chip_id == RTL8922D) { 8123 7820 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be, 8124 7821 edcca_regs->rpt_sel_be_mask, 4); 8125 7822 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b); ··· 8130 7821 pwdb[1] = u32_get_bits(tmp, MASKBYTE2); 8131 7822 pwdb[2] = u32_get_bits(tmp, MASKBYTE1); 8132 7823 pwdb[3] = u32_get_bits(tmp, MASKBYTE0); 8133 8133 - per20_bitmap = rtw89_phy_read32_mask(rtwdev, edcca_p_regs->rpt_a, 8134 8134 - MASKBYTE0); 8135 7824 8136 7825 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be, 8137 7826 edcca_regs->rpt_sel_be_mask, 5); ··· 8351 8044 .ifs_clm_ofdm_fa_mask = B_IFS_CLM_OFDM_FA_MSK, 8352 8045 .ifs_clm_cck_fa_mask = B_IFS_CLM_CCK_FA_MSK, 8353 8046 .ifs_his_addr = R_IFS_HIS, 8047 8047 + .ifs_his_addr2 = R_IFS_HIS, 8354 8048 .ifs_t4_his_mask = B_IFS_T4_HIS_MSK, 8355 8049 .ifs_t3_his_mask = B_IFS_T3_HIS_MSK, 8356 8050 .ifs_t2_his_mask = B_IFS_T2_HIS_MSK, ··· 8397 8089 8398 8090 const struct rtw89_phy_gen_def rtw89_phy_gen_ax = { 8399 8091 .cr_base = 0x10000, 8092 8092 + .physt_bmp_start = R_PHY_STS_BITMAP_ADDR_START, 8093 8093 + .physt_bmp_eht = 0xfc, 8400 8094 .ccx = &rtw89_ccx_regs_ax, 8401 8095 .physts = &rtw89_physts_regs_ax, 8402 8096 .cfo = &rtw89_cfo_regs_ax, 8097 8097 + .bb_wrap = NULL, 8403 8098 .phy0_phy1_offset = rtw89_phy0_phy1_offset_ax, 8404 8099 .config_bb_gain = rtw89_phy_config_bb_gain_ax, 8405 8100 .preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_ax,

+35 -1

drivers/net/wireless/realtek/rtw89/phy.h

reviewed

··· 139 139 RTW89_PHY_C2H_FUNC_STS_RPT, 140 140 RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT, 141 141 RTW89_PHY_C2H_FUNC_TXSTS, 142 142 - RTW89_PHY_C2H_FUNC_RA_MAX, 142 142 + RTW89_PHY_C2H_FUNC_ACCELERATE_EN = 0x7, 143 143 + 144 144 + RTW89_PHY_C2H_FUNC_RA_NUM, 143 145 }; 144 146 145 147 enum rtw89_phy_c2h_rfk_log_func { ··· 152 150 RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI = 4, 153 151 RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK = 5, 154 152 RTW89_PHY_C2H_RFK_LOG_FUNC_TAS_PWR = 9, 153 153 + RTW89_PHY_C2H_RFK_LOG_FUNC_TXIQK = 0xc, 154 154 + RTW89_PHY_C2H_RFK_LOG_FUNC_CIM3K = 0xe, 155 155 156 156 RTW89_PHY_C2H_RFK_LOG_FUNC_NUM, 157 157 }; ··· 169 165 RTW89_PHY_C2H_DM_FUNC_SIGB, 170 166 RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY, 171 167 RTW89_PHY_C2H_DM_FUNC_MCC_DIG, 168 168 + RTW89_PHY_C2H_DM_FUNC_LPS = 0x9, 169 169 + RTW89_PHY_C2H_DM_FUNC_ENV_MNTR = 0xa, 172 170 RTW89_PHY_C2H_DM_FUNC_FW_SCAN = 0xc, 173 171 RTW89_PHY_C2H_DM_FUNC_NUM, 174 172 }; ··· 422 416 u32 ifs_clm_ofdm_fa_mask; 423 417 u32 ifs_clm_cck_fa_mask; 424 418 u32 ifs_his_addr; 419 419 + u32 ifs_his_addr2; 425 420 u32 ifs_t4_his_mask; 426 421 u32 ifs_t3_his_mask; 427 422 u32 ifs_t2_his_mask; ··· 464 457 u32 weighting_mask; 465 458 u32 comp_seg0; 466 459 u32 valid_0_mask; 460 460 + }; 461 461 + 462 462 + struct rtw89_bb_wrap_regs { 463 463 + u32 pwr_macid_lmt; 464 464 + u32 pwr_macid_path; 467 465 }; 468 466 469 467 enum rtw89_bandwidth_section_num_ax { ··· 543 531 544 532 struct rtw89_phy_gen_def { 545 533 u32 cr_base; 534 534 + u32 physt_bmp_start; 535 535 + u32 physt_bmp_eht; 546 536 const struct rtw89_ccx_regs *ccx; 547 537 const struct rtw89_physts_regs *physts; 548 538 const struct rtw89_cfo_regs *cfo; 539 539 + const struct rtw89_bb_wrap_regs *bb_wrap; 549 540 u32 (*phy0_phy1_offset)(struct rtw89_dev *rtwdev, u32 addr); 550 541 void (*config_bb_gain)(struct rtw89_dev *rtwdev, 551 542 const struct rtw89_reg2_def *reg, ··· 574 559 575 560 extern const struct rtw89_phy_gen_def rtw89_phy_gen_ax; 576 561 extern const struct rtw89_phy_gen_def rtw89_phy_gen_be; 562 562 + extern const struct rtw89_phy_gen_def rtw89_phy_gen_be_v1; 577 563 578 564 static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev, 579 565 u32 addr, u8 data) ··· 839 823 u32 addr, u32 mask); 840 824 u32 rtw89_phy_read_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 841 825 u32 addr, u32 mask); 826 826 + u32 rtw89_phy_read_rf_v3(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 827 827 + u32 addr, u32 mask); 842 828 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 843 829 u32 addr, u32 mask, u32 data); 844 830 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 845 831 u32 addr, u32 mask, u32 data); 846 832 bool rtw89_phy_write_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 833 833 + u32 addr, u32 mask, u32 data); 834 834 + bool rtw89_phy_write_rf_v3(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 847 835 u32 addr, u32 mask, u32 data); 848 836 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev); 849 837 void rtw89_phy_init_bb_afe(struct rtw89_dev *rtwdev); ··· 898 878 if (phy->bb_wrap_init) 899 879 phy->bb_wrap_init(rtwdev); 900 880 } 881 881 + 882 882 + void rtw89_phy_bb_wrap_set_rfsi_ct_opt(struct rtw89_dev *rtwdev, 883 883 + enum rtw89_phy_idx phy_idx); 884 884 + void rtw89_phy_bb_wrap_set_rfsi_bandedge_ch(struct rtw89_dev *rtwdev, 885 885 + const struct rtw89_chan *chan, 886 886 + enum rtw89_phy_idx phy_idx); 901 887 902 888 static inline void rtw89_phy_ch_info_init(struct rtw89_dev *rtwdev) 903 889 { ··· 1036 1010 enum rtw89_phy_idx phy_idx, 1037 1011 const struct rtw89_chan *chan, 1038 1012 bool is_chl_k, unsigned int ms); 1013 1013 + int rtw89_phy_rfk_txiqk_and_wait(struct rtw89_dev *rtwdev, 1014 1014 + enum rtw89_phy_idx phy_idx, 1015 1015 + const struct rtw89_chan *chan, 1016 1016 + unsigned int ms); 1017 1017 + int rtw89_phy_rfk_cim3k_and_wait(struct rtw89_dev *rtwdev, 1018 1018 + enum rtw89_phy_idx phy_idx, 1019 1019 + const struct rtw89_chan *chan, 1020 1020 + unsigned int ms); 1039 1021 void rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev *rtwdev, 1040 1022 enum rtw89_phy_idx phy, 1041 1023 const struct rtw89_chan *chan,

+543 -20

drivers/net/wireless/realtek/rtw89/phy_be.c

reviewed

··· 2 2 /* Copyright(c) 2023 Realtek Corporation 3 3 */ 4 4 5 5 + #include "chan.h" 5 6 #include "debug.h" 6 7 #include "mac.h" 7 8 #include "phy.h" ··· 45 44 .ifs_clm_ofdm_fa_mask = B_IFS_CLM_OFDM_FA_MSK, 46 45 .ifs_clm_cck_fa_mask = B_IFS_CLM_CCK_FA_MSK, 47 46 .ifs_his_addr = R_IFS_HIS_V1, 47 47 + .ifs_his_addr2 = R_IFS_HIS_V1, 48 48 .ifs_t4_his_mask = B_IFS_T4_HIS_MSK, 49 49 .ifs_t3_his_mask = B_IFS_T3_HIS_MSK, 50 50 .ifs_t2_his_mask = B_IFS_T2_HIS_MSK, ··· 76 74 .nhm_pwr_method_msk = B_NHM_PWDB_METHOD_MSK, 77 75 }; 78 76 77 77 + static const struct rtw89_ccx_regs rtw89_ccx_regs_be_v1 = { 78 78 + .setting_addr = R_CCX_BE4, 79 79 + .edcca_opt_mask = B_CCX_EDCCA_OPT_MSK_V1, 80 80 + .measurement_trig_mask = B_MEASUREMENT_TRIG_MSK, 81 81 + .trig_opt_mask = B_CCX_TRIG_OPT_MSK, 82 82 + .en_mask = B_CCX_EN_MSK, 83 83 + .ifs_cnt_addr = R_IFS_COUNTER_BE4, 84 84 + .ifs_clm_period_mask = B_IFS_CLM_PERIOD_MSK, 85 85 + .ifs_clm_cnt_unit_mask = B_IFS_CLM_COUNTER_UNIT_MSK, 86 86 + .ifs_clm_cnt_clear_mask = B_IFS_COUNTER_CLR_MSK, 87 87 + .ifs_collect_en_mask = B_IFS_COLLECT_EN, 88 88 + .ifs_t1_addr = R_IFS_T1_BE4, 89 89 + .ifs_t1_th_h_mask = B_IFS_T1_TH_HIGH_MSK, 90 90 + .ifs_t1_en_mask = B_IFS_T1_EN_MSK, 91 91 + .ifs_t1_th_l_mask = B_IFS_T1_TH_LOW_MSK, 92 92 + .ifs_t2_addr = R_IFS_T2_BE4, 93 93 + .ifs_t2_th_h_mask = B_IFS_T2_TH_HIGH_MSK, 94 94 + .ifs_t2_en_mask = B_IFS_T2_EN_MSK, 95 95 + .ifs_t2_th_l_mask = B_IFS_T2_TH_LOW_MSK, 96 96 + .ifs_t3_addr = R_IFS_T3_BE4, 97 97 + .ifs_t3_th_h_mask = B_IFS_T3_TH_HIGH_MSK, 98 98 + .ifs_t3_en_mask = B_IFS_T3_EN_MSK, 99 99 + .ifs_t3_th_l_mask = B_IFS_T3_TH_LOW_MSK, 100 100 + .ifs_t4_addr = R_IFS_T4_BE4, 101 101 + .ifs_t4_th_h_mask = B_IFS_T4_TH_HIGH_MSK, 102 102 + .ifs_t4_en_mask = B_IFS_T4_EN_MSK, 103 103 + .ifs_t4_th_l_mask = B_IFS_T4_TH_LOW_MSK, 104 104 + .ifs_clm_tx_cnt_addr = R_IFS_CLM_TX_CNT_BE4, 105 105 + .ifs_clm_edcca_excl_cca_fa_mask = B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK, 106 106 + .ifs_clm_tx_cnt_msk = B_IFS_CLM_TX_CNT_MSK, 107 107 + .ifs_clm_cca_addr = R_IFS_CLM_CCA_BE4, 108 108 + .ifs_clm_ofdmcca_excl_fa_mask = B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK, 109 109 + .ifs_clm_cckcca_excl_fa_mask = B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK, 110 110 + .ifs_clm_fa_addr = R_IFS_CLM_FA_BE4, 111 111 + .ifs_clm_ofdm_fa_mask = B_IFS_CLM_OFDM_FA_MSK, 112 112 + .ifs_clm_cck_fa_mask = B_IFS_CLM_CCK_FA_MSK, 113 113 + .ifs_his_addr = R_IFS_T1_HIS_BE4, 114 114 + .ifs_his_addr2 = R_IFS_T3_HIS_BE4, /* for 3/4 */ 115 115 + .ifs_t4_his_mask = B_IFS_T4_HIS_BE4, 116 116 + .ifs_t3_his_mask = B_IFS_T3_HIS_BE4, 117 117 + .ifs_t2_his_mask = B_IFS_T2_HIS_BE4, 118 118 + .ifs_t1_his_mask = B_IFS_T1_HIS_BE4, 119 119 + .ifs_avg_l_addr = R_IFS_T1_AVG_BE4, 120 120 + .ifs_t2_avg_mask = B_IFS_T2_AVG_BE4, 121 121 + .ifs_t1_avg_mask = B_IFS_T1_AVG_BE4, 122 122 + .ifs_avg_h_addr = R_IFS_T3_AVG_BE4, 123 123 + .ifs_t4_avg_mask = B_IFS_T4_AVG_BE4, 124 124 + .ifs_t3_avg_mask = B_IFS_T3_AVG_BE4, 125 125 + .ifs_cca_l_addr = R_IFS_T1_CLM_BE4, 126 126 + .ifs_t2_cca_mask = B_IFS_T2_CLM_BE4, 127 127 + .ifs_t1_cca_mask = B_IFS_T1_CLM_BE4, 128 128 + .ifs_cca_h_addr = R_IFS_T3_CLM_BE4, 129 129 + .ifs_t4_cca_mask = B_IFS_T4_CLM_BE4, 130 130 + .ifs_t3_cca_mask = B_IFS_T3_CLM_BE4, 131 131 + .ifs_total_addr = R_IFS_TOTAL_BE4, 132 132 + .ifs_cnt_done_mask = B_IFS_CNT_DONE_BE4, 133 133 + .ifs_total_mask = B_IFS_TOTAL_BE4, 134 134 + }; 135 135 + 79 136 static const struct rtw89_physts_regs rtw89_physts_regs_be = { 80 137 .setting_addr = R_PLCP_HISTOGRAM, 81 138 .dis_trigger_fail_mask = B_STS_DIS_TRIG_BY_FAIL, 82 139 .dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK, 83 140 }; 84 141 142 142 + static const struct rtw89_physts_regs rtw89_physts_regs_be_v1 = { 143 143 + .setting_addr = R_PLCP_HISTOGRAM_BE_V1, 144 144 + .dis_trigger_fail_mask = B_STS_DIS_TRIG_BY_FAIL, 145 145 + .dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK, 146 146 + }; 147 147 + 85 148 static const struct rtw89_cfo_regs rtw89_cfo_regs_be = { 86 86 - .comp = R_DCFO_WEIGHT_V1, 87 87 - .weighting_mask = B_DCFO_WEIGHT_MSK_V1, 88 88 - .comp_seg0 = R_DCFO_OPT_V1, 89 89 - .valid_0_mask = B_DCFO_OPT_EN_V1, 149 149 + .comp = R_DCFO_WEIGHT_BE, 150 150 + .weighting_mask = B_DCFO_WEIGHT_MSK_BE, 151 151 + .comp_seg0 = R_DCFO_OPT_BE, 152 152 + .valid_0_mask = B_DCFO_OPT_EN_BE, 153 153 + }; 154 154 + 155 155 + static const struct rtw89_cfo_regs rtw89_cfo_regs_be_v1 = { 156 156 + .comp = R_DCFO_WEIGHT_BE_V1, 157 157 + .weighting_mask = B_DCFO_WEIGHT_MSK_BE, 158 158 + .comp_seg0 = R_DCFO_OPT_BE_V1, 159 159 + .valid_0_mask = B_DCFO_OPT_EN_BE, 160 160 + }; 161 161 + 162 162 + static const struct rtw89_bb_wrap_regs rtw89_bb_wrap_regs_be = { 163 163 + .pwr_macid_lmt = R_BE_PWR_MACID_LMT_BASE, 164 164 + .pwr_macid_path = R_BE_PWR_MACID_PATH_BASE, 165 165 + }; 166 166 + 167 167 + static const struct rtw89_bb_wrap_regs rtw89_bb_wrap_regs_be_v1 = { 168 168 + .pwr_macid_lmt = R_BE_PWR_MACID_LMT_BASE_V1, 169 169 + .pwr_macid_path = R_BE_PWR_MACID_PATH_BASE_V1, 90 170 }; 91 171 92 172 static u32 rtw89_phy0_phy1_offset_be(struct rtw89_dev *rtwdev, u32 addr) ··· 182 98 (phy_page >= 0x60 && phy_page <= 0x6f) || 183 99 (phy_page >= 0xE4 && phy_page <= 0xE5) || 184 100 (phy_page >= 0xE8 && phy_page <= 0xED)) 101 101 + ofst = 0x1000; 102 102 + else 103 103 + ofst = 0x0; 104 104 + 105 105 + return ofst; 106 106 + } 107 107 + 108 108 + static u32 rtw89_phy0_phy1_offset_be_v1(struct rtw89_dev *rtwdev, u32 addr) 109 109 + { 110 110 + u32 phy_page = addr >> 8; 111 111 + u32 ofst = 0; 112 112 + 113 113 + if ((phy_page >= 0x204 && phy_page <= 0x20F) || 114 114 + (phy_page >= 0x220 && phy_page <= 0x22F) || 115 115 + (phy_page >= 0x240 && phy_page <= 0x24f) || 116 116 + (phy_page >= 0x260 && phy_page <= 0x26f) || 117 117 + (phy_page >= 0x2C0 && phy_page <= 0x2C9) || 118 118 + (phy_page >= 0x2E4 && phy_page <= 0x2E8) || 119 119 + phy_page == 0x2EE) 185 120 ofst = 0x1000; 186 121 else 187 122 ofst = 0x0; ··· 404 301 } 405 302 } 406 303 304 304 + static void rtw89_phy_preinit_rf_nctl_be_v1(struct rtw89_dev *rtwdev) 305 305 + { 306 306 + rtw89_phy_write32_mask(rtwdev, R_GOTX_IQKDPK_C0_BE4, B_GOTX_IQKDPK, 0x3); 307 307 + rtw89_phy_write32_mask(rtwdev, R_GOTX_IQKDPK_C1_BE4, B_GOTX_IQKDPK, 0x3); 308 308 + rtw89_phy_write32_mask(rtwdev, R_IOQ_IQK_DPK_BE4, B_IOQ_IQK_DPK_RST, 0x1); 309 309 + rtw89_phy_write32_mask(rtwdev, R_IQK_DPK_RST_BE4, B_IQK_DPK_RST, 0x1); 310 310 + rtw89_phy_write32_mask(rtwdev, R_IQK_DPK_PRST_BE4, B_IQK_DPK_PRST, 0x1); 311 311 + rtw89_phy_write32_mask(rtwdev, R_IQK_DPK_PRST_C1_BE4, B_IQK_DPK_PRST, 0x1); 312 312 + } 313 313 + 314 314 + static u32 rtw89_phy_bb_wrap_flush_addr(struct rtw89_dev *rtwdev, u32 addr) 315 315 + { 316 316 + struct rtw89_hal *hal = &rtwdev->hal; 317 317 + 318 318 + if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 319 319 + return 0; 320 320 + 321 321 + if (rtwdev->chip->chip_id == RTL8922D && hal->cid == RTL8922D_CID7025) { 322 322 + if (addr >= R_BE_PWR_MACID_PATH_BASE_V1 && 323 323 + addr <= R_BE_PWR_MACID_PATH_BASE_V1 + 0xFF) 324 324 + return addr + 0x800; 325 325 + 326 326 + if (addr >= R_BE_PWR_MACID_LMT_BASE_V1 && 327 327 + addr <= R_BE_PWR_MACID_LMT_BASE_V1 + 0xFF) 328 328 + return addr - 0x800; 329 329 + } 330 330 + 331 331 + return 0; 332 332 + } 333 333 + 334 334 + static 335 335 + void rtw89_write_bb_wrap_flush(struct rtw89_dev *rtwdev, u32 addr, u32 data) 336 336 + { 337 337 + /* To write registers of pwr_macid_lmt and pwr_macid_path with flush */ 338 338 + u32 flush_addr; 339 339 + u32 val32; 340 340 + 341 341 + flush_addr = rtw89_phy_bb_wrap_flush_addr(rtwdev, addr); 342 342 + if (flush_addr) { 343 343 + val32 = rtw89_read32(rtwdev, flush_addr); 344 344 + rtw89_write32(rtwdev, flush_addr, val32); 345 345 + } 346 346 + 347 347 + rtw89_write32(rtwdev, addr, data); 348 348 + } 349 349 + 407 350 static 408 351 void rtw89_phy_bb_wrap_pwr_by_macid_init(struct rtw89_dev *rtwdev) 409 352 { 410 410 - u32 macid_idx, cr, base_macid_lmt, max_macid = 32; 353 353 + const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 354 354 + const struct rtw89_bb_wrap_regs *bb_wrap = phy->bb_wrap; 355 355 + u32 max_macid = rtwdev->chip->support_macid_num; 356 356 + u32 macid_idx, cr, base_macid_lmt; 411 357 412 412 - base_macid_lmt = R_BE_PWR_MACID_LMT_BASE; 358 358 + base_macid_lmt = bb_wrap->pwr_macid_lmt; 413 359 414 360 for (macid_idx = 0; macid_idx < 4 * max_macid; macid_idx += 4) { 415 361 cr = base_macid_lmt + macid_idx; 416 416 - rtw89_write32(rtwdev, cr, 0x03007F7F); 362 362 + rtw89_write_bb_wrap_flush(rtwdev, cr, 0); 417 363 } 418 364 } 419 365 420 366 static 421 367 void rtw89_phy_bb_wrap_tx_path_by_macid_init(struct rtw89_dev *rtwdev) 422 368 { 423 423 - int i, max_macid = 32; 424 424 - u32 cr = R_BE_PWR_MACID_PATH_BASE; 369 369 + const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 370 370 + const struct rtw89_bb_wrap_regs *bb_wrap = phy->bb_wrap; 371 371 + u32 max_macid = rtwdev->chip->support_macid_num; 372 372 + u32 cr = bb_wrap->pwr_macid_path; 373 373 + int i; 425 374 426 375 for (i = 0; i < max_macid; i++, cr += 4) 427 427 - rtw89_write32(rtwdev, cr, 0x03C86000); 376 376 + rtw89_write_bb_wrap_flush(rtwdev, cr, 0); 428 377 } 429 378 430 379 static void rtw89_phy_bb_wrap_tpu_set_all(struct rtw89_dev *rtwdev, 431 380 enum rtw89_mac_idx mac_idx) 432 381 { 433 433 - u32 addr; 382 382 + u32 addr, t; 434 383 435 435 - for (addr = R_BE_PWR_BY_RATE; addr <= R_BE_PWR_BY_RATE_END; addr += 4) 436 436 - rtw89_write32(rtwdev, addr, 0); 437 437 - for (addr = R_BE_PWR_RULMT_START; addr <= R_BE_PWR_RULMT_END; addr += 4) 438 438 - rtw89_write32(rtwdev, addr, 0); 439 439 - for (addr = R_BE_PWR_RATE_OFST_CTRL; addr <= R_BE_PWR_RATE_OFST_END; addr += 4) 440 440 - rtw89_write32(rtwdev, addr, 0); 384 384 + addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_FTM_SS, mac_idx); 385 385 + rtw89_write32_mask(rtwdev, addr, B_BE_PWR_BY_RATE_DBW_ON, 0x3); 386 386 + 387 387 + for (addr = R_BE_PWR_BY_RATE; addr <= R_BE_PWR_BY_RATE_END; addr += 4) { 388 388 + t = rtw89_mac_reg_by_idx(rtwdev, addr, mac_idx); 389 389 + rtw89_write32(rtwdev, t, 0); 390 390 + } 391 391 + for (addr = R_BE_PWR_RULMT_START; addr <= R_BE_PWR_RULMT_END; addr += 4) { 392 392 + t = rtw89_mac_reg_by_idx(rtwdev, addr, mac_idx); 393 393 + rtw89_write32(rtwdev, t, 0); 394 394 + } 395 395 + for (addr = R_BE_PWR_RATE_OFST_CTRL; addr <= R_BE_PWR_RATE_OFST_END; addr += 4) { 396 396 + t = rtw89_mac_reg_by_idx(rtwdev, addr, mac_idx); 397 397 + rtw89_write32(rtwdev, t, 0); 398 398 + } 441 399 442 400 addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_REF_CTRL, mac_idx); 443 401 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_OFST_LMT_DB, 0); ··· 558 394 rtw89_write32_mask(rtwdev, addr, 0x7, 0); 559 395 } 560 396 397 397 + static u32 rtw89_phy_bb_wrap_be_bandedge_decision(struct rtw89_dev *rtwdev, 398 398 + const struct rtw89_chan *chan) 399 399 + { 400 400 + u8 pri_ch = chan->primary_channel; 401 401 + u32 val = 0; 402 402 + 403 403 + switch (chan->band_type) { 404 404 + default: 405 405 + case RTW89_BAND_2G: 406 406 + if (pri_ch == 1 || pri_ch == 13) 407 407 + val = BIT(1) | BIT(0); 408 408 + else if (pri_ch == 3 || pri_ch == 11) 409 409 + val = BIT(1); 410 410 + break; 411 411 + case RTW89_BAND_5G: 412 412 + if (pri_ch == 36 || pri_ch == 64 || pri_ch == 100) 413 413 + val = BIT(3) | BIT(2) | BIT(1) | BIT(0); 414 414 + else if (pri_ch == 40 || pri_ch == 60 || pri_ch == 104) 415 415 + val = BIT(3) | BIT(2) | BIT(1); 416 416 + else if ((pri_ch > 40 && pri_ch < 60) || pri_ch == 108 || pri_ch == 112) 417 417 + val = BIT(3) | BIT(2); 418 418 + else if (pri_ch > 112 && pri_ch < 132) 419 419 + val = BIT(3); 420 420 + break; 421 421 + case RTW89_BAND_6G: 422 422 + if (pri_ch == 233) 423 423 + val = BIT(0); 424 424 + break; 425 425 + } 426 426 + 427 427 + return val; 428 428 + } 429 429 + 430 430 + void rtw89_phy_bb_wrap_set_rfsi_ct_opt(struct rtw89_dev *rtwdev, 431 431 + enum rtw89_phy_idx phy_idx) 432 432 + { 433 433 + u32 reg; 434 434 + 435 435 + reg = rtw89_mac_reg_by_idx(rtwdev, R_RFSI_CT_OPT_0_BE4, phy_idx); 436 436 + rtw89_write32(rtwdev, reg, 0x00010001); 437 437 + 438 438 + reg = rtw89_mac_reg_by_idx(rtwdev, R_RFSI_CT_OPT_8_BE4, phy_idx); 439 439 + rtw89_write32(rtwdev, reg, 0x00010001); 440 440 + } 441 441 + EXPORT_SYMBOL(rtw89_phy_bb_wrap_set_rfsi_ct_opt); 442 442 + 443 443 + void rtw89_phy_bb_wrap_set_rfsi_bandedge_ch(struct rtw89_dev *rtwdev, 444 444 + const struct rtw89_chan *chan, 445 445 + enum rtw89_phy_idx phy_idx) 446 446 + { 447 447 + u32 reg; 448 448 + u32 val; 449 449 + 450 450 + val = rtw89_phy_bb_wrap_be_bandedge_decision(rtwdev, chan); 451 451 + 452 452 + rtw89_phy_write32_idx(rtwdev, R_TX_CFR_MANUAL_EN_BE4, B_TX_CFR_MANUAL_EN_BE4_M, 453 453 + chan->primary_channel == 13, phy_idx); 454 454 + 455 455 + reg = rtw89_mac_reg_by_idx(rtwdev, R_BANDEDGE_DBWX_BE4, phy_idx); 456 456 + rtw89_write32_mask(rtwdev, reg, B_BANDEDGE_DBW20_BE4, val & BIT(0)); 457 457 + reg = rtw89_mac_reg_by_idx(rtwdev, R_BANDEDGE_DBWX_BE4, phy_idx); 458 458 + rtw89_write32_mask(rtwdev, reg, B_BANDEDGE_DBW40_BE4, (val & BIT(1)) >> 1); 459 459 + reg = rtw89_mac_reg_by_idx(rtwdev, R_BANDEDGE_DBWX_BE4, phy_idx); 460 460 + rtw89_write32_mask(rtwdev, reg, B_BANDEDGE_DBW80_BE4, (val & BIT(2)) >> 2); 461 461 + reg = rtw89_mac_reg_by_idx(rtwdev, R_BANDEDGE_DBWY_BE4, phy_idx); 462 462 + rtw89_write32_mask(rtwdev, reg, B_BANDEDGE_DBW160_BE4, (val & BIT(3)) >> 3); 463 463 + } 464 464 + EXPORT_SYMBOL(rtw89_phy_bb_wrap_set_rfsi_bandedge_ch); 465 465 + 466 466 + static void rtw89_phy_bb_wrap_tx_rfsi_qam_comp_th_init(struct rtw89_dev *rtwdev, 467 467 + enum rtw89_mac_idx mac_idx) 468 468 + { 469 469 + /* TH0 */ 470 470 + rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_0_BE4, 0x1, mac_idx); 471 471 + rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_3_BE4, 0x1, mac_idx); 472 472 + rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_1_BE4, 0x1, mac_idx); 473 473 + rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_4_BE4, 0x1, mac_idx); 474 474 + rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_7_BE4, 0x1, mac_idx); 475 475 + rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_0_BE4, 0x1, mac_idx); 476 476 + rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_3_BE4, 0x1, mac_idx); 477 477 + rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_6_BE4, 0x1, mac_idx); 478 478 + /* TH1 */ 479 479 + rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_1_BE4, 0x2, mac_idx); 480 480 + rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_4_BE4, 0x2, mac_idx); 481 481 + rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_2_BE4, 0x2, mac_idx); 482 482 + rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_5_BE4, 0x2, mac_idx); 483 483 + rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_8_BE4, 0x2, mac_idx); 484 484 + rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_1_BE4, 0x2, mac_idx); 485 485 + rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_4_BE4, 0x2, mac_idx); 486 486 + rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_7_BE4, 0x2, mac_idx); 487 487 + /* TH2 */ 488 488 + rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_2_BE4, 0x4, mac_idx); 489 489 + rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_0_BE4, 0x4, mac_idx); 490 490 + rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_3_BE4, 0x4, mac_idx); 491 491 + rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_6_BE4, 0x4, mac_idx); 492 492 + rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_9_BE4, 0x4, mac_idx); 493 493 + rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_2_BE4, 0x4, mac_idx); 494 494 + rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_5_BE4, 0x4, mac_idx); 495 495 + rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_8_BE4, 0x4, mac_idx); 496 496 + /* DPD 160M */ 497 497 + rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_0_BE4, 0x1, mac_idx); 498 498 + rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_1_BE4, 0x1, mac_idx); 499 499 + rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_2_BE4, 0x1, mac_idx); 500 500 + rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_3_BE4, 0x1, mac_idx); 501 501 + rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_4_BE4, 0x1, mac_idx); 502 502 + rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH1_BE4, B_DPD_DBW160_TH1_5_BE4, 0x1, mac_idx); 503 503 + rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH1_BE4, B_DPD_DBW160_TH1_6_BE4, 0x1, mac_idx); 504 504 + rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH1_BE4, B_DPD_DBW160_TH1_7_BE4, 0x1, mac_idx); 505 505 + /* DPD 20M */ 506 506 + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_0_BE4, 0x2, mac_idx); 507 507 + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_1_BE4, 0x2, mac_idx); 508 508 + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_2_BE4, 0x2, mac_idx); 509 509 + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_3_BE4, 0x2, mac_idx); 510 510 + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_4_BE4, 0x2, mac_idx); 511 511 + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_5_BE4, 0x2, mac_idx); 512 512 + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_6_BE4, 0x2, mac_idx); 513 513 + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW20_TH1_7_BE4, 0x2, mac_idx); 514 514 + /* DPD 40M */ 515 515 + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW40_TH1_0_BE4, 0x2, mac_idx); 516 516 + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW40_TH1_1_BE4, 0x2, mac_idx); 517 517 + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW40_TH1_2_BE4, 0x2, mac_idx); 518 518 + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW40_TH1_3_BE4, 0x2, mac_idx); 519 519 + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW40_TH1_4_BE4, 0x2, mac_idx); 520 520 + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW20_TH0_3_BE4, 0x2, mac_idx); 521 521 + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW20_TH0_4_BE4, 0x2, mac_idx); 522 522 + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW20_TH0_5_BE4, 0x2, mac_idx); 523 523 + /* DPD 80M */ 524 524 + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW80_TH1_0_BE4, 0x2, mac_idx); 525 525 + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH2_BE4, B_DPD_CBW80_TH2_1_BE4, 0x2, mac_idx); 526 526 + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH2_BE4, B_DPD_CBW80_TH2_2_BE4, 0x2, mac_idx); 527 527 + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH2_BE4, B_DPD_CBW80_TH2_3_BE4, 0x2, mac_idx); 528 528 + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH2_BE4, B_DPD_CBW80_TH2_4_BE4, 0x2, mac_idx); 529 529 + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH2_BE4, B_DPD_CBW80_TH2_5_BE4, 0x2, mac_idx); 530 530 + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH2_BE4, B_DPD_CBW80_TH2_6_BE4, 0x2, mac_idx); 531 531 + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH2_BE4, B_DPD_CBW80_TH2_7_BE4, 0x2, mac_idx); 532 532 + /* CIM3K */ 533 533 + rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_TH2_BE4, 0x2, mac_idx); 534 534 + } 535 535 + 536 536 + static void rtw89_phy_bb_wrap_tx_rfsi_scenario_def(struct rtw89_dev *rtwdev, 537 537 + enum rtw89_mac_idx mac_idx) 538 538 + { 539 539 + rtw89_write32_idx(rtwdev, R_RFSI_CT_DEF_BE4, B_RFSI_CT_ER_BE4, 0x0, mac_idx); 540 540 + rtw89_write32_idx(rtwdev, R_RFSI_CT_DEF_BE4, B_RFSI_CT_SUBF_BE4, 0x0, mac_idx); 541 541 + rtw89_write32_idx(rtwdev, R_RFSI_CT_DEF_BE4, B_RFSI_CT_FTM_BE4, 0x0, mac_idx); 542 542 + rtw89_write32_idx(rtwdev, R_RFSI_CT_DEF_BE4, B_RFSI_CT_SENS_BE4, 0x0, mac_idx); 543 543 + 544 544 + rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_DEF_BE, 0x0, mac_idx); 545 545 + rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_PB_BE4, 0x0, mac_idx); 546 546 + rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_DL_WO_BE4, 0x0, mac_idx); 547 547 + rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_DL_BF_BE4, 0x0, mac_idx); 548 548 + rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_MUMIMO_BE4, 0x0, mac_idx); 549 549 + rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_FTM_BE4, 0x0, mac_idx); 550 550 + rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_SENS_BE4, 0x0, mac_idx); 551 551 + } 552 552 + 553 553 + static void rtw89_phy_bb_wrap_tx_rfsi_qam_comp_val(struct rtw89_dev *rtwdev, 554 554 + enum rtw89_mac_idx mac_idx) 555 555 + { 556 556 + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH0_BE4, MASKLWORD, 0x4010, mac_idx); 557 557 + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH0_BE4, MASKHWORD, 0x4410, mac_idx); 558 558 + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH1_BE4, MASKLWORD, 0x0, mac_idx); 559 559 + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH1_BE4, MASKHWORD, 0x0, mac_idx); 560 560 + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH2_BE4, MASKLWORD, 0x0, mac_idx); 561 561 + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH2_BE4, MASKHWORD, 0x0, mac_idx); 562 562 + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH3_BE4, MASKLWORD, 0x0, mac_idx); 563 563 + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH3_BE4, MASKHWORD, 0x0, mac_idx); 564 564 + 565 565 + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_L, 0x8, mac_idx); 566 566 + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_M, 0x8, mac_idx); 567 567 + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_H, 0x0, mac_idx); 568 568 + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_L, 0x0, mac_idx); 569 569 + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_M, 0x0, mac_idx); 570 570 + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_H, 0x0, mac_idx); 571 571 + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH6_BE4, B_QAM_COMP_TH6_L, 0x0, mac_idx); 572 572 + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH6_BE4, B_QAM_COMP_TH6_M, 0x0, mac_idx); 573 573 + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_2L, 0x8, mac_idx); 574 574 + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_2M, 0x8, mac_idx); 575 575 + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_2H, 0x0, mac_idx); 576 576 + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_2L, 0x0, mac_idx); 577 577 + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_2M, 0x0, mac_idx); 578 578 + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_2H, 0x0, mac_idx); 579 579 + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH6_BE4, B_QAM_COMP_TH6_2L, 0x0, mac_idx); 580 580 + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH6_BE4, B_QAM_COMP_TH6_2M, 0x0, mac_idx); 581 581 + 582 582 + rtw89_write32_idx(rtwdev, R_OW_VAL_0_BE4, MASKLWORD, 0x4010, mac_idx); 583 583 + rtw89_write32_idx(rtwdev, R_OW_VAL_0_BE4, MASKHWORD, 0x4010, mac_idx); 584 584 + rtw89_write32_idx(rtwdev, R_OW_VAL_1_BE4, MASKLWORD, 0x0, mac_idx); 585 585 + rtw89_write32_idx(rtwdev, R_OW_VAL_1_BE4, MASKHWORD, 0x0, mac_idx); 586 586 + rtw89_write32_idx(rtwdev, R_OW_VAL_2_BE4, MASKLWORD, 0x0, mac_idx); 587 587 + rtw89_write32_idx(rtwdev, R_OW_VAL_2_BE4, MASKHWORD, 0x0, mac_idx); 588 588 + rtw89_write32_idx(rtwdev, R_OW_VAL_3_BE4, MASKLWORD, 0x0, mac_idx); 589 589 + rtw89_write32_idx(rtwdev, R_OW_VAL_3_BE4, MASKHWORD, 0x0, mac_idx); 590 590 + } 591 591 + 592 592 + static void rtw89_phy_bb_set_oob_dpd_qam_comp_val(struct rtw89_dev *rtwdev, 593 593 + enum rtw89_mac_idx mac_idx) 594 594 + { 595 595 + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK0_BE4, 0x0, mac_idx); 596 596 + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK1_BE4, 0x0, mac_idx); 597 597 + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK2_BE4, 0x0, mac_idx); 598 598 + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK3_BE4, 0x0, mac_idx); 599 599 + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK4_BE4, 0x0, mac_idx); 600 600 + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK5_BE4, 0x0, mac_idx); 601 601 + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK6_BE4, 0x0, mac_idx); 602 602 + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK7_BE4, 0x0, mac_idx); 603 603 + 604 604 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK0_BE4, 0x0, mac_idx); 605 605 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK1_BE4, 0x0, mac_idx); 606 606 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK2_BE4, 0x0, mac_idx); 607 607 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK3_BE4, 0x0, mac_idx); 608 608 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK4_BE4, 0x0, mac_idx); 609 609 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK5_BE4, 0x0, mac_idx); 610 610 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK6_BE4, 0x0, mac_idx); 611 611 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK7_BE4, 0x0, mac_idx); 612 612 + 613 613 + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH0_BE4, 0x0, mac_idx); 614 614 + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH1_BE4, 0x0, mac_idx); 615 615 + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH2_BE4, 0x0, mac_idx); 616 616 + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH3_BE4, 0x0, mac_idx); 617 617 + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH4_BE4, 0x0, mac_idx); 618 618 + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH5_BE4, 0x0, mac_idx); 619 619 + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH6_BE4, 0x0, mac_idx); 620 620 + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH7_BE4, 0x0, mac_idx); 621 621 + 622 622 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH0_BE4, 0x0, mac_idx); 623 623 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH1_BE4, 0x0, mac_idx); 624 624 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH2_BE4, 0x0, mac_idx); 625 625 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH3_BE4, 0x0, mac_idx); 626 626 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH4_BE4, 0x0, mac_idx); 627 627 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH5_BE4, 0x0, mac_idx); 628 628 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH6_BE4, 0x0, mac_idx); 629 629 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH7_BE4, 0x0, mac_idx); 630 630 + 631 631 + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH0_BE4, 0x0, mac_idx); 632 632 + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH1_BE4, 0x0, mac_idx); 633 633 + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH2_BE4, 0x0, mac_idx); 634 634 + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH3_BE4, 0x0, mac_idx); 635 635 + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH4_BE4, 0x0, mac_idx); 636 636 + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH5_BE4, 0x0, mac_idx); 637 637 + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH6_BE4, 0x0, mac_idx); 638 638 + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH7_BE4, 0x0, mac_idx); 639 639 + 640 640 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW0_BE4, 0x0, mac_idx); 641 641 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW1_BE4, 0x0, mac_idx); 642 642 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW2_BE4, 0x0, mac_idx); 643 643 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW3_BE4, 0x0, mac_idx); 644 644 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW4_BE4, 0x0, mac_idx); 645 645 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW5_BE4, 0x0, mac_idx); 646 646 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW6_BE4, 0x0, mac_idx); 647 647 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW7_BE4, 0x0, mac_idx); 648 648 + 649 649 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW0_BE4, 0x0, mac_idx); 650 650 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW1_BE4, 0x0, mac_idx); 651 651 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW2_BE4, 0x0, mac_idx); 652 652 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW3_BE4, 0x0, mac_idx); 653 653 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW4_BE4, 0x0, mac_idx); 654 654 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW5_BE4, 0x0, mac_idx); 655 655 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW6_BE4, 0x0, mac_idx); 656 656 + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW7_BE4, 0x0, mac_idx); 657 657 + 658 658 + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW0_BE4, 0x0, mac_idx); 659 659 + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW1_BE4, 0x0, mac_idx); 660 660 + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW2_BE4, 0x0, mac_idx); 661 661 + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW3_BE4, 0x0, mac_idx); 662 662 + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW4_BE4, 0x0, mac_idx); 663 663 + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW5_BE4, 0x0, mac_idx); 664 664 + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW6_BE4, 0x0, mac_idx); 665 665 + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW7_BE4, 0x0, mac_idx); 666 666 + } 667 667 + 668 668 + static void rtw89_phy_bb_set_mdpd_qam_comp_val(struct rtw89_dev *rtwdev, 669 669 + enum rtw89_mac_idx mac_idx) 670 670 + { 671 671 + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH0_BE4, 0x0, mac_idx); 672 672 + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH1_BE4, 0x0, mac_idx); 673 673 + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH2_BE4, 0x0, mac_idx); 674 674 + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH3_BE4, 0x0, mac_idx); 675 675 + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH4_BE4, 0x0, mac_idx); 676 676 + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH5_BE4, 0x0, mac_idx); 677 677 + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH6_BE4, 0x0, mac_idx); 678 678 + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH7_BE4, 0x0, mac_idx); 679 679 + 680 680 + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW0_BE4, 0x0, mac_idx); 681 681 + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW1_BE4, 0x0, mac_idx); 682 682 + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW2_BE4, 0x0, mac_idx); 683 683 + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW3_BE4, 0x0, mac_idx); 684 684 + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW4_BE4, 0x0, mac_idx); 685 685 + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW5_BE4, 0x0, mac_idx); 686 686 + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW6_BE4, 0x0, mac_idx); 687 687 + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW7_BE4, 0x0, mac_idx); 688 688 + } 689 689 + 690 690 + static void rtw89_phy_bb_set_cim3k_val(struct rtw89_dev *rtwdev, 691 691 + enum rtw89_mac_idx mac_idx) 692 692 + { 693 693 + rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_TH_BE4, 0x0, mac_idx); 694 694 + rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_OW_BE4, 0x0, mac_idx); 695 695 + rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_NONBE_BE4, 0x1, mac_idx); 696 696 + rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_BANDEDGE_BE4, 0x1, mac_idx); 697 697 + } 698 698 + 699 699 + static void rtw89_phy_bb_wrap_tx_rfsi_ctrl_init(struct rtw89_dev *rtwdev, 700 700 + enum rtw89_mac_idx mac_idx) 701 701 + { 702 702 + enum rtw89_phy_idx phy_idx = mac_idx != RTW89_MAC_0 ? RTW89_PHY_1 : RTW89_PHY_0; 703 703 + enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 704 704 + const struct rtw89_chan *chan; 705 705 + 706 706 + if (chip_id != RTL8922D) 707 707 + return; 708 708 + 709 709 + rtw89_phy_bb_wrap_tx_rfsi_qam_comp_th_init(rtwdev, mac_idx); 710 710 + rtw89_phy_bb_wrap_tx_rfsi_scenario_def(rtwdev, mac_idx); 711 711 + rtw89_phy_bb_wrap_tx_rfsi_qam_comp_val(rtwdev, mac_idx); 712 712 + rtw89_phy_bb_set_oob_dpd_qam_comp_val(rtwdev, mac_idx); 713 713 + rtw89_phy_bb_set_mdpd_qam_comp_val(rtwdev, mac_idx); 714 714 + rtw89_phy_bb_set_cim3k_val(rtwdev, mac_idx); 715 715 + 716 716 + rtw89_phy_bb_wrap_set_rfsi_ct_opt(rtwdev, phy_idx); 717 717 + 718 718 + chan = rtw89_mgnt_chan_get(rtwdev, phy_idx); 719 719 + if (chan) 720 720 + rtw89_phy_bb_wrap_set_rfsi_bandedge_ch(rtwdev, chan, phy_idx); 721 721 + } 722 722 + 561 723 static void rtw89_phy_bb_wrap_ul_pwr(struct rtw89_dev *rtwdev) 562 724 { 563 725 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; ··· 904 414 static void __rtw89_phy_bb_wrap_init_be(struct rtw89_dev *rtwdev, 905 415 enum rtw89_mac_idx mac_idx) 906 416 { 907 907 - rtw89_phy_bb_wrap_pwr_by_macid_init(rtwdev); 908 417 rtw89_phy_bb_wrap_tx_path_by_macid_init(rtwdev); 909 909 - rtw89_phy_bb_wrap_listen_path_en_init(rtwdev); 418 418 + rtw89_phy_bb_wrap_pwr_by_macid_init(rtwdev); 419 419 + rtw89_phy_bb_wrap_tpu_set_all(rtwdev, mac_idx); 420 420 + rtw89_phy_bb_wrap_tx_rfsi_ctrl_init(rtwdev, mac_idx); 910 421 rtw89_phy_bb_wrap_force_cr_init(rtwdev, mac_idx); 911 422 rtw89_phy_bb_wrap_ftm_init(rtwdev, mac_idx); 912 912 - rtw89_phy_bb_wrap_tpu_set_all(rtwdev, mac_idx); 423 423 + rtw89_phy_bb_wrap_listen_path_en_init(rtwdev); 913 424 rtw89_phy_bb_wrap_ul_pwr(rtwdev); 914 425 } 915 426 ··· 930 439 rtw89_phy_set_phy_regs(rtwdev, R_CHINFO_ELM_SRC, B_CHINFO_SRC, 0x0); 931 440 rtw89_phy_set_phy_regs(rtwdev, R_CHINFO_TYPE_SCAL, B_CHINFO_TYPE, 0x3); 932 441 rtw89_phy_set_phy_regs(rtwdev, R_CHINFO_TYPE_SCAL, B_CHINFO_SCAL, 0x0); 442 442 + } 443 443 + 444 444 + static void rtw89_phy_ch_info_init_be_v1(struct rtw89_dev *rtwdev) 445 445 + { 446 446 + rtw89_phy_write32_mask(rtwdev, R_CHINFO_SEG_BE4, B_CHINFO_SEG_LEN_BE4, 0); 447 447 + rtw89_phy_set_phy_regs(rtwdev, R_CHINFO_OPT_BE4, B_CHINFO_OPT_BE4, 0x3); 448 448 + rtw89_phy_set_phy_regs(rtwdev, R_CHINFO_NX_BE4, B_CHINFO_NX_BE4, 0x669); 449 449 + rtw89_phy_set_phy_regs(rtwdev, R_CHINFO_ALG_BE4, B_CHINFO_ALG_BE4, 0); 933 450 } 934 451 935 452 struct rtw89_byr_spec_ent_be { ··· 1503 1004 1504 1005 const struct rtw89_phy_gen_def rtw89_phy_gen_be = { 1505 1006 .cr_base = 0x20000, 1007 1007 + .physt_bmp_start = R_PHY_STS_BITMAP_ADDR_START, 1008 1008 + .physt_bmp_eht = R_PHY_STS_BITMAP_EHT, 1506 1009 .ccx = &rtw89_ccx_regs_be, 1507 1010 .physts = &rtw89_physts_regs_be, 1508 1011 .cfo = &rtw89_cfo_regs_be, 1012 1012 + .bb_wrap = &rtw89_bb_wrap_regs_be, 1509 1013 .phy0_phy1_offset = rtw89_phy0_phy1_offset_be, 1510 1014 .config_bb_gain = rtw89_phy_config_bb_gain_be, 1511 1015 .preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_be, ··· 1521 1019 .set_txpwr_limit_ru = rtw89_phy_set_txpwr_limit_ru_be, 1522 1020 }; 1523 1021 EXPORT_SYMBOL(rtw89_phy_gen_be); 1022 1022 + 1023 1023 + const struct rtw89_phy_gen_def rtw89_phy_gen_be_v1 = { 1024 1024 + .cr_base = 0x0, 1025 1025 + .physt_bmp_start = R_PHY_STS_BITMAP_ADDR_START_BE4, 1026 1026 + .physt_bmp_eht = R_PHY_STS_BITMAP_EHT_BE4, 1027 1027 + .ccx = &rtw89_ccx_regs_be_v1, 1028 1028 + .physts = &rtw89_physts_regs_be_v1, 1029 1029 + .cfo = &rtw89_cfo_regs_be_v1, 1030 1030 + .bb_wrap = &rtw89_bb_wrap_regs_be_v1, 1031 1031 + .phy0_phy1_offset = rtw89_phy0_phy1_offset_be_v1, 1032 1032 + .config_bb_gain = rtw89_phy_config_bb_gain_be, 1033 1033 + .preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_be_v1, 1034 1034 + .bb_wrap_init = rtw89_phy_bb_wrap_init_be, 1035 1035 + .ch_info_init = rtw89_phy_ch_info_init_be_v1, 1036 1036 + 1037 1037 + .set_txpwr_byrate = rtw89_phy_set_txpwr_byrate_be, 1038 1038 + .set_txpwr_offset = rtw89_phy_set_txpwr_offset_be, 1039 1039 + .set_txpwr_limit = rtw89_phy_set_txpwr_limit_be, 1040 1040 + .set_txpwr_limit_ru = rtw89_phy_set_txpwr_limit_ru_be, 1041 1041 + }; 1042 1042 + EXPORT_SYMBOL(rtw89_phy_gen_be_v1);

+2

drivers/net/wireless/realtek/rtw89/ps.c

reviewed

··· 189 189 190 190 if (RTW89_CHK_FW_FEATURE(LPS_CH_INFO, &rtwdev->fw)) 191 191 rtw89_fw_h2c_lps_ch_info(rtwdev, rtwvif); 192 192 + else if (RTW89_CHK_FW_FEATURE(LPS_ML_INFO_V1, &rtwdev->fw)) 193 193 + rtw89_fw_h2c_lps_ml_cmn_info_v1(rtwdev, rtwvif); 192 194 else 193 195 rtw89_fw_h2c_lps_ml_cmn_info(rtwdev, rtwvif); 194 196

+364 -4

drivers/net/wireless/realtek/rtw89/reg.h

reviewed

··· 4315 4315 4316 4316 #define R_BE_SECURE_BOOT_MALLOC_INFO 0x0184 4317 4317 4318 4318 + #define R_BE_FWS0IMR 0x0190 4319 4319 + #define B_BE_FS_HALT_H2C_INT_EN BIT(31) 4320 4320 + #define B_BE_FS_FSM_HIOE_TO_EVENT_INT_EN BIT(30) 4321 4321 + #define B_BE_FS_HCI_SUS_INT_EN BIT(29) 4322 4322 + #define B_BE_FS_HCI_RES_INT_EN BIT(28) 4323 4323 + #define B_BE_FS_HCI_RESET_INT_EN BIT(27) 4324 4324 + #define B_BE_FS_BT_SB1_INT_EN BIT(26) 4325 4325 + #define B_BE_FS_ACT2RECOVERY_INT_EN BIT(25) 4326 4326 + #define B_BE_FS_GEN1GEN2_SWITCH_INT_EN BIT(24) 4327 4327 + #define B_BE_FS_USB_LPMRSM_INT_EN BIT(22) 4328 4328 + #define B_BE_FS_USB_LPMINT_INT_EN BIT(21) 4329 4329 + #define B_BE_FS_PWMERR_INT_EN BIT(20) 4330 4330 + #define B_BE_FS_PDNINT_EN BIT(19) 4331 4331 + #define B_BE_FS_SPSA_OCP_INT_EN BIT(18) 4332 4332 + #define B_BE_FS_SPSD_OCP_INT_EN BIT(17) 4333 4333 + #define B_BE_FS_BT_SB0_INT_EN BIT(16) 4334 4334 + #define B_BE_FS_GPIOF_INT_EN BIT(15) 4335 4335 + #define B_BE_FS_GPIOE_INT_EN BIT(14) 4336 4336 + #define B_BE_FS_GPIOD_INT_EN BIT(13) 4337 4337 + #define B_BE_FS_GPIOC_INT_EN BIT(12) 4338 4338 + #define B_BE_FS_GPIOB_INT_EN BIT(11) 4339 4339 + #define B_BE_FS_GPIOA_INT_EN BIT(10) 4340 4340 + #define B_BE_FS_GPIO9_INT_EN BIT(9) 4341 4341 + #define B_BE_FS_GPIO8_INT_EN BIT(8) 4342 4342 + #define B_BE_FS_GPIO7_INT_EN BIT(7) 4343 4343 + #define B_BE_FS_GPIO6_INT_EN BIT(6) 4344 4344 + #define B_BE_FS_GPIO5_INT_EN BIT(5) 4345 4345 + #define B_BE_FS_GPIO4_INT_EN BIT(4) 4346 4346 + #define B_BE_FS_GPIO3_INT_EN BIT(3) 4347 4347 + #define B_BE_FS_GPIO2_INT_EN BIT(2) 4348 4348 + #define B_BE_FS_GPIO1_INT_EN BIT(1) 4349 4349 + #define B_BE_FS_GPIO0_INT_EN BIT(0) 4350 4350 + 4351 4351 + #define R_BE_FWS0ISR 0x0194 4352 4352 + #define B_BE_FS_HALT_H2C_INT BIT(31) 4353 4353 + #define B_BE_FS_FSM_HIOE_TO_EVENT_INT BIT(30) 4354 4354 + #define B_BE_FS_HCI_SUS_INT BIT(29) 4355 4355 + #define B_BE_FS_HCI_RES_INT BIT(28) 4356 4356 + #define B_BE_FS_HCI_RESET_INT BIT(27) 4357 4357 + #define B_BE_FS_BT_SB1_INT BIT(26) 4358 4358 + #define B_BE_FS_ACT2RECOVERY_INT BIT(25) 4359 4359 + #define B_BE_FS_GEN1GEN2_SWITCH_INT BIT(24) 4360 4360 + #define B_BE_FS_USB_LPMRSM_INT BIT(22) 4361 4361 + #define B_BE_FS_USB_LPMINT_INT BIT(21) 4362 4362 + #define B_BE_FS_PWMERR_INT BIT(20) 4363 4363 + #define B_BE_FS_PDNINT BIT(19) 4364 4364 + #define B_BE_FS_SPSA_OCP_INT BIT(18) 4365 4365 + #define B_BE_FS_SPSD_OCP_INT BIT(17) 4366 4366 + #define B_BE_FS_BT_SB0_INT BIT(16) 4367 4367 + #define B_BE_FS_GPIOF_INT BIT(15) 4368 4368 + #define B_BE_FS_GPIOE_INT BIT(14) 4369 4369 + #define B_BE_FS_GPIOD_INT BIT(13) 4370 4370 + #define B_BE_FS_GPIOC_INT BIT(12) 4371 4371 + #define B_BE_FS_GPIOB_INT BIT(11) 4372 4372 + #define B_BE_FS_GPIOA_INT BIT(10) 4373 4373 + #define B_BE_FS_GPIO9_INT BIT(9) 4374 4374 + #define B_BE_FS_GPIO8_INT BIT(8) 4375 4375 + #define B_BE_FS_GPIO7_INT BIT(7) 4376 4376 + #define B_BE_FS_GPIO6_INT BIT(6) 4377 4377 + #define B_BE_FS_GPIO5_INT BIT(5) 4378 4378 + #define B_BE_FS_GPIO4_INT BIT(4) 4379 4379 + #define B_BE_FS_GPIO3_INT BIT(3) 4380 4380 + #define B_BE_FS_GPIO2_INT BIT(2) 4381 4381 + #define B_BE_FS_GPIO1_INT BIT(1) 4382 4382 + #define B_BE_FS_GPIO0_INT BIT(0) 4383 4383 + 4318 4384 #define R_BE_FWS1IMR 0x0198 4319 4385 #define B_BE_FS_RPWM_INT_EN_V1 BIT(24) 4320 4386 #define B_BE_PCIE_HOTRST_EN BIT(22) ··· 4959 4893 4960 4894 #define R_BE_SER_L1_DBG_CNT_7 0x845C 4961 4895 #define B_BE_SER_L1_DBG_2_MASK GENMASK(31, 0) 4896 4896 + 4897 4897 + #define R_BE_FW_TRIGGER_IDCT_ISR 0x8508 4898 4898 + #define B_BE_DMAC_FW_ERR_IDCT_IMR BIT(31) 4899 4899 + #define B_BE_DMAC_FW_TRIG_IDCT BIT(0) 4962 4900 4963 4901 #define R_BE_DMAC_ERR_IMR 0x8520 4964 4902 #define B_BE_DMAC_NOTX_ERR_INT_EN BIT(21) ··· 6436 6366 #define B_BE_PTA_GNT_BT1_BB_SWCTRL BIT(0) 6437 6367 6438 6368 #define R_BE_PWR_MACID_PATH_BASE 0x0E500 6369 6369 + #define R_BE_PWR_MACID_PATH_BASE_V1 0x1C000 6439 6370 #define R_BE_PWR_MACID_LMT_BASE 0x0ED00 6371 6371 + #define R_BE_PWR_MACID_LMT_BASE_V1 0x1C800 6440 6372 6441 6373 #define R_BE_CMAC_FUNC_EN 0x10000 6442 6374 #define R_BE_CMAC_FUNC_EN_C1 0x14000 ··· 6500 6428 #define BE_WMAC_RFMOD_80M 2 6501 6429 #define BE_WMAC_RFMOD_160M 3 6502 6430 #define BE_WMAC_RFMOD_320M 4 6431 6431 + 6432 6432 + #define R_BE_GID_POSITION0 0x10070 6433 6433 + #define R_BE_GID_POSITION0_C1 0x14070 6434 6434 + #define R_BE_GID_POSITION1 0x10074 6435 6435 + #define R_BE_GID_POSITION1_C1 0x14074 6436 6436 + #define R_BE_GID_POSITION2 0x10078 6437 6437 + #define R_BE_GID_POSITION2_C1 0x14078 6438 6438 + #define R_BE_GID_POSITION3 0x1007C 6439 6439 + #define R_BE_GID_POSITION3_C1 0x1407C 6440 6440 + #define R_BE_GID_POSITION_EN0 0x10080 6441 6441 + #define R_BE_GID_POSITION_EN0_C1 0x14080 6442 6442 + #define R_BE_GID_POSITION_EN1 0x10084 6443 6443 + #define R_BE_GID_POSITION_EN1_C1 0x14084 6503 6444 6504 6445 #define R_BE_TX_SUB_BAND_VALUE 0x10088 6505 6446 #define R_BE_TX_SUB_BAND_VALUE_C1 0x14088 ··· 8328 8243 8329 8244 #define R_BE_PWR_FTM 0x11B00 8330 8245 #define R_BE_PWR_FTM_SS 0x11B04 8246 8246 + #define B_BE_PWR_BY_RATE_DBW_ON GENMASK(27, 26) 8331 8247 8332 8248 #define R_BE_PWR_BY_RATE 0x11E00 8333 8249 #define R_BE_PWR_BY_RATE_MAX 0x11FA8 ··· 8637 8551 #define B_UPD_P0_EN BIT(31) 8638 8552 #define R_EMLSR 0x0044 8639 8553 #define B_EMLSR_PARM GENMASK(27, 12) 8554 8554 + #define R_CHK_LPS_STAT_BE4 0x3007C 8640 8555 #define R_CHK_LPS_STAT 0x0058 8641 8556 #define B_CHK_LPS_STAT BIT(0) 8642 8557 #define R_SPOOF_CG 0x00B4 ··· 8711 8624 #define R_MAC_PIN_SEL 0x0734 8712 8625 #define B_CH_IDX_SEG0 GENMASK(23, 16) 8713 8626 #define R_PLCP_HISTOGRAM 0x0738 8627 8627 + #define R_PLCP_HISTOGRAM_BE_V1 0x20738 8714 8628 #define B_STS_PARSING_TIME GENMASK(19, 16) 8715 8629 #define B_STS_DIS_TRIG_BY_FAIL BIT(3) 8716 8630 #define B_STS_DIS_TRIG_BY_BRK BIT(2) 8717 8631 #define R_PHY_STS_BITMAP_ADDR_START R_PHY_STS_BITMAP_SEARCH_FAIL 8632 8632 + #define R_PHY_STS_BITMAP_ADDR_START_BE4 0x2073C 8718 8633 #define B_PHY_STS_BITMAP_ADDR_MASK GENMASK(6, 2) 8719 8634 #define R_PHY_STS_BITMAP_SEARCH_FAIL 0x073C 8720 8635 #define B_PHY_STS_BITMAP_MSK_52A 0x337cff3f ··· 8735 8646 #define R_PHY_STS_BITMAP_VHT 0x0770 8736 8647 #define R_PHY_STS_BITMAP_HE 0x0774 8737 8648 #define R_PHY_STS_BITMAP_EHT 0x0788 8649 8649 + #define R_PHY_STS_BITMAP_EHT_BE4 0x20788 8738 8650 #define R_EDCCA_RPTREG_SEL_BE 0x078C 8739 8651 #define B_EDCCA_RPTREG_SEL_BE_MSK GENMASK(22, 20) 8740 8652 #define R_PMAC_GNT 0x0980 ··· 8766 8676 #define R_DBCC_80P80_SEL_EVM_RPT 0x0A10 8767 8677 #define B_DBCC_80P80_SEL_EVM_RPT_EN BIT(0) 8768 8678 #define R_CCX 0x0C00 8679 8679 + #define R_CCX_BE4 0x20C00 8769 8680 #define B_CCX_EDCCA_OPT_MSK GENMASK(6, 4) 8770 8681 #define B_CCX_EDCCA_OPT_MSK_V1 GENMASK(7, 4) 8771 8682 #define B_MEASUREMENT_TRIG_MSK BIT(2) ··· 8795 8704 #define R_FAHM 0x0C1C 8796 8705 #define B_RXTD_CKEN BIT(2) 8797 8706 #define R_IFS_COUNTER 0x0C28 8707 8707 + #define R_IFS_COUNTER_BE4 0x20C28 8798 8708 #define B_IFS_CLM_PERIOD_MSK GENMASK(31, 16) 8799 8709 #define B_IFS_CLM_COUNTER_UNIT_MSK GENMASK(15, 14) 8800 8710 #define B_IFS_COUNTER_CLR_MSK BIT(13) 8801 8711 #define B_IFS_COLLECT_EN BIT(12) 8802 8712 #define R_IFS_T1 0x0C2C 8713 8713 + #define R_IFS_T1_BE4 0x20C2C 8803 8714 #define B_IFS_T1_TH_HIGH_MSK GENMASK(31, 16) 8804 8715 #define B_IFS_T1_EN_MSK BIT(15) 8805 8716 #define B_IFS_T1_TH_LOW_MSK GENMASK(14, 0) 8806 8717 #define R_IFS_T2 0x0C30 8718 8718 + #define R_IFS_T2_BE4 0x20C30 8807 8719 #define B_IFS_T2_TH_HIGH_MSK GENMASK(31, 16) 8808 8720 #define B_IFS_T2_EN_MSK BIT(15) 8809 8721 #define B_IFS_T2_TH_LOW_MSK GENMASK(14, 0) 8810 8722 #define R_IFS_T3 0x0C34 8723 8723 + #define R_IFS_T3_BE4 0x20C34 8811 8724 #define B_IFS_T3_TH_HIGH_MSK GENMASK(31, 16) 8812 8725 #define B_IFS_T3_EN_MSK BIT(15) 8813 8726 #define B_IFS_T3_TH_LOW_MSK GENMASK(14, 0) 8814 8727 #define R_IFS_T4 0x0C38 8728 8728 + #define R_IFS_T4_BE4 0x20C38 8815 8729 #define B_IFS_T4_TH_HIGH_MSK GENMASK(31, 16) 8816 8730 #define B_IFS_T4_EN_MSK BIT(15) 8817 8731 #define B_IFS_T4_TH_LOW_MSK GENMASK(14, 0) 8818 8732 #define R_PD_CTRL 0x0C3C 8819 8733 #define B_PD_HIT_DIS BIT(9) 8820 8734 #define R_IOQ_IQK_DPK 0x0C60 8735 8735 + #define R_IOQ_IQK_DPK_BE4 0x20C60 8821 8736 #define B_IOQ_IQK_DPK_CLKEN GENMASK(1, 0) 8822 8737 #define B_IOQ_IQK_DPK_EN BIT(1) 8738 8738 + #define B_IOQ_IQK_DPK_RST BIT(0) 8823 8739 #define R_GNT_BT_WGT_EN 0x0C6C 8824 8740 #define B_GNT_BT_WGT_EN BIT(21) 8825 8741 #define R_IQK_DPK_RST 0x0C6C 8742 8742 + #define R_IQK_DPK_RST_BE4 0x20C6C 8826 8743 #define R_IQK_DPK_RST_C1 0x1C6C 8827 8744 #define B_IQK_DPK_RST BIT(0) 8828 8745 #define R_TX_COLLISION_T2R_ST 0x0C70 ··· 8948 8849 #define B_NHM_READY_MSK BIT(16) 8949 8850 #define R_IFS_CLM_TX_CNT 0x1ACC 8950 8851 #define R_IFS_CLM_TX_CNT_V1 0x0ECC 8852 8852 + #define R_IFS_CLM_TX_CNT_BE4 0x20ECC 8951 8853 #define B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK GENMASK(31, 16) 8952 8854 #define B_IFS_CLM_TX_CNT_MSK GENMASK(15, 0) 8953 8855 #define R_IFS_CLM_CCA 0x1AD0 8954 8856 #define R_IFS_CLM_CCA_V1 0x0ED0 8857 8857 + #define R_IFS_CLM_CCA_BE4 0x20ED0 8955 8858 #define B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK GENMASK(31, 16) 8956 8859 #define B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK GENMASK(15, 0) 8957 8860 #define R_IFS_CLM_FA 0x1AD4 8958 8861 #define R_IFS_CLM_FA_V1 0x0ED4 8862 8862 + #define R_IFS_CLM_FA_BE4 0x20ED4 8959 8863 #define B_IFS_CLM_OFDM_FA_MSK GENMASK(31, 16) 8960 8864 #define B_IFS_CLM_CCK_FA_MSK GENMASK(15, 0) 8961 8865 #define R_IFS_HIS 0x1AD8 ··· 9615 9513 #define B_S0_DACKQ7_K GENMASK(15, 8) 9616 9514 #define R_S0_DACKQ8 0x5E98 9617 9515 #define B_S0_DACKQ8_K GENMASK(15, 8) 9618 9618 - #define R_DCFO_WEIGHT_V1 0x6244 9619 9619 - #define B_DCFO_WEIGHT_MSK_V1 GENMASK(31, 28) 9516 9516 + #define R_DCFO_WEIGHT_BE 0x6244 9517 9517 + #define R_DCFO_WEIGHT_BE_V1 0x24808 9518 9518 + #define B_DCFO_WEIGHT_MSK_BE GENMASK(31, 28) 9620 9519 #define R_DAC_CLK 0x625C 9621 9520 #define B_DAC_CLK GENMASK(31, 30) 9622 9622 - #define R_DCFO_OPT_V1 0x6260 9623 9623 - #define B_DCFO_OPT_EN_V1 BIT(17) 9521 9521 + #define R_DCFO_OPT_BE 0x6260 9522 9522 + #define R_DCFO_OPT_BE_V1 0x24824 9523 9523 + #define B_DCFO_OPT_EN_BE BIT(17) 9624 9524 #define R_TXFCTR 0x627C 9625 9525 #define B_TXFCTR_THD GENMASK(19, 10) 9626 9526 #define R_TXSCALE 0x6284 ··· 10132 10028 #define R_GAIN_MAP1 0xE54C 10133 10029 #define B_GAIN_MAP1_EN BIT(0) 10134 10030 #define R_GOTX_IQKDPK_C0 0xE464 10031 10031 + #define R_GOTX_IQKDPK_C0_BE4 0x2E464 10135 10032 #define R_GOTX_IQKDPK_C1 0xE564 10033 10033 + #define R_GOTX_IQKDPK_C1_BE4 0x2E564 10136 10034 #define B_GOTX_IQKDPK GENMASK(28, 27) 10137 10035 #define R_IQK_DPK_PRST 0xE4AC 10036 10036 + #define R_IQK_DPK_PRST_BE4 0x2E4AC 10138 10037 #define R_IQK_DPK_PRST_C1 0xE5AC 10038 10038 + #define R_IQK_DPK_PRST_C1_BE4 0x2E5AC 10139 10039 #define B_IQK_DPK_PRST BIT(27) 10140 10040 #define R_TXPWR_RSTA 0xE60C 10141 10041 #define B_TXPWR_RSTA BIT(16) ··· 10165 10057 #define B_TXAGC_CCK_REF_DBM_P1 GENMASK(17, 9) 10166 10058 #define R_TSSI_K_P1 0xE7A0 10167 10059 #define B_TSSI_K_OFDM_P1 GENMASK(29, 20) 10060 10060 + 10061 10061 + #define R_COMP_CIM3K_BE4 0x11998 10062 10062 + #define B_COMP_CIM3K_OW_BE4 BIT(1) 10063 10063 + #define B_COMP_CIM3K_TH_BE4 BIT(2) 10064 10064 + #define B_COMP_CIM3K_TH2_BE4 GENMASK(5, 3) 10065 10065 + #define B_COMP_CIM3K_TXPWR_EN_BE4 BIT(6) 10066 10066 + #define B_COMP_CIM3K_NONBE_BE4 BIT(7) 10067 10067 + #define B_COMP_CIM3K_BANDEDGE_BE4 BIT(8) 10068 10068 + #define R_DPD_CBW160_BE4 0x119B4 10069 10069 + #define B_DPD_CBW160_TH0_BE4 BIT(0) 10070 10070 + #define B_DPD_CBW160_TH1_BE4 BIT(1) 10071 10071 + #define B_DPD_CBW160_TH2_BE4 BIT(2) 10072 10072 + #define B_DPD_CBW160_TH3_BE4 BIT(3) 10073 10073 + #define B_DPD_CBW160_TH4_BE4 BIT(4) 10074 10074 + #define B_DPD_CBW160_TH5_BE4 BIT(5) 10075 10075 + #define B_DPD_CBW160_TH6_BE4 BIT(6) 10076 10076 + #define B_DPD_CBW160_TH7_BE4 BIT(7) 10077 10077 + #define B_DPD_CBW160_OW0_BE4 BIT(8) 10078 10078 + #define B_DPD_CBW160_OW1_BE4 BIT(9) 10079 10079 + #define B_DPD_CBW160_OW2_BE4 BIT(10) 10080 10080 + #define B_DPD_CBW160_OW3_BE4 BIT(11) 10081 10081 + #define B_DPD_CBW160_OW4_BE4 BIT(12) 10082 10082 + #define B_DPD_CBW160_OW5_BE4 BIT(13) 10083 10083 + #define B_DPD_CBW160_OW6_BE4 BIT(14) 10084 10084 + #define B_DPD_CBW160_OW7_BE4 BIT(15) 10085 10085 + #define R_OOB_CBW20_BE4 0x119B4 10086 10086 + #define B_OOB_CBW20_CCK0_BE4 BIT(16) 10087 10087 + #define B_OOB_CBW20_CCK1_BE4 BIT(17) 10088 10088 + #define B_OOB_CBW20_CCK2_BE4 BIT(18) 10089 10089 + #define B_OOB_CBW20_CCK3_BE4 BIT(19) 10090 10090 + #define B_OOB_CBW20_CCK4_BE4 BIT(20) 10091 10091 + #define B_OOB_CBW20_CCK5_BE4 BIT(21) 10092 10092 + #define B_OOB_CBW20_CCK6_BE4 BIT(22) 10093 10093 + #define B_OOB_CBW20_CCK7_BE4 BIT(23) 10094 10094 + #define B_OOB_CBW20_TH0_BE4 BIT(24) 10095 10095 + #define B_OOB_CBW20_TH1_BE4 BIT(25) 10096 10096 + #define B_OOB_CBW20_TH2_BE4 BIT(26) 10097 10097 + #define B_OOB_CBW20_TH3_BE4 BIT(27) 10098 10098 + #define B_OOB_CBW20_TH4_BE4 BIT(28) 10099 10099 + #define B_OOB_CBW20_TH5_BE4 BIT(29) 10100 10100 + #define B_OOB_CBW20_TH6_BE4 BIT(30) 10101 10101 + #define B_OOB_CBW20_TH7_BE4 BIT(31) 10102 10102 + #define R_OOB_CBW40_BE4 0x119B8 10103 10103 + #define B_OOB_CBW20_OW0_BE4 BIT(0) 10104 10104 + #define B_OOB_CBW20_OW1_BE4 BIT(1) 10105 10105 + #define B_OOB_CBW20_OW2_BE4 BIT(2) 10106 10106 + #define B_OOB_CBW20_OW3_BE4 BIT(3) 10107 10107 + #define B_OOB_CBW20_OW4_BE4 BIT(4) 10108 10108 + #define B_OOB_CBW20_OW5_BE4 BIT(5) 10109 10109 + #define B_OOB_CBW20_OW6_BE4 BIT(6) 10110 10110 + #define B_OOB_CBW20_OW7_BE4 BIT(7) 10111 10111 + #define B_OOB_CBW40_CCK0_BE4 BIT(8) 10112 10112 + #define B_OOB_CBW40_CCK1_BE4 BIT(9) 10113 10113 + #define B_OOB_CBW40_CCK2_BE4 BIT(10) 10114 10114 + #define B_OOB_CBW40_CCK3_BE4 BIT(11) 10115 10115 + #define B_OOB_CBW40_CCK4_BE4 BIT(12) 10116 10116 + #define B_OOB_CBW40_CCK5_BE4 BIT(13) 10117 10117 + #define B_OOB_CBW40_CCK6_BE4 BIT(14) 10118 10118 + #define B_OOB_CBW40_CCK7_BE4 BIT(15) 10119 10119 + #define B_OOB_CBW40_TH0_BE4 BIT(16) 10120 10120 + #define B_OOB_CBW40_TH1_BE4 BIT(17) 10121 10121 + #define B_OOB_CBW40_TH2_BE4 BIT(18) 10122 10122 + #define B_OOB_CBW40_TH3_BE4 BIT(19) 10123 10123 + #define B_OOB_CBW40_TH4_BE4 BIT(20) 10124 10124 + #define B_OOB_CBW40_TH5_BE4 BIT(21) 10125 10125 + #define B_OOB_CBW40_TH6_BE4 BIT(22) 10126 10126 + #define B_OOB_CBW40_TH7_BE4 BIT(23) 10127 10127 + #define B_OOB_CBW40_OW0_BE4 BIT(24) 10128 10128 + #define B_OOB_CBW40_OW1_BE4 BIT(25) 10129 10129 + #define B_OOB_CBW40_OW2_BE4 BIT(26) 10130 10130 + #define B_OOB_CBW40_OW3_BE4 BIT(27) 10131 10131 + #define B_OOB_CBW40_OW4_BE4 BIT(28) 10132 10132 + #define B_OOB_CBW40_OW5_BE4 BIT(29) 10133 10133 + #define B_OOB_CBW40_OW6_BE4 BIT(30) 10134 10134 + #define B_OOB_CBW40_OW7_BE4 BIT(31) 10135 10135 + #define R_OOB_CBW80_BE4 0x119BC 10136 10136 + #define B_OOB_CBW80_TH0_BE4 BIT(0) 10137 10137 + #define B_OOB_CBW80_TH1_BE4 BIT(1) 10138 10138 + #define B_OOB_CBW80_TH2_BE4 BIT(2) 10139 10139 + #define B_OOB_CBW80_TH3_BE4 BIT(3) 10140 10140 + #define B_OOB_CBW80_TH4_BE4 BIT(4) 10141 10141 + #define B_OOB_CBW80_TH5_BE4 BIT(5) 10142 10142 + #define B_OOB_CBW80_TH6_BE4 BIT(6) 10143 10143 + #define B_OOB_CBW80_TH7_BE4 BIT(7) 10144 10144 + #define B_OOB_CBW80_OW0_BE4 BIT(8) 10145 10145 + #define B_OOB_CBW80_OW1_BE4 BIT(9) 10146 10146 + #define B_OOB_CBW80_OW2_BE4 BIT(10) 10147 10147 + #define B_OOB_CBW80_OW3_BE4 BIT(11) 10148 10148 + #define B_OOB_CBW80_OW4_BE4 BIT(12) 10149 10149 + #define B_OOB_CBW80_OW5_BE4 BIT(13) 10150 10150 + #define B_OOB_CBW80_OW6_BE4 BIT(14) 10151 10151 + #define B_OOB_CBW80_OW7_BE4 BIT(15) 10152 10152 + #define R_DPD_DBW160_TH0_BE4 0x119BC 10153 10153 + #define B_DPD_DBW160_TH0_0_BE4 GENMASK(18, 16) 10154 10154 + #define B_DPD_DBW160_TH0_1_BE4 GENMASK(21, 19) 10155 10155 + #define B_DPD_DBW160_TH0_2_BE4 GENMASK(24, 22) 10156 10156 + #define B_DPD_DBW160_TH0_3_BE4 GENMASK(27, 25) 10157 10157 + #define B_DPD_DBW160_TH0_4_BE4 GENMASK(30, 28) 10158 10158 + #define R_DPD_DBW160_TH1_BE4 0x119C0 10159 10159 + #define B_DPD_DBW160_TH1_5_BE4 GENMASK(2, 0) 10160 10160 + #define B_DPD_DBW160_TH1_6_BE4 GENMASK(5, 3) 10161 10161 + #define B_DPD_DBW160_TH1_7_BE4 GENMASK(8, 6) 10162 10162 + #define R_DPD_CBW_TH0_BE4 0x119C0 10163 10163 + #define B_DPD_CBW20_TH0_0_BE4 GENMASK(11, 9) 10164 10164 + #define B_DPD_CBW20_TH0_1_BE4 GENMASK(14, 12) 10165 10165 + #define B_DPD_CBW20_TH0_2_BE4 GENMASK(17, 15) 10166 10166 + #define B_DPD_CBW20_TH0_3_BE4 GENMASK(20, 18) 10167 10167 + #define B_DPD_CBW20_TH0_4_BE4 GENMASK(23, 21) 10168 10168 + #define B_DPD_CBW20_TH0_5_BE4 GENMASK(26, 24) 10169 10169 + #define B_DPD_CBW20_TH0_6_BE4 GENMASK(29, 27) 10170 10170 + #define R_DPD_CBW_TH1_BE4 0x119C4 10171 10171 + #define B_DPD_CBW20_TH1_7_BE4 GENMASK(2, 0) 10172 10172 + #define B_DPD_CBW40_TH1_0_BE4 GENMASK(5, 3) 10173 10173 + #define B_DPD_CBW40_TH1_1_BE4 GENMASK(8, 6) 10174 10174 + #define B_DPD_CBW40_TH1_2_BE4 GENMASK(11, 9) 10175 10175 + #define B_DPD_CBW40_TH1_3_BE4 GENMASK(14, 12) 10176 10176 + #define B_DPD_CBW40_TH1_4_BE4 GENMASK(17, 15) 10177 10177 + #define B_DPD_CBW40_TH1_5_BE4 GENMASK(20, 18) 10178 10178 + #define B_DPD_CBW40_TH1_6_BE4 GENMASK(23, 21) 10179 10179 + #define B_DPD_CBW40_TH1_7_BE4 GENMASK(26, 24) 10180 10180 + #define B_DPD_CBW80_TH1_0_BE4 GENMASK(29, 27) 10181 10181 + #define R_DPD_CBW_TH2_BE4 0x119C8 10182 10182 + #define B_DPD_CBW80_TH2_1_BE4 GENMASK(2, 0) 10183 10183 + #define B_DPD_CBW80_TH2_2_BE4 GENMASK(5, 3) 10184 10184 + #define B_DPD_CBW80_TH2_3_BE4 GENMASK(8, 6) 10185 10185 + #define B_DPD_CBW80_TH2_4_BE4 GENMASK(11, 9) 10186 10186 + #define B_DPD_CBW80_TH2_5_BE4 GENMASK(14, 12) 10187 10187 + #define B_DPD_CBW80_TH2_6_BE4 GENMASK(17, 15) 10188 10188 + #define B_DPD_CBW80_TH2_7_BE4 GENMASK(20, 18) 10189 10189 + #define R_QAM_TH0_BE4 0x119E4 10190 10190 + #define B_QAM_TH0_0_BE4 GENMASK(18, 16) 10191 10191 + #define B_QAM_TH0_1_BE4 GENMASK(21, 19) 10192 10192 + #define B_QAM_TH0_2_BE4 GENMASK(24, 22) 10193 10193 + #define B_QAM_TH0_3_BE4 GENMASK(27, 25) 10194 10194 + #define B_QAM_TH0_4_BE4 GENMASK(30, 28) 10195 10195 + #define R_QAM_TH1_BE4 0x119E8 10196 10196 + #define B_QAM_TH1_0_BE4 GENMASK(2, 0) 10197 10197 + #define B_QAM_TH1_1_BE4 GENMASK(5, 3) 10198 10198 + #define B_QAM_TH1_2_BE4 GENMASK(8, 6) 10199 10199 + #define B_QAM_TH1_3_BE4 GENMASK(11, 9) 10200 10200 + #define B_QAM_TH1_4_BE4 GENMASK(14, 12) 10201 10201 + #define B_QAM_TH1_5_BE4 GENMASK(17, 15) 10202 10202 + #define B_QAM_TH1_6_BE4 GENMASK(20, 18) 10203 10203 + #define B_QAM_TH1_7_BE4 GENMASK(23, 21) 10204 10204 + #define B_QAM_TH1_8_BE4 GENMASK(26, 24) 10205 10205 + #define B_QAM_TH1_9_BE4 GENMASK(29, 27) 10206 10206 + #define R_QAM_TH2_BE4 0x119EC 10207 10207 + #define B_QAM_TH2_0_BE4 GENMASK(2, 0) 10208 10208 + #define B_QAM_TH2_1_BE4 GENMASK(5, 3) 10209 10209 + #define B_QAM_TH2_2_BE4 GENMASK(8, 6) 10210 10210 + #define B_QAM_TH2_3_BE4 GENMASK(11, 9) 10211 10211 + #define B_QAM_TH2_4_BE4 GENMASK(14, 12) 10212 10212 + #define B_QAM_TH2_5_BE4 GENMASK(17, 15) 10213 10213 + #define B_QAM_TH2_6_BE4 GENMASK(20, 18) 10214 10214 + #define B_QAM_TH2_7_BE4 GENMASK(23, 21) 10215 10215 + #define B_QAM_TH2_8_BE4 GENMASK(26, 24) 10216 10216 + #define R_RFSI_CT_DEF_BE4 0x119F0 10217 10217 + #define B_RFSI_CT_ER_BE4 GENMASK(18, 15) 10218 10218 + #define B_RFSI_CT_SUBF_BE4 GENMASK(22, 19) 10219 10219 + #define B_RFSI_CT_FTM_BE4 GENMASK(26, 23) 10220 10220 + #define B_RFSI_CT_SENS_BE4 GENMASK(30, 27) 10221 10221 + #define R_FBTB_CT_DEF_BE4 0x119F4 10222 10222 + #define B_FBTB_CT_DEF_BE GENMASK(3, 0) 10223 10223 + #define B_FBTB_CT_PB_BE4 GENMASK(7, 4) 10224 10224 + #define B_FBTB_CT_DL_WO_BE4 GENMASK(11, 8) 10225 10225 + #define B_FBTB_CT_DL_BF_BE4 GENMASK(15, 12) 10226 10226 + #define B_FBTB_CT_MUMIMO_BE4 GENMASK(19, 16) 10227 10227 + #define B_FBTB_CT_FTM_BE4 GENMASK(23, 20) 10228 10228 + #define B_FBTB_CT_SENS_BE4 GENMASK(27, 24) 10229 10229 + #define R_RFSI_CT_OPT_0_BE4 0x11A94 10230 10230 + #define R_RFSI_CT_OPT_8_BE4 0x11A98 10231 10231 + #define R_QAM_COMP_TH0_BE4 0x11A9C 10232 10232 + #define R_QAM_COMP_TH1_BE4 0x11AA0 10233 10233 + #define R_QAM_COMP_TH2_BE4 0x11AA4 10234 10234 + #define R_QAM_COMP_TH3_BE4 0x11AA8 10235 10235 + #define R_QAM_COMP_TH4_BE4 0x11ABC 10236 10236 + #define B_QAM_COMP_TH4_L GENMASK(4, 0) 10237 10237 + #define B_QAM_COMP_TH4_M GENMASK(14, 10) 10238 10238 + #define B_QAM_COMP_TH4_H GENMASK(24, 20) 10239 10239 + #define B_QAM_COMP_TH4_2L GENMASK(9, 5) 10240 10240 + #define B_QAM_COMP_TH4_2M GENMASK(19, 15) 10241 10241 + #define B_QAM_COMP_TH4_2H GENMASK(29, 25) 10242 10242 + #define R_QAM_COMP_TH5_BE4 0x11AC0 10243 10243 + #define B_QAM_COMP_TH5_L GENMASK(4, 0) 10244 10244 + #define B_QAM_COMP_TH5_M GENMASK(14, 10) 10245 10245 + #define B_QAM_COMP_TH5_H GENMASK(24, 20) 10246 10246 + #define B_QAM_COMP_TH5_2L GENMASK(9, 5) 10247 10247 + #define B_QAM_COMP_TH5_2M GENMASK(19, 15) 10248 10248 + #define B_QAM_COMP_TH5_2H GENMASK(29, 25) 10249 10249 + #define R_QAM_COMP_TH6_BE4 0x11AC4 10250 10250 + #define B_QAM_COMP_TH6_L GENMASK(4, 0) 10251 10251 + #define B_QAM_COMP_TH6_M GENMASK(14, 10) 10252 10252 + #define B_QAM_COMP_TH6_2L GENMASK(9, 5) 10253 10253 + #define B_QAM_COMP_TH6_2M GENMASK(19, 15) 10254 10254 + #define R_OW_VAL_0_BE4 0x11AAC 10255 10255 + #define R_OW_VAL_1_BE4 0x11AB0 10256 10256 + #define R_OW_VAL_2_BE4 0x11AB4 10257 10257 + #define R_OW_VAL_3_BE4 0x11AB8 10258 10258 + #define R_BANDEDGE_DBWX_BE4 0x11ACC 10259 10259 + #define B_BANDEDGE_DBW20_BE4 BIT(29) 10260 10260 + #define B_BANDEDGE_DBW40_BE4 BIT(30) 10261 10261 + #define B_BANDEDGE_DBW80_BE4 BIT(31) 10262 10262 + #define R_BANDEDGE_DBWY_BE4 0x11AD0 10263 10263 + #define B_BANDEDGE_DBW160_BE4 BIT(0) 10264 10264 + 10265 10265 + #define R_CHINFO_SEG_BE4 0x200B4 10266 10266 + #define B_CHINFO_SEG_LEN_BE4 GENMASK(12, 10) 10267 10267 + #define R_STS_HDR2_PARSING_BE4 0x2070C 10268 10268 + #define B_STS_HDR2_PARSING_BE4 BIT(10) 10269 10269 + #define R_SW_SI_WDATA_BE4 0x20370 10270 10270 + #define B_SW_SI_DATA_PATH_BE4 GENMASK(31, 28) 10271 10271 + #define B_SW_SI_DATA_ADR_BE4 GENMASK(27, 20) 10272 10272 + #define B_SW_SI_DATA_DAT_BE4 GENMASK(19, 0) 10273 10273 + #define R_SW_SI_READ_ADDR_BE4 0x20378 10274 10274 + #define B_SW_SI_READ_ADDR_BE4 GENMASK(10, 0) 10275 10275 + #define R_IFS_T1_AVG_BE4 0x20EDC 10276 10276 + #define B_IFS_T1_AVG_BE4 GENMASK(15, 0) 10277 10277 + #define B_IFS_T2_AVG_BE4 GENMASK(31, 16) 10278 10278 + #define R_IFS_T3_AVG_BE4 0x20EE0 10279 10279 + #define B_IFS_T3_AVG_BE4 GENMASK(15, 0) 10280 10280 + #define B_IFS_T4_AVG_BE4 GENMASK(31, 16) 10281 10281 + #define R_IFS_T1_CLM_BE4 0x20EE4 10282 10282 + #define B_IFS_T1_CLM_BE4 GENMASK(15, 0) 10283 10283 + #define B_IFS_T2_CLM_BE4 GENMASK(31, 16) 10284 10284 + #define R_IFS_T3_CLM_BE4 0x20EE8 10285 10285 + #define B_IFS_T3_CLM_BE4 GENMASK(15, 0) 10286 10286 + #define B_IFS_T4_CLM_BE4 GENMASK(31, 16) 10287 10287 + #define R_IFS_TOTAL_BE4 0x20EEC 10288 10288 + #define B_IFS_TOTAL_BE4 GENMASK(15, 0) 10289 10289 + #define B_IFS_CNT_DONE_BE4 BIT(16) 10290 10290 + #define R_IFS_T1_HIS_BE4 0x20F50 10291 10291 + #define B_IFS_T1_HIS_BE4 GENMASK(15, 0) 10292 10292 + #define B_IFS_T2_HIS_BE4 GENMASK(31, 16) 10293 10293 + #define R_IFS_T3_HIS_BE4 0x20F54 10294 10294 + #define B_IFS_T3_HIS_BE4 GENMASK(15, 0) 10295 10295 + #define B_IFS_T4_HIS_BE4 GENMASK(31, 16) 10296 10296 + 10297 10297 + #define R_TX_CFR_MANUAL_EN_BE4 0x2483C 10298 10298 + #define B_TX_CFR_MANUAL_EN_BE4_M BIT(30) 10299 10299 + 10300 10300 + #define R_CHINFO_OPT_BE4 0x267C8 10301 10301 + #define B_CHINFO_OPT_BE4 GENMASK(14, 13) 10302 10302 + #define R_CHINFO_NX_BE4 0x267D0 10303 10303 + #define B_CHINFO_NX_BE4 GENMASK(16, 6) 10304 10304 + #define R_CHINFO_ALG_BE4 0x267C8 10305 10305 + #define B_CHINFO_ALG_BE4 GENMASK(31, 30) 10306 10306 + 10307 10307 + #define R_SW_SI_DATA_BE4 0x2CF4C 10308 10308 + #define B_SW_SI_READ_DATA_BE4 GENMASK(19, 0) 10309 10309 + #define B_SW_SI_W_BUSY_BE4 BIT(24) 10310 10310 + #define B_SW_SI_R_BUSY_BE4 BIT(25) 10311 10311 + #define B_SW_SI_READ_DATA_DONE_BE4 BIT(26) 10168 10312 10169 10313 /* WiFi CPU local domain */ 10170 10314 #define R_AX_WDT_CTRL 0x0040

+10 -10

drivers/net/wireless/realtek/rtw89/regd.c

reviewed

··· 38 38 COUNTRY_REGD("MX", RTW89_MEXICO, RTW89_MEXICO, RTW89_FCC, 0x0), 39 39 COUNTRY_REGD("NI", RTW89_FCC, RTW89_FCC, RTW89_NA, 0x0), 40 40 COUNTRY_REGD("PA", RTW89_FCC, RTW89_FCC, RTW89_NA, 0x0), 41 41 - COUNTRY_REGD("PY", RTW89_FCC, RTW89_FCC, RTW89_NA, 0x0), 41 41 + COUNTRY_REGD("PY", RTW89_FCC, RTW89_FCC, RTW89_FCC, 0x0), 42 42 COUNTRY_REGD("PE", RTW89_FCC, RTW89_FCC, RTW89_FCC, 0x0), 43 43 COUNTRY_REGD("US", RTW89_FCC, RTW89_FCC, RTW89_FCC, 0x1), 44 44 COUNTRY_REGD("UY", RTW89_FCC, RTW89_FCC, RTW89_NA, 0x0), ··· 95 95 COUNTRY_REGD("MK", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), 96 96 COUNTRY_REGD("MA", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), 97 97 COUNTRY_REGD("MZ", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), 98 98 - COUNTRY_REGD("NA", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), 98 98 + COUNTRY_REGD("NA", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), 99 99 COUNTRY_REGD("NG", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), 100 100 COUNTRY_REGD("OM", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), 101 101 COUNTRY_REGD("QA", RTW89_QATAR, RTW89_QATAR, RTW89_QATAR, 0x0), ··· 111 111 COUNTRY_REGD("AE", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), 112 112 COUNTRY_REGD("YE", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), 113 113 COUNTRY_REGD("ZW", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), 114 114 - COUNTRY_REGD("BD", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), 114 114 + COUNTRY_REGD("BD", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), 115 115 COUNTRY_REGD("KH", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), 116 116 COUNTRY_REGD("CN", RTW89_CN, RTW89_CN, RTW89_CN, 0x0), 117 117 COUNTRY_REGD("HK", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), 118 118 COUNTRY_REGD("IN", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), 119 119 - COUNTRY_REGD("ID", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), 119 119 + COUNTRY_REGD("ID", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), 120 120 COUNTRY_REGD("KR", RTW89_KCC, RTW89_KCC, RTW89_KCC, 0x1), 121 121 COUNTRY_REGD("MY", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), 122 122 COUNTRY_REGD("PK", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), ··· 125 125 COUNTRY_REGD("LK", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), 126 126 COUNTRY_REGD("TW", RTW89_FCC, RTW89_FCC, RTW89_ETSI, 0x0), 127 127 COUNTRY_REGD("TH", RTW89_THAILAND, RTW89_THAILAND, RTW89_THAILAND, 0x0), 128 128 - COUNTRY_REGD("VN", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), 128 128 + COUNTRY_REGD("VN", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), 129 129 COUNTRY_REGD("AU", RTW89_ACMA, RTW89_ACMA, RTW89_ACMA, 0x0), 130 130 COUNTRY_REGD("NZ", RTW89_ACMA, RTW89_ACMA, RTW89_ACMA, 0x0), 131 131 COUNTRY_REGD("PG", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), ··· 134 134 COUNTRY_REGD("JM", RTW89_FCC, RTW89_FCC, RTW89_FCC, 0x0), 135 135 COUNTRY_REGD("AN", RTW89_FCC, RTW89_FCC, RTW89_FCC, 0x0), 136 136 COUNTRY_REGD("TT", RTW89_FCC, RTW89_FCC, RTW89_NA, 0x0), 137 137 - COUNTRY_REGD("TN", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), 137 137 + COUNTRY_REGD("TN", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), 138 138 COUNTRY_REGD("AF", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), 139 139 COUNTRY_REGD("DZ", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), 140 140 COUNTRY_REGD("AS", RTW89_FCC, RTW89_FCC, RTW89_NA, 0x0), ··· 187 187 COUNTRY_REGD("GM", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), 188 188 COUNTRY_REGD("GE", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), 189 189 COUNTRY_REGD("GI", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), 190 190 - COUNTRY_REGD("GL", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), 190 190 + COUNTRY_REGD("GL", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), 191 191 COUNTRY_REGD("GD", RTW89_FCC, RTW89_FCC, RTW89_FCC, 0x0), 192 192 - COUNTRY_REGD("GP", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), 192 192 + COUNTRY_REGD("GP", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), 193 193 COUNTRY_REGD("GU", RTW89_FCC, RTW89_FCC, RTW89_FCC, 0x0), 194 194 COUNTRY_REGD("GG", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), 195 195 COUNTRY_REGD("GN", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), ··· 214 214 COUNTRY_REGD("MQ", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), 215 215 COUNTRY_REGD("MR", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), 216 216 COUNTRY_REGD("MU", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), 217 217 - COUNTRY_REGD("YT", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), 217 217 + COUNTRY_REGD("YT", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), 218 218 COUNTRY_REGD("FM", RTW89_FCC, RTW89_FCC, RTW89_FCC, 0x0), 219 219 COUNTRY_REGD("MD", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), 220 220 COUNTRY_REGD("MN", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), ··· 260 260 COUNTRY_REGD("UZ", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), 261 261 COUNTRY_REGD("VU", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), 262 262 COUNTRY_REGD("WF", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), 263 263 - COUNTRY_REGD("EH", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), 263 263 + COUNTRY_REGD("EH", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), 264 264 COUNTRY_REGD("ZM", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), 265 265 COUNTRY_REGD("CU", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), 266 266 COUNTRY_REGD("IR", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0),

+1

drivers/net/wireless/realtek/rtw89/rtw8851b.c

reviewed

··· 2530 2530 .cfg_txrx_path = rtw8851b_bb_cfg_txrx_path, 2531 2531 .set_txpwr_ul_tb_offset = rtw8851b_set_txpwr_ul_tb_offset, 2532 2532 .digital_pwr_comp = NULL, 2533 2533 + .calc_rx_gain_normal = NULL, 2533 2534 .pwr_on_func = rtw8851b_pwr_on_func, 2534 2535 .pwr_off_func = rtw8851b_pwr_off_func, 2535 2536 .query_rxdesc = rtw89_core_query_rxdesc,

+1

drivers/net/wireless/realtek/rtw89/rtw8852a.c

reviewed

··· 2224 2224 .cfg_txrx_path = NULL, 2225 2225 .set_txpwr_ul_tb_offset = rtw8852a_set_txpwr_ul_tb_offset, 2226 2226 .digital_pwr_comp = NULL, 2227 2227 + .calc_rx_gain_normal = NULL, 2227 2228 .pwr_on_func = NULL, 2228 2229 .pwr_off_func = NULL, 2229 2230 .query_rxdesc = rtw89_core_query_rxdesc,

+1

drivers/net/wireless/realtek/rtw89/rtw8852b.c

reviewed

··· 857 857 .cfg_txrx_path = rtw8852bx_bb_cfg_txrx_path, 858 858 .set_txpwr_ul_tb_offset = rtw8852bx_set_txpwr_ul_tb_offset, 859 859 .digital_pwr_comp = NULL, 860 860 + .calc_rx_gain_normal = NULL, 860 861 .pwr_on_func = rtw8852b_pwr_on_func, 861 862 .pwr_off_func = rtw8852b_pwr_off_func, 862 863 .query_rxdesc = rtw89_core_query_rxdesc,

+1

drivers/net/wireless/realtek/rtw89/rtw8852bt.c

reviewed

··· 703 703 .cfg_txrx_path = rtw8852bx_bb_cfg_txrx_path, 704 704 .set_txpwr_ul_tb_offset = rtw8852bx_set_txpwr_ul_tb_offset, 705 705 .digital_pwr_comp = NULL, 706 706 + .calc_rx_gain_normal = NULL, 706 707 .pwr_on_func = rtw8852bt_pwr_on_func, 707 708 .pwr_off_func = rtw8852bt_pwr_off_func, 708 709 .query_rxdesc = rtw89_core_query_rxdesc,

+1

drivers/net/wireless/realtek/rtw89/rtw8852c.c

reviewed

··· 3065 3065 .cfg_txrx_path = rtw8852c_bb_cfg_txrx_path, 3066 3066 .set_txpwr_ul_tb_offset = rtw8852c_set_txpwr_ul_tb_offset, 3067 3067 .digital_pwr_comp = NULL, 3068 3068 + .calc_rx_gain_normal = NULL, 3068 3069 .pwr_on_func = rtw8852c_pwr_on_func, 3069 3070 .pwr_off_func = rtw8852c_pwr_off_func, 3070 3071 .query_rxdesc = rtw89_core_query_rxdesc,

+2

drivers/net/wireless/realtek/rtw89/rtw8852cu.c

reviewed

··· 46 46 .driver_info = (kernel_ulong_t)&rtw89_8852cu_info }, 47 47 { USB_DEVICE_AND_INTERFACE_INFO(0x0db0, 0x991d, 0xff, 0xff, 0xff), 48 48 .driver_info = (kernel_ulong_t)&rtw89_8852cu_info }, 49 49 + { USB_DEVICE_AND_INTERFACE_INFO(0x28de, 0x2432, 0xff, 0xff, 0xff), 50 50 + .driver_info = (kernel_ulong_t)&rtw89_8852cu_info }, 49 51 { USB_DEVICE_AND_INTERFACE_INFO(0x35b2, 0x0502, 0xff, 0xff, 0xff), 50 52 .driver_info = (kernel_ulong_t)&rtw89_8852cu_info }, 51 53 { USB_DEVICE_AND_INTERFACE_INFO(0x35bc, 0x0101, 0xff, 0xff, 0xff),

+48 -10

drivers/net/wireless/realtek/rtw89/rtw8922a.c

reviewed

··· 1768 1768 } 1769 1769 1770 1770 #define DIGITAL_PWR_COMP_REG_NUM 22 1771 1771 + static const u32 rtw8922a_digital_pwr_comp_2g_s0_val[][DIGITAL_PWR_COMP_REG_NUM] = { 1772 1772 + {0x012C0064, 0x04B00258, 0x00432710, 0x019000A7, 0x06400320, 1773 1773 + 0x0D05091D, 0x14D50FA0, 0x00000000, 0x01010000, 0x00000101, 1774 1774 + 0x01010101, 0x02020201, 0x02010000, 0x03030202, 0x00000303, 1775 1775 + 0x03020101, 0x06060504, 0x01010000, 0x06050403, 0x01000606, 1776 1776 + 0x05040202, 0x07070706}, 1777 1777 + {0x012C0064, 0x04B00258, 0x00432710, 0x019000A7, 0x06400320, 1778 1778 + 0x0D05091D, 0x14D50FA0, 0x00000000, 0x01010100, 0x00000101, 1779 1779 + 0x01000000, 0x01010101, 0x01010000, 0x02020202, 0x00000404, 1780 1780 + 0x03020101, 0x04040303, 0x02010000, 0x03030303, 0x00000505, 1781 1781 + 0x03030201, 0x05050303}, 1782 1782 + }; 1783 1783 + 1784 1784 + static const u32 rtw8922a_digital_pwr_comp_2g_s1_val[][DIGITAL_PWR_COMP_REG_NUM] = { 1785 1785 + {0x012C0064, 0x04B00258, 0x00432710, 0x019000A7, 0x06400320, 1786 1786 + 0x0D05091D, 0x14D50FA0, 0x01010000, 0x01010101, 0x00000101, 1787 1787 + 0x01010100, 0x01010101, 0x01010000, 0x02020202, 0x01000202, 1788 1788 + 0x02020101, 0x03030202, 0x02010000, 0x05040403, 0x01000606, 1789 1789 + 0x05040302, 0x07070605}, 1790 1790 + {0x012C0064, 0x04B00258, 0x00432710, 0x019000A7, 0x06400320, 1791 1791 + 0x0D05091D, 0x14D50FA0, 0x00000000, 0x01010100, 0x00000101, 1792 1792 + 0x01010000, 0x02020201, 0x02010100, 0x03030202, 0x01000404, 1793 1793 + 0x04030201, 0x05050404, 0x01010100, 0x04030303, 0x01000505, 1794 1794 + 0x03030101, 0x05050404}, 1795 1795 + }; 1796 1796 + 1771 1797 static const u32 rtw8922a_digital_pwr_comp_val[][DIGITAL_PWR_COMP_REG_NUM] = { 1772 1798 {0x012C0096, 0x044C02BC, 0x00322710, 0x015E0096, 0x03C8028A, 1773 1799 0x0BB80708, 0x17701194, 0x02020100, 0x03030303, 0x01000303, ··· 1808 1782 }; 1809 1783 1810 1784 static void rtw8922a_set_digital_pwr_comp(struct rtw89_dev *rtwdev, 1811 1811 - bool enable, u8 nss, 1785 1785 + u8 band, u8 nss, 1812 1786 enum rtw89_rf_path path) 1813 1787 { 1814 1788 static const u32 ltpc_t0[2] = {R_BE_LTPC_T0_PATH0, R_BE_LTPC_T0_PATH1}; ··· 1816 1790 u32 addr, val; 1817 1791 u32 i; 1818 1792 1819 1819 - if (nss == 1) 1820 1820 - digital_pwr_comp = rtw8922a_digital_pwr_comp_val[0]; 1821 1821 - else 1822 1822 - digital_pwr_comp = rtw8922a_digital_pwr_comp_val[1]; 1793 1793 + if (nss == 1) { 1794 1794 + if (band == RTW89_BAND_2G) 1795 1795 + digital_pwr_comp = path == RF_PATH_A ? 1796 1796 + rtw8922a_digital_pwr_comp_2g_s0_val[0] : 1797 1797 + rtw8922a_digital_pwr_comp_2g_s1_val[0]; 1798 1798 + else 1799 1799 + digital_pwr_comp = rtw8922a_digital_pwr_comp_val[0]; 1800 1800 + } else { 1801 1801 + if (band == RTW89_BAND_2G) 1802 1802 + digital_pwr_comp = path == RF_PATH_A ? 1803 1803 + rtw8922a_digital_pwr_comp_2g_s0_val[1] : 1804 1804 + rtw8922a_digital_pwr_comp_2g_s1_val[1]; 1805 1805 + else 1806 1806 + digital_pwr_comp = rtw8922a_digital_pwr_comp_val[1]; 1807 1807 + } 1823 1808 1824 1809 addr = ltpc_t0[path]; 1825 1810 for (i = 0; i < DIGITAL_PWR_COMP_REG_NUM; i++, addr += 4) { 1826 1826 - val = enable ? digital_pwr_comp[i] : 0; 1811 1811 + val = digital_pwr_comp[i]; 1827 1812 rtw89_phy_write32(rtwdev, addr, val); 1828 1813 } 1829 1814 } ··· 1843 1806 enum rtw89_phy_idx phy_idx) 1844 1807 { 1845 1808 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 1846 1846 - bool enable = chan->band_type != RTW89_BAND_2G; 1809 1809 + u8 band = chan->band_type; 1847 1810 u8 path; 1848 1811 1849 1812 if (rtwdev->mlo_dbcc_mode == MLO_1_PLUS_1_1RF) { ··· 1851 1814 path = RF_PATH_A; 1852 1815 else 1853 1816 path = RF_PATH_B; 1854 1854 - rtw8922a_set_digital_pwr_comp(rtwdev, enable, 1, path); 1817 1817 + rtw8922a_set_digital_pwr_comp(rtwdev, band, 1, path); 1855 1818 } else { 1856 1856 - rtw8922a_set_digital_pwr_comp(rtwdev, enable, 2, RF_PATH_A); 1857 1857 - rtw8922a_set_digital_pwr_comp(rtwdev, enable, 2, RF_PATH_B); 1819 1819 + rtw8922a_set_digital_pwr_comp(rtwdev, band, 2, RF_PATH_A); 1820 1820 + rtw8922a_set_digital_pwr_comp(rtwdev, band, 2, RF_PATH_B); 1858 1821 } 1859 1822 } 1860 1823 ··· 2875 2838 .cfg_txrx_path = rtw8922a_bb_cfg_txrx_path, 2876 2839 .set_txpwr_ul_tb_offset = NULL, 2877 2840 .digital_pwr_comp = rtw8922a_digital_pwr_comp, 2841 2841 + .calc_rx_gain_normal = NULL, 2878 2842 .pwr_on_func = rtw8922a_pwr_on_func, 2879 2843 .pwr_off_func = rtw8922a_pwr_off_func, 2880 2844 .query_rxdesc = rtw89_core_query_rxdesc_v2,

+3 -3

drivers/net/wireless/realtek/rtw89/wow.c

reviewed

··· 1267 1267 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1268 1268 const struct rtw89_chip_info *chip = rtwdev->chip; 1269 1269 bool include_bb = !!chip->bbmcu_nr; 1270 1270 - bool disable_intr_for_dlfw = false; 1270 1270 + bool disable_intr_for_dlfw = true; 1271 1271 struct ieee80211_sta *wow_sta; 1272 1272 struct rtw89_sta_link *rtwsta_link = NULL; 1273 1273 struct rtw89_sta *rtwsta; 1274 1274 bool is_conn = true; 1275 1275 int ret; 1276 1276 1277 1277 - if (chip_id == RTL8852C || chip_id == RTL8922A) 1278 1278 - disable_intr_for_dlfw = true; 1277 1277 + if (chip->chip_gen == RTW89_CHIP_AX && chip_id != RTL8852C) 1278 1278 + disable_intr_for_dlfw = false; 1279 1279 1280 1280 wow_sta = ieee80211_find_sta(wow_vif, wow_vif->cfg.ap_addr); 1281 1281 if (wow_sta) {