Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
misc: rtsx_pci: Add separate CD/WP pin polarity reversal support
Previously, the Card Detect (CD) and Write Protect (WP) pins shared the
same reverse polarity setting in the configuration space. This meant both
signals were reversed together, without the ability to configure them
individually.
This patch introduces two new parameters:
sd_cd_reverse_en – enable reverse polarity for the CD pin.
sd_wp_reverse_en – enable reverse polarity for the WP pin.
With this change, the controller can now support:
1.Reversing both CD and WP pins together (original behavior).
2.Reversing CD and WP pins separately (newly added behavior), if
supported by the configuration space.
This provides greater flexibility when dealing with devices that have
independent polarity requirements for CD and WP pins.
Signed-off-by: Ricky Wu <ricky_wu@realtek.com>
Link: https://lore.kernel.org/r/20250812063521.2427696-1-ricky_wu@realtek.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
authored by
Ricky Wu
and committed by
Greg Kroah-Hartman
807221d3
6e6fe5a9
+54
-12
+10
-3
drivers/misc/cardreader/rts5227.c
+10
-3
drivers/misc/cardreader/rts5227.c
···
79
79
pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
80
80
if (rtsx_reg_check_reverse_socket(reg))
81
81
pcr->flags |= PCR_REVERSE_SOCKET;
82
+
if (rtsx_reg_check_cd_reverse(reg))
83
+
pcr->option.sd_cd_reverse_en = 1;
84
+
if (rtsx_reg_check_wp_reverse(reg))
85
+
pcr->option.sd_wp_reverse_en = 1;
82
86
}
83
87
84
88
static void rts5227_init_from_cfg(struct rtsx_pcr *pcr)
···
131
127
/* Configure force_clock_req */
132
128
if (pcr->flags & PCR_REVERSE_SOCKET)
133
129
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x30);
134
-
else
135
-
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x00);
130
+
else {
131
+
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x20, option->sd_cd_reverse_en << 5);
132
+
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x10, option->sd_wp_reverse_en << 4);
133
+
}
136
134
137
135
if (CHK_PCI_PID(pcr, 0x522A))
138
136
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_AUTOLOAD_CFG1,
···
356
350
pcr->ms_pull_ctl_disable_tbl = rts5227_ms_pull_ctl_disable_tbl;
357
351
358
352
pcr->reg_pm_ctrl3 = PM_CTRL3;
353
+
pcr->option.sd_cd_reverse_en = 0;
354
+
pcr->option.sd_wp_reverse_en = 0;
359
355
}
360
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357
static int rts522a_optimize_phy(struct rtsx_pcr *pcr)
···
516
508
pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
517
509
pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
518
510
pcr->option.sd_800mA_ocp_thd = RTS522A_OCP_THD_800;
519
-
520
511
}
+10
-2
drivers/misc/cardreader/rts5228.c
+10
-2
drivers/misc/cardreader/rts5228.c
···
84
84
pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
85
85
if (rtsx_reg_check_reverse_socket(reg))
86
86
pcr->flags |= PCR_REVERSE_SOCKET;
87
+
if (rtsx_reg_check_cd_reverse(reg))
88
+
pcr->option.sd_cd_reverse_en = 1;
89
+
if (rtsx_reg_check_wp_reverse(reg))
90
+
pcr->option.sd_wp_reverse_en = 1;
87
91
}
88
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static int rts5228_optimize_phy(struct rtsx_pcr *pcr)
···
436
432
437
433
if (pcr->flags & PCR_REVERSE_SOCKET)
438
434
rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30);
439
-
else
440
-
rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00);
435
+
else {
436
+
rtsx_pci_write_register(pcr, PETXCFG, 0x20, option->sd_cd_reverse_en << 5);
437
+
rtsx_pci_write_register(pcr, PETXCFG, 0x10, option->sd_wp_reverse_en << 4);
438
+
}
441
439
442
440
/*
443
441
* If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
···
726
720
hw_param->interrupt_en |= SD_OC_INT_EN;
727
721
hw_param->ocp_glitch = SD_OCP_GLITCH_800U;
728
722
option->sd_800mA_ocp_thd = RTS5228_LDO1_OCP_THD_930;
723
+
option->sd_cd_reverse_en = 0;
724
+
option->sd_wp_reverse_en = 0;
729
725
}
+13
-3
drivers/misc/cardreader/rts5249.c
+13
-3
drivers/misc/cardreader/rts5249.c
···
60
60
61
61
pci_read_config_dword(pdev, PCR_SETTING_REG1, ®);
62
62
pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
63
+
pci_write_config_dword(pdev, 0x718, 0x0007C000);
63
64
64
65
if (!rtsx_vendor_setting_valid(reg)) {
65
66
pcr_dbg(pcr, "skip fetch vendor setting\n");
···
83
82
pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
84
83
if (rtsx_reg_check_reverse_socket(reg))
85
84
pcr->flags |= PCR_REVERSE_SOCKET;
85
+
if (rtsx_reg_check_cd_reverse(reg))
86
+
pcr->option.sd_cd_reverse_en = 1;
87
+
if (rtsx_reg_check_wp_reverse(reg))
88
+
pcr->option.sd_wp_reverse_en = 1;
86
89
}
87
90
88
91
static void rts5249_init_from_cfg(struct rtsx_pcr *pcr)
···
259
254
/* Configure driving */
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rts5249_fill_driving(pcr, OUTPUT_3V3);
261
256
if (pcr->flags & PCR_REVERSE_SOCKET)
262
-
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
263
-
else
264
-
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
257
+
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x30);
258
+
else {
259
+
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x20, option->sd_cd_reverse_en << 5);
260
+
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x10, option->sd_wp_reverse_en << 4);
261
+
}
265
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266
263
rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
267
264
···
579
572
option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5249_DEF;
580
573
option->ltr_l1off_snooze_sspwrgate =
581
574
LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF;
575
+
576
+
option->sd_cd_reverse_en = 0;
577
+
option->sd_wp_reverse_en = 0;
582
578
}
583
579
584
580
static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val)
+16
-4
drivers/misc/cardreader/rts5264.c
+16
-4
drivers/misc/cardreader/rts5264.c
···
527
527
528
528
pcr->rtd3_en = rts5264_reg_to_rtd3(lval2);
529
529
530
-
if (rts5264_reg_check_reverse_socket(lval2))
531
-
pcr->flags |= PCR_REVERSE_SOCKET;
530
+
if (rts5264_reg_check_reverse_socket(lval2)) {
531
+
if (is_version_higher_than(pcr, PID_5264, RTS5264_IC_VER_B))
532
+
pcr->option.sd_cd_reverse_en = 1;
533
+
else
534
+
pcr->flags |= PCR_REVERSE_SOCKET;
535
+
}
536
+
537
+
if (rts5264_reg_check_wp_reverse(lval2) &&
538
+
is_version_higher_than(pcr, PID_5264, RTS5264_IC_VER_B))
539
+
pcr->option.sd_wp_reverse_en = 1;
532
540
533
541
pci_read_config_dword(pdev, setting_reg1, &lval1);
534
542
pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", setting_reg1, lval1);
···
630
622
631
623
if (pcr->flags & PCR_REVERSE_SOCKET)
632
624
rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30);
633
-
else
634
-
rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00);
625
+
else {
626
+
rtsx_pci_write_register(pcr, PETXCFG, 0x20, option->sd_cd_reverse_en << 5);
627
+
rtsx_pci_write_register(pcr, PETXCFG, 0x10, option->sd_wp_reverse_en << 4);
628
+
}
635
629
636
630
/*
637
631
* If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
···
967
957
hw_param->interrupt_en |= (SD_OC_INT_EN | SD_OVP_INT_EN);
968
958
hw_param->ocp_glitch = SD_OCP_GLITCH_800U | SDVIO_OCP_GLITCH_800U;
969
959
option->sd_800mA_ocp_thd = RTS5264_LDO1_OCP_THD_1150;
960
+
option->sd_cd_reverse_en = 0;
961
+
option->sd_wp_reverse_en = 0;
970
962
}
+1
drivers/misc/cardreader/rts5264.h
+1
drivers/misc/cardreader/rts5264.h
···
14
14
#define rts5264_reg_to_aspm(reg) \
15
15
(((~(reg) >> 28) & 0x02) | (((reg) >> 28) & 0x01))
16
16
#define rts5264_reg_check_reverse_socket(reg) ((reg) & 0x04)
17
+
#define rts5264_reg_check_wp_reverse(reg) ((reg) & 0x8000)
17
18
#define rts5264_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 22) & 0x03)
18
19
#define rts5264_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 16) & 0x03)
19
20
#define rts5264_reg_to_rtd3(reg) ((reg) & 0x08)
+2
drivers/misc/cardreader/rtsx_pcr.h
+2
drivers/misc/cardreader/rtsx_pcr.h
···
100
100
#define rtsx_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 5) & 0x03)
101
101
#define rtsx_reg_to_card_drive_sel(reg) ((((reg) >> 25) & 0x01) << 6)
102
102
#define rtsx_reg_check_reverse_socket(reg) ((reg) & 0x4000)
103
+
#define rtsx_reg_check_cd_reverse(reg) ((reg) & 0x800000)
104
+
#define rtsx_reg_check_wp_reverse(reg) ((reg) & 0x400000)
103
105
#define rts5209_reg_to_aspm(reg) (((reg) >> 5) & 0x03)
104
106
#define rts5209_reg_check_ms_pmos(reg) (!((reg) & 0x08))
105
107
#define rts5209_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 3) & 0x07)