Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: samsung: Add clock PLL support for ARTPEC-8 SoC
Add below clock PLL support for Axis ARTPEC-8 SoC platform:
- pll_1017x: Integer PLL with mid frequency FVCO (950 to 2400 MHz)
This is used in ARTPEC-8 SoC for shared PLL
- pll_1031x: Integer/Fractional PLL with mid frequency FVCO
(600 to 1200 MHz)
This is used in ARTPEC-8 SoC for Audio PLL
FOUT calculation for pll_1017x and pll_1031x:
FOUT = (MDIV x FIN)/(PDIV x 2^SDIV) for integer PLL
FOUT = (((MDIV + KDIV)/65536) x FIN)/(PDIV x 2^SDIV) for fractional PLL
Signed-off-by: Hakyeong Kim <hgkim05@coasia.com>
Signed-off-by: SeonGu Kang <ksk4725@coasia.com>
Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
Link: https://lore.kernel.org/r/20250825114436.46882-3-ravi.patel@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
authored by
Hakyeong Kim
and committed by
Krzysztof Kozlowski
80770fcc
aac0892c
+129
-1
+127
-1
drivers/clk/samsung/clk-pll.c
+127
-1
drivers/clk/samsung/clk-pll.c
···
278
278
}
279
279
280
280
/* Set PLL lock time. */
281
-
if (pll->type == pll_142xx)
281
+
if (pll->type == pll_142xx || pll->type == pll_1017x)
282
282
writel_relaxed(rate->pdiv * PLL142XX_LOCK_FACTOR,
283
283
pll->lock_reg);
284
284
else
···
1330
1330
.recalc_rate = samsung_pll531x_recalc_rate,
1331
1331
};
1332
1332
1333
+
/*
1334
+
* PLL1031x Clock Type
1335
+
*/
1336
+
#define PLL1031X_LOCK_FACTOR (500)
1337
+
1338
+
#define PLL1031X_MDIV_MASK (0x3ff)
1339
+
#define PLL1031X_PDIV_MASK (0x3f)
1340
+
#define PLL1031X_SDIV_MASK (0x7)
1341
+
#define PLL1031X_MDIV_SHIFT (16)
1342
+
#define PLL1031X_PDIV_SHIFT (8)
1343
+
#define PLL1031X_SDIV_SHIFT (0)
1344
+
1345
+
#define PLL1031X_KDIV_MASK (0xffff)
1346
+
#define PLL1031X_KDIV_SHIFT (0)
1347
+
#define PLL1031X_MFR_MASK (0x3f)
1348
+
#define PLL1031X_MRR_MASK (0x1f)
1349
+
#define PLL1031X_MFR_SHIFT (16)
1350
+
#define PLL1031X_MRR_SHIFT (24)
1351
+
1352
+
static unsigned long samsung_pll1031x_recalc_rate(struct clk_hw *hw,
1353
+
unsigned long parent_rate)
1354
+
{
1355
+
struct samsung_clk_pll *pll = to_clk_pll(hw);
1356
+
u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con3;
1357
+
u64 fvco = parent_rate;
1358
+
1359
+
pll_con0 = readl_relaxed(pll->con_reg);
1360
+
pll_con3 = readl_relaxed(pll->con_reg + 0xc);
1361
+
mdiv = (pll_con0 >> PLL1031X_MDIV_SHIFT) & PLL1031X_MDIV_MASK;
1362
+
pdiv = (pll_con0 >> PLL1031X_PDIV_SHIFT) & PLL1031X_PDIV_MASK;
1363
+
sdiv = (pll_con0 >> PLL1031X_SDIV_SHIFT) & PLL1031X_SDIV_MASK;
1364
+
kdiv = (pll_con3 & PLL1031X_KDIV_MASK);
1365
+
1366
+
fvco *= (mdiv << PLL1031X_MDIV_SHIFT) + kdiv;
1367
+
do_div(fvco, (pdiv << sdiv));
1368
+
fvco >>= PLL1031X_MDIV_SHIFT;
1369
+
1370
+
return (unsigned long)fvco;
1371
+
}
1372
+
1373
+
static bool samsung_pll1031x_mpk_change(u32 pll_con0, u32 pll_con3,
1374
+
const struct samsung_pll_rate_table *rate)
1375
+
{
1376
+
u32 old_mdiv, old_pdiv, old_kdiv;
1377
+
1378
+
old_mdiv = (pll_con0 >> PLL1031X_MDIV_SHIFT) & PLL1031X_MDIV_MASK;
1379
+
old_pdiv = (pll_con0 >> PLL1031X_PDIV_SHIFT) & PLL1031X_PDIV_MASK;
1380
+
old_kdiv = (pll_con3 >> PLL1031X_KDIV_SHIFT) & PLL1031X_KDIV_MASK;
1381
+
1382
+
return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv ||
1383
+
old_kdiv != rate->kdiv);
1384
+
}
1385
+
1386
+
static int samsung_pll1031x_set_rate(struct clk_hw *hw, unsigned long drate,
1387
+
unsigned long prate)
1388
+
{
1389
+
struct samsung_clk_pll *pll = to_clk_pll(hw);
1390
+
const struct samsung_pll_rate_table *rate;
1391
+
u32 con0, con3;
1392
+
1393
+
/* Get required rate settings from table */
1394
+
rate = samsung_get_pll_settings(pll, drate);
1395
+
if (!rate) {
1396
+
pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
1397
+
drate, clk_hw_get_name(hw));
1398
+
return -EINVAL;
1399
+
}
1400
+
1401
+
con0 = readl_relaxed(pll->con_reg);
1402
+
con3 = readl_relaxed(pll->con_reg + 0xc);
1403
+
1404
+
if (!(samsung_pll1031x_mpk_change(con0, con3, rate))) {
1405
+
/* If only s change, change just s value only */
1406
+
con0 &= ~(PLL1031X_SDIV_MASK << PLL1031X_SDIV_SHIFT);
1407
+
con0 |= rate->sdiv << PLL1031X_SDIV_SHIFT;
1408
+
writel_relaxed(con0, pll->con_reg);
1409
+
1410
+
return 0;
1411
+
}
1412
+
1413
+
/* Set PLL lock time. */
1414
+
writel_relaxed(rate->pdiv * PLL1031X_LOCK_FACTOR, pll->lock_reg);
1415
+
1416
+
/* Set PLL M, P, and S values. */
1417
+
con0 &= ~((PLL1031X_MDIV_MASK << PLL1031X_MDIV_SHIFT) |
1418
+
(PLL1031X_PDIV_MASK << PLL1031X_PDIV_SHIFT) |
1419
+
(PLL1031X_SDIV_MASK << PLL1031X_SDIV_SHIFT));
1420
+
1421
+
con0 |= (rate->mdiv << PLL1031X_MDIV_SHIFT) |
1422
+
(rate->pdiv << PLL1031X_PDIV_SHIFT) |
1423
+
(rate->sdiv << PLL1031X_SDIV_SHIFT);
1424
+
1425
+
/* Set PLL K, MFR and MRR values. */
1426
+
con3 = readl_relaxed(pll->con_reg + 0xc);
1427
+
con3 &= ~((PLL1031X_KDIV_MASK << PLL1031X_KDIV_SHIFT) |
1428
+
(PLL1031X_MFR_MASK << PLL1031X_MFR_SHIFT) |
1429
+
(PLL1031X_MRR_MASK << PLL1031X_MRR_SHIFT));
1430
+
con3 |= (rate->kdiv << PLL1031X_KDIV_SHIFT) |
1431
+
(rate->mfr << PLL1031X_MFR_SHIFT) |
1432
+
(rate->mrr << PLL1031X_MRR_SHIFT);
1433
+
1434
+
/* Write configuration to PLL */
1435
+
writel_relaxed(con0, pll->con_reg);
1436
+
writel_relaxed(con3, pll->con_reg + 0xc);
1437
+
1438
+
/* Wait for PLL lock if the PLL is enabled */
1439
+
return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
1440
+
}
1441
+
1442
+
static const struct clk_ops samsung_pll1031x_clk_ops = {
1443
+
.recalc_rate = samsung_pll1031x_recalc_rate,
1444
+
.determine_rate = samsung_pll_determine_rate,
1445
+
.set_rate = samsung_pll1031x_set_rate,
1446
+
};
1447
+
1448
+
static const struct clk_ops samsung_pll1031x_clk_min_ops = {
1449
+
.recalc_rate = samsung_pll1031x_recalc_rate,
1450
+
};
1451
+
1333
1452
static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
1334
1453
const struct samsung_pll_clock *pll_clk)
1335
1454
{
···
1497
1378
case pll_1451x:
1498
1379
case pll_1452x:
1499
1380
case pll_142xx:
1381
+
case pll_1017x:
1500
1382
pll->enable_offs = PLL35XX_ENABLE_SHIFT;
1501
1383
pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT;
1502
1384
if (!pll->rate_table)
···
1592
1472
case pll_531x:
1593
1473
case pll_4311:
1594
1474
init.ops = &samsung_pll531x_clk_ops;
1475
+
break;
1476
+
case pll_1031x:
1477
+
if (!pll->rate_table)
1478
+
init.ops = &samsung_pll1031x_clk_min_ops;
1479
+
else
1480
+
init.ops = &samsung_pll1031x_clk_ops;
1595
1481
break;
1596
1482
default:
1597
1483
pr_warn("%s: Unknown pll type for pll clk %s\n",