Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'for-v6.13/clk-dt-bindings' into next/clk
+692
+239
Documentation/devicetree/bindings/clock/samsung,exynos8895-clock.yaml
+239
Documentation/devicetree/bindings/clock/samsung,exynos8895-clock.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/samsung,exynos8895-clock.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Samsung Exynos8895 SoC clock controller
8
+
9
+
maintainers:
10
+
- Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
11
+
- Chanwoo Choi <cw00.choi@samsung.com>
12
+
- Krzysztof Kozlowski <krzk@kernel.org>
13
+
14
+
description: |
15
+
Exynos8895 clock controller is comprised of several CMU units, generating
16
+
clocks for different domains. Those CMU units are modeled as separate device
17
+
tree nodes, and might depend on each other. The root clock in that root tree
18
+
is an external clock: OSCCLK (26 MHz). This external clock must be defined
19
+
as a fixed-rate clock in dts.
20
+
21
+
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
22
+
dividers; all other clocks of function blocks (other CMUs) are usually
23
+
derived from CMU_TOP.
24
+
25
+
Each clock is assigned an identifier and client nodes can use this identifier
26
+
to specify the clock which they consume. All clocks available for usage
27
+
in clock consumer nodes are defined as preprocessor macros in
28
+
'include/dt-bindings/clock/samsung,exynos8895.h' header.
29
+
30
+
properties:
31
+
compatible:
32
+
enum:
33
+
- samsung,exynos8895-cmu-fsys0
34
+
- samsung,exynos8895-cmu-fsys1
35
+
- samsung,exynos8895-cmu-peric0
36
+
- samsung,exynos8895-cmu-peric1
37
+
- samsung,exynos8895-cmu-peris
38
+
- samsung,exynos8895-cmu-top
39
+
40
+
clocks:
41
+
minItems: 1
42
+
maxItems: 16
43
+
44
+
clock-names:
45
+
minItems: 1
46
+
maxItems: 16
47
+
48
+
"#clock-cells":
49
+
const: 1
50
+
51
+
reg:
52
+
maxItems: 1
53
+
54
+
required:
55
+
- compatible
56
+
- clocks
57
+
- clock-names
58
+
- reg
59
+
- "#clock-cells"
60
+
61
+
allOf:
62
+
- if:
63
+
properties:
64
+
compatible:
65
+
contains:
66
+
const: samsung,exynos8895-cmu-fsys0
67
+
68
+
then:
69
+
properties:
70
+
clocks:
71
+
items:
72
+
- description: External reference clock (26 MHz)
73
+
- description: CMU_FSYS0 BUS clock (from CMU_TOP)
74
+
- description: CMU_FSYS0 DPGTC clock (from CMU_TOP)
75
+
- description: CMU_FSYS0 MMC_EMBD clock (from CMU_TOP)
76
+
- description: CMU_FSYS0 UFS_EMBD clock (from CMU_TOP)
77
+
- description: CMU_FSYS0 USBDRD30 clock (from CMU_TOP)
78
+
79
+
clock-names:
80
+
items:
81
+
- const: oscclk
82
+
- const: bus
83
+
- const: dpgtc
84
+
- const: mmc
85
+
- const: ufs
86
+
- const: usbdrd30
87
+
88
+
- if:
89
+
properties:
90
+
compatible:
91
+
contains:
92
+
const: samsung,exynos8895-cmu-fsys1
93
+
94
+
then:
95
+
properties:
96
+
clocks:
97
+
items:
98
+
- description: External reference clock (26 MHz)
99
+
- description: CMU_FSYS1 BUS clock (from CMU_TOP)
100
+
- description: CMU_FSYS1 PCIE clock (from CMU_TOP)
101
+
- description: CMU_FSYS1 UFS_CARD clock (from CMU_TOP)
102
+
- description: CMU_FSYS1 MMC_CARD clock (from CMU_TOP)
103
+
104
+
clock-names:
105
+
items:
106
+
- const: oscclk
107
+
- const: bus
108
+
- const: pcie
109
+
- const: ufs
110
+
- const: mmc
111
+
112
+
- if:
113
+
properties:
114
+
compatible:
115
+
contains:
116
+
const: samsung,exynos8895-cmu-peric0
117
+
118
+
then:
119
+
properties:
120
+
clocks:
121
+
items:
122
+
- description: External reference clock (26 MHz)
123
+
- description: CMU_PERIC0 BUS clock (from CMU_TOP)
124
+
- description: CMU_PERIC0 UART_DBG clock (from CMU_TOP)
125
+
- description: CMU_PERIC0 USI00 clock (from CMU_TOP)
126
+
- description: CMU_PERIC0 USI01 clock (from CMU_TOP)
127
+
- description: CMU_PERIC0 USI02 clock (from CMU_TOP)
128
+
- description: CMU_PERIC0 USI03 clock (from CMU_TOP)
129
+
130
+
clock-names:
131
+
items:
132
+
- const: oscclk
133
+
- const: bus
134
+
- const: uart
135
+
- const: usi0
136
+
- const: usi1
137
+
- const: usi2
138
+
- const: usi3
139
+
140
+
- if:
141
+
properties:
142
+
compatible:
143
+
contains:
144
+
const: samsung,exynos8895-cmu-peric1
145
+
146
+
then:
147
+
properties:
148
+
clocks:
149
+
items:
150
+
- description: External reference clock (26 MHz)
151
+
- description: CMU_PERIC1 BUS clock (from CMU_TOP)
152
+
- description: CMU_PERIC1 SPEEDY2 clock (from CMU_TOP)
153
+
- description: CMU_PERIC1 SPI_CAM0 clock (from CMU_TOP)
154
+
- description: CMU_PERIC1 SPI_CAM1 clock (from CMU_TOP)
155
+
- description: CMU_PERIC1 UART_BT clock (from CMU_TOP)
156
+
- description: CMU_PERIC1 USI04 clock (from CMU_TOP)
157
+
- description: CMU_PERIC1 USI05 clock (from CMU_TOP)
158
+
- description: CMU_PERIC1 USI06 clock (from CMU_TOP)
159
+
- description: CMU_PERIC1 USI07 clock (from CMU_TOP)
160
+
- description: CMU_PERIC1 USI08 clock (from CMU_TOP)
161
+
- description: CMU_PERIC1 USI09 clock (from CMU_TOP)
162
+
- description: CMU_PERIC1 USI10 clock (from CMU_TOP)
163
+
- description: CMU_PERIC1 USI11 clock (from CMU_TOP)
164
+
- description: CMU_PERIC1 USI12 clock (from CMU_TOP)
165
+
- description: CMU_PERIC1 USI13 clock (from CMU_TOP)
166
+
167
+
clock-names:
168
+
items:
169
+
- const: oscclk
170
+
- const: bus
171
+
- const: speedy
172
+
- const: cam0
173
+
- const: cam1
174
+
- const: uart
175
+
- const: usi4
176
+
- const: usi5
177
+
- const: usi6
178
+
- const: usi7
179
+
- const: usi8
180
+
- const: usi9
181
+
- const: usi10
182
+
- const: usi11
183
+
- const: usi12
184
+
- const: usi13
185
+
186
+
- if:
187
+
properties:
188
+
compatible:
189
+
contains:
190
+
const: samsung,exynos8895-cmu-peris
191
+
192
+
then:
193
+
properties:
194
+
clocks:
195
+
items:
196
+
- description: External reference clock (26 MHz)
197
+
- description: CMU_PERIS BUS clock (from CMU_TOP)
198
+
199
+
clock-names:
200
+
items:
201
+
- const: oscclk
202
+
- const: bus
203
+
204
+
- if:
205
+
properties:
206
+
compatible:
207
+
contains:
208
+
const: samsung,exynos8895-cmu-top
209
+
210
+
then:
211
+
properties:
212
+
clocks:
213
+
items:
214
+
- description: External reference clock (26 MHz)
215
+
216
+
clock-names:
217
+
items:
218
+
- const: oscclk
219
+
220
+
additionalProperties: false
221
+
222
+
examples:
223
+
- |
224
+
#include <dt-bindings/clock/samsung,exynos8895.h>
225
+
226
+
cmu_fsys1: clock-controller@11400000 {
227
+
compatible = "samsung,exynos8895-cmu-fsys1";
228
+
reg = <0x11400000 0x8000>;
229
+
#clock-cells = <1>;
230
+
231
+
clocks = <&oscclk>,
232
+
<&cmu_top CLK_DOUT_CMU_FSYS1_BUS>,
233
+
<&cmu_top CLK_DOUT_CMU_FSYS1_PCIE>,
234
+
<&cmu_top CLK_DOUT_CMU_FSYS1_UFS_CARD>,
235
+
<&cmu_top CLK_DOUT_CMU_FSYS1_MMC_CARD>;
236
+
clock-names = "oscclk", "bus", "pcie", "ufs", "mmc";
237
+
};
238
+
239
+
...
+453
include/dt-bindings/clock/samsung,exynos8895.h
+453
include/dt-bindings/clock/samsung,exynos8895.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (C) 2024 Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
4
+
* Author: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
5
+
*
6
+
* Device Tree binding constants for Exynos8895 clock controller.
7
+
*/
8
+
9
+
#ifndef _DT_BINDINGS_CLOCK_EXYNOS8895_H
10
+
#define _DT_BINDINGS_CLOCK_EXYNOS8895_H
11
+
12
+
/* CMU_TOP */
13
+
#define CLK_FOUT_SHARED0_PLL 1
14
+
#define CLK_FOUT_SHARED1_PLL 2
15
+
#define CLK_FOUT_SHARED2_PLL 3
16
+
#define CLK_FOUT_SHARED3_PLL 4
17
+
#define CLK_FOUT_SHARED4_PLL 5
18
+
#define CLK_MOUT_PLL_SHARED0 6
19
+
#define CLK_MOUT_PLL_SHARED1 7
20
+
#define CLK_MOUT_PLL_SHARED2 8
21
+
#define CLK_MOUT_PLL_SHARED3 9
22
+
#define CLK_MOUT_PLL_SHARED4 10
23
+
#define CLK_MOUT_CP2AP_MIF_CLK_USER 11
24
+
#define CLK_MOUT_CMU_ABOX_CPUABOX 12
25
+
#define CLK_MOUT_CMU_APM_BUS 13
26
+
#define CLK_MOUT_CMU_BUS1_BUS 14
27
+
#define CLK_MOUT_CMU_BUSC_BUS 15
28
+
#define CLK_MOUT_CMU_BUSC_BUSPHSI2C 16
29
+
#define CLK_MOUT_CMU_CAM_BUS 17
30
+
#define CLK_MOUT_CMU_CAM_TPU0 18
31
+
#define CLK_MOUT_CMU_CAM_TPU1 19
32
+
#define CLK_MOUT_CMU_CAM_VRA 20
33
+
#define CLK_MOUT_CMU_CIS_CLK0 21
34
+
#define CLK_MOUT_CMU_CIS_CLK1 22
35
+
#define CLK_MOUT_CMU_CIS_CLK2 23
36
+
#define CLK_MOUT_CMU_CIS_CLK3 24
37
+
#define CLK_MOUT_CMU_CORE_BUS 25
38
+
#define CLK_MOUT_CMU_CPUCL0_SWITCH 26
39
+
#define CLK_MOUT_CMU_CPUCL1_SWITCH 27
40
+
#define CLK_MOUT_CMU_DBG_BUS 28
41
+
#define CLK_MOUT_CMU_DCAM_BUS 29
42
+
#define CLK_MOUT_CMU_DCAM_IMGD 30
43
+
#define CLK_MOUT_CMU_DPU_BUS 31
44
+
#define CLK_MOUT_CMU_DROOPDETECTOR 32
45
+
#define CLK_MOUT_CMU_DSP_BUS 33
46
+
#define CLK_MOUT_CMU_FSYS0_BUS 34
47
+
#define CLK_MOUT_CMU_FSYS0_DPGTC 35
48
+
#define CLK_MOUT_CMU_FSYS0_MMC_EMBD 36
49
+
#define CLK_MOUT_CMU_FSYS0_UFS_EMBD 37
50
+
#define CLK_MOUT_CMU_FSYS0_USBDRD30 38
51
+
#define CLK_MOUT_CMU_FSYS1_BUS 39
52
+
#define CLK_MOUT_CMU_FSYS1_MMC_CARD 40
53
+
#define CLK_MOUT_CMU_FSYS1_PCIE 41
54
+
#define CLK_MOUT_CMU_FSYS1_UFS_CARD 42
55
+
#define CLK_MOUT_CMU_G2D_G2D 43
56
+
#define CLK_MOUT_CMU_G2D_JPEG 44
57
+
#define CLK_MOUT_CMU_HPM 45
58
+
#define CLK_MOUT_CMU_IMEM_BUS 46
59
+
#define CLK_MOUT_CMU_ISPHQ_BUS 47
60
+
#define CLK_MOUT_CMU_ISPLP_BUS 48
61
+
#define CLK_MOUT_CMU_IVA_BUS 49
62
+
#define CLK_MOUT_CMU_MFC_BUS 50
63
+
#define CLK_MOUT_CMU_MIF_SWITCH 51
64
+
#define CLK_MOUT_CMU_PERIC0_BUS 52
65
+
#define CLK_MOUT_CMU_PERIC0_UART_DBG 53
66
+
#define CLK_MOUT_CMU_PERIC0_USI00 54
67
+
#define CLK_MOUT_CMU_PERIC0_USI01 55
68
+
#define CLK_MOUT_CMU_PERIC0_USI02 56
69
+
#define CLK_MOUT_CMU_PERIC0_USI03 57
70
+
#define CLK_MOUT_CMU_PERIC1_BUS 58
71
+
#define CLK_MOUT_CMU_PERIC1_SPEEDY2 59
72
+
#define CLK_MOUT_CMU_PERIC1_SPI_CAM0 60
73
+
#define CLK_MOUT_CMU_PERIC1_SPI_CAM1 61
74
+
#define CLK_MOUT_CMU_PERIC1_UART_BT 62
75
+
#define CLK_MOUT_CMU_PERIC1_USI04 63
76
+
#define CLK_MOUT_CMU_PERIC1_USI05 64
77
+
#define CLK_MOUT_CMU_PERIC1_USI06 65
78
+
#define CLK_MOUT_CMU_PERIC1_USI07 66
79
+
#define CLK_MOUT_CMU_PERIC1_USI08 67
80
+
#define CLK_MOUT_CMU_PERIC1_USI09 68
81
+
#define CLK_MOUT_CMU_PERIC1_USI10 69
82
+
#define CLK_MOUT_CMU_PERIC1_USI11 70
83
+
#define CLK_MOUT_CMU_PERIC1_USI12 71
84
+
#define CLK_MOUT_CMU_PERIC1_USI13 72
85
+
#define CLK_MOUT_CMU_PERIS_BUS 73
86
+
#define CLK_MOUT_CMU_SRDZ_BUS 74
87
+
#define CLK_MOUT_CMU_SRDZ_IMGD 75
88
+
#define CLK_MOUT_CMU_VPU_BUS 76
89
+
#define CLK_DOUT_CMU_ABOX_CPUABOX 77
90
+
#define CLK_DOUT_CMU_APM_BUS 78
91
+
#define CLK_DOUT_CMU_BUS1_BUS 79
92
+
#define CLK_DOUT_CMU_BUSC_BUS 80
93
+
#define CLK_DOUT_CMU_BUSC_BUSPHSI2C 81
94
+
#define CLK_DOUT_CMU_CAM_BUS 82
95
+
#define CLK_DOUT_CMU_CAM_TPU0 83
96
+
#define CLK_DOUT_CMU_CAM_TPU1 84
97
+
#define CLK_DOUT_CMU_CAM_VRA 85
98
+
#define CLK_DOUT_CMU_CIS_CLK0 86
99
+
#define CLK_DOUT_CMU_CIS_CLK1 87
100
+
#define CLK_DOUT_CMU_CIS_CLK2 88
101
+
#define CLK_DOUT_CMU_CIS_CLK3 89
102
+
#define CLK_DOUT_CMU_CORE_BUS 90
103
+
#define CLK_DOUT_CMU_CPUCL0_SWITCH 91
104
+
#define CLK_DOUT_CMU_CPUCL1_SWITCH 92
105
+
#define CLK_DOUT_CMU_DBG_BUS 93
106
+
#define CLK_DOUT_CMU_DCAM_BUS 94
107
+
#define CLK_DOUT_CMU_DCAM_IMGD 95
108
+
#define CLK_DOUT_CMU_DPU_BUS 96
109
+
#define CLK_DOUT_CMU_DSP_BUS 97
110
+
#define CLK_DOUT_CMU_FSYS0_BUS 98
111
+
#define CLK_DOUT_CMU_FSYS0_DPGTC 99
112
+
#define CLK_DOUT_CMU_FSYS0_MMC_EMBD 100
113
+
#define CLK_DOUT_CMU_FSYS0_UFS_EMBD 101
114
+
#define CLK_DOUT_CMU_FSYS0_USBDRD30 102
115
+
#define CLK_DOUT_CMU_FSYS1_BUS 103
116
+
#define CLK_DOUT_CMU_FSYS1_MMC_CARD 104
117
+
#define CLK_DOUT_CMU_FSYS1_UFS_CARD 105
118
+
#define CLK_DOUT_CMU_G2D_G2D 106
119
+
#define CLK_DOUT_CMU_G2D_JPEG 107
120
+
#define CLK_DOUT_CMU_G3D_SWITCH 108
121
+
#define CLK_DOUT_CMU_HPM 109
122
+
#define CLK_DOUT_CMU_IMEM_BUS 110
123
+
#define CLK_DOUT_CMU_ISPHQ_BUS 111
124
+
#define CLK_DOUT_CMU_ISPLP_BUS 112
125
+
#define CLK_DOUT_CMU_IVA_BUS 113
126
+
#define CLK_DOUT_CMU_MFC_BUS 114
127
+
#define CLK_DOUT_CMU_MODEM_SHARED0 115
128
+
#define CLK_DOUT_CMU_MODEM_SHARED1 116
129
+
#define CLK_DOUT_CMU_PERIC0_BUS 117
130
+
#define CLK_DOUT_CMU_PERIC0_UART_DBG 118
131
+
#define CLK_DOUT_CMU_PERIC0_USI00 119
132
+
#define CLK_DOUT_CMU_PERIC0_USI01 120
133
+
#define CLK_DOUT_CMU_PERIC0_USI02 121
134
+
#define CLK_DOUT_CMU_PERIC0_USI03 122
135
+
#define CLK_DOUT_CMU_PERIC1_BUS 123
136
+
#define CLK_DOUT_CMU_PERIC1_SPEEDY2 124
137
+
#define CLK_DOUT_CMU_PERIC1_SPI_CAM0 125
138
+
#define CLK_DOUT_CMU_PERIC1_SPI_CAM1 126
139
+
#define CLK_DOUT_CMU_PERIC1_UART_BT 127
140
+
#define CLK_DOUT_CMU_PERIC1_USI04 128
141
+
#define CLK_DOUT_CMU_PERIC1_USI05 129
142
+
#define CLK_DOUT_CMU_PERIC1_USI06 130
143
+
#define CLK_DOUT_CMU_PERIC1_USI07 131
144
+
#define CLK_DOUT_CMU_PERIC1_USI08 132
145
+
#define CLK_DOUT_CMU_PERIC1_USI09 133
146
+
#define CLK_DOUT_CMU_PERIC1_USI10 134
147
+
#define CLK_DOUT_CMU_PERIC1_USI11 135
148
+
#define CLK_DOUT_CMU_PERIC1_USI12 136
149
+
#define CLK_DOUT_CMU_PERIC1_USI13 137
150
+
#define CLK_DOUT_CMU_PERIS_BUS 138
151
+
#define CLK_DOUT_CMU_SRDZ_BUS 139
152
+
#define CLK_DOUT_CMU_SRDZ_IMGD 140
153
+
#define CLK_DOUT_CMU_VPU_BUS 141
154
+
#define CLK_DOUT_CMU_SHARED0_DIV2 142
155
+
#define CLK_DOUT_CMU_SHARED0_DIV4 143
156
+
#define CLK_DOUT_CMU_SHARED1_DIV2 144
157
+
#define CLK_DOUT_CMU_SHARED1_DIV4 145
158
+
#define CLK_DOUT_CMU_SHARED2_DIV2 146
159
+
#define CLK_DOUT_CMU_SHARED3_DIV2 147
160
+
#define CLK_DOUT_CMU_SHARED4_DIV2 148
161
+
#define CLK_DOUT_CMU_FSYS1_PCIE 149
162
+
#define CLK_DOUT_CMU_CP2AP_MIF_CLK_DIV2 150
163
+
#define CLK_DOUT_CMU_CMU_OTP 151
164
+
#define CLK_GOUT_CMU_DROOPDETECTOR 152
165
+
#define CLK_GOUT_CMU_MIF_SWITCH 153
166
+
#define CLK_GOUT_CMU_ABOX_CPUABOX 154
167
+
#define CLK_GOUT_CMU_APM_BUS 155
168
+
#define CLK_GOUT_CMU_BUS1_BUS 156
169
+
#define CLK_GOUT_CMU_BUSC_BUS 157
170
+
#define CLK_GOUT_CMU_BUSC_BUSPHSI2C 158
171
+
#define CLK_GOUT_CMU_CAM_BUS 159
172
+
#define CLK_GOUT_CMU_CAM_TPU0 160
173
+
#define CLK_GOUT_CMU_CAM_TPU1 161
174
+
#define CLK_GOUT_CMU_CAM_VRA 162
175
+
#define CLK_GOUT_CMU_CIS_CLK0 163
176
+
#define CLK_GOUT_CMU_CIS_CLK1 164
177
+
#define CLK_GOUT_CMU_CIS_CLK2 165
178
+
#define CLK_GOUT_CMU_CIS_CLK3 166
179
+
#define CLK_GOUT_CMU_CORE_BUS 167
180
+
#define CLK_GOUT_CMU_CPUCL0_SWITCH 168
181
+
#define CLK_GOUT_CMU_CPUCL1_SWITCH 169
182
+
#define CLK_GOUT_CMU_DBG_BUS 170
183
+
#define CLK_GOUT_CMU_DCAM_BUS 171
184
+
#define CLK_GOUT_CMU_DCAM_IMGD 172
185
+
#define CLK_GOUT_CMU_DPU_BUS 173
186
+
#define CLK_GOUT_CMU_DSP_BUS 174
187
+
#define CLK_GOUT_CMU_FSYS0_BUS 175
188
+
#define CLK_GOUT_CMU_FSYS0_DPGTC 176
189
+
#define CLK_GOUT_CMU_FSYS0_MMC_EMBD 177
190
+
#define CLK_GOUT_CMU_FSYS0_UFS_EMBD 178
191
+
#define CLK_GOUT_CMU_FSYS0_USBDRD30 179
192
+
#define CLK_GOUT_CMU_FSYS1_BUS 180
193
+
#define CLK_GOUT_CMU_FSYS1_MMC_CARD 181
194
+
#define CLK_GOUT_CMU_FSYS1_PCIE 182
195
+
#define CLK_GOUT_CMU_FSYS1_UFS_CARD 183
196
+
#define CLK_GOUT_CMU_G2D_G2D 184
197
+
#define CLK_GOUT_CMU_G2D_JPEG 185
198
+
#define CLK_GOUT_CMU_G3D_SWITCH 186
199
+
#define CLK_GOUT_CMU_HPM 187
200
+
#define CLK_GOUT_CMU_IMEM_BUS 188
201
+
#define CLK_GOUT_CMU_ISPHQ_BUS 189
202
+
#define CLK_GOUT_CMU_ISPLP_BUS 190
203
+
#define CLK_GOUT_CMU_IVA_BUS 191
204
+
#define CLK_GOUT_CMU_MFC_BUS 192
205
+
#define CLK_GOUT_CMU_MODEM_SHARED0 193
206
+
#define CLK_GOUT_CMU_MODEM_SHARED1 194
207
+
#define CLK_GOUT_CMU_PERIC0_BUS 195
208
+
#define CLK_GOUT_CMU_PERIC0_UART_DBG 196
209
+
#define CLK_GOUT_CMU_PERIC0_USI00 197
210
+
#define CLK_GOUT_CMU_PERIC0_USI01 198
211
+
#define CLK_GOUT_CMU_PERIC0_USI02 199
212
+
#define CLK_GOUT_CMU_PERIC0_USI03 200
213
+
#define CLK_GOUT_CMU_PERIC1_BUS 201
214
+
#define CLK_GOUT_CMU_PERIC1_SPEEDY2 202
215
+
#define CLK_GOUT_CMU_PERIC1_SPI_CAM0 203
216
+
#define CLK_GOUT_CMU_PERIC1_SPI_CAM1 204
217
+
#define CLK_GOUT_CMU_PERIC1_UART_BT 205
218
+
#define CLK_GOUT_CMU_PERIC1_USI04 206
219
+
#define CLK_GOUT_CMU_PERIC1_USI05 207
220
+
#define CLK_GOUT_CMU_PERIC1_USI06 208
221
+
#define CLK_GOUT_CMU_PERIC1_USI07 209
222
+
#define CLK_GOUT_CMU_PERIC1_USI08 210
223
+
#define CLK_GOUT_CMU_PERIC1_USI09 211
224
+
#define CLK_GOUT_CMU_PERIC1_USI10 212
225
+
#define CLK_GOUT_CMU_PERIC1_USI11 213
226
+
#define CLK_GOUT_CMU_PERIC1_USI12 214
227
+
#define CLK_GOUT_CMU_PERIC1_USI13 215
228
+
#define CLK_GOUT_CMU_PERIS_BUS 216
229
+
#define CLK_GOUT_CMU_SRDZ_BUS 217
230
+
#define CLK_GOUT_CMU_SRDZ_IMGD 218
231
+
#define CLK_GOUT_CMU_VPU_BUS 219
232
+
233
+
/* CMU_PERIS */
234
+
#define CLK_MOUT_PERIS_BUS_USER 1
235
+
#define CLK_MOUT_PERIS_GIC 2
236
+
#define CLK_GOUT_PERIS_CMU_PERIS_PCLK 3
237
+
#define CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKM 4
238
+
#define CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKS 5
239
+
#define CLK_GOUT_PERIS_AXI2APB_PERISP0_ACLK 6
240
+
#define CLK_GOUT_PERIS_AXI2APB_PERISP1_ACLK 7
241
+
#define CLK_GOUT_PERIS_BUSIF_TMU_PCLK 8
242
+
#define CLK_GOUT_PERIS_GIC_CLK 9
243
+
#define CLK_GOUT_PERIS_LHM_AXI_P_PERIS_I_CLK 10
244
+
#define CLK_GOUT_PERIS_MCT_PCLK 11
245
+
#define CLK_GOUT_PERIS_OTP_CON_BIRA_PCLK 12
246
+
#define CLK_GOUT_PERIS_OTP_CON_TOP_PCLK 13
247
+
#define CLK_GOUT_PERIS_PMU_PERIS_PCLK 14
248
+
#define CLK_GOUT_PERIS_RSTNSYNC_CLK_PERIS_BUSP_CLK 15
249
+
#define CLK_GOUT_PERIS_RSTNSYNC_CLK_PERIS_GIC_CLK 16
250
+
#define CLK_GOUT_PERIS_SYSREG_PERIS_PCLK 17
251
+
#define CLK_GOUT_PERIS_TZPC00_PCLK 18
252
+
#define CLK_GOUT_PERIS_TZPC01_PCLK 19
253
+
#define CLK_GOUT_PERIS_TZPC02_PCLK 20
254
+
#define CLK_GOUT_PERIS_TZPC03_PCLK 21
255
+
#define CLK_GOUT_PERIS_TZPC04_PCLK 22
256
+
#define CLK_GOUT_PERIS_TZPC05_PCLK 23
257
+
#define CLK_GOUT_PERIS_TZPC06_PCLK 24
258
+
#define CLK_GOUT_PERIS_TZPC07_PCLK 25
259
+
#define CLK_GOUT_PERIS_TZPC08_PCLK 26
260
+
#define CLK_GOUT_PERIS_TZPC09_PCLK 27
261
+
#define CLK_GOUT_PERIS_TZPC10_PCLK 28
262
+
#define CLK_GOUT_PERIS_TZPC11_PCLK 29
263
+
#define CLK_GOUT_PERIS_TZPC12_PCLK 30
264
+
#define CLK_GOUT_PERIS_TZPC13_PCLK 31
265
+
#define CLK_GOUT_PERIS_TZPC14_PCLK 32
266
+
#define CLK_GOUT_PERIS_TZPC15_PCLK 33
267
+
#define CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK 34
268
+
#define CLK_GOUT_PERIS_WDT_CLUSTER1_PCLK 35
269
+
#define CLK_GOUT_PERIS_XIU_P_PERIS_ACLK 36
270
+
271
+
/* CMU_FSYS0 */
272
+
#define CLK_MOUT_FSYS0_BUS_USER 1
273
+
#define CLK_MOUT_FSYS0_DPGTC_USER 2
274
+
#define CLK_MOUT_FSYS0_MMC_EMBD_USER 3
275
+
#define CLK_MOUT_FSYS0_UFS_EMBD_USER 4
276
+
#define CLK_MOUT_FSYS0_USBDRD30_USER 5
277
+
#define CLK_GOUT_FSYS0_FSYS0_CMU_FSYS0_PCLK 6
278
+
#define CLK_GOUT_FSYS0_AHBBR_FSYS0_HCLK 7
279
+
#define CLK_GOUT_FSYS0_AXI2AHB_FSYS0_ACLK 8
280
+
#define CLK_GOUT_FSYS0_AXI2AHB_USB_FSYS0_ACLK 9
281
+
#define CLK_GOUT_FSYS0_AXI2APB_FSYS0_ACLK 10
282
+
#define CLK_GOUT_FSYS0_BTM_FSYS0_I_ACLK 11
283
+
#define CLK_GOUT_FSYS0_BTM_FSYS0_I_PCLK 12
284
+
#define CLK_GOUT_FSYS0_DP_LINK_I_GTC_EXT_CLK 13
285
+
#define CLK_GOUT_FSYS0_DP_LINK_I_PCLK 14
286
+
#define CLK_GOUT_FSYS0_ETR_MIU_I_ACLK 15
287
+
#define CLK_GOUT_FSYS0_ETR_MIU_I_PCLK 16
288
+
#define CLK_GOUT_FSYS0_GPIO_FSYS0_PCLK 17
289
+
#define CLK_GOUT_FSYS0_LHM_AXI_D_USBTV_I_CLK 18
290
+
#define CLK_GOUT_FSYS0_LHM_AXI_G_ETR_I_CLK 19
291
+
#define CLK_GOUT_FSYS0_LHM_AXI_P_FSYS0_I_CLK 20
292
+
#define CLK_GOUT_FSYS0_LHS_ACEL_D_FSYS0_I_CLK 21
293
+
#define CLK_GOUT_FSYS0_MMC_EMBD_I_ACLK 22
294
+
#define CLK_GOUT_FSYS0_MMC_EMBD_SDCLKIN 23
295
+
#define CLK_GOUT_FSYS0_PMU_FSYS0_PCLK 24
296
+
#define CLK_GOUT_FSYS0_BCM_FSYS0_ACLK 25
297
+
#define CLK_GOUT_FSYS0_BCM_FSYS0_PCLK 26
298
+
#define CLK_GOUT_FSYS0_RSTNSYNC_CLK_FSYS0_BUS_CLK 27
299
+
#define CLK_GOUT_FSYS0_SYSREG_FSYS0_PCLK 28
300
+
#define CLK_GOUT_FSYS0_UFS_EMBD_I_ACLK 29
301
+
#define CLK_GOUT_FSYS0_UFS_EMBD_I_CLK_UNIPRO 30
302
+
#define CLK_GOUT_FSYS0_UFS_EMBD_I_FMP_CLK 31
303
+
#define CLK_GOUT_FSYS0_USBTV_I_USB30DRD_ACLK 32
304
+
#define CLK_GOUT_FSYS0_USBTV_I_USB30DRD_REF_CLK 33
305
+
#define CLK_GOUT_FSYS0_USBTV_I_USB30DRD_SUSPEND_CLK 34
306
+
#define CLK_GOUT_FSYS0_USBTV_I_USBTVH_AHB_CLK 35
307
+
#define CLK_GOUT_FSYS0_USBTV_I_USBTVH_CORE_CLK 36
308
+
#define CLK_GOUT_FSYS0_USBTV_I_USBTVH_XIU_CLK 37
309
+
#define CLK_GOUT_FSYS0_US_D_FSYS0_USB_ACLK 38
310
+
#define CLK_GOUT_FSYS0_XIU_D_FSYS0_ACLK 39
311
+
#define CLK_GOUT_FSYS0_XIU_D_FSYS0_USB_ACLK 40
312
+
#define CLK_GOUT_FSYS0_XIU_P_FSYS0_ACLK 41
313
+
314
+
/* CMU_FSYS1 */
315
+
#define CLK_MOUT_FSYS1_BUS_USER 1
316
+
#define CLK_MOUT_FSYS1_MMC_CARD_USER 2
317
+
#define CLK_MOUT_FSYS1_PCIE_USER 3
318
+
#define CLK_MOUT_FSYS1_UFS_CARD_USER 4
319
+
#define CLK_GOUT_FSYS1_PCIE_PHY_REF_CLK_IN 5
320
+
#define CLK_GOUT_FSYS1_ADM_AHB_SSS_HCLKM 6
321
+
#define CLK_GOUT_FSYS1_AHBBR_FSYS1_HCLK 7
322
+
#define CLK_GOUT_FSYS1_AXI2AHB_FSYS1_ACLK 8
323
+
#define CLK_GOUT_FSYS1_AXI2APB_FSYS1P0_ACLK 9
324
+
#define CLK_GOUT_FSYS1_AXI2APB_FSYS1P1_ACLK 10
325
+
#define CLK_GOUT_FSYS1_BTM_FSYS1_I_ACLK 11
326
+
#define CLK_GOUT_FSYS1_BTM_FSYS1_I_PCLK 12
327
+
#define CLK_GOUT_FSYS1_FSYS1_CMU_FSYS1_PCLK 13
328
+
#define CLK_GOUT_FSYS1_GPIO_FSYS1_PCLK 14
329
+
#define CLK_GOUT_FSYS1_LHM_AXI_P_FSYS1_I_CLK 15
330
+
#define CLK_GOUT_FSYS1_LHS_ACEL_D_FSYS1_I_CLK 16
331
+
#define CLK_GOUT_FSYS1_MMC_CARD_I_ACLK 17
332
+
#define CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN 18
333
+
#define CLK_GOUT_FSYS1_PCIE_DBI_ACLK_0 19
334
+
#define CLK_GOUT_FSYS1_PCIE_DBI_ACLK_1 20
335
+
#define CLK_GOUT_FSYS1_PCIE_IEEE1500_WRAPPER_FOR_PCIE_PHY_LC_X2_INST_0_I_SCL_APB_PCLK 21
336
+
#define CLK_GOUT_FSYS1_PCIE_MSTR_ACLK_0 22
337
+
#define CLK_GOUT_FSYS1_PCIE_MSTR_ACLK_1 23
338
+
#define CLK_GOUT_FSYS1_PCIE_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 24
339
+
#define CLK_GOUT_FSYS1_PCIE_PCIE_SUB_CTRL_INST_1_I_DRIVER_APB_CLK 25
340
+
#define CLK_GOUT_FSYS1_PCIE_PIPE2_DIGITAL_X2_WRAP_INST_0_I_APB_PCLK_SCL 26
341
+
#define CLK_GOUT_FSYS1_PCIE_SLV_ACLK_0 27
342
+
#define CLK_GOUT_FSYS1_PCIE_SLV_ACLK_1 28
343
+
#define CLK_GOUT_FSYS1_PMU_FSYS1_PCLK 29
344
+
#define CLK_GOUT_FSYS1_BCM_FSYS1_ACLK 30
345
+
#define CLK_GOUT_FSYS1_BCM_FSYS1_PCLK 31
346
+
#define CLK_GOUT_FSYS1_RSTNSYNC_CLK_FSYS1_BUS_CLK 32
347
+
#define CLK_GOUT_FSYS1_RTIC_I_ACLK 33
348
+
#define CLK_GOUT_FSYS1_RTIC_I_PCLK 34
349
+
#define CLK_GOUT_FSYS1_SSS_I_ACLK 35
350
+
#define CLK_GOUT_FSYS1_SSS_I_PCLK 36
351
+
#define CLK_GOUT_FSYS1_SYSREG_FSYS1_PCLK 37
352
+
#define CLK_GOUT_FSYS1_TOE_WIFI0_I_CLK 38
353
+
#define CLK_GOUT_FSYS1_TOE_WIFI1_I_CLK 39
354
+
#define CLK_GOUT_FSYS1_UFS_CARD_I_ACLK 40
355
+
#define CLK_GOUT_FSYS1_UFS_CARD_I_CLK_UNIPRO 41
356
+
#define CLK_GOUT_FSYS1_UFS_CARD_I_FMP_CLK 42
357
+
#define CLK_GOUT_FSYS1_XIU_D_FSYS1_ACLK 43
358
+
#define CLK_GOUT_FSYS1_XIU_P_FSYS1_ACLK 44
359
+
360
+
/* CMU_PERIC0 */
361
+
#define CLK_MOUT_PERIC0_BUS_USER 1
362
+
#define CLK_MOUT_PERIC0_UART_DBG_USER 2
363
+
#define CLK_MOUT_PERIC0_USI00_USER 3
364
+
#define CLK_MOUT_PERIC0_USI01_USER 4
365
+
#define CLK_MOUT_PERIC0_USI02_USER 5
366
+
#define CLK_MOUT_PERIC0_USI03_USER 6
367
+
#define CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK 7
368
+
#define CLK_GOUT_PERIC0_AXI2APB_PERIC0_ACLK 8
369
+
#define CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK 9
370
+
#define CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK 10
371
+
#define CLK_GOUT_PERIC0_PMU_PERIC0_PCLK 11
372
+
#define CLK_GOUT_PERIC0_PWM_I_PCLK_S0 12
373
+
#define CLK_GOUT_PERIC0_RSTNSYNC_CLK_PERIC0_BUSP_CLK 13
374
+
#define CLK_GOUT_PERIC0_SPEEDY2_TSP_CLK 14
375
+
#define CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK 15
376
+
#define CLK_GOUT_PERIC0_UART_DBG_EXT_UCLK 16
377
+
#define CLK_GOUT_PERIC0_UART_DBG_PCLK 17
378
+
#define CLK_GOUT_PERIC0_USI00_I_PCLK 18
379
+
#define CLK_GOUT_PERIC0_USI00_I_SCLK_USI 19
380
+
#define CLK_GOUT_PERIC0_USI01_I_PCLK 20
381
+
#define CLK_GOUT_PERIC0_USI01_I_SCLK_USI 21
382
+
#define CLK_GOUT_PERIC0_USI02_I_PCLK 22
383
+
#define CLK_GOUT_PERIC0_USI02_I_SCLK_USI 23
384
+
#define CLK_GOUT_PERIC0_USI03_I_PCLK 24
385
+
#define CLK_GOUT_PERIC0_USI03_I_SCLK_USI 25
386
+
387
+
/* CMU_PERIC1 */
388
+
#define CLK_MOUT_PERIC1_BUS_USER 1
389
+
#define CLK_MOUT_PERIC1_SPEEDY2_USER 2
390
+
#define CLK_MOUT_PERIC1_SPI_CAM0_USER 3
391
+
#define CLK_MOUT_PERIC1_SPI_CAM1_USER 4
392
+
#define CLK_MOUT_PERIC1_UART_BT_USER 5
393
+
#define CLK_MOUT_PERIC1_USI04_USER 6
394
+
#define CLK_MOUT_PERIC1_USI05_USER 7
395
+
#define CLK_MOUT_PERIC1_USI06_USER 8
396
+
#define CLK_MOUT_PERIC1_USI07_USER 9
397
+
#define CLK_MOUT_PERIC1_USI08_USER 10
398
+
#define CLK_MOUT_PERIC1_USI09_USER 11
399
+
#define CLK_MOUT_PERIC1_USI10_USER 12
400
+
#define CLK_MOUT_PERIC1_USI11_USER 13
401
+
#define CLK_MOUT_PERIC1_USI12_USER 14
402
+
#define CLK_MOUT_PERIC1_USI13_USER 15
403
+
#define CLK_GOUT_PERIC1_PERIC1_CMU_PERIC1_PCLK 16
404
+
#define CLK_GOUT_PERIC1_RSTNSYNC_CLK_PERIC1_SPEEDY2_CLK 17
405
+
#define CLK_GOUT_PERIC1_AXI2APB_PERIC1P0_ACLK 18
406
+
#define CLK_GOUT_PERIC1_AXI2APB_PERIC1P1_ACLK 19
407
+
#define CLK_GOUT_PERIC1_AXI2APB_PERIC1P2_ACLK 20
408
+
#define CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK 21
409
+
#define CLK_GOUT_PERIC1_HSI2C_CAM0_IPCLK 22
410
+
#define CLK_GOUT_PERIC1_HSI2C_CAM1_IPCLK 23
411
+
#define CLK_GOUT_PERIC1_HSI2C_CAM2_IPCLK 24
412
+
#define CLK_GOUT_PERIC1_HSI2C_CAM3_IPCLK 25
413
+
#define CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK 26
414
+
#define CLK_GOUT_PERIC1_PMU_PERIC1_PCLK 27
415
+
#define CLK_GOUT_PERIC1_RSTNSYNC_CLK_PERIC1_BUSP_CLK 28
416
+
#define CLK_GOUT_PERIC1_SPEEDY2_DDI1_CLK 29
417
+
#define CLK_GOUT_PERIC1_SPEEDY2_DDI1_SCLK 30
418
+
#define CLK_GOUT_PERIC1_SPEEDY2_DDI2_CLK 31
419
+
#define CLK_GOUT_PERIC1_SPEEDY2_DDI2_SCLK 32
420
+
#define CLK_GOUT_PERIC1_SPEEDY2_DDI_CLK 33
421
+
#define CLK_GOUT_PERIC1_SPEEDY2_DDI_SCLK 34
422
+
#define CLK_GOUT_PERIC1_SPEEDY2_TSP1_CLK 35
423
+
#define CLK_GOUT_PERIC1_SPEEDY2_TSP2_CLK 36
424
+
#define CLK_GOUT_PERIC1_SPI_CAM0_PCLK 37
425
+
#define CLK_GOUT_PERIC1_SPI_CAM0_SPI_EXT_CLK 38
426
+
#define CLK_GOUT_PERIC1_SPI_CAM1_PCLK 39
427
+
#define CLK_GOUT_PERIC1_SPI_CAM1_SPI_EXT_CLK 40
428
+
#define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK 41
429
+
#define CLK_GOUT_PERIC1_UART_BT_EXT_UCLK 42
430
+
#define CLK_GOUT_PERIC1_UART_BT_PCLK 43
431
+
#define CLK_GOUT_PERIC1_USI04_I_PCLK 44
432
+
#define CLK_GOUT_PERIC1_USI04_I_SCLK_USI 45
433
+
#define CLK_GOUT_PERIC1_USI05_I_PCLK 46
434
+
#define CLK_GOUT_PERIC1_USI05_I_SCLK_USI 47
435
+
#define CLK_GOUT_PERIC1_USI06_I_PCLK 48
436
+
#define CLK_GOUT_PERIC1_USI06_I_SCLK_USI 49
437
+
#define CLK_GOUT_PERIC1_USI07_I_PCLK 50
438
+
#define CLK_GOUT_PERIC1_USI07_I_SCLK_USI 51
439
+
#define CLK_GOUT_PERIC1_USI08_I_PCLK 52
440
+
#define CLK_GOUT_PERIC1_USI08_I_SCLK_USI 53
441
+
#define CLK_GOUT_PERIC1_USI09_I_PCLK 54
442
+
#define CLK_GOUT_PERIC1_USI09_I_SCLK_USI 55
443
+
#define CLK_GOUT_PERIC1_USI10_I_PCLK 56
444
+
#define CLK_GOUT_PERIC1_USI10_I_SCLK_USI 57
445
+
#define CLK_GOUT_PERIC1_USI11_I_PCLK 58
446
+
#define CLK_GOUT_PERIC1_USI11_I_SCLK_USI 59
447
+
#define CLK_GOUT_PERIC1_USI12_I_PCLK 60
448
+
#define CLK_GOUT_PERIC1_USI12_I_SCLK_USI 61
449
+
#define CLK_GOUT_PERIC1_USI13_I_PCLK 62
450
+
#define CLK_GOUT_PERIC1_USI13_I_SCLK_USI 63
451
+
#define CLK_GOUT_PERIC1_XIU_P_PERIC1_ACLK 64
452
+
453
+
#endif /* _DT_BINDINGS_CLOCK_EXYNOS8895_H */