Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux
Tariq Toukan says:
====================
mlx5-next updates 2025-07-08
The following pull-request contains common mlx5 updates
for your *net-next* tree.
v2: https://lore.kernel.org/1751574385-24672-1-git-send-email-tariqt@nvidia.com
* 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux:
net/mlx5: Check device memory pointer before usage
net/mlx5: fs, fix RDMA TRANSPORT init cleanup flow
net/mlx5: Add IFC bits for PCIe Congestion Event object
net/mlx5: Small refactor for general object capabilities
net/mlx5: fs, add multiple prios to RDMA TRANSPORT steering domain
====================
Link: https://patch.msgid.link/1752002102-11316-1-git-send-email-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+96
-26
+1
-1
drivers/infiniband/hw/mlx5/dm.c
+1
-1
drivers/infiniband/hw/mlx5/dm.c
+36
-8
drivers/net/ethernet/mellanox/mlx5/core/fs_core.c
+36
-8
drivers/net/ethernet/mellanox/mlx5/core/fs_core.c
···
3245
3245
init_rdma_transport_rx_root_ns_one(struct mlx5_flow_steering *steering,
3246
3246
int vport_idx)
3247
3247
{
3248
+
struct mlx5_flow_root_namespace *root_ns;
3248
3249
struct fs_prio *prio;
3250
+
int ret;
3251
+
int i;
3249
3252
3250
3253
steering->rdma_transport_rx_root_ns[vport_idx] =
3251
3254
create_root_ns(steering, FS_FT_RDMA_TRANSPORT_RX);
3252
3255
if (!steering->rdma_transport_rx_root_ns[vport_idx])
3253
3256
return -ENOMEM;
3254
3257
3255
-
/* create 1 prio*/
3256
-
prio = fs_create_prio(&steering->rdma_transport_rx_root_ns[vport_idx]->ns,
3257
-
MLX5_RDMA_TRANSPORT_BYPASS_PRIO, 1);
3258
-
return PTR_ERR_OR_ZERO(prio);
3258
+
root_ns = steering->rdma_transport_rx_root_ns[vport_idx];
3259
+
3260
+
for (i = 0; i < MLX5_RDMA_TRANSPORT_BYPASS_PRIO; i++) {
3261
+
prio = fs_create_prio(&root_ns->ns, i, 1);
3262
+
if (IS_ERR(prio)) {
3263
+
ret = PTR_ERR(prio);
3264
+
goto err;
3265
+
}
3266
+
}
3267
+
set_prio_attrs(root_ns);
3268
+
return 0;
3269
+
3270
+
err:
3271
+
cleanup_root_ns(root_ns);
3272
+
return ret;
3259
3273
}
3260
3274
3261
3275
static int
3262
3276
init_rdma_transport_tx_root_ns_one(struct mlx5_flow_steering *steering,
3263
3277
int vport_idx)
3264
3278
{
3279
+
struct mlx5_flow_root_namespace *root_ns;
3265
3280
struct fs_prio *prio;
3281
+
int ret;
3282
+
int i;
3266
3283
3267
3284
steering->rdma_transport_tx_root_ns[vport_idx] =
3268
3285
create_root_ns(steering, FS_FT_RDMA_TRANSPORT_TX);
3269
3286
if (!steering->rdma_transport_tx_root_ns[vport_idx])
3270
3287
return -ENOMEM;
3271
3288
3272
-
/* create 1 prio*/
3273
-
prio = fs_create_prio(&steering->rdma_transport_tx_root_ns[vport_idx]->ns,
3274
-
MLX5_RDMA_TRANSPORT_BYPASS_PRIO, 1);
3275
-
return PTR_ERR_OR_ZERO(prio);
3289
+
root_ns = steering->rdma_transport_tx_root_ns[vport_idx];
3290
+
3291
+
for (i = 0; i < MLX5_RDMA_TRANSPORT_BYPASS_PRIO; i++) {
3292
+
prio = fs_create_prio(&root_ns->ns, i, 1);
3293
+
if (IS_ERR(prio)) {
3294
+
ret = PTR_ERR(prio);
3295
+
goto err;
3296
+
}
3297
+
}
3298
+
set_prio_attrs(root_ns);
3299
+
return 0;
3300
+
3301
+
err:
3302
+
cleanup_root_ns(root_ns);
3303
+
return ret;
3276
3304
}
3277
3305
3278
3306
static int init_rdma_transport_rx_root_ns(struct mlx5_flow_steering *steering)
+2
-2
drivers/net/ethernet/mellanox/mlx5/core/lib/dm.c
+2
-2
drivers/net/ethernet/mellanox/mlx5/core/lib/dm.c
···
30
30
31
31
dm = kzalloc(sizeof(*dm), GFP_KERNEL);
32
32
if (!dm)
33
-
return ERR_PTR(-ENOMEM);
33
+
return NULL;
34
34
35
35
spin_lock_init(&dm->lock);
36
36
···
96
96
err_steering:
97
97
kfree(dm);
98
98
99
-
return ERR_PTR(-ENOMEM);
99
+
return NULL;
100
100
}
101
101
102
102
void mlx5_dm_cleanup(struct mlx5_core_dev *dev)
-3
drivers/net/ethernet/mellanox/mlx5/core/main.c
-3
drivers/net/ethernet/mellanox/mlx5/core/main.c
···
1102
1102
}
1103
1103
1104
1104
dev->dm = mlx5_dm_create(dev);
1105
-
if (IS_ERR(dev->dm))
1106
-
mlx5_core_warn(dev, "Failed to init device memory %ld\n", PTR_ERR(dev->dm));
1107
-
1108
1105
dev->tracer = mlx5_fw_tracer_create(dev);
1109
1106
dev->hv_vhca = mlx5_hv_vhca_create(dev);
1110
1107
dev->rsc_dump = mlx5_rsc_dump_create(dev);
+1
-1
include/linux/mlx5/fs.h
+1
-1
include/linux/mlx5/fs.h
+56
-11
include/linux/mlx5/mlx5_ifc.h
+56
-11
include/linux/mlx5/mlx5_ifc.h
···
12502
12502
};
12503
12503
12504
12504
enum {
12505
-
MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
12506
-
MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
12507
-
MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
12508
-
MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24),
12509
-
};
12510
-
12511
-
enum {
12512
-
MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL = BIT_ULL(0x13),
12513
-
};
12514
-
12515
-
enum {
12516
12505
MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
12517
12506
MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
12518
12507
MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
···
12509
12520
MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27,
12510
12521
MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47,
12511
12522
MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL = 0x53,
12523
+
MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT = 0x58,
12512
12524
MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15,
12525
+
};
12526
+
12527
+
enum {
12528
+
MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY =
12529
+
BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY),
12530
+
MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC =
12531
+
BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_IPSEC),
12532
+
MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER =
12533
+
BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_SAMPLER),
12534
+
MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO =
12535
+
BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO),
12536
+
};
12537
+
12538
+
enum {
12539
+
MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL =
12540
+
BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL - 0x40),
12541
+
MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT =
12542
+
BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT - 0x40),
12513
12543
};
12514
12544
12515
12545
enum {
···
13285
13277
u8 rt_clock_identity[0x40];
13286
13278
13287
13279
u8 reserved_at_80[0x180];
13280
+
};
13281
+
13282
+
struct mlx5_ifc_pcie_cong_event_obj_bits {
13283
+
u8 modify_select_field[0x40];
13284
+
13285
+
u8 inbound_event_en[0x1];
13286
+
u8 outbound_event_en[0x1];
13287
+
u8 reserved_at_42[0x1e];
13288
+
13289
+
u8 reserved_at_60[0x1];
13290
+
u8 inbound_cong_state[0x3];
13291
+
u8 reserved_at_64[0x1];
13292
+
u8 outbound_cong_state[0x3];
13293
+
u8 reserved_at_68[0x18];
13294
+
13295
+
u8 inbound_cong_low_threshold[0x10];
13296
+
u8 inbound_cong_high_threshold[0x10];
13297
+
13298
+
u8 outbound_cong_low_threshold[0x10];
13299
+
u8 outbound_cong_high_threshold[0x10];
13300
+
13301
+
u8 reserved_at_e0[0x340];
13302
+
};
13303
+
13304
+
struct mlx5_ifc_pcie_cong_event_cmd_in_bits {
13305
+
struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
13306
+
struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj;
13307
+
};
13308
+
13309
+
struct mlx5_ifc_pcie_cong_event_cmd_out_bits {
13310
+
struct mlx5_ifc_general_obj_out_cmd_hdr_bits hdr;
13311
+
struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj;
13312
+
};
13313
+
13314
+
enum mlx5e_pcie_cong_event_mod_field {
13315
+
MLX5_PCIE_CONG_EVENT_MOD_EVENT_EN = BIT(0),
13316
+
MLX5_PCIE_CONG_EVENT_MOD_THRESH = BIT(2),
13288
13317
};
13289
13318
13290
13319
#endif /* MLX5_IFC_H */