tjh.dev / kernel
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Merge tag 'pci-v6.11-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci

Pull pci fixes from Bjorn Helgaas:

- Add Manivannan Sadhasivam as PCI native host bridge and endpoint
driver reviewer (Manivannan Sadhasivam)

- Disable MHI RAM data parity error interrupt for qcom SA8775P SoC to
work around hardware erratum that causes a constant stream of
interrupts (Manivannan Sadhasivam)

- Don't try to fall back to qcom Operating Performance Points (OPP)
support unless the platform actually supports OPP (Manivannan
Sadhasivam)

- Add imx@lists.linux.dev mailing list to MAINTAINERS for NXP
layerscape and imx6 PCI controller drivers (Frank Li)

* tag 'pci-v6.11-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci:
MAINTAINERS: PCI: Add NXP PCI controller mailing list imx@lists.linux.dev
PCI: qcom: Use OPP only if the platform supports it
PCI: qcom-ep: Disable MHI RAM data parity error interrupt for SA8775P SoC
MAINTAINERS: Add Manivannan Sadhasivam as Reviewer for PCI native host bridge and endpoint drivers

Linus Torvalds 8101b276 216d1631

+21 -2
+3
MAINTAINERS
··· 17439 17439 L: linuxppc-dev@lists.ozlabs.org 17440 17440 L: linux-pci@vger.kernel.org 17441 17441 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 17442 + L: imx@lists.linux.dev 17442 17443 S: Maintained 17443 17444 F: drivers/pci/controller/dwc/*layerscape* 17444 17445 ··· 17466 17465 M: Lucas Stach <l.stach@pengutronix.de> 17467 17466 L: linux-pci@vger.kernel.org 17468 17467 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 17468 + L: imx@lists.linux.dev 17469 17469 S: Maintained 17470 17470 F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml 17471 17471 F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml ··· 17645 17643 PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS 17646 17644 M: Lorenzo Pieralisi <lpieralisi@kernel.org> 17647 17645 M: Krzysztof Wilczyński <kw@linux.com> 17646 + R: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 17648 17647 R: Rob Herring <robh@kernel.org> 17649 17648 L: linux-pci@vger.kernel.org 17650 17649 S: Supported
+13
drivers/pci/controller/dwc/pcie-qcom-ep.c
··· 58 58 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88 59 59 #define PARF_DEVICE_TYPE 0x1000 60 60 #define PARF_BDF_TO_SID_CFG 0x2c00 61 + #define PARF_INT_ALL_5_MASK 0x2dcc 61 62 62 63 /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */ 63 64 #define PARF_INT_ALL_LINK_DOWN BIT(1) ··· 128 127 /* PARF_CFG_BITS register fields */ 129 128 #define PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN BIT(1) 130 129 130 + /* PARF_INT_ALL_5_MASK fields */ 131 + #define PARF_INT_ALL_5_MHI_RAM_DATA_PARITY_ERR BIT(0) 132 + 131 133 /* ELBI registers */ 132 134 #define ELBI_SYS_STTS 0x08 133 135 #define ELBI_CS2_ENABLE 0xa4 ··· 162 158 * struct qcom_pcie_ep_cfg - Per SoC config struct 163 159 * @hdma_support: HDMA support on this SoC 164 160 * @override_no_snoop: Override NO_SNOOP attribute in TLP to enable cache snooping 161 + * @disable_mhi_ram_parity_check: Disable MHI RAM data parity error check 165 162 */ 166 163 struct qcom_pcie_ep_cfg { 167 164 bool hdma_support; 168 165 bool override_no_snoop; 166 + bool disable_mhi_ram_parity_check; 169 167 }; 170 168 171 169 /** ··· 485 479 PARF_INT_ALL_PM_TURNOFF | PARF_INT_ALL_DSTATE_CHANGE | 486 480 PARF_INT_ALL_LINK_UP | PARF_INT_ALL_EDMA; 487 481 writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK); 482 + 483 + if (pcie_ep->cfg && pcie_ep->cfg->disable_mhi_ram_parity_check) { 484 + val = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_5_MASK); 485 + val &= ~PARF_INT_ALL_5_MHI_RAM_DATA_PARITY_ERR; 486 + writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_5_MASK); 487 + } 488 488 489 489 ret = dw_pcie_ep_init_registers(&pcie_ep->pci.ep); 490 490 if (ret) { ··· 913 901 static const struct qcom_pcie_ep_cfg cfg_1_34_0 = { 914 902 .hdma_support = true, 915 903 .override_no_snoop = true, 904 + .disable_mhi_ram_parity_check = true, 916 905 }; 917 906 918 907 static const struct of_device_id qcom_pcie_ep_match[] = {
+5 -2
drivers/pci/controller/dwc/pcie-qcom.c
··· 261 261 const struct qcom_pcie_cfg *cfg; 262 262 struct dentry *debugfs; 263 263 bool suspended; 264 + bool use_pm_opp; 264 265 }; 265 266 266 267 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) ··· 1434 1433 dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", 1435 1434 ret); 1436 1435 } 1437 - } else { 1436 + } else if (pcie->use_pm_opp) { 1438 1437 freq_mbps = pcie_dev_speed_mbps(pcie_link_speed[speed]); 1439 1438 if (freq_mbps < 0) 1440 1439 return; ··· 1593 1592 max_freq); 1594 1593 goto err_pm_runtime_put; 1595 1594 } 1595 + 1596 + pcie->use_pm_opp = true; 1596 1597 } else { 1597 1598 /* Skip ICC init if OPP is supported as it is handled by OPP */ 1598 1599 ret = qcom_pcie_icc_init(pcie); ··· 1686 1683 if (ret) 1687 1684 dev_err(dev, "Failed to disable CPU-PCIe interconnect path: %d\n", ret); 1688 1685 1689 - if (!pcie->icc_mem) 1686 + if (pcie->use_pm_opp) 1690 1687 dev_pm_opp_set_opp(pcie->pci->dev, NULL); 1691 1688 } 1692 1689 return ret;