Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm: dpu: Add tracing around CTL_FLUSH
I found these tracepoints useful for debugging cursor/ctl, someone else
might find them useful too
Reviewed-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
+65
-8
+18
-8
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+18
-8
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
···
15
15
#include "dpu_hw_ctl.h"
16
16
#include "dpu_dbg.h"
17
17
#include "dpu_kms.h"
18
+
#include "dpu_trace.h"
18
19
19
20
#define CTL_LAYER(lm) \
20
21
(((lm) == LM_5) ? (0x024) : (((lm) - LM_0) * 0x004))
···
73
72
return stages;
74
73
}
75
74
75
+
static inline u32 dpu_hw_ctl_get_flush_register(struct dpu_hw_ctl *ctx)
76
+
{
77
+
struct dpu_hw_blk_reg_map *c = &ctx->hw;
78
+
79
+
return DPU_REG_READ(c, CTL_FLUSH);
80
+
}
81
+
76
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static inline void dpu_hw_ctl_trigger_start(struct dpu_hw_ctl *ctx)
77
83
{
84
+
trace_dpu_hw_ctl_trigger_start(ctx->pending_flush_mask,
85
+
dpu_hw_ctl_get_flush_register(ctx));
78
86
DPU_REG_WRITE(&ctx->hw, CTL_START, 0x1);
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}
80
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81
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static inline void dpu_hw_ctl_trigger_pending(struct dpu_hw_ctl *ctx)
82
90
{
91
+
trace_dpu_hw_ctl_trigger_prepare(ctx->pending_flush_mask,
92
+
dpu_hw_ctl_get_flush_register(ctx));
83
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DPU_REG_WRITE(&ctx->hw, CTL_PREPARE, 0x1);
84
94
}
85
95
86
96
static inline void dpu_hw_ctl_clear_pending_flush(struct dpu_hw_ctl *ctx)
87
97
{
98
+
trace_dpu_hw_ctl_clear_pending_flush(ctx->pending_flush_mask,
99
+
dpu_hw_ctl_get_flush_register(ctx));
88
100
ctx->pending_flush_mask = 0x0;
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101
}
90
102
91
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static inline void dpu_hw_ctl_update_pending_flush(struct dpu_hw_ctl *ctx,
92
104
u32 flushbits)
93
105
{
106
+
trace_dpu_hw_ctl_update_pending_flush(flushbits,
107
+
ctx->pending_flush_mask);
94
108
ctx->pending_flush_mask |= flushbits;
95
109
}
96
110
···
119
103
120
104
static inline void dpu_hw_ctl_trigger_flush(struct dpu_hw_ctl *ctx)
121
105
{
122
-
106
+
trace_dpu_hw_ctl_trigger_pending_flush(ctx->pending_flush_mask,
107
+
dpu_hw_ctl_get_flush_register(ctx));
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108
DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask);
124
-
}
125
-
126
-
static inline u32 dpu_hw_ctl_get_flush_register(struct dpu_hw_ctl *ctx)
127
-
{
128
-
struct dpu_hw_blk_reg_map *c = &ctx->hw;
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-
130
-
return DPU_REG_READ(c, CTL_FLUSH);
131
109
}
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111
static inline uint32_t dpu_hw_ctl_get_bitmask_sspp(struct dpu_hw_ctl *ctx,
+47
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+47
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
···
1004
1004
__entry->stop_req ? "true" : "false", __entry->clk_rate)
1005
1005
);
1006
1006
1007
+
TRACE_EVENT(dpu_hw_ctl_update_pending_flush,
1008
+
TP_PROTO(u32 new_bits, u32 pending_mask),
1009
+
TP_ARGS(new_bits, pending_mask),
1010
+
TP_STRUCT__entry(
1011
+
__field( u32, new_bits )
1012
+
__field( u32, pending_mask )
1013
+
),
1014
+
TP_fast_assign(
1015
+
__entry->new_bits = new_bits;
1016
+
__entry->pending_mask = pending_mask;
1017
+
),
1018
+
TP_printk("new=%x existing=%x", __entry->new_bits,
1019
+
__entry->pending_mask)
1020
+
);
1021
+
1022
+
DECLARE_EVENT_CLASS(dpu_hw_ctl_pending_flush_template,
1023
+
TP_PROTO(u32 pending_mask, u32 ctl_flush),
1024
+
TP_ARGS(pending_mask, ctl_flush),
1025
+
TP_STRUCT__entry(
1026
+
__field( u32, pending_mask )
1027
+
__field( u32, ctl_flush )
1028
+
),
1029
+
TP_fast_assign(
1030
+
__entry->pending_mask = pending_mask;
1031
+
__entry->ctl_flush = ctl_flush;
1032
+
),
1033
+
TP_printk("pending_mask=%x CTL_FLUSH=%x", __entry->pending_mask,
1034
+
__entry->ctl_flush)
1035
+
);
1036
+
DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_clear_pending_flush,
1037
+
TP_PROTO(u32 pending_mask, u32 ctl_flush),
1038
+
TP_ARGS(pending_mask, ctl_flush)
1039
+
);
1040
+
DEFINE_EVENT(dpu_hw_ctl_pending_flush_template,
1041
+
dpu_hw_ctl_trigger_pending_flush,
1042
+
TP_PROTO(u32 pending_mask, u32 ctl_flush),
1043
+
TP_ARGS(pending_mask, ctl_flush)
1044
+
);
1045
+
DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_trigger_prepare,
1046
+
TP_PROTO(u32 pending_mask, u32 ctl_flush),
1047
+
TP_ARGS(pending_mask, ctl_flush)
1048
+
);
1049
+
DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_trigger_start,
1050
+
TP_PROTO(u32 pending_mask, u32 ctl_flush),
1051
+
TP_ARGS(pending_mask, ctl_flush)
1052
+
);
1053
+
1007
1054
#define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0)
1008
1055
#define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1)
1009
1056
#define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__)