Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/dp: convert to struct intel_display
Going forward, struct intel_display is the main device data structure
for display. Switch to it internally in DP code.
v2/v3: Rebase
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/d712a2894addde5fd7a8b593fbea87314df37e1f.1734083244.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+359
-325
+359
-325
drivers/gpu/drm/i915/display/intel_dp.c
+359
-325
drivers/gpu/drm/i915/display/intel_dp.c
···
94
94
#include "intel_vrr.h"
95
95
#include "intel_crtc_state_dump.h"
96
96
97
-
#define dp_to_i915(__intel_dp) to_i915(dp_to_dig_port(__intel_dp)->base.base.dev)
98
-
99
97
/* DP DSC throughput values used for slice count calculations KPixels/s */
100
98
#define DP_DSC_PEAK_PIXEL_RATE 2720000
101
99
#define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
···
265
267
266
268
static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
267
269
{
270
+
struct intel_display *display = to_intel_display(intel_dp);
268
271
struct intel_connector *connector = intel_dp->attached_connector;
269
272
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
270
273
struct intel_encoder *encoder = &intel_dig_port->base;
···
275
276
if (intel_dp->num_sink_rates)
276
277
return;
277
278
278
-
drm_err(&dp_to_i915(intel_dp)->drm,
279
+
drm_err(display->drm,
279
280
"[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",
280
281
connector->base.base.id, connector->base.name,
281
282
encoder->base.base.id, encoder->base.name);
···
290
291
291
292
static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
292
293
{
294
+
struct intel_display *display = to_intel_display(intel_dp);
293
295
struct intel_connector *connector = intel_dp->attached_connector;
294
296
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
295
297
struct intel_encoder *encoder = &intel_dig_port->base;
···
304
304
return;
305
305
}
306
306
307
-
drm_err(&dp_to_i915(intel_dp)->drm,
307
+
drm_err(display->drm,
308
308
"[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",
309
309
connector->base.base.id, connector->base.name,
310
310
encoder->base.base.id, encoder->base.name,
···
337
337
338
338
int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
339
339
{
340
-
if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
340
+
struct intel_display *display = to_intel_display(intel_dp);
341
+
342
+
if (drm_WARN_ON(display->drm,
341
343
index < 0 || index >= intel_dp->num_common_rates))
342
344
return 162000;
343
345
···
466
464
467
465
bool intel_dp_has_joiner(struct intel_dp *intel_dp)
468
466
{
467
+
struct intel_display *display = to_intel_display(intel_dp);
469
468
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
470
469
struct intel_encoder *encoder = &intel_dig_port->base;
471
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
472
470
473
471
/* eDP MSO is not compatible with joiner */
474
472
if (intel_dp->mso_link_count)
475
473
return false;
476
474
477
-
return DISPLAY_VER(dev_priv) >= 12 ||
478
-
(DISPLAY_VER(dev_priv) == 11 &&
475
+
return DISPLAY_VER(display) >= 12 ||
476
+
(DISPLAY_VER(display) == 11 &&
479
477
encoder->port != PORT_A);
480
478
}
481
479
···
504
502
505
503
static int mtl_max_source_rate(struct intel_dp *intel_dp)
506
504
{
505
+
struct intel_display *display = to_intel_display(intel_dp);
507
506
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
508
507
509
508
if (intel_encoder_is_c10phy(encoder))
510
509
return 810000;
511
510
512
-
if (DISPLAY_VERx100(to_i915(encoder->base.dev)) == 1401)
511
+
if (DISPLAY_VERx100(display) == 1401)
513
512
return 1350000;
514
513
515
514
return 2000000;
···
564
561
static const int g4x_rates[] = {
565
562
162000, 270000
566
563
};
567
-
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
568
-
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
564
+
struct intel_display *display = to_intel_display(intel_dp);
569
565
const int *source_rates;
570
566
int size, max_rate = 0, vbt_max_rate;
571
567
572
568
/* This should only be done once */
573
-
drm_WARN_ON(&dev_priv->drm,
569
+
drm_WARN_ON(display->drm,
574
570
intel_dp->source_rates || intel_dp->num_source_rates);
575
571
576
-
if (DISPLAY_VER(dev_priv) >= 14) {
577
-
if (IS_BATTLEMAGE(dev_priv)) {
572
+
if (DISPLAY_VER(display) >= 14) {
573
+
if (display->platform.battlemage) {
578
574
source_rates = bmg_rates;
579
575
size = ARRAY_SIZE(bmg_rates);
580
576
} else {
···
581
579
size = ARRAY_SIZE(mtl_rates);
582
580
}
583
581
max_rate = mtl_max_source_rate(intel_dp);
584
-
} else if (DISPLAY_VER(dev_priv) >= 11) {
582
+
} else if (DISPLAY_VER(display) >= 11) {
585
583
source_rates = icl_rates;
586
584
size = ARRAY_SIZE(icl_rates);
587
-
if (IS_DG2(dev_priv))
585
+
if (display->platform.dg2)
588
586
max_rate = dg2_max_source_rate(intel_dp);
589
-
else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
590
-
IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
587
+
else if (display->platform.alderlake_p || display->platform.alderlake_s ||
588
+
display->platform.dg1 || display->platform.rocketlake)
591
589
max_rate = 810000;
592
-
else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
590
+
else if (display->platform.jasperlake || display->platform.elkhartlake)
593
591
max_rate = ehl_max_source_rate(intel_dp);
594
592
else
595
593
max_rate = icl_max_source_rate(intel_dp);
596
-
} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
594
+
} else if (display->platform.geminilake || display->platform.broxton) {
597
595
source_rates = bxt_rates;
598
596
size = ARRAY_SIZE(bxt_rates);
599
-
} else if (DISPLAY_VER(dev_priv) == 9) {
597
+
} else if (DISPLAY_VER(display) == 9) {
600
598
source_rates = skl_rates;
601
599
size = ARRAY_SIZE(skl_rates);
602
-
} else if ((IS_HASWELL(dev_priv) && !IS_HASWELL_ULX(dev_priv)) ||
603
-
IS_BROADWELL(dev_priv)) {
600
+
} else if ((display->platform.haswell && !display->platform.haswell_ulx) ||
601
+
display->platform.broadwell) {
604
602
source_rates = hsw_rates;
605
603
size = ARRAY_SIZE(hsw_rates);
606
604
} else {
···
691
689
692
690
static void intel_dp_link_config_init(struct intel_dp *intel_dp)
693
691
{
694
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
692
+
struct intel_display *display = to_intel_display(intel_dp);
695
693
struct intel_dp_link_config *lc;
696
694
int num_common_lane_configs;
697
695
int i;
698
696
int j;
699
697
700
-
if (drm_WARN_ON(&i915->drm, !is_power_of_2(intel_dp_max_common_lane_count(intel_dp))))
698
+
if (drm_WARN_ON(display->drm, !is_power_of_2(intel_dp_max_common_lane_count(intel_dp))))
701
699
return;
702
700
703
701
num_common_lane_configs = ilog2(intel_dp_max_common_lane_count(intel_dp)) + 1;
704
702
705
-
if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates * num_common_lane_configs >
703
+
if (drm_WARN_ON(display->drm, intel_dp->num_common_rates * num_common_lane_configs >
706
704
ARRAY_SIZE(intel_dp->link.configs)))
707
705
return;
708
706
···
726
724
727
725
void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count)
728
726
{
729
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
727
+
struct intel_display *display = to_intel_display(intel_dp);
730
728
const struct intel_dp_link_config *lc;
731
729
732
-
if (drm_WARN_ON(&i915->drm, idx < 0 || idx >= intel_dp->link.num_configs))
730
+
if (drm_WARN_ON(display->drm, idx < 0 || idx >= intel_dp->link.num_configs))
733
731
idx = 0;
734
732
735
733
lc = &intel_dp->link.configs[idx];
···
758
756
759
757
static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
760
758
{
761
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
759
+
struct intel_display *display = to_intel_display(intel_dp);
762
760
763
-
drm_WARN_ON(&i915->drm,
761
+
drm_WARN_ON(display->drm,
764
762
!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
765
763
766
764
intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
···
770
768
intel_dp->common_rates);
771
769
772
770
/* Paranoia, there should always be something in common. */
773
-
if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
771
+
if (drm_WARN_ON(display->drm, intel_dp->num_common_rates == 0)) {
774
772
intel_dp->common_rates[0] = 162000;
775
773
intel_dp->num_common_rates = 1;
776
774
}
···
818
816
}
819
817
820
818
static int
821
-
small_joiner_ram_size_bits(struct drm_i915_private *i915)
819
+
small_joiner_ram_size_bits(struct intel_display *display)
822
820
{
823
-
if (DISPLAY_VER(i915) >= 13)
821
+
if (DISPLAY_VER(display) >= 13)
824
822
return 17280 * 8;
825
-
else if (DISPLAY_VER(i915) >= 11)
823
+
else if (DISPLAY_VER(display) >= 11)
826
824
return 7680 * 8;
827
825
else
828
826
return 6144 * 8;
···
830
828
831
829
u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp)
832
830
{
831
+
struct intel_display *display = &i915->display;
833
832
u32 bits_per_pixel = bpp;
834
833
int i;
835
834
836
835
/* Error out if the max bpp is less than smallest allowed valid bpp */
837
836
if (bits_per_pixel < valid_dsc_bpp[0]) {
838
-
drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
837
+
drm_dbg_kms(display->drm, "Unsupported BPP %u, min %u\n",
839
838
bits_per_pixel, valid_dsc_bpp[0]);
840
839
return 0;
841
840
}
842
841
843
842
/* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
844
-
if (DISPLAY_VER(i915) >= 13) {
843
+
if (DISPLAY_VER(display) >= 13) {
845
844
bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
846
845
847
846
/*
···
854
851
* DSC enabled.
855
852
*/
856
853
if (bits_per_pixel < 8) {
857
-
drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min 8\n",
854
+
drm_dbg_kms(display->drm,
855
+
"Unsupported BPP %u, min 8\n",
858
856
bits_per_pixel);
859
857
return 0;
860
858
}
···
866
862
if (bits_per_pixel < valid_dsc_bpp[i + 1])
867
863
break;
868
864
}
869
-
drm_dbg_kms(&i915->drm, "Set dsc bpp from %d to VESA %d\n",
865
+
drm_dbg_kms(display->drm, "Set dsc bpp from %d to VESA %d\n",
870
866
bits_per_pixel, valid_dsc_bpp[i]);
871
867
872
868
bits_per_pixel = valid_dsc_bpp[i];
···
901
897
u32 mode_hdisplay,
902
898
int num_joined_pipes)
903
899
{
904
-
struct drm_i915_private *i915 = to_i915(display->drm);
905
900
u32 max_bpp;
906
901
907
902
/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
908
-
max_bpp = small_joiner_ram_size_bits(i915) / mode_hdisplay;
903
+
max_bpp = small_joiner_ram_size_bits(display) / mode_hdisplay;
909
904
910
905
max_bpp *= num_joined_pipes;
911
906
···
922
919
}
923
920
924
921
static
925
-
u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915,
922
+
u32 get_max_compressed_bpp_with_joiner(struct intel_display *display,
926
923
u32 mode_clock, u32 mode_hdisplay,
927
924
int num_joined_pipes)
928
925
{
929
-
struct intel_display *display = to_intel_display(&i915->drm);
930
926
u32 max_bpp = small_joiner_ram_max_bpp(display, mode_hdisplay, num_joined_pipes);
931
927
932
928
if (num_joined_pipes > 1)
···
945
943
u32 pipe_bpp,
946
944
u32 timeslots)
947
945
{
946
+
struct intel_display *display = &i915->display;
948
947
u32 bits_per_pixel, joiner_max_bpp;
949
948
950
949
/*
···
980
977
if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
981
978
bits_per_pixel = min_t(u32, bits_per_pixel, 31);
982
979
983
-
drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
980
+
drm_dbg_kms(display->drm, "Max link bpp is %u for %u timeslots "
984
981
"total bw %u pixel clock %u\n",
985
982
bits_per_pixel, timeslots,
986
983
(link_clock * lane_count * 8),
987
984
intel_dp_mode_to_fec_clock(mode_clock));
988
985
989
-
joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, mode_clock,
986
+
joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, mode_clock,
990
987
mode_hdisplay, num_joined_pipes);
991
988
bits_per_pixel = min(bits_per_pixel, joiner_max_bpp);
992
989
···
999
996
int mode_clock, int mode_hdisplay,
1000
997
int num_joined_pipes)
1001
998
{
1002
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
999
+
struct intel_display *display = to_intel_display(connector);
1003
1000
u8 min_slice_count, i;
1004
1001
int max_slice_width;
1005
1002
···
1014
1011
* Due to some DSC engine BW limitations, we need to enable second
1015
1012
* slice and VDSC engine, whenever we approach close enough to max CDCLK
1016
1013
*/
1017
-
if (mode_clock >= ((i915->display.cdclk.max_cdclk_freq * 85) / 100))
1014
+
if (mode_clock >= ((display->cdclk.max_cdclk_freq * 85) / 100))
1018
1015
min_slice_count = max_t(u8, min_slice_count, 2);
1019
1016
1020
1017
max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd);
1021
1018
if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
1022
-
drm_dbg_kms(&i915->drm,
1019
+
drm_dbg_kms(display->drm,
1023
1020
"Unsupported slice width %d by DP DSC Sink device\n",
1024
1021
max_slice_width);
1025
1022
return 0;
···
1059
1056
return test_slice_count;
1060
1057
}
1061
1058
1062
-
drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
1059
+
drm_dbg_kms(display->drm, "Unsupported Slice Count %d\n",
1063
1060
min_slice_count);
1064
1061
return 0;
1065
1062
}
···
1067
1064
static bool source_can_output(struct intel_dp *intel_dp,
1068
1065
enum intel_output_format format)
1069
1066
{
1070
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1067
+
struct intel_display *display = to_intel_display(intel_dp);
1071
1068
1072
1069
switch (format) {
1073
1070
case INTEL_OUTPUT_FORMAT_RGB:
···
1079
1076
* Also, ILK doesn't seem capable of DP YCbCr output.
1080
1077
* The displayed image is severly corrupted. SNB+ is fine.
1081
1078
*/
1082
-
return !HAS_GMCH(i915) && !IS_IRONLAKE(i915);
1079
+
return !HAS_GMCH(display) && !display->platform.ironlake;
1083
1080
1084
1081
case INTEL_OUTPUT_FORMAT_YCBCR420:
1085
1082
/* Platform < Gen 11 cannot output YCbCr420 format */
1086
-
return DISPLAY_VER(i915) >= 11;
1083
+
return DISPLAY_VER(display) >= 11;
1087
1084
1088
1085
default:
1089
1086
MISSING_CASE(format);
···
1143
1140
intel_dp_output_format(struct intel_connector *connector,
1144
1141
enum intel_output_format sink_format)
1145
1142
{
1143
+
struct intel_display *display = to_intel_display(connector);
1146
1144
struct intel_dp *intel_dp = intel_attached_dp(connector);
1147
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1148
1145
enum intel_output_format force_dsc_output_format =
1149
1146
intel_dp->force_dsc_output_format;
1150
1147
enum intel_output_format output_format;
···
1155
1152
dfp_can_convert(intel_dp, force_dsc_output_format, sink_format)))
1156
1153
return force_dsc_output_format;
1157
1154
1158
-
drm_dbg_kms(&i915->drm, "Cannot force DSC output format\n");
1155
+
drm_dbg_kms(display->drm, "Cannot force DSC output format\n");
1159
1156
}
1160
1157
1161
1158
if (sink_format == INTEL_OUTPUT_FORMAT_RGB ||
···
1169
1166
else
1170
1167
output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1171
1168
1172
-
drm_WARN_ON(&i915->drm, !source_can_output(intel_dp, output_format));
1169
+
drm_WARN_ON(display->drm, !source_can_output(intel_dp, output_format));
1173
1170
1174
1171
return output_format;
1175
1172
}
···
1220
1217
return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
1221
1218
}
1222
1219
1223
-
static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
1220
+
static bool intel_dp_hdisplay_bad(struct intel_display *display,
1224
1221
int hdisplay)
1225
1222
{
1226
1223
/*
···
1236
1233
*
1237
1234
* TODO: confirm the behaviour on HSW+
1238
1235
*/
1239
-
return hdisplay == 4096 && !HAS_DDI(dev_priv);
1236
+
return hdisplay == 4096 && !HAS_DDI(display);
1240
1237
}
1241
1238
1242
1239
static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
···
1337
1334
int hdisplay, int clock,
1338
1335
int num_joined_pipes)
1339
1336
{
1340
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1337
+
struct intel_display *display = to_intel_display(intel_dp);
1341
1338
int hdisplay_limit;
1342
1339
1343
1340
if (!intel_dp_has_joiner(intel_dp))
···
1345
1342
1346
1343
num_joined_pipes /= 2;
1347
1344
1348
-
hdisplay_limit = DISPLAY_VER(i915) >= 30 ? 6144 : 5120;
1345
+
hdisplay_limit = DISPLAY_VER(display) >= 30 ? 6144 : 5120;
1349
1346
1350
-
return clock > num_joined_pipes * i915->display.cdclk.max_dotclk_freq ||
1347
+
return clock > num_joined_pipes * display->cdclk.max_dotclk_freq ||
1351
1348
hdisplay > num_joined_pipes * hdisplay_limit;
1352
1349
}
1353
1350
···
1373
1370
1374
1371
bool intel_dp_has_dsc(const struct intel_connector *connector)
1375
1372
{
1376
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
1373
+
struct intel_display *display = to_intel_display(connector);
1377
1374
1378
-
if (!HAS_DSC(i915))
1375
+
if (!HAS_DSC(display))
1379
1376
return false;
1380
1377
1381
-
if (connector->mst_port && !HAS_DSC_MST(i915))
1378
+
if (connector->mst_port && !HAS_DSC_MST(display))
1382
1379
return false;
1383
1380
1384
1381
if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP &&
···
1395
1392
intel_dp_mode_valid(struct drm_connector *_connector,
1396
1393
struct drm_display_mode *mode)
1397
1394
{
1395
+
struct intel_display *display = to_intel_display(_connector->dev);
1398
1396
struct intel_connector *connector = to_intel_connector(_connector);
1399
1397
struct intel_dp *intel_dp = intel_attached_dp(connector);
1400
1398
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1401
1399
const struct drm_display_mode *fixed_mode;
1402
1400
int target_clock = mode->clock;
1403
1401
int max_rate, mode_rate, max_lanes, max_link_clock;
1404
-
int max_dotclk = dev_priv->display.cdclk.max_dotclk_freq;
1402
+
int max_dotclk = display->cdclk.max_dotclk_freq;
1405
1403
u16 dsc_max_compressed_bpp = 0;
1406
1404
u8 dsc_slice_count = 0;
1407
1405
enum drm_mode_status status;
···
1435
1431
if (target_clock > max_dotclk)
1436
1432
return MODE_CLOCK_HIGH;
1437
1433
1438
-
if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
1434
+
if (intel_dp_hdisplay_bad(display, mode->hdisplay))
1439
1435
return MODE_H_ILLEGAL;
1440
1436
1441
1437
max_link_clock = intel_dp_max_link_rate(intel_dp);
···
1503
1499
1504
1500
bool intel_dp_source_supports_tps3(struct drm_i915_private *i915)
1505
1501
{
1506
-
return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915);
1502
+
struct intel_display *display = &i915->display;
1503
+
1504
+
return DISPLAY_VER(display) >= 9 ||
1505
+
display->platform.broadwell || display->platform.haswell;
1507
1506
}
1508
1507
1509
1508
bool intel_dp_source_supports_tps4(struct drm_i915_private *i915)
1510
1509
{
1511
-
return DISPLAY_VER(i915) >= 10;
1510
+
struct intel_display *display = &i915->display;
1511
+
1512
+
return DISPLAY_VER(display) >= 10;
1512
1513
}
1513
1514
1514
1515
static void seq_buf_print_array(struct seq_buf *s, const int *array, int nelem)
···
1578
1569
1579
1570
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1580
1571
{
1581
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1572
+
struct intel_display *display = to_intel_display(intel_dp);
1582
1573
int i = intel_dp_rate_index(intel_dp->sink_rates,
1583
1574
intel_dp->num_sink_rates, rate);
1584
1575
1585
-
if (drm_WARN_ON(&i915->drm, i < 0))
1576
+
if (drm_WARN_ON(display->drm, i < 0))
1586
1577
i = 0;
1587
1578
1588
1579
return i;
···
1612
1603
static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1613
1604
const struct intel_crtc_state *pipe_config)
1614
1605
{
1606
+
struct intel_display *display = to_intel_display(intel_dp);
1615
1607
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1616
-
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1617
1608
1618
-
if (DISPLAY_VER(dev_priv) >= 12)
1609
+
if (DISPLAY_VER(display) >= 12)
1619
1610
return true;
1620
1611
1621
-
if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A &&
1612
+
if (DISPLAY_VER(display) == 11 && encoder->port != PORT_A &&
1622
1613
!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
1623
1614
return true;
1624
1615
···
1681
1672
const struct intel_crtc_state *crtc_state,
1682
1673
bool respect_downstream_limits)
1683
1674
{
1684
-
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1675
+
struct intel_display *display = to_intel_display(intel_dp);
1685
1676
struct intel_connector *connector = intel_dp->attached_connector;
1686
1677
int bpp, bpc;
1687
1678
···
1707
1698
if (connector->base.display_info.bpc == 0 &&
1708
1699
connector->panel.vbt.edp.bpp &&
1709
1700
connector->panel.vbt.edp.bpp < bpp) {
1710
-
drm_dbg_kms(&dev_priv->drm,
1701
+
drm_dbg_kms(display->drm,
1711
1702
"clamping bpp for eDP panel to BIOS-provided %i\n",
1712
1703
connector->panel.vbt.edp.bpp);
1713
1704
bpp = connector->panel.vbt.edp.bpp;
···
1788
1779
}
1789
1780
1790
1781
static
1791
-
u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
1782
+
u8 intel_dp_dsc_max_src_input_bpc(struct intel_display *display)
1792
1783
{
1793
1784
/* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1794
-
if (DISPLAY_VER(i915) >= 12)
1785
+
if (DISPLAY_VER(display) >= 12)
1795
1786
return 12;
1796
-
if (DISPLAY_VER(i915) == 11)
1787
+
if (DISPLAY_VER(display) == 11)
1797
1788
return 10;
1798
1789
1799
1790
return 0;
···
1802
1793
int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
1803
1794
u8 max_req_bpc)
1804
1795
{
1805
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
1796
+
struct intel_display *display = to_intel_display(connector);
1806
1797
int i, num_bpc;
1807
1798
u8 dsc_bpc[3] = {};
1808
1799
u8 dsc_max_bpc;
1809
1800
1810
-
dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
1801
+
dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
1811
1802
1812
1803
if (!dsc_max_bpc)
1813
1804
return dsc_max_bpc;
···
1824
1815
return 0;
1825
1816
}
1826
1817
1827
-
static int intel_dp_source_dsc_version_minor(struct drm_i915_private *i915)
1818
+
static int intel_dp_source_dsc_version_minor(struct intel_display *display)
1828
1819
{
1829
-
return DISPLAY_VER(i915) >= 14 ? 2 : 1;
1820
+
return DISPLAY_VER(display) >= 14 ? 2 : 1;
1830
1821
}
1831
1822
1832
1823
static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
···
1860
1851
static int intel_dp_dsc_compute_params(const struct intel_connector *connector,
1861
1852
struct intel_crtc_state *crtc_state)
1862
1853
{
1863
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
1854
+
struct intel_display *display = to_intel_display(connector);
1864
1855
struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1865
1856
int ret;
1866
1857
···
1883
1874
(connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1884
1875
DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1885
1876
vdsc_cfg->dsc_version_minor =
1886
-
min(intel_dp_source_dsc_version_minor(i915),
1877
+
min(intel_dp_source_dsc_version_minor(display),
1887
1878
intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd));
1888
1879
if (vdsc_cfg->convert_rgb)
1889
1880
vdsc_cfg->convert_rgb =
···
1893
1884
vdsc_cfg->line_buf_depth = min(INTEL_DP_DSC_MAX_LINE_BUF_DEPTH,
1894
1885
drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd));
1895
1886
if (!vdsc_cfg->line_buf_depth) {
1896
-
drm_dbg_kms(&i915->drm,
1887
+
drm_dbg_kms(display->drm,
1897
1888
"DSC Sink Line Buffer Depth invalid\n");
1898
1889
return -EINVAL;
1899
1890
}
···
1908
1899
static bool intel_dp_dsc_supports_format(const struct intel_connector *connector,
1909
1900
enum intel_output_format output_format)
1910
1901
{
1911
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
1902
+
struct intel_display *display = to_intel_display(connector);
1912
1903
u8 sink_dsc_format;
1913
1904
1914
1905
switch (output_format) {
···
1919
1910
sink_dsc_format = DP_DSC_YCbCr444;
1920
1911
break;
1921
1912
case INTEL_OUTPUT_FORMAT_YCBCR420:
1922
-
if (min(intel_dp_source_dsc_version_minor(i915),
1913
+
if (min(intel_dp_source_dsc_version_minor(display),
1923
1914
intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2)
1924
1915
return false;
1925
1916
sink_dsc_format = DP_DSC_YCbCr420_Native;
···
2038
2029
2039
2030
static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp)
2040
2031
{
2041
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2032
+
struct intel_display *display = to_intel_display(intel_dp);
2042
2033
2043
2034
/*
2044
2035
* Forcing DSC and using the platform's max compressed bpp is seen to cause
···
2053
2044
* Max Compressed bpp for Gen 13+ is 27bpp.
2054
2045
* For earlier platform is 23bpp. (Bspec:49259).
2055
2046
*/
2056
-
if (DISPLAY_VER(i915) < 13)
2047
+
if (DISPLAY_VER(display) < 13)
2057
2048
return 23;
2058
2049
else
2059
2050
return 27;
···
2114
2105
int pipe_bpp,
2115
2106
int timeslots)
2116
2107
{
2108
+
struct intel_display *display = to_intel_display(intel_dp);
2117
2109
u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd);
2118
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2119
2110
u16 compressed_bppx16;
2120
2111
u8 bppx16_step;
2121
2112
int ret;
2122
2113
2123
-
if (DISPLAY_VER(i915) < 14 || bppx16_incr <= 1)
2114
+
if (DISPLAY_VER(display) < 14 || bppx16_incr <= 1)
2124
2115
bppx16_step = 16;
2125
2116
else
2126
2117
bppx16_step = 16 / bppx16_incr;
···
2144
2135
pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16;
2145
2136
if (intel_dp->force_dsc_fractional_bpp_en &&
2146
2137
fxp_q4_to_frac(compressed_bppx16))
2147
-
drm_dbg_kms(&i915->drm, "Forcing DSC fractional bpp\n");
2138
+
drm_dbg_kms(display->drm,
2139
+
"Forcing DSC fractional bpp\n");
2148
2140
2149
2141
return 0;
2150
2142
}
···
2160
2150
int pipe_bpp,
2161
2151
int timeslots)
2162
2152
{
2153
+
struct intel_display *display = to_intel_display(intel_dp);
2163
2154
const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2164
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2165
2155
int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
2166
2156
int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
2167
2157
int dsc_joiner_max_bpp;
···
2178
2168
pipe_bpp / 3);
2179
2169
dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
2180
2170
2181
-
dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,
2171
+
dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, adjusted_mode->clock,
2182
2172
adjusted_mode->hdisplay,
2183
2173
num_joined_pipes);
2184
2174
dsc_max_bpp = min(dsc_max_bpp, dsc_joiner_max_bpp);
2185
2175
dsc_max_bpp = min(dsc_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16));
2186
2176
2187
-
if (DISPLAY_VER(i915) >= 13)
2177
+
if (DISPLAY_VER(display) >= 13)
2188
2178
return xelpd_dsc_compute_link_config(intel_dp, connector, pipe_config, limits,
2189
2179
dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
2190
2180
return icl_dsc_compute_link_config(intel_dp, pipe_config, limits,
···
2192
2182
}
2193
2183
2194
2184
static
2195
-
u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
2185
+
u8 intel_dp_dsc_min_src_input_bpc(struct intel_display *display)
2196
2186
{
2197
2187
/* Min DSC Input BPC for ICL+ is 8 */
2198
-
return HAS_DSC(i915) ? 8 : 0;
2188
+
return HAS_DSC(display) ? 8 : 0;
2199
2189
}
2200
2190
2201
2191
static
2202
-
bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,
2192
+
bool is_dsc_pipe_bpp_sufficient(struct intel_display *display,
2203
2193
struct drm_connector_state *conn_state,
2204
2194
struct link_config_limits *limits,
2205
2195
int pipe_bpp)
2206
2196
{
2207
2197
u8 dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp;
2208
2198
2209
-
dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(i915), conn_state->max_requested_bpc);
2210
-
dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
2199
+
dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(display), conn_state->max_requested_bpc);
2200
+
dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(display);
2211
2201
2212
2202
dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
2213
2203
dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
···
2221
2211
struct drm_connector_state *conn_state,
2222
2212
struct link_config_limits *limits)
2223
2213
{
2224
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2214
+
struct intel_display *display = to_intel_display(intel_dp);
2225
2215
int forced_bpp;
2226
2216
2227
2217
if (!intel_dp->force_dsc_bpc)
···
2229
2219
2230
2220
forced_bpp = intel_dp->force_dsc_bpc * 3;
2231
2221
2232
-
if (is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, forced_bpp)) {
2233
-
drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc);
2222
+
if (is_dsc_pipe_bpp_sufficient(display, conn_state, limits, forced_bpp)) {
2223
+
drm_dbg_kms(display->drm, "Input DSC BPC forced to %d\n",
2224
+
intel_dp->force_dsc_bpc);
2234
2225
return forced_bpp;
2235
2226
}
2236
2227
2237
-
drm_dbg_kms(&i915->drm, "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
2228
+
drm_dbg_kms(display->drm,
2229
+
"Cannot force DSC BPC:%d, due to DSC BPC limits\n",
2238
2230
intel_dp->force_dsc_bpc);
2239
2231
2240
2232
return 0;
···
2248
2236
struct link_config_limits *limits,
2249
2237
int timeslots)
2250
2238
{
2251
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2239
+
struct intel_display *display = to_intel_display(intel_dp);
2252
2240
const struct intel_connector *connector =
2253
2241
to_intel_connector(conn_state->connector);
2254
2242
u8 max_req_bpc = conn_state->max_requested_bpc;
···
2269
2257
}
2270
2258
}
2271
2259
2272
-
dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
2260
+
dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
2273
2261
if (!dsc_max_bpc)
2274
2262
return -EINVAL;
2275
2263
2276
2264
dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
2277
2265
dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
2278
2266
2279
-
dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
2267
+
dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(display);
2280
2268
dsc_min_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
2281
2269
2282
2270
/*
···
2306
2294
struct drm_connector_state *conn_state,
2307
2295
struct link_config_limits *limits)
2308
2296
{
2309
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2297
+
struct intel_display *display = to_intel_display(intel_dp);
2310
2298
struct intel_connector *connector =
2311
2299
to_intel_connector(conn_state->connector);
2312
2300
int pipe_bpp, forced_bpp;
···
2322
2310
2323
2311
/* For eDP use max bpp that can be supported with DSC. */
2324
2312
pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc);
2325
-
if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
2326
-
drm_dbg_kms(&i915->drm,
2313
+
if (!is_dsc_pipe_bpp_sufficient(display, conn_state, limits, pipe_bpp)) {
2314
+
drm_dbg_kms(display->drm,
2327
2315
"Computed BPC is not in DSC BPC limits\n");
2328
2316
return -EINVAL;
2329
2317
}
···
2361
2349
int timeslots,
2362
2350
bool compute_pipe_bpp)
2363
2351
{
2364
-
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2365
-
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2352
+
struct intel_display *display = to_intel_display(intel_dp);
2366
2353
const struct intel_connector *connector =
2367
2354
to_intel_connector(conn_state->connector);
2368
2355
const struct drm_display_mode *adjusted_mode =
···
2399
2388
ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2400
2389
conn_state, limits, timeslots);
2401
2390
if (ret) {
2402
-
drm_dbg_kms(&dev_priv->drm,
2391
+
drm_dbg_kms(display->drm,
2403
2392
"No Valid pipe bpp for given mode ret = %d\n", ret);
2404
2393
return ret;
2405
2394
}
···
2411
2400
drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,
2412
2401
true);
2413
2402
if (!pipe_config->dsc.slice_count) {
2414
-
drm_dbg_kms(&dev_priv->drm, "Unsupported Slice Count %d\n",
2403
+
drm_dbg_kms(display->drm,
2404
+
"Unsupported Slice Count %d\n",
2415
2405
pipe_config->dsc.slice_count);
2416
2406
return -EINVAL;
2417
2407
}
···
2425
2413
adjusted_mode->crtc_hdisplay,
2426
2414
num_joined_pipes);
2427
2415
if (!dsc_dp_slice_count) {
2428
-
drm_dbg_kms(&dev_priv->drm,
2416
+
drm_dbg_kms(display->drm,
2429
2417
"Compressed Slice Count not supported\n");
2430
2418
return -EINVAL;
2431
2419
}
···
2449
2437
2450
2438
ret = intel_dp_dsc_compute_params(connector, pipe_config);
2451
2439
if (ret < 0) {
2452
-
drm_dbg_kms(&dev_priv->drm,
2440
+
drm_dbg_kms(display->drm,
2453
2441
"Cannot compute valid DSC parameters for Input Bpp = %d"
2454
2442
"Compressed BPP = " FXP_Q4_FMT "\n",
2455
2443
pipe_config->pipe_bpp,
···
2458
2446
}
2459
2447
2460
2448
pipe_config->dsc.compression_enable = true;
2461
-
drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
2449
+
drm_dbg_kms(display->drm, "DP DSC computed with Input Bpp = %d "
2462
2450
"Compressed Bpp = " FXP_Q4_FMT " Slice Count = %d\n",
2463
2451
pipe_config->pipe_bpp,
2464
2452
FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),
···
2477
2465
bool dsc,
2478
2466
struct link_config_limits *limits)
2479
2467
{
2480
-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2468
+
struct intel_display *display = to_intel_display(intel_dp);
2481
2469
const struct drm_display_mode *adjusted_mode =
2482
2470
&crtc_state->hw.adjusted_mode;
2483
2471
const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
···
2505
2493
2506
2494
limits->link.max_bpp_x16 = max_link_bpp_x16;
2507
2495
2508
-
drm_dbg_kms(&i915->drm,
2496
+
drm_dbg_kms(display->drm,
2509
2497
"[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " FXP_Q4_FMT "\n",
2510
2498
encoder->base.base.id, encoder->base.name,
2511
2499
crtc->base.base.id, crtc->base.name,
···
2593
2581
bool intel_dp_joiner_needs_dsc(struct drm_i915_private *i915,
2594
2582
int num_joined_pipes)
2595
2583
{
2584
+
struct intel_display *display = &i915->display;
2585
+
2596
2586
/*
2597
2587
* Pipe joiner needs compression up to display 12 due to bandwidth
2598
2588
* limitation. DG2 onwards pipe joiner can be enabled without
2599
2589
* compression.
2600
2590
* Ultrajoiner always needs compression.
2601
2591
*/
2602
-
return (!HAS_UNCOMPRESSED_JOINER(i915) && num_joined_pipes == 2) ||
2592
+
return (!HAS_UNCOMPRESSED_JOINER(display) && num_joined_pipes == 2) ||
2603
2593
num_joined_pipes == 4;
2604
2594
}
2605
2595
···
2611
2597
struct drm_connector_state *conn_state,
2612
2598
bool respect_downstream_limits)
2613
2599
{
2600
+
struct intel_display *display = to_intel_display(encoder);
2614
2601
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2615
2602
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2616
2603
struct intel_connector *connector =
···
2654
2639
}
2655
2640
2656
2641
if (dsc_needed) {
2657
-
drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
2642
+
drm_dbg_kms(display->drm,
2643
+
"Try DSC (fallback=%s, joiner=%s, force=%s)\n",
2658
2644
str_yes_no(ret), str_yes_no(joiner_needs_dsc),
2659
2645
str_yes_no(intel_dp->force_dsc_en));
2660
2646
···
2671
2655
return ret;
2672
2656
}
2673
2657
2674
-
drm_dbg_kms(&i915->drm,
2658
+
drm_dbg_kms(display->drm,
2675
2659
"DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " link rate required %d available %d\n",
2676
2660
pipe_config->lane_count, pipe_config->port_clock,
2677
2661
pipe_config->pipe_bpp,
···
2717
2701
}
2718
2702
}
2719
2703
2720
-
static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
2721
-
enum port port)
2704
+
static bool intel_dp_port_has_audio(struct intel_display *display, enum port port)
2722
2705
{
2723
-
if (IS_G4X(dev_priv))
2706
+
if (display->platform.g4x)
2724
2707
return false;
2725
-
if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
2708
+
if (DISPLAY_VER(display) < 12 && port == PORT_A)
2726
2709
return false;
2727
2710
2728
2711
return true;
···
2731
2716
const struct drm_connector_state *conn_state,
2732
2717
struct drm_dp_vsc_sdp *vsc)
2733
2718
{
2734
-
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2735
-
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2719
+
struct intel_display *display = to_intel_display(crtc_state);
2736
2720
2737
2721
if (crtc_state->has_panel_replay) {
2738
2722
/*
···
2808
2794
vsc->bpc = crtc_state->pipe_bpp / 3;
2809
2795
2810
2796
/* only RGB pixelformat supports 6 bpc */
2811
-
drm_WARN_ON(&dev_priv->drm,
2797
+
drm_WARN_ON(display->drm,
2812
2798
vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2813
2799
2814
2800
/* all YCbCr are always limited range */
···
2898
2884
struct intel_crtc_state *crtc_state,
2899
2885
const struct drm_connector_state *conn_state)
2900
2886
{
2887
+
struct intel_display *display = to_intel_display(intel_dp);
2901
2888
int ret;
2902
-
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2903
2889
struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2904
2890
2905
2891
if (!conn_state->hdr_output_metadata)
···
2908
2894
ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2909
2895
2910
2896
if (ret) {
2911
-
drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
2897
+
drm_dbg_kms(display->drm,
2898
+
"couldn't set HDR metadata in infoframe\n");
2912
2899
return;
2913
2900
}
2914
2901
···
2951
2936
struct intel_crtc_state *pipe_config,
2952
2937
int link_bpp_x16)
2953
2938
{
2939
+
struct intel_display *display = to_intel_display(connector);
2954
2940
struct drm_i915_private *i915 = to_i915(connector->base.dev);
2955
2941
const struct drm_display_mode *downclock_mode =
2956
2942
intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
···
2970
2954
return;
2971
2955
}
2972
2956
2973
-
if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915))
2957
+
if (display->platform.ironlake || display->platform.sandybridge ||
2958
+
display->platform.ivybridge)
2974
2959
pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;
2975
2960
2976
2961
pipe_config->has_drrs = true;
···
2993
2976
static bool intel_dp_has_audio(struct intel_encoder *encoder,
2994
2977
const struct drm_connector_state *conn_state)
2995
2978
{
2996
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2979
+
struct intel_display *display = to_intel_display(encoder);
2997
2980
const struct intel_digital_connector_state *intel_conn_state =
2998
2981
to_intel_digital_connector_state(conn_state);
2999
2982
struct intel_connector *connector =
3000
2983
to_intel_connector(conn_state->connector);
3001
2984
3002
-
if (!intel_dp_port_has_audio(i915, encoder->port))
2985
+
if (!intel_dp_port_has_audio(display, encoder->port))
3003
2986
return false;
3004
2987
3005
2988
if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
···
3014
2997
struct drm_connector_state *conn_state,
3015
2998
bool respect_downstream_limits)
3016
2999
{
3017
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3000
+
struct intel_display *display = to_intel_display(encoder);
3018
3001
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3019
3002
struct intel_connector *connector = intel_dp->attached_connector;
3020
3003
const struct drm_display_info *info = &connector->base.display_info;
···
3025
3008
ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
3026
3009
3027
3010
if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {
3028
-
drm_dbg_kms(&i915->drm,
3011
+
drm_dbg_kms(display->drm,
3029
3012
"YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
3030
3013
crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
3031
3014
} else {
···
3109
3092
struct intel_crtc_state *pipe_config,
3110
3093
struct drm_connector_state *conn_state)
3111
3094
{
3112
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3095
+
struct intel_display *display = to_intel_display(encoder);
3113
3096
struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
3114
3097
struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
3115
3098
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
···
3134
3117
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
3135
3118
return -EINVAL;
3136
3119
3137
-
if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
3120
+
if (intel_dp_hdisplay_bad(display, adjusted_mode->crtc_hdisplay))
3138
3121
return -EINVAL;
3139
3122
3140
3123
/*
···
3174
3157
pipe_config->splitter.link_count = n;
3175
3158
pipe_config->splitter.pixel_overlap = overlap;
3176
3159
3177
-
drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
3160
+
drm_dbg_kms(display->drm,
3161
+
"MSO link count %d, pixel overlap %d\n",
3178
3162
n, overlap);
3179
3163
3180
3164
adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
···
3236
3218
void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
3237
3219
const struct drm_connector_state *conn_state)
3238
3220
{
3221
+
struct intel_display *display = to_intel_display(crtc_state);
3239
3222
struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
3240
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3241
3223
3242
3224
if (!intel_dp_is_edp(intel_dp))
3243
3225
return;
3244
3226
3245
-
drm_dbg_kms(&i915->drm, "\n");
3227
+
drm_dbg_kms(display->drm, "\n");
3246
3228
3247
3229
intel_backlight_enable(crtc_state, conn_state);
3248
3230
intel_pps_backlight_on(intel_dp);
···
3252
3234
void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
3253
3235
{
3254
3236
struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
3255
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3237
+
struct intel_display *display = to_intel_display(intel_dp);
3256
3238
3257
3239
if (!intel_dp_is_edp(intel_dp))
3258
3240
return;
3259
3241
3260
-
drm_dbg_kms(&i915->drm, "\n");
3242
+
drm_dbg_kms(display->drm, "\n");
3261
3243
3262
3244
intel_pps_backlight_off(intel_dp);
3263
3245
intel_backlight_disable(old_conn_state);
···
3300
3282
intel_dp_sink_set_dsc_decompression(struct intel_connector *connector,
3301
3283
bool enable)
3302
3284
{
3303
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
3285
+
struct intel_display *display = to_intel_display(connector);
3304
3286
3305
3287
if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux,
3306
3288
DP_DECOMPRESSION_EN, enable) < 0)
3307
-
drm_dbg_kms(&i915->drm,
3289
+
drm_dbg_kms(display->drm,
3308
3290
"Failed to %s sink decompression state\n",
3309
3291
str_enable_disable(enable));
3310
3292
}
···
3313
3295
intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector,
3314
3296
bool enable)
3315
3297
{
3316
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
3298
+
struct intel_display *display = to_intel_display(connector);
3317
3299
struct drm_dp_aux *aux = connector->port ?
3318
3300
connector->port->passthrough_aux : NULL;
3319
3301
···
3322
3304
3323
3305
if (write_dsc_decompression_flag(aux,
3324
3306
DP_DSC_PASSTHROUGH_EN, enable) < 0)
3325
-
drm_dbg_kms(&i915->drm,
3307
+
drm_dbg_kms(display->drm,
3326
3308
"Failed to %s sink compression passthrough state\n",
3327
3309
str_enable_disable(enable));
3328
3310
}
···
3331
3313
const struct intel_connector *connector,
3332
3314
bool for_get_ref)
3333
3315
{
3334
-
struct drm_i915_private *i915 = to_i915(state->base.dev);
3316
+
struct intel_display *display = to_intel_display(state);
3335
3317
struct drm_connector *_connector_iter;
3336
3318
struct drm_connector_state *old_conn_state;
3337
3319
struct drm_connector_state *new_conn_state;
···
3356
3338
if (!connector_iter->dp.dsc_decompression_enabled)
3357
3339
continue;
3358
3340
3359
-
drm_WARN_ON(&i915->drm,
3341
+
drm_WARN_ON(display->drm,
3360
3342
(for_get_ref && !new_conn_state->crtc) ||
3361
3343
(!for_get_ref && !old_conn_state->crtc));
3362
3344
···
3403
3385
struct intel_connector *connector,
3404
3386
const struct intel_crtc_state *new_crtc_state)
3405
3387
{
3406
-
struct drm_i915_private *i915 = to_i915(state->base.dev);
3388
+
struct intel_display *display = to_intel_display(state);
3407
3389
3408
3390
if (!new_crtc_state->dsc.compression_enable)
3409
3391
return;
3410
3392
3411
-
if (drm_WARN_ON(&i915->drm,
3393
+
if (drm_WARN_ON(display->drm,
3412
3394
!connector->dp.dsc_decompression_aux ||
3413
3395
connector->dp.dsc_decompression_enabled))
3414
3396
return;
···
3434
3416
struct intel_connector *connector,
3435
3417
const struct intel_crtc_state *old_crtc_state)
3436
3418
{
3437
-
struct drm_i915_private *i915 = to_i915(state->base.dev);
3419
+
struct intel_display *display = to_intel_display(state);
3438
3420
3439
3421
if (!old_crtc_state->dsc.compression_enable)
3440
3422
return;
3441
3423
3442
-
if (drm_WARN_ON(&i915->drm,
3424
+
if (drm_WARN_ON(display->drm,
3443
3425
!connector->dp.dsc_decompression_aux ||
3444
3426
!connector->dp.dsc_decompression_enabled))
3445
3427
return;
···
3491
3473
3492
3474
void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
3493
3475
{
3476
+
struct intel_display *display = to_intel_display(intel_dp);
3494
3477
struct intel_connector *connector = intel_dp->attached_connector;
3495
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3496
3478
3497
-
drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n",
3479
+
drm_dbg_kms(display->drm,
3480
+
"[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n",
3498
3481
connector->base.base.id, connector->base.name,
3499
3482
connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
3500
3483
···
3506
3487
/* If the device supports it, try to set the power state appropriately */
3507
3488
void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
3508
3489
{
3490
+
struct intel_display *display = to_intel_display(intel_dp);
3509
3491
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3510
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3511
3492
int ret, i;
3512
3493
3513
3494
/* Should have a valid DPCD by this point */
···
3543
3524
}
3544
3525
3545
3526
if (ret != 1)
3546
-
drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
3527
+
drm_dbg_kms(display->drm,
3528
+
"[ENCODER:%d:%s] Set power to %s failed\n",
3547
3529
encoder->base.base.id, encoder->base.name,
3548
3530
mode == DP_SET_POWER_D0 ? "D0" : "D3");
3549
3531
}
···
3587
3567
bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
3588
3568
struct intel_crtc_state *crtc_state)
3589
3569
{
3590
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3570
+
struct intel_display *display = to_intel_display(encoder);
3591
3571
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3592
3572
bool fastset = true;
3593
3573
···
3597
3577
*/
3598
3578
if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
3599
3579
crtc_state->port_clock) < 0) {
3600
-
drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n",
3580
+
drm_dbg_kms(display->drm,
3581
+
"[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n",
3601
3582
encoder->base.base.id, encoder->base.name);
3602
3583
crtc_state->uapi.connectors_changed = true;
3603
3584
fastset = false;
···
3612
3591
* Remove once we have readout for DSC.
3613
3592
*/
3614
3593
if (crtc_state->dsc.compression_enable) {
3615
-
drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n",
3594
+
drm_dbg_kms(display->drm,
3595
+
"[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n",
3616
3596
encoder->base.base.id, encoder->base.name);
3617
3597
crtc_state->uapi.mode_changed = true;
3618
3598
fastset = false;
3619
3599
}
3620
3600
3621
3601
if (CAN_PANEL_REPLAY(intel_dp)) {
3622
-
drm_dbg_kms(&i915->drm,
3602
+
drm_dbg_kms(display->drm,
3623
3603
"[ENCODER:%d:%s] Forcing full modeset to compute panel replay state\n",
3624
3604
encoder->base.base.id, encoder->base.name);
3625
3605
crtc_state->uapi.mode_changed = true;
···
3632
3610
3633
3611
static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
3634
3612
{
3635
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3613
+
struct intel_display *display = to_intel_display(intel_dp);
3636
3614
3637
3615
/* Clear the cached register set to avoid using stale values */
3638
3616
···
3641
3619
if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
3642
3620
intel_dp->pcon_dsc_dpcd,
3643
3621
sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
3644
-
drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
3622
+
drm_err(display->drm, "Failed to read DPCD register 0x%x\n",
3645
3623
DP_PCON_DSC_ENCODER);
3646
3624
3647
-
drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
3625
+
drm_dbg_kms(display->drm, "PCON ENCODER DSC DPCD: %*ph\n",
3648
3626
(int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
3649
3627
}
3650
3628
···
3716
3694
3717
3695
static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
3718
3696
{
3697
+
struct intel_display *display = to_intel_display(intel_dp);
3719
3698
#define TIMEOUT_FRL_READY_MS 500
3720
3699
#define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
3721
-
3722
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3723
3700
int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
3724
3701
u8 max_frl_bw_mask = 0, frl_trained_mask;
3725
3702
bool is_active;
3726
3703
3727
3704
max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
3728
-
drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
3705
+
drm_dbg(display->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
3729
3706
3730
3707
max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
3731
-
drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
3708
+
drm_dbg(display->drm, "Sink max rate from EDID = %d Gbps\n",
3709
+
max_edid_frl_bw);
3732
3710
3733
3711
max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
3734
3712
···
3736
3714
return -EINVAL;
3737
3715
3738
3716
max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
3739
-
drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
3717
+
drm_dbg(display->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
3740
3718
3741
3719
if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))
3742
3720
goto frl_trained;
···
3773
3751
return -ETIMEDOUT;
3774
3752
3775
3753
frl_trained:
3776
-
drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
3754
+
drm_dbg(display->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
3777
3755
intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
3778
3756
intel_dp->frl.is_trained = true;
3779
-
drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
3757
+
drm_dbg(display->drm, "FRL trained with : %d Gbps\n",
3758
+
intel_dp->frl.trained_rate_gbps);
3780
3759
3781
3760
return 0;
3782
3761
}
···
3816
3793
3817
3794
void intel_dp_check_frl_training(struct intel_dp *intel_dp)
3818
3795
{
3819
-
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3796
+
struct intel_display *display = to_intel_display(intel_dp);
3820
3797
3821
3798
/*
3822
3799
* Always go for FRL training if:
···
3831
3808
if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
3832
3809
int ret, mode;
3833
3810
3834
-
drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
3811
+
drm_dbg(display->drm,
3812
+
"Couldn't set FRL mode, continuing with TMDS mode\n");
3835
3813
ret = intel_dp_pcon_set_tmds_mode(intel_dp);
3836
3814
mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
3837
3815
3838
3816
if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
3839
-
drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
3817
+
drm_dbg(display->drm,
3818
+
"Issue with PCON, cannot set TMDS mode\n");
3840
3819
} else {
3841
-
drm_dbg(&dev_priv->drm, "FRL training Completed\n");
3820
+
drm_dbg(display->drm, "FRL training Completed\n");
3842
3821
}
3843
3822
}
3844
3823
···
3890
3865
intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
3891
3866
const struct intel_crtc_state *crtc_state)
3892
3867
{
3868
+
struct intel_display *display = to_intel_display(intel_dp);
3893
3869
struct intel_connector *connector = intel_dp->attached_connector;
3894
3870
const struct drm_display_info *info;
3895
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3896
3871
u8 pps_param[6];
3897
3872
int slice_height;
3898
3873
int slice_width;
···
3940
3915
3941
3916
ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
3942
3917
if (ret < 0)
3943
-
drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
3918
+
drm_dbg_kms(display->drm, "Failed to set pcon DSC\n");
3944
3919
}
3945
3920
3946
3921
void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
3947
3922
const struct intel_crtc_state *crtc_state)
3948
3923
{
3949
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3924
+
struct intel_display *display = to_intel_display(intel_dp);
3950
3925
bool ycbcr444_to_420 = false;
3951
3926
bool rgb_to_ycbcr = false;
3952
3927
u8 tmp;
···
3961
3936
3962
3937
if (drm_dp_dpcd_writeb(&intel_dp->aux,
3963
3938
DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
3964
-
drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
3939
+
drm_dbg_kms(display->drm,
3940
+
"Failed to %s protocol converter HDMI mode\n",
3965
3941
str_enable_disable(intel_dp_has_hdmi_sink(intel_dp)));
3966
3942
3967
3943
if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
···
3997
3971
3998
3972
if (drm_dp_dpcd_writeb(&intel_dp->aux,
3999
3973
DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
4000
-
drm_dbg_kms(&i915->drm,
3974
+
drm_dbg_kms(display->drm,
4001
3975
"Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
4002
3976
str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
4003
3977
4004
3978
tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
4005
3979
4006
3980
if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
4007
-
drm_dbg_kms(&i915->drm,
3981
+
drm_dbg_kms(display->drm,
4008
3982
"Failed to %s protocol converter RGB->YCbCr conversion mode\n",
4009
3983
str_enable_disable(tmp));
4010
3984
}
···
4037
4011
4038
4012
void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector)
4039
4013
{
4040
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
4014
+
struct intel_display *display = to_intel_display(connector);
4041
4015
4042
4016
/*
4043
4017
* Clear the cached register set to avoid using stale values
···
4056
4030
4057
4031
if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY,
4058
4032
&connector->dp.fec_capability) < 0) {
4059
-
drm_err(&i915->drm, "Failed to read FEC DPCD register\n");
4033
+
drm_err(display->drm, "Failed to read FEC DPCD register\n");
4060
4034
return;
4061
4035
}
4062
4036
4063
-
drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
4037
+
drm_dbg_kms(display->drm, "FEC CAPABILITY: %x\n",
4064
4038
connector->dp.fec_capability);
4065
4039
}
4066
4040
···
4075
4049
static void
4076
4050
intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector)
4077
4051
{
4078
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4052
+
struct intel_display *display = to_intel_display(intel_dp);
4079
4053
4080
4054
/* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
4081
-
if (!HAS_DSC(i915))
4055
+
if (!HAS_DSC(display))
4082
4056
return;
4083
4057
4084
4058
if (intel_dp_is_edp(intel_dp))
···
4092
4066
static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
4093
4067
struct drm_display_mode *mode)
4094
4068
{
4069
+
struct intel_display *display = to_intel_display(connector);
4095
4070
struct intel_dp *intel_dp = intel_attached_dp(connector);
4096
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
4097
4071
int n = intel_dp->mso_link_count;
4098
4072
int overlap = intel_dp->mso_pixel_overlap;
4099
4073
···
4108
4082
4109
4083
drm_mode_set_name(mode);
4110
4084
4111
-
drm_dbg_kms(&i915->drm,
4085
+
drm_dbg_kms(display->drm,
4112
4086
"[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",
4113
4087
connector->base.base.id, connector->base.name,
4114
4088
DRM_MODE_ARG(mode));
···
4116
4090
4117
4091
void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)
4118
4092
{
4119
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4093
+
struct intel_display *display = to_intel_display(encoder);
4120
4094
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4121
4095
struct intel_connector *connector = intel_dp->attached_connector;
4122
4096
···
4134
4108
* up by the BIOS, and thus we can't get the mode at module
4135
4109
* load.
4136
4110
*/
4137
-
drm_dbg_kms(&dev_priv->drm,
4111
+
drm_dbg_kms(display->drm,
4138
4112
"pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
4139
4113
pipe_bpp, connector->panel.vbt.edp.bpp);
4140
4114
connector->panel.vbt.edp.bpp = pipe_bpp;
···
4143
4117
4144
4118
static void intel_edp_mso_init(struct intel_dp *intel_dp)
4145
4119
{
4146
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4120
+
struct intel_display *display = to_intel_display(intel_dp);
4147
4121
struct intel_connector *connector = intel_dp->attached_connector;
4148
4122
struct drm_display_info *info = &connector->base.display_info;
4149
4123
u8 mso;
···
4152
4126
return;
4153
4127
4154
4128
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
4155
-
drm_err(&i915->drm, "Failed to read MSO cap\n");
4129
+
drm_err(display->drm, "Failed to read MSO cap\n");
4156
4130
return;
4157
4131
}
4158
4132
4159
4133
/* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
4160
4134
mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
4161
4135
if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
4162
-
drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
4136
+
drm_err(display->drm, "Invalid MSO link count cap %u\n", mso);
4163
4137
mso = 0;
4164
4138
}
4165
4139
4166
4140
if (mso) {
4167
-
drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",
4141
+
drm_dbg_kms(display->drm,
4142
+
"Sink MSO %ux%u configuration, pixel overlap %u\n",
4168
4143
mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
4169
4144
info->mso_pixel_overlap);
4170
-
if (!HAS_MSO(i915)) {
4171
-
drm_err(&i915->drm, "No source MSO support, disabling\n");
4145
+
if (!HAS_MSO(display)) {
4146
+
drm_err(display->drm,
4147
+
"No source MSO support, disabling\n");
4172
4148
mso = 0;
4173
4149
}
4174
4150
}
···
4221
4193
static bool
4222
4194
intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
4223
4195
{
4224
-
struct drm_i915_private *dev_priv =
4225
-
to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4196
+
struct intel_display *display = to_intel_display(intel_dp);
4226
4197
4227
4198
/* this function is meant to be called only once */
4228
-
drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
4199
+
drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
4229
4200
4230
4201
if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
4231
4202
return false;
···
4248
4221
if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4249
4222
intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4250
4223
sizeof(intel_dp->edp_dpcd)) {
4251
-
drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
4224
+
drm_dbg_kms(display->drm, "eDP DPCD: %*ph\n",
4252
4225
(int)sizeof(intel_dp->edp_dpcd),
4253
4226
intel_dp->edp_dpcd);
4254
4227
···
4359
4332
intel_dp_mst_mode_choose(struct intel_dp *intel_dp,
4360
4333
enum drm_dp_mst_mode sink_mst_mode)
4361
4334
{
4362
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4335
+
struct intel_display *display = to_intel_display(intel_dp);
4363
4336
4364
-
if (!i915->display.params.enable_dp_mst)
4337
+
if (!display->params.enable_dp_mst)
4365
4338
return DRM_DP_SST;
4366
4339
4367
4340
if (!intel_dp_mst_source_support(intel_dp))
···
4377
4350
static enum drm_dp_mst_mode
4378
4351
intel_dp_mst_detect(struct intel_dp *intel_dp)
4379
4352
{
4380
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4353
+
struct intel_display *display = to_intel_display(intel_dp);
4381
4354
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4382
4355
enum drm_dp_mst_mode sink_mst_mode;
4383
4356
enum drm_dp_mst_mode mst_detect;
···
4386
4359
4387
4360
mst_detect = intel_dp_mst_mode_choose(intel_dp, sink_mst_mode);
4388
4361
4389
-
drm_dbg_kms(&i915->drm,
4362
+
drm_dbg_kms(display->drm,
4390
4363
"[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s -> enable: %s\n",
4391
4364
encoder->base.base.id, encoder->base.name,
4392
4365
str_yes_no(intel_dp_mst_source_support(intel_dp)),
4393
4366
intel_dp_mst_mode_str(sink_mst_mode),
4394
-
str_yes_no(i915->display.params.enable_dp_mst),
4367
+
str_yes_no(display->params.enable_dp_mst),
4395
4368
intel_dp_mst_mode_str(mst_detect));
4396
4369
4397
4370
return mst_detect;
···
4417
4390
static void
4418
4391
intel_dp_mst_disconnect(struct intel_dp *intel_dp)
4419
4392
{
4420
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4393
+
struct intel_display *display = to_intel_display(intel_dp);
4421
4394
4422
4395
if (!intel_dp->is_mst)
4423
4396
return;
4424
4397
4425
-
drm_dbg_kms(&i915->drm, "MST device may have disappeared %d vs %d\n",
4398
+
drm_dbg_kms(display->drm,
4399
+
"MST device may have disappeared %d vs %d\n",
4426
4400
intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4427
4401
intel_dp->is_mst = false;
4428
4402
drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
···
4504
4476
}
4505
4477
4506
4478
static ssize_t
4507
-
intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
4479
+
intel_dp_hdr_metadata_infoframe_sdp_pack(struct intel_display *display,
4508
4480
const struct hdmi_drm_infoframe *drm_infoframe,
4509
4481
struct dp_sdp *sdp,
4510
4482
size_t size)
···
4521
4493
4522
4494
len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
4523
4495
if (len < 0) {
4524
-
drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n");
4496
+
drm_dbg_kms(display->drm,
4497
+
"buffer size is smaller than hdr metadata infoframe\n");
4525
4498
return -ENOSPC;
4526
4499
}
4527
4500
4528
4501
if (len != infoframe_size) {
4529
-
drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
4502
+
drm_dbg_kms(display->drm, "wrong static hdr metadata size\n");
4530
4503
return -ENOSPC;
4531
4504
}
4532
4505
···
4585
4556
const struct intel_crtc_state *crtc_state,
4586
4557
unsigned int type)
4587
4558
{
4559
+
struct intel_display *display = to_intel_display(encoder);
4588
4560
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4589
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4590
4561
struct dp_sdp sdp = {};
4591
4562
ssize_t len;
4592
4563
···
4599
4570
len = drm_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp);
4600
4571
break;
4601
4572
case HDMI_PACKET_TYPE_GAMUT_METADATA:
4602
-
len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
4573
+
len = intel_dp_hdr_metadata_infoframe_sdp_pack(display,
4603
4574
&crtc_state->infoframes.drm.drm,
4604
4575
&sdp, sizeof(sdp));
4605
4576
break;
···
4612
4583
return;
4613
4584
}
4614
4585
4615
-
if (drm_WARN_ON(&dev_priv->drm, len < 0))
4586
+
if (drm_WARN_ON(display->drm, len < 0))
4616
4587
return;
4617
4588
4618
4589
dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
···
4623
4594
const struct intel_crtc_state *crtc_state,
4624
4595
const struct drm_connector_state *conn_state)
4625
4596
{
4626
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4627
-
i915_reg_t reg = HSW_TVIDEO_DIP_CTL(dev_priv,
4628
-
crtc_state->cpu_transcoder);
4597
+
struct intel_display *display = to_intel_display(encoder);
4598
+
i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder);
4629
4599
u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
4630
4600
VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
4631
4601
VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
4632
4602
4633
-
if (HAS_AS_SDP(dev_priv))
4603
+
if (HAS_AS_SDP(display))
4634
4604
dip_enable |= VIDEO_DIP_ENABLE_AS_ADL;
4635
4605
4636
-
u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
4606
+
u32 val = intel_de_read(display, reg) & ~dip_enable;
4637
4607
4638
4608
/* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
4639
-
if (!enable && HAS_DSC(dev_priv))
4609
+
if (!enable && HAS_DSC(display))
4640
4610
val &= ~VDIP_ENABLE_PPS;
4641
4611
4642
4612
/*
···
4645
4617
if (!enable || !crtc_state->has_psr)
4646
4618
val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
4647
4619
4648
-
intel_de_write(dev_priv, reg, val);
4649
-
intel_de_posting_read(dev_priv, reg);
4620
+
intel_de_write(display, reg, val);
4621
+
intel_de_posting_read(display, reg);
4650
4622
4651
4623
if (!enable)
4652
4624
return;
···
4767
4739
struct intel_crtc_state *crtc_state,
4768
4740
struct drm_dp_as_sdp *as_sdp)
4769
4741
{
4742
+
struct intel_display *display = to_intel_display(encoder);
4770
4743
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4771
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4772
4744
unsigned int type = DP_SDP_ADAPTIVE_SYNC;
4773
4745
struct dp_sdp sdp = {};
4774
4746
int ret;
···
4782
4754
4783
4755
ret = intel_dp_as_sdp_unpack(as_sdp, &sdp, sizeof(sdp));
4784
4756
if (ret)
4785
-
drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP AS SDP\n");
4757
+
drm_dbg_kms(display->drm, "Failed to unpack DP AS SDP\n");
4786
4758
}
4787
4759
4788
4760
static int
···
4835
4807
struct intel_crtc_state *crtc_state,
4836
4808
struct drm_dp_vsc_sdp *vsc)
4837
4809
{
4810
+
struct intel_display *display = to_intel_display(encoder);
4838
4811
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4839
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4840
4812
unsigned int type = DP_SDP_VSC;
4841
4813
struct dp_sdp sdp = {};
4842
4814
int ret;
···
4850
4822
ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
4851
4823
4852
4824
if (ret)
4853
-
drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
4825
+
drm_dbg_kms(display->drm, "Failed to unpack DP VSC SDP\n");
4854
4826
}
4855
4827
4856
4828
static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
4857
4829
struct intel_crtc_state *crtc_state,
4858
4830
struct hdmi_drm_infoframe *drm_infoframe)
4859
4831
{
4832
+
struct intel_display *display = to_intel_display(encoder);
4860
4833
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4861
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4862
4834
unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
4863
4835
struct dp_sdp sdp = {};
4864
4836
int ret;
···
4874
4846
sizeof(sdp));
4875
4847
4876
4848
if (ret)
4877
-
drm_dbg_kms(&dev_priv->drm,
4849
+
drm_dbg_kms(display->drm,
4878
4850
"Failed to unpack DP HDR Metadata Infoframe SDP\n");
4879
4851
}
4880
4852
···
4904
4876
static bool intel_dp_link_ok(struct intel_dp *intel_dp,
4905
4877
u8 link_status[DP_LINK_STATUS_SIZE])
4906
4878
{
4879
+
struct intel_display *display = to_intel_display(intel_dp);
4907
4880
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4908
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4909
4881
bool uhbr = intel_dp->link_rate >= 1000000;
4910
4882
bool ok;
4911
4883
···
4919
4891
return true;
4920
4892
4921
4893
intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
4922
-
drm_dbg_kms(&i915->drm,
4894
+
drm_dbg_kms(display->drm,
4923
4895
"[ENCODER:%d:%s] %s link not ok, retraining\n",
4924
4896
encoder->base.base.id, encoder->base.name,
4925
4897
uhbr ? "128b/132b" : "8b/10b");
···
4942
4914
4943
4915
static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
4944
4916
{
4917
+
struct intel_display *display = to_intel_display(intel_dp);
4945
4918
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4946
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4947
4919
u8 link_status[DP_LINK_STATUS_SIZE] = {};
4948
4920
const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
4949
4921
4950
4922
if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,
4951
4923
esi_link_status_size) != esi_link_status_size) {
4952
-
drm_err(&i915->drm,
4924
+
drm_err(display->drm,
4953
4925
"[ENCODER:%d:%s] Failed to read link status\n",
4954
4926
encoder->base.base.id, encoder->base.name);
4955
4927
return false;
···
4975
4947
static bool
4976
4948
intel_dp_check_mst_status(struct intel_dp *intel_dp)
4977
4949
{
4978
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4950
+
struct intel_display *display = to_intel_display(intel_dp);
4979
4951
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4980
4952
struct intel_encoder *encoder = &dig_port->base;
4981
4953
bool link_ok = true;
4982
4954
bool reprobe_needed = false;
4983
4955
4984
-
drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
4956
+
drm_WARN_ON_ONCE(display->drm, intel_dp->active_mst_links < 0);
4985
4957
4986
4958
for (;;) {
4987
4959
u8 esi[4] = {};
4988
4960
u8 ack[4] = {};
4989
4961
4990
4962
if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
4991
-
drm_dbg_kms(&i915->drm,
4963
+
drm_dbg_kms(display->drm,
4992
4964
"failed to get ESI - device may have failed\n");
4993
4965
link_ok = false;
4994
4966
4995
4967
break;
4996
4968
}
4997
4969
4998
-
drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi);
4970
+
drm_dbg_kms(display->drm, "DPRX ESI: %4ph\n", esi);
4999
4971
5000
4972
if (intel_dp->active_mst_links > 0 && link_ok &&
5001
4973
esi[3] & LINK_STATUS_CHANGED) {
···
5007
4979
intel_dp_mst_hpd_irq(intel_dp, esi, ack);
5008
4980
5009
4981
if (esi[3] & DP_TUNNELING_IRQ) {
5010
-
if (drm_dp_tunnel_handle_irq(i915->display.dp_tunnel_mgr,
4982
+
if (drm_dp_tunnel_handle_irq(display->dp_tunnel_mgr,
5011
4983
&intel_dp->aux))
5012
4984
reprobe_needed = true;
5013
4985
ack[3] |= DP_TUNNELING_IRQ;
···
5017
4989
break;
5018
4990
5019
4991
if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
5020
-
drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");
4992
+
drm_dbg_kms(display->drm, "Failed to ack ESI\n");
5021
4993
5022
4994
if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY))
5023
4995
drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr);
···
5105
5077
bool intel_dp_has_connector(struct intel_dp *intel_dp,
5106
5078
const struct drm_connector_state *conn_state)
5107
5079
{
5108
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5080
+
struct intel_display *display = to_intel_display(intel_dp);
5109
5081
struct intel_encoder *encoder;
5110
5082
enum pipe pipe;
5111
5083
···
5118
5090
return true;
5119
5091
5120
5092
/* MST */
5121
-
for_each_pipe(i915, pipe) {
5093
+
for_each_pipe(display, pipe) {
5122
5094
encoder = &intel_dp->mst_encoders[pipe]->base;
5123
5095
if (conn_state->best_encoder == &encoder->base)
5124
5096
return true;
···
5146
5118
struct drm_modeset_acquire_ctx *ctx,
5147
5119
u8 *pipe_mask)
5148
5120
{
5149
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5121
+
struct intel_display *display = to_intel_display(intel_dp);
5150
5122
struct drm_connector_list_iter conn_iter;
5151
5123
struct intel_connector *connector;
5152
5124
int ret = 0;
5153
5125
5154
5126
*pipe_mask = 0;
5155
5127
5156
-
drm_connector_list_iter_begin(&i915->drm, &conn_iter);
5128
+
drm_connector_list_iter_begin(display->drm, &conn_iter);
5157
5129
for_each_intel_connector_iter(connector, &conn_iter) {
5158
5130
struct drm_connector_state *conn_state =
5159
5131
connector->base.state;
···
5173
5145
5174
5146
crtc_state = to_intel_crtc_state(crtc->base.state);
5175
5147
5176
-
drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
5148
+
drm_WARN_ON(display->drm,
5149
+
!intel_crtc_has_dp_encoder(crtc_state));
5177
5150
5178
5151
if (!crtc_state->hw.active)
5179
5152
continue;
···
5204
5175
static int intel_dp_retrain_link(struct intel_encoder *encoder,
5205
5176
struct drm_modeset_acquire_ctx *ctx)
5206
5177
{
5178
+
struct intel_display *display = to_intel_display(encoder);
5207
5179
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5208
5180
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5209
5181
u8 pipe_mask;
···
5213
5183
if (!intel_dp_is_connected(intel_dp))
5214
5184
return 0;
5215
5185
5216
-
ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5186
+
ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex,
5217
5187
ctx);
5218
5188
if (ret)
5219
5189
return ret;
···
5231
5201
if (!intel_dp_needs_link_retrain(intel_dp))
5232
5202
return 0;
5233
5203
5234
-
drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link (forced %s)\n",
5204
+
drm_dbg_kms(display->drm,
5205
+
"[ENCODER:%d:%s] retraining link (forced %s)\n",
5235
5206
encoder->base.base.id, encoder->base.name,
5236
5207
str_yes_no(intel_dp->link.force_retrain));
5237
5208
···
5243
5212
intel_dp->link.force_retrain = false;
5244
5213
5245
5214
if (ret)
5246
-
drm_dbg_kms(&dev_priv->drm,
5215
+
drm_dbg_kms(display->drm,
5247
5216
"[ENCODER:%d:%s] link retraining failed: %pe\n",
5248
5217
encoder->base.base.id, encoder->base.name,
5249
5218
ERR_PTR(ret));
···
5276
5245
5277
5246
static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
5278
5247
{
5279
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5248
+
struct intel_display *display = to_intel_display(intel_dp);
5280
5249
u8 val;
5281
5250
5282
5251
if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
···
5295
5264
intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
5296
5265
5297
5266
if (val & DP_SINK_SPECIFIC_IRQ)
5298
-
drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
5267
+
drm_dbg_kms(display->drm, "Sink specific irq unhandled\n");
5299
5268
}
5300
5269
5301
5270
static bool intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
5302
5271
{
5303
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5272
+
struct intel_display *display = to_intel_display(intel_dp);
5304
5273
bool reprobe_needed = false;
5305
5274
u8 val;
5306
5275
···
5312
5281
return false;
5313
5282
5314
5283
if ((val & DP_TUNNELING_IRQ) &&
5315
-
drm_dp_tunnel_handle_irq(i915->display.dp_tunnel_mgr,
5284
+
drm_dp_tunnel_handle_irq(display->dp_tunnel_mgr,
5316
5285
&intel_dp->aux))
5317
5286
reprobe_needed = true;
5318
5287
···
5381
5350
static enum drm_connector_status
5382
5351
intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5383
5352
{
5384
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5353
+
struct intel_display *display = to_intel_display(intel_dp);
5385
5354
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5386
5355
u8 *dpcd = intel_dp->dpcd;
5387
5356
u8 type;
5388
5357
5389
-
if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
5358
+
if (drm_WARN_ON(display->drm, intel_dp_is_edp(intel_dp)))
5390
5359
return connector_status_connected;
5391
5360
5392
5361
lspcon_resume(dig_port);
···
5429
5398
}
5430
5399
5431
5400
/* Anything else is out of spec, warn and ignore */
5432
-
drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
5401
+
drm_dbg_kms(display->drm, "Broken DP branch device, ignoring\n");
5433
5402
return connector_status_disconnected;
5434
5403
}
5435
5404
···
5524
5493
intel_dp_update_dfp(struct intel_dp *intel_dp,
5525
5494
const struct drm_edid *drm_edid)
5526
5495
{
5527
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5496
+
struct intel_display *display = to_intel_display(intel_dp);
5528
5497
struct intel_connector *connector = intel_dp->attached_connector;
5529
5498
5530
5499
intel_dp->dfp.max_bpc =
···
5548
5517
drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
5549
5518
intel_dp->downstream_ports);
5550
5519
5551
-
drm_dbg_kms(&i915->drm,
5520
+
drm_dbg_kms(display->drm,
5552
5521
"[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
5553
5522
connector->base.base.id, connector->base.name,
5554
5523
intel_dp->dfp.max_bpc,
···
5581
5550
static void
5582
5551
intel_dp_update_420(struct intel_dp *intel_dp)
5583
5552
{
5584
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5553
+
struct intel_display *display = to_intel_display(intel_dp);
5585
5554
struct intel_connector *connector = intel_dp->attached_connector;
5586
5555
5587
5556
intel_dp->dfp.ycbcr420_passthrough =
···
5599
5568
5600
5569
connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp);
5601
5570
5602
-
drm_dbg_kms(&i915->drm,
5571
+
drm_dbg_kms(display->drm,
5603
5572
"[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
5604
5573
connector->base.base.id, connector->base.name,
5605
5574
str_yes_no(intel_dp->dfp.rgb_to_ycbcr),
···
5610
5579
static void
5611
5580
intel_dp_set_edid(struct intel_dp *intel_dp)
5612
5581
{
5613
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5582
+
struct intel_display *display = to_intel_display(intel_dp);
5614
5583
struct intel_connector *connector = intel_dp->attached_connector;
5615
5584
const struct drm_edid *drm_edid;
5616
5585
bool vrr_capable;
···
5623
5592
drm_edid_connector_update(&connector->base, drm_edid);
5624
5593
5625
5594
vrr_capable = intel_vrr_is_capable(connector);
5626
-
drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
5595
+
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
5627
5596
connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));
5628
5597
drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
5629
5598
···
5660
5629
static void
5661
5630
intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
5662
5631
{
5663
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5632
+
struct intel_display *display = to_intel_display(intel_dp);
5664
5633
5665
-
intel_dp->as_sdp_supported = HAS_AS_SDP(i915) &&
5634
+
intel_dp->as_sdp_supported = HAS_AS_SDP(display) &&
5666
5635
drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);
5667
5636
}
5668
5637
···
5672
5641
bool force)
5673
5642
{
5674
5643
struct intel_display *display = to_intel_display(_connector->dev);
5675
-
struct drm_i915_private *dev_priv = to_i915(_connector->dev);
5676
5644
struct intel_connector *connector = to_intel_connector(_connector);
5677
5645
struct intel_dp *intel_dp = intel_attached_dp(connector);
5678
5646
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
···
5679
5649
enum drm_connector_status status;
5680
5650
int ret;
5681
5651
5682
-
drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5652
+
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
5683
5653
connector->base.base.id, connector->base.name);
5684
-
drm_WARN_ON(&dev_priv->drm,
5685
-
!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5654
+
drm_WARN_ON(display->drm,
5655
+
!drm_modeset_is_locked(&display->drm->mode_config.connection_mutex));
5686
5656
5687
5657
if (!intel_display_device_enabled(display))
5688
5658
return connector_status_disconnected;
···
5810
5780
{
5811
5781
struct intel_display *display = to_intel_display(connector->dev);
5812
5782
struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5813
-
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5814
-
struct intel_encoder *encoder = &dig_port->base;
5815
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5816
5783
5817
-
drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5784
+
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
5818
5785
connector->base.id, connector->name);
5819
5786
5820
5787
if (!intel_display_driver_check_access(display))
···
5860
5833
static int
5861
5834
intel_dp_connector_register(struct drm_connector *connector)
5862
5835
{
5863
-
struct drm_i915_private *i915 = to_i915(connector->dev);
5836
+
struct intel_display *display = to_intel_display(connector->dev);
5864
5837
struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5865
5838
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5866
5839
struct intel_lspcon *lspcon = &dig_port->lspcon;
···
5870
5843
if (ret)
5871
5844
return ret;
5872
5845
5873
-
drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
5846
+
drm_dbg_kms(display->drm, "registering %s bus for %s\n",
5874
5847
intel_dp->aux.name, connector->kdev->kobj.name);
5875
5848
5876
5849
intel_dp->aux.dev = connector->kdev;
···
5907
5880
void intel_dp_connector_sync_state(struct intel_connector *connector,
5908
5881
const struct intel_crtc_state *crtc_state)
5909
5882
{
5910
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
5883
+
struct intel_display *display = to_intel_display(connector);
5911
5884
5912
5885
if (crtc_state && crtc_state->dsc.compression_enable) {
5913
-
drm_WARN_ON(&i915->drm, !connector->dp.dsc_decompression_aux);
5886
+
drm_WARN_ON(display->drm,
5887
+
!connector->dp.dsc_decompression_aux);
5914
5888
connector->dp.dsc_decompression_enabled = true;
5915
5889
} else {
5916
5890
connector->dp.dsc_decompression_enabled = false;
···
5960
5932
static int intel_modeset_tile_group(struct intel_atomic_state *state,
5961
5933
int tile_group_id)
5962
5934
{
5963
-
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5935
+
struct intel_display *display = to_intel_display(state);
5964
5936
struct drm_connector_list_iter conn_iter;
5965
5937
struct drm_connector *connector;
5966
5938
int ret = 0;
5967
5939
5968
-
drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
5940
+
drm_connector_list_iter_begin(display->drm, &conn_iter);
5969
5941
drm_for_each_connector_iter(connector, &conn_iter) {
5970
5942
struct drm_connector_state *conn_state;
5971
5943
struct intel_crtc_state *crtc_state;
···
6001
5973
6002
5974
static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
6003
5975
{
6004
-
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5976
+
struct intel_display *display = to_intel_display(state);
6005
5977
struct intel_crtc *crtc;
6006
5978
6007
5979
if (transcoders == 0)
6008
5980
return 0;
6009
5981
6010
-
for_each_intel_crtc(&dev_priv->drm, crtc) {
5982
+
for_each_intel_crtc(display->drm, crtc) {
6011
5983
struct intel_crtc_state *crtc_state;
6012
5984
int ret;
6013
5985
···
6034
6006
transcoders &= ~BIT(crtc_state->cpu_transcoder);
6035
6007
}
6036
6008
6037
-
drm_WARN_ON(&dev_priv->drm, transcoders != 0);
6009
+
drm_WARN_ON(display->drm, transcoders != 0);
6038
6010
6039
6011
return 0;
6040
6012
}
···
6068
6040
static int intel_dp_connector_atomic_check(struct drm_connector *conn,
6069
6041
struct drm_atomic_state *_state)
6070
6042
{
6071
-
struct drm_i915_private *dev_priv = to_i915(conn->dev);
6043
+
struct intel_display *display = to_intel_display(conn->dev);
6072
6044
struct intel_atomic_state *state = to_intel_atomic_state(_state);
6073
6045
struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(_state, conn);
6074
6046
struct intel_connector *intel_conn = to_intel_connector(conn);
···
6098
6070
* We don't enable port sync on BDW due to missing w/as and
6099
6071
* due to not having adjusted the modeset sequence appropriately.
6100
6072
*/
6101
-
if (DISPLAY_VER(dev_priv) < 9)
6073
+
if (DISPLAY_VER(display) < 9)
6102
6074
return 0;
6103
6075
6104
6076
if (conn->has_tile) {
···
6113
6085
static void intel_dp_oob_hotplug_event(struct drm_connector *connector,
6114
6086
enum drm_connector_status hpd_state)
6115
6087
{
6088
+
struct intel_display *display = to_intel_display(connector->dev);
6116
6089
struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
6117
6090
struct drm_i915_private *i915 = to_i915(connector->dev);
6118
6091
bool hpd_high = hpd_state == connector_status_connected;
···
6121
6092
bool need_work = false;
6122
6093
6123
6094
spin_lock_irq(&i915->irq_lock);
6124
-
if (hpd_high != test_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state)) {
6125
-
i915->display.hotplug.event_bits |= BIT(hpd_pin);
6095
+
if (hpd_high != test_bit(hpd_pin, &display->hotplug.oob_hotplug_last_state)) {
6096
+
display->hotplug.event_bits |= BIT(hpd_pin);
6126
6097
6127
-
__assign_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state, hpd_high);
6098
+
__assign_bit(hpd_pin,
6099
+
&display->hotplug.oob_hotplug_last_state,
6100
+
hpd_high);
6128
6101
need_work = true;
6129
6102
}
6130
6103
spin_unlock_irq(&i915->irq_lock);
···
6158
6127
enum irqreturn
6159
6128
intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
6160
6129
{
6130
+
struct intel_display *display = to_intel_display(dig_port);
6161
6131
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
6162
6132
struct intel_dp *intel_dp = &dig_port->dp;
6163
6133
u8 dpcd[DP_RECEIVER_CAP_SIZE];
···
6173
6141
* would end up in an endless cycle of
6174
6142
* "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
6175
6143
*/
6176
-
drm_dbg_kms(&i915->drm,
6144
+
drm_dbg_kms(display->drm,
6177
6145
"ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
6178
6146
long_hpd ? "long" : "short",
6179
6147
dig_port->base.base.base.id,
···
6181
6149
return IRQ_HANDLED;
6182
6150
}
6183
6151
6184
-
drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
6152
+
drm_dbg_kms(display->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
6185
6153
dig_port->base.base.base.id,
6186
6154
dig_port->base.base.name,
6187
6155
long_hpd ? "long" : "short");
···
6214
6182
return IRQ_HANDLED;
6215
6183
}
6216
6184
6217
-
static bool _intel_dp_is_port_edp(struct drm_i915_private *dev_priv,
6185
+
static bool _intel_dp_is_port_edp(struct intel_display *display,
6218
6186
const struct intel_bios_encoder_data *devdata,
6219
6187
enum port port)
6220
6188
{
···
6222
6190
* eDP not supported on g4x. so bail out early just
6223
6191
* for a bit extra safety in case the VBT is bonkers.
6224
6192
*/
6225
-
if (DISPLAY_VER(dev_priv) < 5)
6193
+
if (DISPLAY_VER(display) < 5)
6226
6194
return false;
6227
6195
6228
-
if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
6196
+
if (DISPLAY_VER(display) < 9 && port == PORT_A)
6229
6197
return true;
6230
6198
6231
6199
return devdata && intel_bios_encoder_supports_edp(devdata);
···
6237
6205
const struct intel_bios_encoder_data *devdata =
6238
6206
intel_bios_encoder_data_lookup(display, port);
6239
6207
6240
-
return _intel_dp_is_port_edp(i915, devdata, port);
6208
+
return _intel_dp_is_port_edp(display, devdata, port);
6241
6209
}
6242
6210
6243
6211
bool
6244
6212
intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder)
6245
6213
{
6246
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
6214
+
struct intel_display *display = to_intel_display(encoder);
6247
6215
enum port port = encoder->port;
6248
6216
6249
6217
if (intel_bios_encoder_is_lspcon(encoder->devdata))
6250
6218
return false;
6251
6219
6252
-
if (DISPLAY_VER(i915) >= 11)
6220
+
if (DISPLAY_VER(display) >= 11)
6253
6221
return true;
6254
6222
6255
6223
if (port == PORT_A)
6256
6224
return false;
6257
6225
6258
-
if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
6259
-
DISPLAY_VER(i915) >= 9)
6226
+
if (display->platform.haswell || display->platform.broadwell ||
6227
+
DISPLAY_VER(display) >= 9)
6260
6228
return true;
6261
6229
6262
6230
return false;
···
6265
6233
static void
6266
6234
intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
6267
6235
{
6268
-
struct drm_i915_private *dev_priv = to_i915(connector->dev);
6236
+
struct intel_display *display = to_intel_display(intel_dp);
6269
6237
enum port port = dp_to_dig_port(intel_dp)->base.port;
6270
6238
6271
6239
if (!intel_dp_is_edp(intel_dp))
6272
6240
drm_connector_attach_dp_subconnector_property(connector);
6273
6241
6274
-
if (!IS_G4X(dev_priv) && port != PORT_A)
6242
+
if (!display->platform.g4x && port != PORT_A)
6275
6243
intel_attach_force_audio_property(connector);
6276
6244
6277
6245
intel_attach_broadcast_rgb_property(connector);
6278
-
if (HAS_GMCH(dev_priv))
6246
+
if (HAS_GMCH(display))
6279
6247
drm_connector_attach_max_bpc_property(connector, 6, 10);
6280
-
else if (DISPLAY_VER(dev_priv) >= 5)
6248
+
else if (DISPLAY_VER(display) >= 5)
6281
6249
drm_connector_attach_max_bpc_property(connector, 6, 12);
6282
6250
6283
6251
/* Register HDMI colorspace for case of lspcon */
···
6291
6259
if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))
6292
6260
drm_connector_attach_hdr_output_metadata_property(connector);
6293
6261
6294
-
if (HAS_VRR(dev_priv))
6262
+
if (HAS_VRR(display))
6295
6263
drm_connector_attach_vrr_capable_property(connector);
6296
6264
}
6297
6265
6298
6266
static void
6299
6267
intel_edp_add_properties(struct intel_dp *intel_dp)
6300
6268
{
6269
+
struct intel_display *display = to_intel_display(intel_dp);
6301
6270
struct intel_connector *connector = intel_dp->attached_connector;
6302
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
6303
6271
const struct drm_display_mode *fixed_mode =
6304
6272
intel_panel_preferred_fixed_mode(connector);
6305
6273
6306
6274
intel_attach_scaling_mode_property(&connector->base);
6307
6275
6308
6276
drm_connector_set_panel_orientation_with_quirk(&connector->base,
6309
-
i915->display.vbt.orientation,
6277
+
display->vbt.orientation,
6310
6278
fixed_mode->hdisplay,
6311
6279
fixed_mode->vdisplay);
6312
6280
}
···
6314
6282
static void intel_edp_backlight_setup(struct intel_dp *intel_dp,
6315
6283
struct intel_connector *connector)
6316
6284
{
6317
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6285
+
struct intel_display *display = to_intel_display(intel_dp);
6318
6286
enum pipe pipe = INVALID_PIPE;
6319
6287
6320
-
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
6288
+
if (display->platform.valleyview || display->platform.cherryview)
6321
6289
pipe = vlv_pps_backlight_initial_pipe(intel_dp);
6322
6290
6323
6291
intel_backlight_setup(connector, pipe);
···
6327
6295
struct intel_connector *connector)
6328
6296
{
6329
6297
struct intel_display *display = to_intel_display(intel_dp);
6330
-
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6298
+
struct drm_i915_private *dev_priv = to_i915(display->drm);
6331
6299
struct drm_display_mode *fixed_mode;
6332
6300
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6333
6301
bool has_dpcd;
···
6343
6311
* with an already powered-on LVDS power sequencer.
6344
6312
*/
6345
6313
if (intel_get_lvds_encoder(dev_priv)) {
6346
-
drm_WARN_ON(&dev_priv->drm,
6314
+
drm_WARN_ON(display->drm,
6347
6315
!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6348
-
drm_info(&dev_priv->drm,
6316
+
drm_info(display->drm,
6349
6317
"LVDS was detected, not registering eDP\n");
6350
6318
6351
6319
return false;
···
6355
6323
encoder->devdata);
6356
6324
6357
6325
if (!intel_pps_init(intel_dp)) {
6358
-
drm_info(&dev_priv->drm,
6326
+
drm_info(display->drm,
6359
6327
"[ENCODER:%d:%s] unusable PPS, disabling eDP\n",
6360
6328
encoder->base.base.id, encoder->base.name);
6361
6329
/*
···
6382
6350
6383
6351
if (!has_dpcd) {
6384
6352
/* if this fails, presume the device is a ghost */
6385
-
drm_info(&dev_priv->drm,
6353
+
drm_info(display->drm,
6386
6354
"[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n",
6387
6355
encoder->base.base.id, encoder->base.name);
6388
6356
goto out_vdd_off;
···
6405
6373
* DPCD read? Would need sort out the VDD handling...
6406
6374
*/
6407
6375
if (!intel_digital_port_connected(encoder)) {
6408
-
drm_info(&dev_priv->drm,
6376
+
drm_info(display->drm,
6409
6377
"[ENCODER:%d:%s] HPD is down, disabling eDP\n",
6410
6378
encoder->base.base.id, encoder->base.name);
6411
6379
goto out_vdd_off;
···
6417
6385
* back to checking for a VGA branch device. Only do this
6418
6386
* on known affected platforms to minimize false positives.
6419
6387
*/
6420
-
if (DISPLAY_VER(dev_priv) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&
6388
+
if (DISPLAY_VER(display) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&
6421
6389
(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) ==
6422
6390
DP_DWN_STRM_PORT_TYPE_ANALOG) {
6423
-
drm_info(&dev_priv->drm,
6391
+
drm_info(display->drm,
6424
6392
"[ENCODER:%d:%s] VGA converter detected, disabling eDP\n",
6425
6393
encoder->base.base.id, encoder->base.name);
6426
6394
goto out_vdd_off;
6427
6395
}
6428
6396
}
6429
6397
6430
-
mutex_lock(&dev_priv->drm.mode_config.mutex);
6398
+
mutex_lock(&display->drm->mode_config.mutex);
6431
6399
drm_edid = drm_edid_read_ddc(&connector->base, connector->base.ddc);
6432
6400
if (!drm_edid) {
6433
6401
/* Fallback to EDID from ACPI OpRegion, if any */
6434
6402
drm_edid = intel_opregion_get_edid(connector);
6435
6403
if (drm_edid)
6436
-
drm_dbg_kms(&dev_priv->drm,
6404
+
drm_dbg_kms(display->drm,
6437
6405
"[CONNECTOR:%d:%s] Using OpRegion EDID\n",
6438
6406
connector->base.base.id, connector->base.name);
6439
6407
}
···
6464
6432
if (!intel_panel_preferred_fixed_mode(connector))
6465
6433
intel_panel_add_vbt_lfp_fixed_mode(connector);
6466
6434
6467
-
mutex_unlock(&dev_priv->drm.mode_config.mutex);
6435
+
mutex_unlock(&display->drm->mode_config.mutex);
6468
6436
6469
6437
if (!intel_panel_preferred_fixed_mode(connector)) {
6470
-
drm_info(&dev_priv->drm,
6438
+
drm_info(display->drm,
6471
6439
"[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n",
6472
6440
encoder->base.base.id, encoder->base.name);
6473
6441
goto out_vdd_off;
···
6543
6511
intel_dp->reset_link_params = true;
6544
6512
6545
6513
/* Preserve the current hw state. */
6546
-
intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
6514
+
intel_dp->DP = intel_de_read(display, intel_dp->output_reg);
6547
6515
intel_dp->attached_connector = connector;
6548
6516
6549
-
if (_intel_dp_is_port_edp(dev_priv, encoder->devdata, port)) {
6517
+
if (_intel_dp_is_port_edp(display, encoder->devdata, port)) {
6550
6518
/*
6551
6519
* Currently we don't support eDP on TypeC ports for DISPLAY_VER < 30,
6552
6520
* although in theory it could work on TypeC legacy ports.
6553
6521
*/
6554
6522
drm_WARN_ON(dev, intel_encoder_is_tc(encoder) &&
6555
-
DISPLAY_VER(dev_priv) < 30);
6523
+
DISPLAY_VER(display) < 30);
6556
6524
type = DRM_MODE_CONNECTOR_eDP;
6557
6525
encoder->type = INTEL_OUTPUT_EDP;
6558
6526
6559
6527
/* eDP only on port B and/or C on vlv/chv */
6560
-
if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
6561
-
IS_CHERRYVIEW(dev_priv)) &&
6528
+
if (drm_WARN_ON(dev, (display->platform.valleyview ||
6529
+
display->platform.cherryview) &&
6562
6530
port != PORT_B && port != PORT_C))
6563
6531
return false;
6564
6532
} else {
···
6568
6536
intel_dp_set_default_sink_rates(intel_dp);
6569
6537
intel_dp_set_default_max_sink_lane_count(intel_dp);
6570
6538
6571
-
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6539
+
if (display->platform.valleyview || display->platform.cherryview)
6572
6540
vlv_pps_pipe_init(intel_dp);
6573
6541
6574
6542
intel_dp_aux_init(intel_dp);
6575
6543
connector->dp.dsc_decompression_aux = &intel_dp->aux;
6576
6544
6577
-
drm_dbg_kms(&dev_priv->drm,
6545
+
drm_dbg_kms(display->drm,
6578
6546
"Adding %s connector on [ENCODER:%d:%s]\n",
6579
6547
type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6580
6548
encoder->base.base.id, encoder->base.name);
···
6583
6551
type, &intel_dp->aux.ddc);
6584
6552
drm_connector_helper_add(&connector->base, &intel_dp_connector_helper_funcs);
6585
6553
6586
-
if (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) < 12)
6554
+
if (!HAS_GMCH(display) && DISPLAY_VER(display) < 12)
6587
6555
connector->base.interlace_allowed = true;
6588
6556
6589
6557
if (type != DRM_MODE_CONNECTOR_eDP)
···
6592
6560
6593
6561
intel_connector_attach_encoder(connector, encoder);
6594
6562
6595
-
if (HAS_DDI(dev_priv))
6563
+
if (HAS_DDI(display))
6596
6564
connector->get_hw_state = intel_ddi_connector_get_hw_state;
6597
6565
else
6598
6566
connector->get_hw_state = intel_connector_get_hw_state;
···
6615
6583
if (is_hdcp_supported(display, port) && !intel_dp_is_edp(intel_dp)) {
6616
6584
int ret = intel_dp_hdcp_init(dig_port, connector);
6617
6585
if (ret)
6618
-
drm_dbg_kms(&dev_priv->drm,
6586
+
drm_dbg_kms(display->drm,
6619
6587
"HDCP init failed, skipping.\n");
6620
6588
}
6621
6589
···
6635
6603
6636
6604
void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
6637
6605
{
6606
+
struct intel_display *display = &dev_priv->display;
6638
6607
struct intel_encoder *encoder;
6639
6608
6640
-
if (!HAS_DISPLAY(dev_priv))
6609
+
if (!HAS_DISPLAY(display))
6641
6610
return;
6642
6611
6643
-
for_each_intel_encoder(&dev_priv->drm, encoder) {
6612
+
for_each_intel_encoder(display->drm, encoder) {
6644
6613
struct intel_dp *intel_dp;
6645
6614
6646
6615
if (encoder->type != INTEL_OUTPUT_DDI)
···
6659
6626
6660
6627
void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
6661
6628
{
6629
+
struct intel_display *display = &dev_priv->display;
6662
6630
struct intel_encoder *encoder;
6663
6631
6664
-
if (!HAS_DISPLAY(dev_priv))
6632
+
if (!HAS_DISPLAY(display))
6665
6633
return;
6666
6634
6667
-
for_each_intel_encoder(&dev_priv->drm, encoder) {
6635
+
for_each_intel_encoder(display->drm, encoder) {
6668
6636
struct intel_dp *intel_dp;
6669
6637
int ret;
6670
6638