Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
dt-bindings: watchdog: indentation, quotes and white-space cleanup
Minor cleanup without functional impact:
1. Indent DTS examples to preferred four-spaces (more readable for DTS),
2. Drop unneeded quotes,
3. Add/drop blank lines to make the code readable.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Acked-by: Justin Chen <justinpopo6@gmail.com>
Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230415095112.51257-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
authored by
Krzysztof Kozlowski
and committed by
Wim Van Sebroeck
819d1413
ab8da076
+83
-83
+5
-5
Documentation/devicetree/bindings/watchdog/amlogic,meson-gxbb-wdt.yaml
+5
-5
Documentation/devicetree/bindings/watchdog/amlogic,meson-gxbb-wdt.yaml
···
2
2
# Copyright 2019 BayLibre, SAS
3
3
%YAML 1.2
4
4
---
5
-
$id: "http://devicetree.org/schemas/watchdog/amlogic,meson-gxbb-wdt.yaml#"
6
-
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
5
+
$id: http://devicetree.org/schemas/watchdog/amlogic,meson-gxbb-wdt.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
7
8
8
title: Meson GXBB SoCs Watchdog timer
9
9
···
36
36
examples:
37
37
- |
38
38
watchdog@98d0 {
39
-
compatible = "amlogic,meson-gxbb-wdt";
40
-
reg = <0x98d0 0x10>;
41
-
clocks = <&xtal>;
39
+
compatible = "amlogic,meson-gxbb-wdt";
40
+
reg = <0x98d0 0x10>;
41
+
clocks = <&xtal>;
42
42
};
-1
Documentation/devicetree/bindings/watchdog/arm,sbsa-gwdt.yaml
-1
Documentation/devicetree/bindings/watchdog/arm,sbsa-gwdt.yaml
+3
-3
Documentation/devicetree/bindings/watchdog/arm,twd-wdt.yaml
+3
-3
Documentation/devicetree/bindings/watchdog/arm,twd-wdt.yaml
···
44
44
#include <dt-bindings/interrupt-controller/arm-gic.h>
45
45
46
46
watchdog@2c000620 {
47
-
compatible = "arm,arm11mp-twd-wdt";
48
-
reg = <0x2c000620 0x20>;
49
-
interrupts = <GIC_PPI 14 0xf01>;
47
+
compatible = "arm,arm11mp-twd-wdt";
48
+
reg = <0x2c000620 0x20>;
49
+
interrupts = <GIC_PPI 14 0xf01>;
50
50
};
+4
-3
Documentation/devicetree/bindings/watchdog/arm-smc-wdt.yaml
+4
-3
Documentation/devicetree/bindings/watchdog/arm-smc-wdt.yaml
···
16
16
compatible:
17
17
enum:
18
18
- arm,smc-wdt
19
+
19
20
arm,smc-id:
20
21
$ref: /schemas/types.yaml#/definitions/uint32
21
22
description: |
···
31
30
examples:
32
31
- |
33
32
watchdog {
34
-
compatible = "arm,smc-wdt";
35
-
arm,smc-id = <0x82003D06>;
36
-
timeout-sec = <15>;
33
+
compatible = "arm,smc-wdt";
34
+
arm,smc-id = <0x82003D06>;
35
+
timeout-sec = <15>;
37
36
};
38
37
39
38
...
+7
-7
Documentation/devicetree/bindings/watchdog/atmel,sama5d4-wdt.yaml
+7
-7
Documentation/devicetree/bindings/watchdog/atmel,sama5d4-wdt.yaml
···
65
65
#include <dt-bindings/interrupt-controller/irq.h>
66
66
67
67
watchdog@fc068640 {
68
-
compatible = "atmel,sama5d4-wdt";
69
-
reg = <0xfc068640 0x10>;
70
-
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 5>;
71
-
timeout-sec = <10>;
72
-
atmel,watchdog-type = "hardware";
73
-
atmel,dbg-halt;
74
-
atmel,idle-halt;
68
+
compatible = "atmel,sama5d4-wdt";
69
+
reg = <0xfc068640 0x10>;
70
+
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 5>;
71
+
timeout-sec = <10>;
72
+
atmel,watchdog-type = "hardware";
73
+
atmel,dbg-halt;
74
+
atmel,idle-halt;
75
75
};
76
76
77
77
...
+3
-3
Documentation/devicetree/bindings/watchdog/brcm,bcm7038-wdt.yaml
+3
-3
Documentation/devicetree/bindings/watchdog/brcm,bcm7038-wdt.yaml
+8
-8
Documentation/devicetree/bindings/watchdog/faraday,ftwdt010.yaml
+8
-8
Documentation/devicetree/bindings/watchdog/faraday,ftwdt010.yaml
···
52
52
- |
53
53
#include <dt-bindings/interrupt-controller/irq.h>
54
54
watchdog@41000000 {
55
-
compatible = "faraday,ftwdt010";
56
-
reg = <0x41000000 0x1000>;
57
-
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
58
-
timeout-sec = <5>;
55
+
compatible = "faraday,ftwdt010";
56
+
reg = <0x41000000 0x1000>;
57
+
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
58
+
timeout-sec = <5>;
59
59
};
60
60
- |
61
61
watchdog: watchdog@98500000 {
62
-
compatible = "moxa,moxart-watchdog", "faraday,ftwdt010";
63
-
reg = <0x98500000 0x10>;
64
-
clocks = <&clk_apb>;
65
-
clock-names = "PCLK";
62
+
compatible = "moxa,moxart-watchdog", "faraday,ftwdt010";
63
+
reg = <0x98500000 0x10>;
64
+
clocks = <&clk_apb>;
65
+
clock-names = "PCLK";
66
66
};
67
67
...
+3
-3
Documentation/devicetree/bindings/watchdog/mediatek,mt7621-wdt.yaml
+3
-3
Documentation/devicetree/bindings/watchdog/mediatek,mt7621-wdt.yaml
+16
-16
Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
+16
-16
Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
···
116
116
#include <dt-bindings/interrupt-controller/arm-gic.h>
117
117
118
118
watchdog@17c10000 {
119
-
compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
120
-
reg = <0x17c10000 0x1000>;
121
-
clocks = <&sleep_clk>;
122
-
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
123
-
timeout-sec = <10>;
119
+
compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
120
+
reg = <0x17c10000 0x1000>;
121
+
clocks = <&sleep_clk>;
122
+
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
123
+
timeout-sec = <10>;
124
124
};
125
125
126
126
- |
127
127
#include <dt-bindings/interrupt-controller/arm-gic.h>
128
128
129
129
watchdog@200a000 {
130
-
compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", "qcom,msm-timer";
131
-
interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
132
-
<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
133
-
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
134
-
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
135
-
<GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
136
-
reg = <0x0200a000 0x100>;
137
-
clock-frequency = <25000000>;
138
-
clocks = <&sleep_clk>;
139
-
clock-names = "sleep";
140
-
cpu-offset = <0x80000>;
130
+
compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", "qcom,msm-timer";
131
+
interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
132
+
<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
133
+
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
134
+
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
135
+
<GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
136
+
reg = <0x0200a000 0x100>;
137
+
clock-frequency = <25000000>;
138
+
clocks = <&sleep_clk>;
139
+
clock-names = "sleep";
140
+
cpu-offset = <0x80000>;
141
141
};
+7
-7
Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml
+7
-7
Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml
···
177
177
#include <dt-bindings/power/r8a7795-sysc.h>
178
178
#include <dt-bindings/interrupt-controller/arm-gic.h>
179
179
wdt0: watchdog@e6020000 {
180
-
compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt";
181
-
reg = <0xe6020000 0x0c>;
182
-
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
183
-
clocks = <&cpg CPG_MOD 402>;
184
-
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
185
-
resets = <&cpg 402>;
186
-
timeout-sec = <60>;
180
+
compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt";
181
+
reg = <0xe6020000 0x0c>;
182
+
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
183
+
clocks = <&cpg CPG_MOD 402>;
184
+
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
185
+
resets = <&cpg 402>;
186
+
timeout-sec = <60>;
187
187
};
+16
-16
Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml
+16
-16
Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml
···
83
83
examples:
84
84
- |
85
85
watchdog@ffd02000 {
86
-
compatible = "snps,dw-wdt";
87
-
reg = <0xffd02000 0x1000>;
88
-
interrupts = <0 171 4>;
89
-
clocks = <&per_base_clk>;
90
-
resets = <&wdt_rst>;
86
+
compatible = "snps,dw-wdt";
87
+
reg = <0xffd02000 0x1000>;
88
+
interrupts = <0 171 4>;
89
+
clocks = <&per_base_clk>;
90
+
resets = <&wdt_rst>;
91
91
};
92
92
93
93
- |
94
94
watchdog@ffd02000 {
95
-
compatible = "snps,dw-wdt";
96
-
reg = <0xffd02000 0x1000>;
97
-
interrupts = <0 171 4>;
98
-
clocks = <&per_base_clk>;
99
-
clock-names = "tclk";
100
-
snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
101
-
0x000007FF 0x0000FFFF 0x0001FFFF
102
-
0x0003FFFF 0x0007FFFF 0x000FFFFF
103
-
0x001FFFFF 0x003FFFFF 0x007FFFFF
104
-
0x00FFFFFF 0x01FFFFFF 0x03FFFFFF
105
-
0x07FFFFFF>;
95
+
compatible = "snps,dw-wdt";
96
+
reg = <0xffd02000 0x1000>;
97
+
interrupts = <0 171 4>;
98
+
clocks = <&per_base_clk>;
99
+
clock-names = "tclk";
100
+
snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
101
+
0x000007FF 0x0000FFFF 0x0001FFFF
102
+
0x0003FFFF 0x0007FFFF 0x000FFFFF
103
+
0x001FFFFF 0x003FFFFF 0x007FFFFF
104
+
0x00FFFFFF 0x01FFFFFF 0x03FFFFFF
105
+
0x07FFFFFF>;
106
106
};
107
107
...
+5
-5
Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.yaml
+5
-5
Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.yaml
···
48
48
- |
49
49
#include <dt-bindings/clock/stm32mp1-clks.h>
50
50
watchdog@5a002000 {
51
-
compatible = "st,stm32mp1-iwdg";
52
-
reg = <0x5a002000 0x400>;
53
-
clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
54
-
clock-names = "pclk", "lsi";
55
-
timeout-sec = <32>;
51
+
compatible = "st,stm32mp1-iwdg";
52
+
reg = <0x5a002000 0x400>;
53
+
clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
54
+
clock-names = "pclk", "lsi";
55
+
timeout-sec = <32>;
56
56
};
57
57
58
58
...
+6
-6
Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.yaml
+6
-6
Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.yaml
···
58
58
examples:
59
59
- |
60
60
watchdog@40100000 {
61
-
compatible = "xlnx,xps-timebase-wdt-1.00.a";
62
-
reg = <0x40100000 0x1000>;
63
-
clock-frequency = <50000000>;
64
-
clocks = <&clkc 15>;
65
-
xlnx,wdt-enable-once = <0x0>;
66
-
xlnx,wdt-interval = <0x1b>;
61
+
compatible = "xlnx,xps-timebase-wdt-1.00.a";
62
+
reg = <0x40100000 0x1000>;
63
+
clock-frequency = <50000000>;
64
+
clocks = <&clkc 15>;
65
+
xlnx,wdt-enable-once = <0x0>;
66
+
xlnx,wdt-interval = <0x1b>;
67
67
};
68
68
...