tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

Merge tag 'pci-v4.10-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI fixes from Bjorn Helgaas:

- recognize that a PCI-to-PCIe bridge originates a PCIe hierarchy, so
we enumerate that hierarchy correctly

- X-Gene: fix a change merged for v4.10 that broke MSI

- Keystone: avoid reading undefined registers, which can cause
asynchronous external aborts

- Supermicro X8DTH-i/6/iF/6F: ignore broken _CRS that caused us to
change (and break) existing I/O port assignments

* tag 'pci-v4.10-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
PCI/MSI: pci-xgene-msi: Fix CPU hotplug registration handling
PCI: Enumerate switches below PCI-to-PCIe bridges
x86/PCI: Ignore _CRS on Supermicro X8DTH-i/6/iF/6F
PCI: designware: Check for iATU unroll only on platforms that use ATU

Linus Torvalds 81aaeaac 2ed5e5af

+23 -11
+10
arch/x86/pci/acpi.c
··· 114 114 DMI_MATCH(DMI_BIOS_VERSION, "6JET85WW (1.43 )"), 115 115 }, 116 116 }, 117 + /* https://bugzilla.kernel.org/show_bug.cgi?id=42606 */ 118 + { 119 + .callback = set_nouse_crs, 120 + .ident = "Supermicro X8DTH", 121 + .matches = { 122 + DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), 123 + DMI_MATCH(DMI_PRODUCT_NAME, "X8DTH-i/6/iF/6F"), 124 + DMI_MATCH(DMI_BIOS_VERSION, "2.0a"), 125 + }, 126 + }, 117 127 118 128 /* https://bugzilla.kernel.org/show_bug.cgi?id=15362 */ 119 129 {
+1 -1
drivers/pci/host/pci-xgene-msi.c
··· 517 517 518 518 rc = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "pci/xgene:online", 519 519 xgene_msi_hwirq_alloc, NULL); 520 - if (rc) 520 + if (rc < 0) 521 521 goto err_cpuhp; 522 522 pci_xgene_online = rc; 523 523 rc = cpuhp_setup_state(CPUHP_PCI_XGENE_DEAD, "pci/xgene:dead", NULL,
+5 -5
drivers/pci/host/pcie-designware.c
··· 807 807 { 808 808 u32 val; 809 809 810 - /* get iATU unroll support */ 811 - pp->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pp); 812 - dev_dbg(pp->dev, "iATU unroll: %s\n", 813 - pp->iatu_unroll_enabled ? "enabled" : "disabled"); 814 - 815 810 /* set the number of lanes */ 816 811 val = dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL); 817 812 val &= ~PORT_LINK_MODE_MASK; ··· 877 882 * we should not program the ATU here. 878 883 */ 879 884 if (!pp->ops->rd_other_conf) { 885 + /* get iATU unroll support */ 886 + pp->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pp); 887 + dev_dbg(pp->dev, "iATU unroll: %s\n", 888 + pp->iatu_unroll_enabled ? "enabled" : "disabled"); 889 + 880 890 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, 881 891 PCIE_ATU_TYPE_MEM, pp->mem_base, 882 892 pp->mem_bus_addr, pp->mem_size);
+7 -5
drivers/pci/probe.c
··· 1169 1169 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); 1170 1170 if (!pos) 1171 1171 return; 1172 + 1172 1173 pdev->pcie_cap = pos; 1173 1174 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16); 1174 1175 pdev->pcie_flags_reg = reg16; ··· 1177 1176 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 1178 1177 1179 1178 /* 1180 - * A Root Port is always the upstream end of a Link. No PCIe 1181 - * component has two Links. Two Links are connected by a Switch 1182 - * that has a Port on each Link and internal logic to connect the 1183 - * two Ports. 1179 + * A Root Port or a PCI-to-PCIe bridge is always the upstream end 1180 + * of a Link. No PCIe component has two Links. Two Links are 1181 + * connected by a Switch that has a Port on each Link and internal 1182 + * logic to connect the two Ports. 1184 1183 */ 1185 1184 type = pci_pcie_type(pdev); 1186 - if (type == PCI_EXP_TYPE_ROOT_PORT) 1185 + if (type == PCI_EXP_TYPE_ROOT_PORT || 1186 + type == PCI_EXP_TYPE_PCIE_BRIDGE) 1187 1187 pdev->has_secondary_link = 1; 1188 1188 else if (type == PCI_EXP_TYPE_UPSTREAM || 1189 1189 type == PCI_EXP_TYPE_DOWNSTREAM) {