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drm/ast: Gen7: Switch default registers to gen4+ state

Change the default register settings for Gen7 to mach Gen4 and
later. Gen7 currently uses the settings for Gen1, which is most
likely incorrect.

Using Gen4+ settings enables E2M linear-access modes in VGACRA2.
It appears to be related to the chip's PCIE2MBOX feature, which
is unused.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>
Link: https://lore.kernel.org/r/20250706162816.211552-11-tzimmermann@suse.de

+1 -35
+1 -32
drivers/gpu/drm/ast/ast_2600.c
··· 33 33 * POST 34 34 */ 35 35 36 - void ast_2600_set_def_ext_reg(struct ast_device *ast) 37 - { 38 - static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff }; 39 - u8 i, index, reg; 40 - const u8 *ext_reg_info; 41 - 42 - /* reset scratch */ 43 - for (i = 0x81; i <= 0x9f; i++) 44 - ast_set_index_reg(ast, AST_IO_VGACRI, i, 0x00); 45 - 46 - ext_reg_info = extreginfo; 47 - index = 0xa0; 48 - while (*ext_reg_info != 0xff) { 49 - ast_set_index_reg_mask(ast, AST_IO_VGACRI, index, 0x00, *ext_reg_info); 50 - index++; 51 - ext_reg_info++; 52 - } 53 - 54 - /* disable standard IO/MEM decode if secondary */ 55 - /* ast_set_index_reg-mask(ast, AST_IO_VGACRI, 0xa1, 0xff, 0x3); */ 56 - 57 - /* Set Ext. Default */ 58 - ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x8c, 0x00, 0x01); 59 - ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x00, 0x00); 60 - 61 - /* Enable RAMDAC for A1 */ 62 - reg = 0x04; 63 - reg |= 0x20; 64 - ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xff, reg); 65 - } 66 - 67 36 int ast_2600_post(struct ast_device *ast) 68 37 { 69 - ast_2600_set_def_ext_reg(ast); 38 + ast_2300_set_def_ext_reg(ast); 70 39 71 40 if (ast->tx_chip == AST_TX_ASTDP) 72 41 return ast_dp_launch(ast);
-3
drivers/gpu/drm/ast/ast_post.h
··· 47 47 /* ast_2300.c */ 48 48 void ast_2300_set_def_ext_reg(struct ast_device *ast); 49 49 50 - /* ast_2600.c */ 51 - void ast_2600_set_def_ext_reg(struct ast_device *ast); 52 - 53 50 #endif