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drm/i915/display: Write PHY_CMN1_CONTROL only when using AUXLess ALPM

We are seeing "dmesg-warn/abort - *ERROR* PHY * failed after 3 retries"
since we started configuring LFPS sending. According to Bspec Configuring
LFPS sending is needed only when using AUXLess ALPM. This patch avoids
these failures by configuring LFPS sending only when using AUXLess ALPM.

Bspec: 68849
Fixes: 9dc619680de4 ("drm/i915/display: Add function to configure LFPS sending")
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://lore.kernel.org/r/20250722125618.1842615-2-jouni.hogander@intel.com

+3 -5
+3 -5
drivers/gpu/drm/i915/display/intel_cx0_phy.c
··· 3240 3240 { 3241 3241 struct intel_display *display = to_intel_display(encoder); 3242 3242 u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder); 3243 - bool enable = intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder), 3244 - crtc_state); 3245 3243 int i; 3246 3244 3247 - if (DISPLAY_VER(display) < 20) 3245 + if (DISPLAY_VER(display) < 20 || 3246 + !intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder), crtc_state)) 3248 3247 return; 3249 3248 3250 3249 for (i = 0; i < 4; i++) { ··· 3255 3256 3256 3257 intel_cx0_rmw(encoder, lane_mask, PHY_CMN1_CONTROL(tx, 0), 3257 3258 CONTROL0_MAC_TRANSMIT_LFPS, 3258 - enable ? CONTROL0_MAC_TRANSMIT_LFPS : 0, 3259 - MB_WRITE_COMMITTED); 3259 + CONTROL0_MAC_TRANSMIT_LFPS, MB_WRITE_COMMITTED); 3260 3260 } 3261 3261 } 3262 3262