Merge tag 'media/v5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media

+7 -7

Documentation/admin-guide/media/vimc.dot

··· 9 9 n00000003:port0 -> n00000008:port0 [style=bold] 10 10 n00000003:port0 -> n0000000f [style=bold] 11 11 n00000005 [label="{{<port0> 0} | Debayer A\n/dev/v4l-subdev2 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green] 12 - n00000005:port1 -> n00000017:port0 12 + n00000005:port1 -> n00000015:port0 13 13 n00000008 [label="{{<port0> 0} | Debayer B\n/dev/v4l-subdev3 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green] 14 - n00000008:port1 -> n00000017:port0 [style=dashed] 14 + n00000008:port1 -> n00000015:port0 [style=dashed] 15 15 n0000000b [label="Raw Capture 0\n/dev/video0", shape=box, style=filled, fillcolor=yellow] 16 16 n0000000f [label="Raw Capture 1\n/dev/video1", shape=box, style=filled, fillcolor=yellow] 17 - n00000013 [label="RGB/YUV Input\n/dev/video2", shape=box, style=filled, fillcolor=yellow] 18 - n00000013 -> n00000017:port0 [style=dashed] 19 - n00000017 [label="{{<port0> 0} | Scaler\n/dev/v4l-subdev4 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green] 20 - n00000017:port1 -> n0000001a [style=bold] 21 - n0000001a [label="RGB/YUV Capture\n/dev/video3", shape=box, style=filled, fillcolor=yellow] 17 + n00000013 [label="{{} | RGB/YUV Input\n/dev/v4l-subdev4 | {<port0> 0}}", shape=Mrecord, style=filled, fillcolor=green] 18 + n00000013:port0 -> n00000015:port0 [style=dashed] 19 + n00000015 [label="{{<port0> 0} | Scaler\n/dev/v4l-subdev5 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green] 20 + n00000015:port1 -> n00000018 [style=bold] 21 + n00000018 [label="RGB/YUV Capture\n/dev/video2", shape=box, style=filled, fillcolor=yellow] 22 22 }

-9

Documentation/devicetree/bindings/media/i2c/dongwoon,dw9807-vcm.txt

··· 1 - Dongwoon Anatech DW9807 voice coil lens driver 2 - 3 - DW9807 is a 10-bit DAC with current sink capability. It is intended for 4 - controlling voice coil lenses. 5 - 6 - Mandatory properties: 7 - 8 - - compatible: "dongwoon,dw9807-vcm" 9 - - reg: I2C slave address

+41

Documentation/devicetree/bindings/media/i2c/dongwoon,dw9807-vcm.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + # Copyright (C) 2018, 2021 Intel Corporation 3 + %YAML 1.2 4 + --- 5 + $id: http://devicetree.org/schemas/media/i2c/dongwoon,dw9807-vcm.yaml# 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 + 8 + title: Dongwoon Anatech DW9807 voice coil lens driver 9 + 10 + maintainers: 11 + - Sakari Ailus <sakari.ailus@linux.intel.com> 12 + 13 + description: | 14 + DW9807 is a 10-bit DAC with current sink capability. It is intended for 15 + controlling voice coil lenses. 16 + 17 + properties: 18 + compatible: 19 + const: dongwoon,dw9807-vcm 20 + 21 + reg: 22 + maxItems: 1 23 + 24 + required: 25 + - compatible 26 + - reg 27 + 28 + additionalProperties: false 29 + 30 + examples: 31 + - | 32 + i2c { 33 + #address-cells = <1>; 34 + #size-cells = <0>; 35 + 36 + lens@e { 37 + compatible = "dongwoon,dw9807-vcm"; 38 + reg = <0x0e>; 39 + }; 40 + }; 41 + ...

+9

Documentation/devicetree/bindings/media/i2c/sony,imx412.yaml

··· 32 32 description: Clock frequency 6MHz, 12MHz, 18MHz, 24MHz or 27MHz 33 33 maxItems: 1 34 34 35 + dovdd-supply: 36 + description: Interface power supply. 37 + 38 + avdd-supply: 39 + description: Analog power supply. 40 + 41 + dvdd-supply: 42 + description: Digital power supply. 43 + 35 44 reset-gpios: 36 45 description: Reference to the GPIO connected to the XCLR pin, if any. 37 46 maxItems: 1

+3

Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml

··· 63 63 description: 64 64 Describes point to scp. 65 65 66 + power-domains: 67 + maxItems: 1 68 + 66 69 required: 67 70 - compatible 68 71 - reg

+3 -1

Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml

··· 47 47 48 48 properties: 49 49 compatible: 50 - const: mediatek,mt8192-vcodec-dec 50 + enum: 51 + - mediatek,mt8192-vcodec-dec 52 + - mediatek,mt8186-vcodec-dec 51 53 52 54 reg: 53 55 maxItems: 1

+1 -1

Documentation/devicetree/bindings/media/microchip,xisc.yaml

··· 67 67 remote-endpoint: true 68 68 69 69 bus-width: 70 - enum: [8, 9, 10, 11, 12] 70 + enum: [8, 9, 10, 11, 12, 14] 71 71 default: 12 72 72 73 73 hsync-active:

+3 -1

Documentation/devicetree/bindings/media/rockchip,vdec.yaml

··· 18 18 oneOf: 19 19 - const: rockchip,rk3399-vdec 20 20 - items: 21 - - const: rockchip,rk3228-vdec 21 + - enum: 22 + - rockchip,rk3228-vdec 23 + - rockchip,rk3328-vdec 22 24 - const: rockchip,rk3399-vdec 23 25 24 26 reg:

+1

Documentation/devicetree/bindings/media/rockchip-vpu.yaml

··· 23 23 - rockchip,rk3328-vpu 24 24 - rockchip,rk3399-vpu 25 25 - rockchip,px30-vpu 26 + - rockchip,rk3568-vpu 26 27 - items: 27 28 - const: rockchip,rk3188-vpu 28 29 - const: rockchip,rk3066-vpu

+1

Documentation/devicetree/bindings/media/video-interfaces.yaml

··· 93 93 - 4 # MIPI CSI-2 D-PHY 94 94 - 5 # Parallel 95 95 - 6 # BT.656 96 + - 7 # DPI 96 97 description: 97 98 Data bus type. 98 99

+12 -1

Documentation/driver-api/media/cec-core.rst

··· 109 109 int (*adap_monitor_all_enable)(struct cec_adapter *adap, bool enable); 110 110 int (*adap_monitor_pin_enable)(struct cec_adapter *adap, bool enable); 111 111 int (*adap_log_addr)(struct cec_adapter *adap, u8 logical_addr); 112 + void (*adap_configured)(struct cec_adapter *adap, bool configured); 112 113 int (*adap_transmit)(struct cec_adapter *adap, u8 attempts, 113 114 u32 signal_free_time, struct cec_msg *msg); 114 115 void (*adap_status)(struct cec_adapter *adap, struct seq_file *file); ··· 118 117 /* Error injection callbacks */ 119 118 ... 120 119 121 - /* High-level callbacks */ 120 + /* High-level callback */ 122 121 ... 123 122 }; 124 123 ··· 177 176 can receive directed messages to that address. 178 177 179 178 Note that adap_log_addr must return 0 if logical_addr is CEC_LOG_ADDR_INVALID. 179 + 180 + 181 + Called when the adapter is fully configured or unconfigured:: 182 + 183 + void (*adap_configured)(struct cec_adapter *adap, bool configured); 184 + 185 + If configured == true, then the adapter is fully configured, i.e. all logical 186 + addresses have been successfully claimed. If configured == false, then the 187 + adapter is unconfigured. If the driver has to take specific actions after 188 + (un)configuration, then that can be done through this optional callback. 180 189 181 190 182 191 To transmit a new message::

+10 -3

Documentation/driver-api/media/mc-core.rst

··· 42 42 embedding the :c:type:`media_device` instance in a larger driver-specific 43 43 structure. 44 44 45 - Drivers register media device instances by calling 46 - :c:func:`__media_device_register()` via the macro ``media_device_register()`` 47 - and unregistered by calling :c:func:`media_device_unregister()`. 45 + Drivers initialise media device instances by calling 46 + :c:func:`media_device_init()`. After initialising a media device instance, it is 47 + registered by calling :c:func:`__media_device_register()` via the macro 48 + ``media_device_register()`` and unregistered by calling 49 + :c:func:`media_device_unregister()`. An initialised media device must be 50 + eventually cleaned up by calling :c:func:`media_device_cleanup()`. 51 + 52 + Note that it is not allowed to unregister a media device instance that was not 53 + previously registered, or clean up a media device instance that was not 54 + previously initialised. 48 55 49 56 Entities 50 57 ^^^^^^^^

+69

Documentation/driver-api/media/v4l2-subdev.rst

··· 518 518 :c:type:`i2c_board_info` structure using the ``client_type`` and the 519 519 ``addr`` to fill it. 520 520 521 + Centrally managed subdev active state 522 + ------------------------------------- 523 + 524 + Traditionally V4L2 subdev drivers maintained internal state for the active 525 + device configuration. This is often implemented as e.g. an array of struct 526 + v4l2_mbus_framefmt, one entry for each pad, and similarly for crop and compose 527 + rectangles. 528 + 529 + In addition to the active configuration, each subdev file handle has an array of 530 + struct v4l2_subdev_pad_config, managed by the V4L2 core, which contains the try 531 + configuration. 532 + 533 + To simplify the subdev drivers the V4L2 subdev API now optionally supports a 534 + centrally managed active configuration represented by 535 + :c:type:`v4l2_subdev_state`. One instance of state, which contains the active 536 + device configuration, is stored in the sub-device itself as part of 537 + the :c:type:`v4l2_subdev` structure, while the core associates a try state to 538 + each open file handle, to store the try configuration related to that file 539 + handle. 540 + 541 + Sub-device drivers can opt-in and use state to manage their active configuration 542 + by initializing the subdevice state with a call to v4l2_subdev_init_finalize() 543 + before registering the sub-device. They must also call v4l2_subdev_cleanup() 544 + to release all the allocated resources before unregistering the sub-device. 545 + The core automatically allocates and initializes a state for each open file 546 + handle to store the try configurations and frees it when closing the file 547 + handle. 548 + 549 + V4L2 sub-device operations that use both the :ref:`ACTIVE and TRY formats 550 + <v4l2-subdev-format-whence>` receive the correct state to operate on through 551 + the 'state' parameter. The state must be locked and unlocked by the 552 + caller by calling :c:func:`v4l2_subdev_lock_state()` and 553 + :c:func:`v4l2_subdev_unlock_state()`. The caller can do so by calling the subdev 554 + operation through the :c:func:`v4l2_subdev_call_state_active()` macro. 555 + 556 + Operations that do not receive a state parameter implicitly operate on the 557 + subdevice active state, which drivers can exclusively access by 558 + calling :c:func:`v4l2_subdev_lock_and_get_active_state()`. The sub-device active 559 + state must equally be released by calling :c:func:`v4l2_subdev_unlock_state()`. 560 + 561 + Drivers must never manually access the state stored in the :c:type:`v4l2_subdev` 562 + or in the file handle without going through the designated helpers. 563 + 564 + While the V4L2 core passes the correct try or active state to the subdevice 565 + operations, many existing device drivers pass a NULL state when calling 566 + operations with :c:func:`v4l2_subdev_call()`. This legacy construct causes 567 + issues with subdevice drivers that let the V4L2 core manage the active state, 568 + as they expect to receive the appropriate state as a parameter. To help the 569 + conversion of subdevice drivers to a managed active state without having to 570 + convert all callers at the same time, an additional wrapper layer has been 571 + added to v4l2_subdev_call(), which handles the NULL case by geting and locking 572 + the callee's active state with :c:func:`v4l2_subdev_lock_and_get_active_state()`, 573 + and unlocking the state after the call. 574 + 575 + The whole subdev state is in reality split into three parts: the 576 + v4l2_subdev_state, subdev controls and subdev driver's internal state. In the 577 + future these parts should be combined into a single state. For the time being 578 + we need a way to handle the locking for these parts. This can be accomplished 579 + by sharing a lock. The v4l2_ctrl_handler already supports this via its 'lock' 580 + pointer and the same model is used with states. The driver can do the following 581 + before calling v4l2_subdev_init_finalize(): 582 + 583 + .. code-block:: c 584 + 585 + sd->ctrl_handler->lock = &priv->mutex; 586 + sd->state_lock = &priv->mutex; 587 + 588 + This shares the driver's private mutex between the controls and the states. 589 + 521 590 V4L2 sub-device functions and data structures 522 591 --------------------------------------------- 523 592

+1 -1

Documentation/userspace-api/media/drivers/uvcvideo.rst

··· 7 7 driver-specific ioctls and implementation notes. 8 8 9 9 Questions and remarks can be sent to the Linux UVC development mailing list at 10 - linux-uvc-devel@lists.berlios.de. 10 + linux-media@vger.kernel.org. 11 11 12 12 13 13 Extension Unit (XU) support

+6

Documentation/userspace-api/media/mediactl/media-controller-model.rst

··· 33 33 34 34 - An **interface link** is a point-to-point bidirectional control 35 35 connection between a Linux Kernel interface and an entity. 36 + 37 + - An **ancillary link** is a point-to-point connection denoting that two 38 + entities form a single logical unit. For example this could represent the 39 + fact that a particular camera sensor and lens controller form a single 40 + physical module, meaning this lens controller drives the lens for this 41 + camera sensor.

+12 -5

Documentation/userspace-api/media/mediactl/media-types.rst

··· 412 412 is set by drivers and is read-only for applications. 413 413 414 414 * - ``MEDIA_LNK_FL_LINK_TYPE`` 415 - - This is a bitmask that defines the type of the link. Currently, 416 - two types of links are supported: 415 + - This is a bitmask that defines the type of the link. The following 416 + link types are currently supported: 417 417 418 418 .. _MEDIA-LNK-FL-DATA-LINK: 419 419 420 - ``MEDIA_LNK_FL_DATA_LINK`` if the link is between two pads 420 + ``MEDIA_LNK_FL_DATA_LINK`` for links that represent a data connection 421 + between two pads. 421 422 422 423 .. _MEDIA-LNK-FL-INTERFACE-LINK: 423 424 424 - ``MEDIA_LNK_FL_INTERFACE_LINK`` if the link is between an 425 - interface and an entity 425 + ``MEDIA_LNK_FL_INTERFACE_LINK`` for links that associate an entity to its 426 + interface. 427 + 428 + .. _MEDIA-LNK-FL-ANCILLARY-LINK: 429 + 430 + ``MEDIA_LNK_FL_ANCILLARY_LINK`` for links that represent a physical 431 + relationship between two entities. The link may or may not be 432 + immutable, so applications must not assume either case.

+8 -1

Documentation/userspace-api/media/v4l/dev-decoder.rst

··· 72 72 coded width 73 73 width for given coded resolution. 74 74 75 + coding tree unit 76 + processing unit of the HEVC codec (corresponds to macroblock units in 77 + H.264, VP8, VP9), 78 + can use block structures of up to 64×64 pixels. 79 + Good at sub-partitioning the picture into variable sized structures. 80 + 75 81 decode order 76 82 the order in which frames are decoded; may differ from display order if the 77 83 coded format includes a feature of frame reordering; for decoders, ··· 110 104 macroblock 111 105 a processing unit in image and video compression formats based on linear 112 106 block transforms (e.g. H.264, VP8, VP9); codec-specific, but for most of 113 - popular codecs the size is 16x16 samples (pixels). 107 + popular codecs the size is 16x16 samples (pixels). The HEVC codec uses a 108 + slightly more flexible processing unit called coding tree unit (CTU). 114 109 115 110 OUTPUT 116 111 the source buffer queue; for decoders, the queue of buffers containing

+8 -2

Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst

··· 649 649 :c:type:`timeval` in struct :c:type:`v4l2_buffer` to a __u64. 650 650 * - __u32 651 651 - ``pic_num`` 652 - - 652 + - For short term references, this must match the derived value PicNum 653 + (8-28) and for long term references it must match the derived value 654 + LongTermPicNum (8-29). When decoding frames (as opposed to fields) 655 + pic_num is the same as FrameNumWrap. 653 656 * - __u16 654 657 - ``frame_num`` 655 - - 658 + - For short term references, this must match the frame_num value from 659 + the slice header syntax (the driver will wrap the value if needed). For 660 + long term references, this must be set to the value of 661 + long_term_frame_idx described in the dec_ref_pic_marking() syntax. 656 662 * - __u8 657 663 - ``fields`` 658 664 - Specifies how the DPB entry is referenced. See :ref:`Reference Fields <h264_ref_fields>`

+22

Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst

··· 1180 1180 is set to non zero value. 1181 1181 Applicable to H264, H263 and MPEG4 encoder. 1182 1182 1183 + ``V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE (enum)`` 1184 + 1185 + enum v4l2_mpeg_video_intra_refresh_period_type - 1186 + Sets the type of intra refresh. The period to refresh 1187 + the whole frame is specified by V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD. 1188 + Note that if this control is not present, then it is undefined what 1189 + refresh type is used and it is up to the driver to decide. 1190 + Applicable to H264 and HEVC encoders. Possible values are: 1191 + 1192 + .. tabularcolumns:: |p{9.6cm}|p{7.9cm}| 1193 + 1194 + .. flat-table:: 1195 + :header-rows: 0 1196 + :stub-columns: 0 1197 + 1198 + * - ``V4L2_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM`` 1199 + - The whole frame is completely refreshed randomly 1200 + after the specified period. 1201 + * - ``V4L2_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC`` 1202 + - The whole frame MBs are completely refreshed in cyclic order 1203 + after the specified period. 1204 + 1183 1205 ``V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD (integer)`` 1184 1206 Intra macroblock refresh period. This sets the period to refresh 1185 1207 the whole frame. In other words, this defines the number of frames

+19

Documentation/userspace-api/media/v4l/pixfmt-reserved.rst

··· 239 239 It remains an opaque intermediate format and the MDP hardware must be 240 240 used to convert ``V4L2_PIX_FMT_MT21C`` to ``V4L2_PIX_FMT_NV12M``, 241 241 ``V4L2_PIX_FMT_YUV420M`` or ``V4L2_PIX_FMT_YVU420``. 242 + * .. _V4L2-PIX-FMT-QC08C: 243 + 244 + - ``V4L2_PIX_FMT_QC08C`` 245 + - 'QC08C' 246 + - Compressed Macro-tile 8-Bit YUV420 format used by Qualcomm platforms. 247 + It is an opaque intermediate format. The used compression is lossless 248 + and it is used by various multimedia hardware blocks like GPU, display 249 + controllers, ISP and video accelerators. 250 + It contains four planes for progressive video and eight planes for 251 + interlaced video. 252 + * .. _V4L2-PIX-FMT-QC10C: 253 + 254 + - ``V4L2_PIX_FMT_QC10C`` 255 + - 'QC10C' 256 + - Compressed Macro-tile 10-Bit YUV420 format used by Qualcomm platforms. 257 + It is an opaque intermediate format. The used compression is lossless 258 + and it is used by various multimedia hardware blocks like GPU, display 259 + controllers, ISP and video accelerators. 260 + It contains four planes for progressive video. 242 261 .. raw:: latex 243 262 244 263 \normalsize

+13 -1

Documentation/userspace-api/media/v4l/pixfmt-yuv-luma.rst

··· 48 48 - ... 49 49 - ... 50 50 51 + * .. _V4L2-PIX-FMT-IPU3-Y10: 52 + 53 + - ``V4L2_PIX_FMT_IPU3_Y10`` 54 + - 'ip3y' 55 + 56 + - Y'\ :sub:`0`\ [7:0] 57 + - Y'\ :sub:`1`\ [5:0] Y'\ :sub:`0`\ [9:8] 58 + - Y'\ :sub:`2`\ [3:0] Y'\ :sub:`1`\ [9:6] 59 + - Y'\ :sub:`3`\ [1:0] Y'\ :sub:`2`\ [9:4] 60 + - Y'\ :sub:`3`\ [9:2] 61 + 51 62 * .. _V4L2-PIX-FMT-Y10: 52 63 53 64 - ``V4L2_PIX_FMT_Y10`` ··· 144 133 145 134 For the Y16 and Y16_BE formats, the actual sampling precision may be lower 146 135 than 16 bits. For example, 10 bits per pixel uses values in the range 0 to 147 - 1023. 136 + 1023. For the IPU3_Y10 format 25 pixels are packed into 32 bytes, which 137 + leaves the 6 most significant bits of the last byte padded with 0.

+1 -2

Documentation/userspace-api/media/v4l/vidioc-streamon.rst

··· 43 43 Capture hardware is disabled and no input buffers are filled (if there 44 44 are any empty buffers in the incoming queue) until ``VIDIOC_STREAMON`` 45 45 has been called. Output hardware is disabled and no video signal is 46 - produced until ``VIDIOC_STREAMON`` has been called. The ioctl will 47 - succeed when at least one output buffer is in the incoming queue. 46 + produced until ``VIDIOC_STREAMON`` has been called. 48 47 49 48 Memory-to-memory devices will not start until ``VIDIOC_STREAMON`` has 50 49 been called for both the capture and output stream types.

+5 -7

MAINTAINERS

··· 12194 12194 F: Documentation/admin-guide/media/imx7.rst 12195 12195 F: Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml 12196 12196 F: Documentation/devicetree/bindings/media/nxp,imx7-csi.yaml 12197 - F: drivers/media/platform/imx/imx-mipi-csis.c 12197 + F: drivers/media/platform/nxp/imx-mipi-csis.c 12198 12198 F: drivers/staging/media/imx/imx7-media-csi.c 12199 12199 12200 12200 MEDIA DRIVERS FOR HELENE ··· 12249 12249 L: linux-tegra@vger.kernel.org 12250 12250 S: Maintained 12251 12251 T: git git://linuxtv.org/media_tree.git 12252 - F: Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt 12252 + F: Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml 12253 12253 F: drivers/media/platform/nvidia/tegra-vde/ 12254 12254 12255 12255 MEDIA DRIVERS FOR RENESAS - CEU ··· 12412 12412 F: include/dt-bindings/memory/mt*-port.h 12413 12413 12414 12414 MEDIATEK JPEG DRIVER 12415 - M: Rick Chang <rick.chang@mediatek.com> 12416 12415 M: Bin Liu <bin.liu@mediatek.com> 12417 12416 S: Supported 12418 - F: Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.txt 12417 + F: Documentation/devicetree/bindings/media/mediatek-jpeg-*.yaml 12419 12418 F: drivers/media/platform/mediatek/jpeg/ 12420 12419 12421 12420 MEDIATEK MDP DRIVER ··· 12430 12431 M: Tiffany Lin <tiffany.lin@mediatek.com> 12431 12432 M: Andrew-CT Chen <andrew-ct.chen@mediatek.com> 12432 12433 S: Supported 12433 - F: Documentation/devicetree/bindings/media/mediatek-vcodec.txt 12434 + F: Documentation/devicetree/bindings/media/mediatek,vcodec*.yaml 12434 12435 F: Documentation/devicetree/bindings/media/mediatek-vpu.txt 12435 12436 F: drivers/media/platform/mediatek/vcodec/ 12436 12437 F: drivers/media/platform/mediatek/vpu/ ··· 14245 14246 L: linux-media@vger.kernel.org 14246 14247 S: Maintained 14247 14248 F: Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml 14248 - F: drivers/media/platform/imx-jpeg 14249 + F: drivers/media/platform/nxp/imx-jpeg 14249 14250 14250 14251 NZXT-KRAKEN2 HARDWARE MONITORING DRIVER 14251 14252 M: Jonas Malaco <jonas@protocubo.io> ··· 20582 20583 20583 20584 USB VIDEO CLASS 20584 20585 M: Laurent Pinchart <laurent.pinchart@ideasonboard.com> 20585 - L: linux-uvc-devel@lists.sourceforge.net (subscribers-only) 20586 20586 L: linux-media@vger.kernel.org 20587 20587 S: Maintained 20588 20588 W: http://www.ideasonboard.org/uvc/

+180 -114

drivers/media/cec/core/cec-adap.c

··· 27 27 struct cec_msg *msg, 28 28 unsigned int la_idx); 29 29 30 - /* 31 - * 400 ms is the time it takes for one 16 byte message to be 32 - * transferred and 5 is the maximum number of retries. Add 33 - * another 100 ms as a margin. So if the transmit doesn't 34 - * finish before that time something is really wrong and we 35 - * have to time out. 36 - * 37 - * This is a sign that something it really wrong and a warning 38 - * will be issued. 39 - */ 40 - #define CEC_XFER_TIMEOUT_MS (5 * 400 + 100) 41 - 42 - #define call_op(adap, op, arg...) \ 43 - (adap->ops->op ? adap->ops->op(adap, ## arg) : 0) 44 - 45 - #define call_void_op(adap, op, arg...) \ 46 - do { \ 47 - if (adap->ops->op) \ 48 - adap->ops->op(adap, ## arg); \ 49 - } while (0) 50 - 51 30 static int cec_log_addr2idx(const struct cec_adapter *adap, u8 log_addr) 52 31 { 53 32 int i; ··· 345 366 /* 346 367 * A pending CEC transmit needs to be cancelled, either because the CEC 347 368 * adapter is disabled or the transmit takes an impossibly long time to 348 - * finish. 369 + * finish, or the reply timed out. 349 370 * 350 371 * This function is called with adap->lock held. 351 372 */ 352 - static void cec_data_cancel(struct cec_data *data, u8 tx_status) 373 + static void cec_data_cancel(struct cec_data *data, u8 tx_status, u8 rx_status) 353 374 { 375 + struct cec_adapter *adap = data->adap; 376 + 354 377 /* 355 378 * It's either the current transmit, or it is a pending 356 379 * transmit. Take the appropriate action to clear it. 357 380 */ 358 - if (data->adap->transmitting == data) { 359 - data->adap->transmitting = NULL; 381 + if (adap->transmitting == data) { 382 + adap->transmitting = NULL; 360 383 } else { 361 384 list_del_init(&data->list); 362 385 if (!(data->msg.tx_status & CEC_TX_STATUS_OK)) 363 - if (!WARN_ON(!data->adap->transmit_queue_sz)) 364 - data->adap->transmit_queue_sz--; 386 + if (!WARN_ON(!adap->transmit_queue_sz)) 387 + adap->transmit_queue_sz--; 365 388 } 366 389 367 390 if (data->msg.tx_status & CEC_TX_STATUS_OK) { 368 391 data->msg.rx_ts = ktime_get_ns(); 369 - data->msg.rx_status = CEC_RX_STATUS_ABORTED; 392 + data->msg.rx_status = rx_status; 393 + if (!data->blocking) 394 + data->msg.tx_status = 0; 370 395 } else { 371 396 data->msg.tx_ts = ktime_get_ns(); 372 397 data->msg.tx_status |= tx_status | 373 398 CEC_TX_STATUS_MAX_RETRIES; 374 399 data->msg.tx_error_cnt++; 375 400 data->attempts = 0; 401 + if (!data->blocking) 402 + data->msg.rx_status = 0; 376 403 } 377 404 378 405 /* Queue transmitted message for monitoring purposes */ 379 - cec_queue_msg_monitor(data->adap, &data->msg, 1); 406 + cec_queue_msg_monitor(adap, &data->msg, 1); 407 + 408 + if (!data->blocking && data->msg.sequence) 409 + /* Allow drivers to process the message first */ 410 + call_op(adap, received, &data->msg); 380 411 381 412 cec_data_completed(data); 382 413 } ··· 407 418 while (!list_empty(&adap->transmit_queue)) { 408 419 data = list_first_entry(&adap->transmit_queue, 409 420 struct cec_data, list); 410 - cec_data_cancel(data, CEC_TX_STATUS_ABORTED); 421 + cec_data_cancel(data, CEC_TX_STATUS_ABORTED, 0); 411 422 } 412 423 if (adap->transmitting) 413 - cec_data_cancel(adap->transmitting, CEC_TX_STATUS_ABORTED); 424 + adap->transmit_in_progress_aborted = true; 414 425 415 426 /* Cancel the pending timeout work. */ 416 427 list_for_each_entry_safe(data, n, &adap->wait_queue, list) { 417 428 if (cancel_delayed_work(&data->work)) 418 - cec_data_cancel(data, CEC_TX_STATUS_OK); 429 + cec_data_cancel(data, CEC_TX_STATUS_OK, CEC_RX_STATUS_ABORTED); 419 430 /* 420 431 * If cancel_delayed_work returned false, then 421 432 * the cec_wait_timeout function is running, ··· 471 482 kthread_should_stop() || 472 483 (!adap->transmit_in_progress && 473 484 !list_empty(&adap->transmit_queue)), 474 - msecs_to_jiffies(CEC_XFER_TIMEOUT_MS)); 485 + msecs_to_jiffies(adap->xfer_timeout_ms)); 475 486 timeout = err == 0; 476 487 } else { 477 488 /* Otherwise we just wait for something to happen. */ ··· 497 508 * adapter driver, or the CEC bus is in some weird 498 509 * state. On rare occasions it can happen if there is 499 510 * so much traffic on the bus that the adapter was 500 - * unable to transmit for CEC_XFER_TIMEOUT_MS (2.1s). 511 + * unable to transmit for xfer_timeout_ms (2.1s by 512 + * default). 501 513 */ 502 514 if (adap->transmitting) { 503 515 pr_warn("cec-%s: message %*ph timed out\n", adap->name, ··· 506 516 adap->transmitting->msg.msg); 507 517 /* Just give up on this. */ 508 518 cec_data_cancel(adap->transmitting, 509 - CEC_TX_STATUS_TIMEOUT); 519 + CEC_TX_STATUS_TIMEOUT, 0); 510 520 } else { 511 521 pr_warn("cec-%s: transmit timed out\n", adap->name); 512 522 } ··· 562 572 if (data->attempts == 0) 563 573 data->attempts = attempts; 564 574 575 + adap->transmit_in_progress_aborted = false; 565 576 /* Tell the adapter to transmit, cancel on error */ 566 - if (adap->ops->adap_transmit(adap, data->attempts, 567 - signal_free_time, &data->msg)) 568 - cec_data_cancel(data, CEC_TX_STATUS_ABORTED); 577 + if (call_op(adap, adap_transmit, data->attempts, 578 + signal_free_time, &data->msg)) 579 + cec_data_cancel(data, CEC_TX_STATUS_ABORTED, 0); 569 580 else 570 581 adap->transmit_in_progress = true; 571 582 ··· 590 599 struct cec_msg *msg; 591 600 unsigned int attempts_made = arb_lost_cnt + nack_cnt + 592 601 low_drive_cnt + error_cnt; 602 + bool done = status & (CEC_TX_STATUS_MAX_RETRIES | CEC_TX_STATUS_OK); 603 + bool aborted = adap->transmit_in_progress_aborted; 593 604 594 605 dprintk(2, "%s: status 0x%02x\n", __func__, status); 595 606 if (attempts_made < 1) ··· 612 619 goto wake_thread; 613 620 } 614 621 adap->transmit_in_progress = false; 622 + adap->transmit_in_progress_aborted = false; 615 623 616 624 msg = &data->msg; 617 625 ··· 633 639 * the hardware didn't signal that it retried itself (by setting 634 640 * CEC_TX_STATUS_MAX_RETRIES), then we will retry ourselves. 635 641 */ 636 - if (data->attempts > attempts_made && 637 - !(status & (CEC_TX_STATUS_MAX_RETRIES | CEC_TX_STATUS_OK))) { 642 + if (!aborted && data->attempts > attempts_made && !done) { 638 643 /* Retry this message */ 639 644 data->attempts -= attempts_made; 640 645 if (msg->timeout) ··· 648 655 goto wake_thread; 649 656 } 650 657 658 + if (aborted && !done) 659 + status |= CEC_TX_STATUS_ABORTED; 651 660 data->attempts = 0; 652 661 653 662 /* Always set CEC_TX_STATUS_MAX_RETRIES on error */ ··· 728 733 729 734 /* Mark the message as timed out */ 730 735 list_del_init(&data->list); 731 - data->msg.rx_ts = ktime_get_ns(); 732 - data->msg.rx_status = CEC_RX_STATUS_TIMEOUT; 733 - cec_data_completed(data); 736 + cec_data_cancel(data, CEC_TX_STATUS_OK, CEC_RX_STATUS_TIMEOUT); 734 737 unlock: 735 738 mutex_unlock(&adap->lock); 736 739 } ··· 914 921 mutex_lock(&adap->lock); 915 922 916 923 /* Cancel the transmit if it was interrupted */ 917 - if (!data->completed) 918 - cec_data_cancel(data, CEC_TX_STATUS_ABORTED); 924 + if (!data->completed) { 925 + if (data->msg.tx_status & CEC_TX_STATUS_OK) 926 + cec_data_cancel(data, CEC_TX_STATUS_OK, CEC_RX_STATUS_ABORTED); 927 + else 928 + cec_data_cancel(data, CEC_TX_STATUS_ABORTED, 0); 929 + } 919 930 920 931 /* The transmit completed (possibly with an error) */ 921 932 *msg = data->msg; ··· 1275 1278 * While trying to poll the physical address was reset 1276 1279 * and the adapter was unconfigured, so bail out. 1277 1280 */ 1278 - if (!adap->is_configuring) 1281 + if (adap->phys_addr == CEC_PHYS_ADDR_INVALID) 1282 + return -EINTR; 1283 + 1284 + /* Also bail out if the PA changed while configuring. */ 1285 + if (adap->must_reconfigure) 1279 1286 return -EINTR; 1280 1287 1281 1288 if (err) 1282 1289 return err; 1283 1290 1284 1291 /* 1285 - * The message was aborted due to a disconnect or 1292 + * The message was aborted or timed out due to a disconnect or 1286 1293 * unconfigure, just bail out. 1287 1294 */ 1288 - if (msg.tx_status & CEC_TX_STATUS_ABORTED) 1295 + if (msg.tx_status & 1296 + (CEC_TX_STATUS_ABORTED | CEC_TX_STATUS_TIMEOUT)) 1289 1297 return -EINTR; 1290 1298 if (msg.tx_status & CEC_TX_STATUS_OK) 1291 1299 return 0; ··· 1316 1314 * Message not acknowledged, so this logical 1317 1315 * address is free to use. 1318 1316 */ 1319 - err = adap->ops->adap_log_addr(adap, log_addr); 1317 + err = call_op(adap, adap_log_addr, log_addr); 1320 1318 if (err) 1321 1319 return err; 1322 1320 ··· 1333 1331 */ 1334 1332 static void cec_adap_unconfigure(struct cec_adapter *adap) 1335 1333 { 1336 - if (!adap->needs_hpd || 1337 - adap->phys_addr != CEC_PHYS_ADDR_INVALID) 1338 - WARN_ON(adap->ops->adap_log_addr(adap, CEC_LOG_ADDR_INVALID)); 1334 + if (!adap->needs_hpd || adap->phys_addr != CEC_PHYS_ADDR_INVALID) 1335 + WARN_ON(call_op(adap, adap_log_addr, CEC_LOG_ADDR_INVALID)); 1339 1336 adap->log_addrs.log_addr_mask = 0; 1340 - adap->is_configuring = false; 1341 1337 adap->is_configured = false; 1342 1338 cec_flush(adap); 1343 1339 wake_up_interruptible(&adap->kthread_waitq); 1344 1340 cec_post_state_event(adap); 1341 + call_void_op(adap, adap_configured, false); 1345 1342 } 1346 1343 1347 1344 /* ··· 1409 1408 if (las->log_addr_type[0] == CEC_LOG_ADDR_TYPE_UNREGISTERED) 1410 1409 goto configured; 1411 1410 1411 + reconfigure: 1412 1412 for (i = 0; i < las->num_log_addrs; i++) { 1413 1413 unsigned int type = las->log_addr_type[i]; 1414 1414 const u8 *la_list; ··· 1432 1430 last_la = la_list[0]; 1433 1431 1434 1432 err = cec_config_log_addr(adap, i, last_la); 1433 + 1434 + if (adap->must_reconfigure) { 1435 + adap->must_reconfigure = false; 1436 + las->log_addr_mask = 0; 1437 + goto reconfigure; 1438 + } 1439 + 1435 1440 if (err > 0) /* Reused last LA */ 1436 1441 continue; 1437 1442 ··· 1484 1475 las->log_addr[i] = CEC_LOG_ADDR_INVALID; 1485 1476 adap->is_configured = true; 1486 1477 adap->is_configuring = false; 1478 + adap->must_reconfigure = false; 1487 1479 cec_post_state_event(adap); 1488 1480 1489 1481 /* ··· 1531 1521 adap->kthread_config = NULL; 1532 1522 complete(&adap->config_completion); 1533 1523 mutex_unlock(&adap->lock); 1524 + call_void_op(adap, adap_configured, true); 1534 1525 return 0; 1535 1526 1536 1527 unconfigure: 1537 1528 for (i = 0; i < las->num_log_addrs; i++) 1538 1529 las->log_addr[i] = CEC_LOG_ADDR_INVALID; 1539 1530 cec_adap_unconfigure(adap); 1531 + adap->is_configuring = false; 1532 + adap->must_reconfigure = false; 1540 1533 adap->kthread_config = NULL; 1541 - mutex_unlock(&adap->lock); 1542 1534 complete(&adap->config_completion); 1535 + mutex_unlock(&adap->lock); 1543 1536 return 0; 1544 1537 } 1545 1538 ··· 1565 1552 "ceccfg-%s", adap->name); 1566 1553 if (IS_ERR(adap->kthread_config)) { 1567 1554 adap->kthread_config = NULL; 1555 + adap->is_configuring = false; 1568 1556 } else if (block) { 1569 1557 mutex_unlock(&adap->lock); 1570 1558 wait_for_completion(&adap->config_completion); 1571 1559 mutex_lock(&adap->lock); 1572 1560 } 1561 + } 1562 + 1563 + /* 1564 + * Helper function to enable/disable the CEC adapter. 1565 + * 1566 + * This function is called with adap->lock held. 1567 + */ 1568 + static int cec_adap_enable(struct cec_adapter *adap) 1569 + { 1570 + bool enable; 1571 + int ret = 0; 1572 + 1573 + enable = adap->monitor_all_cnt || adap->monitor_pin_cnt || 1574 + adap->log_addrs.num_log_addrs; 1575 + if (adap->needs_hpd) 1576 + enable = enable && adap->phys_addr != CEC_PHYS_ADDR_INVALID; 1577 + 1578 + if (enable == adap->is_enabled) 1579 + return 0; 1580 + 1581 + /* serialize adap_enable */ 1582 + mutex_lock(&adap->devnode.lock); 1583 + if (enable) { 1584 + adap->last_initiator = 0xff; 1585 + adap->transmit_in_progress = false; 1586 + ret = adap->ops->adap_enable(adap, true); 1587 + if (!ret) { 1588 + /* 1589 + * Enable monitor-all/pin modes if needed. We warn, but 1590 + * continue if this fails as this is not a critical error. 1591 + */ 1592 + if (adap->monitor_all_cnt) 1593 + WARN_ON(call_op(adap, adap_monitor_all_enable, true)); 1594 + if (adap->monitor_pin_cnt) 1595 + WARN_ON(call_op(adap, adap_monitor_pin_enable, true)); 1596 + } 1597 + } else { 1598 + /* Disable monitor-all/pin modes if needed (needs_hpd == 1) */ 1599 + if (adap->monitor_all_cnt) 1600 + WARN_ON(call_op(adap, adap_monitor_all_enable, false)); 1601 + if (adap->monitor_pin_cnt) 1602 + WARN_ON(call_op(adap, adap_monitor_pin_enable, false)); 1603 + WARN_ON(adap->ops->adap_enable(adap, false)); 1604 + adap->last_initiator = 0xff; 1605 + adap->transmit_in_progress = false; 1606 + adap->transmit_in_progress_aborted = false; 1607 + if (adap->transmitting) 1608 + cec_data_cancel(adap->transmitting, CEC_TX_STATUS_ABORTED, 0); 1609 + } 1610 + if (!ret) 1611 + adap->is_enabled = enable; 1612 + wake_up_interruptible(&adap->kthread_waitq); 1613 + mutex_unlock(&adap->devnode.lock); 1614 + return ret; 1573 1615 } 1574 1616 1575 1617 /* Set a new physical address and send an event notifying userspace of this. ··· 1633 1565 */ 1634 1566 void __cec_s_phys_addr(struct cec_adapter *adap, u16 phys_addr, bool block) 1635 1567 { 1568 + bool becomes_invalid = phys_addr == CEC_PHYS_ADDR_INVALID; 1569 + bool is_invalid = adap->phys_addr == CEC_PHYS_ADDR_INVALID; 1570 + 1636 1571 if (phys_addr == adap->phys_addr) 1637 1572 return; 1638 - if (phys_addr != CEC_PHYS_ADDR_INVALID && adap->devnode.unregistered) 1573 + if (!becomes_invalid && adap->devnode.unregistered) 1639 1574 return; 1640 1575 1641 1576 dprintk(1, "new physical address %x.%x.%x.%x\n", 1642 1577 cec_phys_addr_exp(phys_addr)); 1643 - if (phys_addr == CEC_PHYS_ADDR_INVALID || 1644 - adap->phys_addr != CEC_PHYS_ADDR_INVALID) { 1578 + if (becomes_invalid || !is_invalid) { 1645 1579 adap->phys_addr = CEC_PHYS_ADDR_INVALID; 1646 1580 cec_post_state_event(adap); 1647 1581 cec_adap_unconfigure(adap); 1648 - /* Disabling monitor all mode should always succeed */ 1649 - if (adap->monitor_all_cnt) 1650 - WARN_ON(call_op(adap, adap_monitor_all_enable, false)); 1651 - /* serialize adap_enable */ 1652 - mutex_lock(&adap->devnode.lock); 1653 - if (adap->needs_hpd || list_empty(&adap->devnode.fhs)) { 1654 - WARN_ON(adap->ops->adap_enable(adap, false)); 1655 - adap->transmit_in_progress = false; 1656 - wake_up_interruptible(&adap->kthread_waitq); 1657 - } 1658 - mutex_unlock(&adap->devnode.lock); 1659 - if (phys_addr == CEC_PHYS_ADDR_INVALID) 1660 - return; 1661 - } 1662 - 1663 - /* serialize adap_enable */ 1664 - mutex_lock(&adap->devnode.lock); 1665 - adap->last_initiator = 0xff; 1666 - adap->transmit_in_progress = false; 1667 - 1668 - if (adap->needs_hpd || list_empty(&adap->devnode.fhs)) { 1669 - if (adap->ops->adap_enable(adap, true)) { 1670 - mutex_unlock(&adap->devnode.lock); 1582 + if (becomes_invalid) { 1583 + cec_adap_enable(adap); 1671 1584 return; 1672 1585 } 1673 1586 } 1674 - 1675 - if (adap->monitor_all_cnt && 1676 - call_op(adap, adap_monitor_all_enable, true)) { 1677 - if (adap->needs_hpd || list_empty(&adap->devnode.fhs)) 1678 - WARN_ON(adap->ops->adap_enable(adap, false)); 1679 - mutex_unlock(&adap->devnode.lock); 1680 - return; 1681 - } 1682 - mutex_unlock(&adap->devnode.lock); 1683 1587 1684 1588 adap->phys_addr = phys_addr; 1589 + if (is_invalid) 1590 + cec_adap_enable(adap); 1591 + 1685 1592 cec_post_state_event(adap); 1686 - if (adap->log_addrs.num_log_addrs) 1593 + if (!adap->log_addrs.num_log_addrs) 1594 + return; 1595 + if (adap->is_configuring) 1596 + adap->must_reconfigure = true; 1597 + else 1687 1598 cec_claim_log_addrs(adap, block); 1688 1599 } 1689 1600 ··· 1717 1670 struct cec_log_addrs *log_addrs, bool block) 1718 1671 { 1719 1672 u16 type_mask = 0; 1673 + int err; 1720 1674 int i; 1721 1675 1722 1676 if (adap->devnode.unregistered) 1723 1677 return -ENODEV; 1724 1678 1725 1679 if (!log_addrs || log_addrs->num_log_addrs == 0) { 1726 - cec_adap_unconfigure(adap); 1680 + if (!adap->log_addrs.num_log_addrs) 1681 + return 0; 1682 + if (adap->is_configuring || adap->is_configured) 1683 + cec_adap_unconfigure(adap); 1727 1684 adap->log_addrs.num_log_addrs = 0; 1728 1685 for (i = 0; i < CEC_MAX_LOG_ADDRS; i++) 1729 1686 adap->log_addrs.log_addr[i] = CEC_LOG_ADDR_INVALID; 1730 1687 adap->log_addrs.osd_name[0] = '\0'; 1731 1688 adap->log_addrs.vendor_id = CEC_VENDOR_ID_NONE; 1732 1689 adap->log_addrs.cec_version = CEC_OP_CEC_VERSION_2_0; 1690 + cec_adap_enable(adap); 1733 1691 return 0; 1734 1692 } 1735 1693 ··· 1870 1818 1871 1819 log_addrs->log_addr_mask = adap->log_addrs.log_addr_mask; 1872 1820 adap->log_addrs = *log_addrs; 1873 - if (adap->phys_addr != CEC_PHYS_ADDR_INVALID) 1821 + err = cec_adap_enable(adap); 1822 + if (!err && adap->phys_addr != CEC_PHYS_ADDR_INVALID) 1874 1823 cec_claim_log_addrs(adap, block); 1875 - return 0; 1824 + return err; 1876 1825 } 1877 1826 1878 1827 int cec_s_log_addrs(struct cec_adapter *adap, ··· 1975 1922 msg->msg[1] != CEC_MSG_CDC_MESSAGE) 1976 1923 return 0; 1977 1924 1978 - if (adap->ops->received) { 1979 - /* Allow drivers to process the message first */ 1980 - if (adap->ops->received(adap, msg) != -ENOMSG) 1981 - return 0; 1982 - } 1925 + /* Allow drivers to process the message first */ 1926 + if (adap->ops->received && !adap->devnode.unregistered && 1927 + adap->ops->received(adap, msg) != -ENOMSG) 1928 + return 0; 1983 1929 1984 1930 /* 1985 1931 * REPORT_PHYSICAL_ADDR, CEC_MSG_USER_CONTROL_PRESSED and ··· 2171 2119 */ 2172 2120 int cec_monitor_all_cnt_inc(struct cec_adapter *adap) 2173 2121 { 2174 - int ret = 0; 2122 + int ret; 2175 2123 2176 - if (adap->monitor_all_cnt == 0) 2177 - ret = call_op(adap, adap_monitor_all_enable, 1); 2178 - if (ret == 0) 2179 - adap->monitor_all_cnt++; 2124 + if (adap->monitor_all_cnt++) 2125 + return 0; 2126 + 2127 + ret = cec_adap_enable(adap); 2128 + if (ret) 2129 + adap->monitor_all_cnt--; 2180 2130 return ret; 2181 2131 } 2182 2132 2183 2133 void cec_monitor_all_cnt_dec(struct cec_adapter *adap) 2184 2134 { 2185 - adap->monitor_all_cnt--; 2186 - if (adap->monitor_all_cnt == 0) 2187 - WARN_ON(call_op(adap, adap_monitor_all_enable, 0)); 2135 + if (WARN_ON(!adap->monitor_all_cnt)) 2136 + return; 2137 + if (--adap->monitor_all_cnt) 2138 + return; 2139 + WARN_ON(call_op(adap, adap_monitor_all_enable, false)); 2140 + cec_adap_enable(adap); 2188 2141 } 2189 2142 2190 2143 /* ··· 2199 2142 */ 2200 2143 int cec_monitor_pin_cnt_inc(struct cec_adapter *adap) 2201 2144 { 2202 - int ret = 0; 2145 + int ret; 2203 2146 2204 - if (adap->monitor_pin_cnt == 0) 2205 - ret = call_op(adap, adap_monitor_pin_enable, 1); 2206 - if (ret == 0) 2207 - adap->monitor_pin_cnt++; 2147 + if (adap->monitor_pin_cnt++) 2148 + return 0; 2149 + 2150 + ret = cec_adap_enable(adap); 2151 + if (ret) 2152 + adap->monitor_pin_cnt--; 2208 2153 return ret; 2209 2154 } 2210 2155 2211 2156 void cec_monitor_pin_cnt_dec(struct cec_adapter *adap) 2212 2157 { 2213 - adap->monitor_pin_cnt--; 2214 - if (adap->monitor_pin_cnt == 0) 2215 - WARN_ON(call_op(adap, adap_monitor_pin_enable, 0)); 2158 + if (WARN_ON(!adap->monitor_pin_cnt)) 2159 + return; 2160 + if (--adap->monitor_pin_cnt) 2161 + return; 2162 + WARN_ON(call_op(adap, adap_monitor_pin_enable, false)); 2163 + cec_adap_enable(adap); 2216 2164 } 2217 2165 2218 2166 #ifdef CONFIG_DEBUG_FS ··· 2231 2169 struct cec_data *data; 2232 2170 2233 2171 mutex_lock(&adap->lock); 2172 + seq_printf(file, "enabled: %d\n", adap->is_enabled); 2234 2173 seq_printf(file, "configured: %d\n", adap->is_configured); 2235 2174 seq_printf(file, "configuring: %d\n", adap->is_configuring); 2236 2175 seq_printf(file, "phys_addr: %x.%x.%x.%x\n", ··· 2246 2183 if (adap->monitor_all_cnt) 2247 2184 seq_printf(file, "file handles in Monitor All mode: %u\n", 2248 2185 adap->monitor_all_cnt); 2186 + if (adap->monitor_pin_cnt) 2187 + seq_printf(file, "file handles in Monitor Pin mode: %u\n", 2188 + adap->monitor_pin_cnt); 2249 2189 if (adap->tx_timeouts) { 2250 2190 seq_printf(file, "transmit timeouts: %u\n", 2251 2191 adap->tx_timeouts);

+5 -19

drivers/media/cec/core/cec-api.c

··· 586 586 return err; 587 587 } 588 588 589 - /* serialize adap_enable */ 590 - mutex_lock(&devnode->lock); 591 - if (list_empty(&devnode->fhs) && 592 - !adap->needs_hpd && 593 - adap->phys_addr == CEC_PHYS_ADDR_INVALID) { 594 - err = adap->ops->adap_enable(adap, true); 595 - if (err) { 596 - mutex_unlock(&devnode->lock); 597 - kfree(fh); 598 - return err; 599 - } 600 - } 601 589 filp->private_data = fh; 602 590 603 591 /* Queue up initial state events */ ··· 595 607 adap->conn_info.type != CEC_CONNECTOR_TYPE_NO_CONNECTOR; 596 608 cec_queue_event_fh(fh, &ev, 0); 597 609 #ifdef CONFIG_CEC_PIN 598 - if (adap->pin && adap->pin->ops->read_hpd) { 610 + if (adap->pin && adap->pin->ops->read_hpd && 611 + !adap->devnode.unregistered) { 599 612 err = adap->pin->ops->read_hpd(adap); 600 613 if (err >= 0) { 601 614 ev.event = err ? CEC_EVENT_PIN_HPD_HIGH : ··· 604 615 cec_queue_event_fh(fh, &ev, 0); 605 616 } 606 617 } 607 - if (adap->pin && adap->pin->ops->read_5v) { 618 + if (adap->pin && adap->pin->ops->read_5v && 619 + !adap->devnode.unregistered) { 608 620 err = adap->pin->ops->read_5v(adap); 609 621 if (err >= 0) { 610 622 ev.event = err ? CEC_EVENT_PIN_5V_HIGH : ··· 615 625 } 616 626 #endif 617 627 628 + mutex_lock(&devnode->lock); 618 629 mutex_lock(&devnode->lock_fhs); 619 630 list_add(&fh->list, &devnode->fhs); 620 631 mutex_unlock(&devnode->lock_fhs); ··· 647 656 cec_monitor_all_cnt_dec(adap); 648 657 mutex_unlock(&adap->lock); 649 658 650 - /* serialize adap_enable */ 651 659 mutex_lock(&devnode->lock); 652 660 mutex_lock(&devnode->lock_fhs); 653 661 list_del(&fh->list); 654 662 mutex_unlock(&devnode->lock_fhs); 655 - if (cec_is_registered(adap) && list_empty(&devnode->fhs) && 656 - !adap->needs_hpd && adap->phys_addr == CEC_PHYS_ADDR_INVALID) { 657 - WARN_ON(adap->ops->adap_enable(adap, false)); 658 - } 659 663 mutex_unlock(&devnode->lock); 660 664 661 665 /* Unhook pending transmits from this filehandle. */

+16 -2

drivers/media/cec/core/cec-core.c

··· 20 20 #define CEC_NUM_DEVICES 256 21 21 #define CEC_NAME "cec" 22 22 23 + /* 24 + * 400 ms is the time it takes for one 16 byte message to be 25 + * transferred and 5 is the maximum number of retries. Add 26 + * another 100 ms as a margin. So if the transmit doesn't 27 + * finish before that time something is really wrong and we 28 + * have to time out. 29 + * 30 + * This is a sign that something it really wrong and a warning 31 + * will be issued. 32 + */ 33 + #define CEC_XFER_TIMEOUT_MS (5 * 400 + 100) 34 + 23 35 int cec_debug; 24 36 module_param_named(debug, cec_debug, int, 0644); 25 37 MODULE_PARM_DESC(debug, "debug level (0-2)"); ··· 216 204 line = strsep(&p, "\n"); 217 205 if (!*line || *line == '#') 218 206 continue; 219 - if (!adap->ops->error_inj_parse_line(adap, line)) { 207 + if (!call_op(adap, error_inj_parse_line, line)) { 220 208 kfree(buf); 221 209 return -EINVAL; 222 210 } ··· 229 217 { 230 218 struct cec_adapter *adap = sf->private; 231 219 232 - return adap->ops->error_inj_show(adap, sf); 220 + return call_op(adap, error_inj_show, sf); 233 221 } 234 222 235 223 static int cec_error_inj_open(struct inode *inode, struct file *file) ··· 343 331 344 332 adap->owner = parent->driver->owner; 345 333 adap->devnode.dev.parent = parent; 334 + if (!adap->xfer_timeout_ms) 335 + adap->xfer_timeout_ms = CEC_XFER_TIMEOUT_MS; 346 336 347 337 #ifdef CONFIG_MEDIA_CEC_RC 348 338 if (adap->capabilities & CEC_CAP_RC) {

+11

drivers/media/cec/core/cec-pin-priv.h

··· 12 12 #include <linux/atomic.h> 13 13 #include <media/cec-pin.h> 14 14 15 + #define call_pin_op(pin, op, arg...) \ 16 + ((pin && pin->ops->op && !pin->adap->devnode.unregistered) ? \ 17 + pin->ops->op(pin->adap, ## arg) : 0) 18 + 19 + #define call_void_pin_op(pin, op, arg...) \ 20 + do { \ 21 + if (pin && pin->ops->op && \ 22 + !pin->adap->devnode.unregistered) \ 23 + pin->ops->op(pin->adap, ## arg); \ 24 + } while (0) 25 + 15 26 enum cec_pin_state { 16 27 /* CEC is off */ 17 28 CEC_ST_OFF,

+40 -32

drivers/media/cec/core/cec-pin.c

··· 135 135 136 136 static bool cec_pin_read(struct cec_pin *pin) 137 137 { 138 - bool v = pin->ops->read(pin->adap); 138 + bool v = call_pin_op(pin, read); 139 139 140 140 cec_pin_update(pin, v, false); 141 141 return v; ··· 143 143 144 144 static void cec_pin_low(struct cec_pin *pin) 145 145 { 146 - pin->ops->low(pin->adap); 146 + call_void_pin_op(pin, low); 147 147 cec_pin_update(pin, false, false); 148 148 } 149 149 150 150 static bool cec_pin_high(struct cec_pin *pin) 151 151 { 152 - pin->ops->high(pin->adap); 152 + call_void_pin_op(pin, high); 153 153 return cec_pin_read(pin); 154 154 } 155 155 ··· 1037 1037 1038 1038 for (;;) { 1039 1039 wait_event_interruptible(pin->kthread_waitq, 1040 - kthread_should_stop() || 1041 - pin->work_rx_msg.len || 1042 - pin->work_tx_status || 1043 - atomic_read(&pin->work_irq_change) || 1044 - atomic_read(&pin->work_pin_num_events)); 1040 + kthread_should_stop() || 1041 + pin->work_rx_msg.len || 1042 + pin->work_tx_status || 1043 + atomic_read(&pin->work_irq_change) || 1044 + atomic_read(&pin->work_pin_num_events)); 1045 + 1046 + if (kthread_should_stop()) 1047 + break; 1045 1048 1046 1049 if (pin->work_rx_msg.len) { 1047 1050 struct cec_msg *msg = &pin->work_rx_msg; ··· 1089 1086 CEC_PIN_IRQ_UNCHANGED)) { 1090 1087 case CEC_PIN_IRQ_DISABLE: 1091 1088 if (irq_enabled) { 1092 - pin->ops->disable_irq(adap); 1089 + call_void_pin_op(pin, disable_irq); 1093 1090 irq_enabled = false; 1094 1091 } 1095 1092 cec_pin_high(pin); 1093 + if (pin->state == CEC_ST_OFF) 1094 + break; 1096 1095 cec_pin_to_idle(pin); 1097 1096 hrtimer_start(&pin->timer, ns_to_ktime(0), 1098 1097 HRTIMER_MODE_REL); ··· 1102 1097 case CEC_PIN_IRQ_ENABLE: 1103 1098 if (irq_enabled) 1104 1099 break; 1105 - pin->enable_irq_failed = !pin->ops->enable_irq(adap); 1100 + pin->enable_irq_failed = !call_pin_op(pin, enable_irq); 1106 1101 if (pin->enable_irq_failed) { 1107 1102 cec_pin_to_idle(pin); 1108 1103 hrtimer_start(&pin->timer, ns_to_ktime(0), ··· 1114 1109 default: 1115 1110 break; 1116 1111 } 1117 - if (kthread_should_stop()) 1118 - break; 1119 1112 } 1120 - if (pin->ops->disable_irq && irq_enabled) 1121 - pin->ops->disable_irq(adap); 1122 - hrtimer_cancel(&pin->timer); 1123 - cec_pin_read(pin); 1124 - cec_pin_to_idle(pin); 1125 - pin->state = CEC_ST_OFF; 1126 1113 return 0; 1127 1114 } 1128 1115 ··· 1123 1126 struct cec_pin *pin = adap->pin; 1124 1127 1125 1128 if (enable) { 1126 - atomic_set(&pin->work_pin_num_events, 0); 1127 - pin->work_pin_events_rd = pin->work_pin_events_wr = 0; 1128 - pin->work_pin_events_dropped = false; 1129 1129 cec_pin_read(pin); 1130 1130 cec_pin_to_idle(pin); 1131 1131 pin->tx_msg.len = 0; 1132 1132 pin->timer_ts = ns_to_ktime(0); 1133 1133 atomic_set(&pin->work_irq_change, CEC_PIN_IRQ_UNCHANGED); 1134 - pin->kthread = kthread_run(cec_pin_thread_func, adap, 1135 - "cec-pin"); 1136 - if (IS_ERR(pin->kthread)) { 1137 - pr_err("cec-pin: kernel_thread() failed\n"); 1138 - return PTR_ERR(pin->kthread); 1134 + if (!pin->kthread) { 1135 + pin->kthread = kthread_run(cec_pin_thread_func, adap, 1136 + "cec-pin"); 1137 + if (IS_ERR(pin->kthread)) { 1138 + int err = PTR_ERR(pin->kthread); 1139 + 1140 + pr_err("cec-pin: kernel_thread() failed\n"); 1141 + pin->kthread = NULL; 1142 + return err; 1143 + } 1139 1144 } 1140 1145 hrtimer_start(&pin->timer, ns_to_ktime(0), 1141 1146 HRTIMER_MODE_REL); 1142 - } else { 1143 - kthread_stop(pin->kthread); 1147 + } else if (pin->kthread) { 1148 + hrtimer_cancel(&pin->timer); 1149 + cec_pin_high(pin); 1150 + cec_pin_to_idle(pin); 1151 + pin->state = CEC_ST_OFF; 1152 + pin->work_tx_status = 0; 1153 + atomic_set(&pin->work_irq_change, CEC_PIN_IRQ_DISABLE); 1154 + wake_up_interruptible(&pin->kthread_waitq); 1144 1155 } 1145 1156 return 0; 1146 1157 } ··· 1212 1207 seq_printf(file, "state: %s\n", states[pin->state].name); 1213 1208 seq_printf(file, "tx_bit: %d\n", pin->tx_bit); 1214 1209 seq_printf(file, "rx_bit: %d\n", pin->rx_bit); 1215 - seq_printf(file, "cec pin: %d\n", pin->ops->read(adap)); 1210 + seq_printf(file, "cec pin: %d\n", call_pin_op(pin, read)); 1216 1211 seq_printf(file, "cec pin events dropped: %u\n", 1217 1212 pin->work_pin_events_dropped_cnt); 1218 1213 seq_printf(file, "irq failed: %d\n", pin->enable_irq_failed); ··· 1265 1260 pin->rx_data_bit_too_long_cnt = 0; 1266 1261 pin->rx_low_drive_cnt = 0; 1267 1262 pin->tx_low_drive_cnt = 0; 1268 - if (pin->ops->status) 1269 - pin->ops->status(adap, file); 1263 + call_void_pin_op(pin, status, file); 1270 1264 } 1271 1265 1272 1266 static int cec_pin_adap_monitor_all_enable(struct cec_adapter *adap, ··· 1281 1277 { 1282 1278 struct cec_pin *pin = adap->pin; 1283 1279 1280 + if (pin->kthread) 1281 + kthread_stop(pin->kthread); 1282 + pin->kthread = NULL; 1284 1283 if (pin->ops->free) 1285 1284 pin->ops->free(adap); 1286 1285 adap->pin = NULL; ··· 1294 1287 { 1295 1288 struct cec_pin *pin = adap->pin; 1296 1289 1297 - if (pin->ops->received) 1290 + if (pin->ops->received && !adap->devnode.unregistered) 1298 1291 return pin->ops->received(adap, msg); 1299 1292 return -ENOMSG; 1300 1293 } ··· 1334 1327 return ERR_PTR(-ENOMEM); 1335 1328 pin->ops = pin_ops; 1336 1329 hrtimer_init(&pin->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1330 + atomic_set(&pin->work_pin_num_events, 0); 1337 1331 pin->timer.function = cec_pin_timer; 1338 1332 init_waitqueue_head(&pin->kthread_waitq); 1339 1333 pin->tx_custom_low_usecs = CEC_TIM_CUSTOM_DEFAULT;

+10

drivers/media/cec/core/cec-priv.h

··· 17 17 pr_info("cec-%s: " fmt, adap->name, ## arg); \ 18 18 } while (0) 19 19 20 + #define call_op(adap, op, arg...) \ 21 + ((adap->ops->op && !adap->devnode.unregistered) ? \ 22 + adap->ops->op(adap, ## arg) : 0) 23 + 24 + #define call_void_op(adap, op, arg...) \ 25 + do { \ 26 + if (adap->ops->op && !adap->devnode.unregistered) \ 27 + adap->ops->op(adap, ## arg); \ 28 + } while (0) 29 + 20 30 /* devnode to cec_adapter */ 21 31 #define to_cec_adapter(node) container_of(node, struct cec_adapter, devnode) 22 32

+5 -17

drivers/media/cec/platform/seco/seco-cec.c

··· 31 31 int irq; 32 32 }; 33 33 34 - #define smb_wr16(cmd, data) smb_word_op(CMD_WORD_DATA, SECOCEC_MICRO_ADDRESS, \ 35 - cmd, data, SMBUS_WRITE, NULL) 36 - #define smb_rd16(cmd, res) smb_word_op(CMD_WORD_DATA, SECOCEC_MICRO_ADDRESS, \ 34 + #define smb_wr16(cmd, data) smb_word_op(SECOCEC_MICRO_ADDRESS, \ 35 + cmd, data, SMBUS_WRITE, NULL) 36 + #define smb_rd16(cmd, res) smb_word_op(SECOCEC_MICRO_ADDRESS, \ 37 37 cmd, 0, SMBUS_READ, res) 38 38 39 - static int smb_word_op(short data_format, u16 slave_addr, u8 cmd, u16 data, 39 + static int smb_word_op(u16 slave_addr, u8 cmd, u16 data, 40 40 u8 operation, u16 *result) 41 41 { 42 42 unsigned int count; 43 - short _data_format; 44 43 int status = 0; 45 - 46 - switch (data_format) { 47 - case CMD_BYTE_DATA: 48 - _data_format = BRA_SMB_CMD_BYTE_DATA; 49 - break; 50 - case CMD_WORD_DATA: 51 - _data_format = BRA_SMB_CMD_WORD_DATA; 52 - break; 53 - default: 54 - return -EINVAL; 55 - } 56 44 57 45 /* Active wait until ready */ 58 46 for (count = 0; count <= SMBTIMEOUT; ++count) { ··· 63 75 outb((u8)(data >> 8), HDAT1); 64 76 } 65 77 66 - outb(BRA_START + _data_format, HCNT); 78 + outb(BRA_START + BRA_SMB_CMD_WORD_DATA, HCNT); 67 79 68 80 for (count = 0; count <= SMBTIMEOUT; count++) { 69 81 if (!(inb(HSTS) & BRA_HOST_BUSY))

-1

drivers/media/common/saa7146/saa7146_video.c

··· 443 443 444 444 strscpy((char *)cap->driver, "saa7146 v4l2", sizeof(cap->driver)); 445 445 strscpy((char *)cap->card, dev->ext->name, sizeof(cap->card)); 446 - sprintf((char *)cap->bus_info, "PCI:%s", pci_name(dev->pci)); 447 446 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OVERLAY | 448 447 V4L2_CAP_READWRITE | V4L2_CAP_STREAMING | 449 448 V4L2_CAP_DEVICE_CAPS;

+1 -2

drivers/media/common/videobuf2/videobuf2-dma-sg.c

··· 126 126 * there is no memory consistency guarantee, hence dma-sg ignores DMA 127 127 * attributes passed from the upper layer. 128 128 */ 129 - buf->pages = kvmalloc_array(buf->num_pages, sizeof(struct page *), 130 - GFP_KERNEL | __GFP_ZERO); 129 + buf->pages = kvcalloc(buf->num_pages, sizeof(struct page *), GFP_KERNEL); 131 130 if (!buf->pages) 132 131 goto fail_pages_array_alloc; 133 132

+10 -16

drivers/media/common/videobuf2/videobuf2-v4l2.c

··· 977 977 * and so they simplify the driver code. 978 978 */ 979 979 980 - /* The queue is busy if there is a owner and you are not that owner. */ 981 - static inline bool vb2_queue_is_busy(struct video_device *vdev, struct file *file) 982 - { 983 - return vdev->queue->owner && vdev->queue->owner != file->private_data; 984 - } 985 - 986 980 /* vb2 ioctl helpers */ 987 981 988 982 int vb2_ioctl_reqbufs(struct file *file, void *priv, ··· 991 997 p->flags = flags; 992 998 if (res) 993 999 return res; 994 - if (vb2_queue_is_busy(vdev, file)) 1000 + if (vb2_queue_is_busy(vdev->queue, file)) 995 1001 return -EBUSY; 996 1002 res = vb2_core_reqbufs(vdev->queue, p->memory, p->flags, &p->count); 997 1003 /* If count == 0, then the owner has released all buffers and he ··· 1020 1026 return res != -EBUSY ? res : 0; 1021 1027 if (res) 1022 1028 return res; 1023 - if (vb2_queue_is_busy(vdev, file)) 1029 + if (vb2_queue_is_busy(vdev->queue, file)) 1024 1030 return -EBUSY; 1025 1031 1026 1032 res = vb2_create_bufs(vdev->queue, p); ··· 1035 1041 { 1036 1042 struct video_device *vdev = video_devdata(file); 1037 1043 1038 - if (vb2_queue_is_busy(vdev, file)) 1044 + if (vb2_queue_is_busy(vdev->queue, file)) 1039 1045 return -EBUSY; 1040 1046 return vb2_prepare_buf(vdev->queue, vdev->v4l2_dev->mdev, p); 1041 1047 } ··· 1054 1060 { 1055 1061 struct video_device *vdev = video_devdata(file); 1056 1062 1057 - if (vb2_queue_is_busy(vdev, file)) 1063 + if (vb2_queue_is_busy(vdev->queue, file)) 1058 1064 return -EBUSY; 1059 1065 return vb2_qbuf(vdev->queue, vdev->v4l2_dev->mdev, p); 1060 1066 } ··· 1064 1070 { 1065 1071 struct video_device *vdev = video_devdata(file); 1066 1072 1067 - if (vb2_queue_is_busy(vdev, file)) 1073 + if (vb2_queue_is_busy(vdev->queue, file)) 1068 1074 return -EBUSY; 1069 1075 return vb2_dqbuf(vdev->queue, p, file->f_flags & O_NONBLOCK); 1070 1076 } ··· 1074 1080 { 1075 1081 struct video_device *vdev = video_devdata(file); 1076 1082 1077 - if (vb2_queue_is_busy(vdev, file)) 1083 + if (vb2_queue_is_busy(vdev->queue, file)) 1078 1084 return -EBUSY; 1079 1085 return vb2_streamon(vdev->queue, i); 1080 1086 } ··· 1084 1090 { 1085 1091 struct video_device *vdev = video_devdata(file); 1086 1092 1087 - if (vb2_queue_is_busy(vdev, file)) 1093 + if (vb2_queue_is_busy(vdev->queue, file)) 1088 1094 return -EBUSY; 1089 1095 return vb2_streamoff(vdev->queue, i); 1090 1096 } ··· 1094 1100 { 1095 1101 struct video_device *vdev = video_devdata(file); 1096 1102 1097 - if (vb2_queue_is_busy(vdev, file)) 1103 + if (vb2_queue_is_busy(vdev->queue, file)) 1098 1104 return -EBUSY; 1099 1105 return vb2_expbuf(vdev->queue, p); 1100 1106 } ··· 1146 1152 return -EINVAL; 1147 1153 if (lock && mutex_lock_interruptible(lock)) 1148 1154 return -ERESTARTSYS; 1149 - if (vb2_queue_is_busy(vdev, file)) 1155 + if (vb2_queue_is_busy(vdev->queue, file)) 1150 1156 goto exit; 1151 1157 err = vb2_write(vdev->queue, buf, count, ppos, 1152 1158 file->f_flags & O_NONBLOCK); ··· 1170 1176 return -EINVAL; 1171 1177 if (lock && mutex_lock_interruptible(lock)) 1172 1178 return -ERESTARTSYS; 1173 - if (vb2_queue_is_busy(vdev, file)) 1179 + if (vb2_queue_is_busy(vdev->queue, file)) 1174 1180 goto exit; 1175 1181 err = vb2_read(vdev->queue, buf, count, ppos, 1176 1182 file->f_flags & O_NONBLOCK);

+1

drivers/media/i2c/Kconfig

··· 372 372 config VIDEO_OV2640 373 373 tristate "OmniVision OV2640 sensor support" 374 374 depends on VIDEO_DEV && I2C 375 + select V4L2_ASYNC 375 376 help 376 377 This is a Video4Linux2 sensor driver for the OmniVision 377 378 OV2640 camera.

+46

drivers/media/i2c/adv7180.c

··· 66 66 #define ADV7180_HUE_DEF 0 67 67 #define ADV7180_HUE_MAX 128 68 68 69 + #define ADV7180_REG_DEF_VALUE_Y 0x000c 70 + #define ADV7180_DEF_VAL_EN 0x1 71 + #define ADV7180_DEF_VAL_AUTO_EN 0x2 69 72 #define ADV7180_REG_CTRL 0x000e 70 73 #define ADV7180_CTRL_IRQ_SPACE 0x20 71 74 ··· 552 549 return ret; 553 550 } 554 551 552 + static const char * const test_pattern_menu[] = { 553 + "Single color", 554 + "Color bars", 555 + "Luma ramp", 556 + "Boundary box", 557 + "Disable", 558 + }; 559 + 560 + static int adv7180_test_pattern(struct adv7180_state *state, int value) 561 + { 562 + unsigned int reg = 0; 563 + 564 + /* Map menu value into register value */ 565 + if (value < 3) 566 + reg = value; 567 + if (value == 3) 568 + reg = 5; 569 + 570 + adv7180_write(state, ADV7180_REG_ANALOG_CLAMP_CTL, reg); 571 + 572 + if (value == ARRAY_SIZE(test_pattern_menu) - 1) { 573 + reg = adv7180_read(state, ADV7180_REG_DEF_VALUE_Y); 574 + reg &= ~ADV7180_DEF_VAL_EN; 575 + adv7180_write(state, ADV7180_REG_DEF_VALUE_Y, reg); 576 + return 0; 577 + } 578 + 579 + reg = adv7180_read(state, ADV7180_REG_DEF_VALUE_Y); 580 + reg |= ADV7180_DEF_VAL_EN | ADV7180_DEF_VAL_AUTO_EN; 581 + adv7180_write(state, ADV7180_REG_DEF_VALUE_Y, reg); 582 + 583 + return 0; 584 + } 585 + 555 586 static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl) 556 587 { 557 588 struct v4l2_subdev *sd = to_adv7180_sd(ctrl); ··· 629 592 adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00); 630 593 } 631 594 break; 595 + case V4L2_CID_TEST_PATTERN: 596 + ret = adv7180_test_pattern(state, val); 597 + break; 632 598 default: 633 599 ret = -EINVAL; 634 600 } ··· 671 631 V4L2_CID_HUE, ADV7180_HUE_MIN, 672 632 ADV7180_HUE_MAX, 1, ADV7180_HUE_DEF); 673 633 v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL); 634 + 635 + v4l2_ctrl_new_std_menu_items(&state->ctrl_hdl, &adv7180_ctrl_ops, 636 + V4L2_CID_TEST_PATTERN, 637 + ARRAY_SIZE(test_pattern_menu) - 1, 638 + 0, ARRAY_SIZE(test_pattern_menu) - 1, 639 + test_pattern_menu); 674 640 675 641 state->sd.ctrl_handler = &state->ctrl_hdl; 676 642 if (state->ctrl_hdl.error) {

+22 -21

drivers/media/i2c/ccs/ccs-core.c

··· 121 121 122 122 linfo = &ccs_limits[ccs_limit_offsets[limit].info]; 123 123 124 - dev_dbg(&client->dev, "quirk: 0x%8.8x \"%s\" %u = %d, 0x%x\n", 124 + dev_dbg(&client->dev, "quirk: 0x%8.8x \"%s\" %u = %u, 0x%x\n", 125 125 linfo->reg, linfo->name, offset, val, val); 126 126 127 127 ccs_assign_limit(ptr, ccs_reg_width(linfo->reg), val); ··· 288 288 CCS_FRAME_FORMAT_DESCRIPTOR_4_PIXELS_MASK; 289 289 } else { 290 290 dev_dbg(&client->dev, 291 - "invalid frame format model type %d\n", 291 + "invalid frame format model type %u\n", 292 292 fmt_model_type); 293 293 return -EINVAL; 294 294 } ··· 320 320 } 321 321 322 322 dev_dbg(&client->dev, 323 - "%s pixels: %d %s (pixelcode %u)\n", 323 + "%s pixels: %u %s (pixelcode %u)\n", 324 324 what, pixels, which, pixelcode); 325 325 326 326 if (i < ncol_desc) { ··· 353 353 sensor->image_start = sensor->embedded_end; 354 354 } 355 355 356 - dev_dbg(&client->dev, "embedded data from lines %d to %d\n", 356 + dev_dbg(&client->dev, "embedded data from lines %u to %u\n", 357 357 sensor->embedded_start, sensor->embedded_end); 358 - dev_dbg(&client->dev, "image data starts at line %d\n", 358 + dev_dbg(&client->dev, "image data starts at line %u\n", 359 359 sensor->image_start); 360 360 361 361 return 0; ··· 571 571 572 572 flip ^= sensor->hvflip_inv_mask; 573 573 574 - dev_dbg(&client->dev, "flip %d\n", flip); 574 + dev_dbg(&client->dev, "flip %u\n", flip); 575 575 return sensor->default_pixel_order ^ flip; 576 576 } 577 577 ··· 1056 1056 1057 1057 type = CCS_LIM(sensor, DATA_FORMAT_MODEL_TYPE); 1058 1058 1059 - dev_dbg(&client->dev, "data_format_model_type %d\n", type); 1059 + dev_dbg(&client->dev, "data_format_model_type %u\n", type); 1060 1060 1061 1061 rval = ccs_read(sensor, PIXEL_ORDER, &pixel_order); 1062 1062 if (rval) 1063 1063 return rval; 1064 1064 1065 1065 if (pixel_order >= ARRAY_SIZE(pixel_order_str)) { 1066 - dev_dbg(&client->dev, "bad pixel order %d\n", pixel_order); 1066 + dev_dbg(&client->dev, "bad pixel order %u\n", pixel_order); 1067 1067 return -EINVAL; 1068 1068 } 1069 1069 1070 - dev_dbg(&client->dev, "pixel order %d (%s)\n", pixel_order, 1070 + dev_dbg(&client->dev, "pixel order %u (%s)\n", pixel_order, 1071 1071 pixel_order_str[pixel_order]); 1072 1072 1073 1073 switch (type) { ··· 1105 1105 (fmt & CCS_DATA_FORMAT_DESCRIPTOR_COMPRESSED_MASK)) 1106 1106 continue; 1107 1107 1108 - dev_dbg(&client->dev, "jolly good! %d\n", j); 1108 + dev_dbg(&client->dev, "jolly good! %u\n", j); 1109 1109 1110 1110 sensor->default_mbus_frame_fmts |= 1 << j; 1111 1111 } ··· 1602 1602 usleep_range(1000, 2000); 1603 1603 } while (--retry); 1604 1604 1605 - if (!reset) 1606 - return -EIO; 1605 + if (!reset) { 1606 + dev_err(dev, "software reset failed\n"); 1607 + rval = -EIO; 1608 + goto out_cci_addr_fail; 1609 + } 1607 1610 } 1608 1611 1609 1612 if (sensor->hwcfg.i2c_addr_alt) { ··· 2002 1999 2003 2000 mutex_lock(&sensor->mutex); 2004 2001 2005 - dev_err(&client->dev, "subdev %s, pad %d, index %d\n", 2002 + dev_err(&client->dev, "subdev %s, pad %u, index %u\n", 2006 2003 subdev->name, code->pad, code->index); 2007 2004 2008 2005 if (subdev != &sensor->src->sd || code->pad != CCS_PAD_SRC) { ··· 2020 2017 2021 2018 if (idx == code->index) { 2022 2019 code->code = ccs_csi_data_formats[i].code; 2023 - dev_err(&client->dev, "found index %d, i %d, code %x\n", 2020 + dev_err(&client->dev, "found index %u, i %u, code %x\n", 2024 2021 code->index, i, code->code); 2025 2022 rval = 0; 2026 2023 break; ··· 2389 2386 max_m = clamp(max_m, CCS_LIM(sensor, SCALER_M_MIN), 2390 2387 CCS_LIM(sensor, SCALER_M_MAX)); 2391 2388 2392 - dev_dbg(&client->dev, "scaling: a %d b %d max_m %d\n", a, b, max_m); 2389 + dev_dbg(&client->dev, "scaling: a %u b %u max_m %u\n", a, b, max_m); 2393 2390 2394 2391 min = min(max_m, min(a, b)); 2395 2392 max = min(max_m, max(a, b)); ··· 2419 2416 sel->r.height, 2420 2417 sel->flags); 2421 2418 2422 - dev_dbg(&client->dev, "trying factor %d (%d)\n", try[i], i); 2419 + dev_dbg(&client->dev, "trying factor %u (%u)\n", try[i], i); 2423 2420 2424 2421 if (this > best) { 2425 2422 scale_m = try[i]; ··· 3186 3183 struct fwnode_handle *ep; 3187 3184 struct fwnode_handle *fwnode = dev_fwnode(dev); 3188 3185 u32 rotation; 3189 - int i; 3186 + unsigned int i; 3190 3187 int rval; 3191 3188 3192 3189 ep = fwnode_graph_get_endpoint_by_id(fwnode, 0, 0, ··· 3224 3221 goto out_err; 3225 3222 } 3226 3223 3227 - dev_dbg(dev, "lanes %u\n", hwcfg->lanes); 3228 - 3229 3224 rval = fwnode_property_read_u32(fwnode, "rotation", &rotation); 3230 3225 if (!rval) { 3231 3226 switch (rotation) { ··· 3245 3244 if (rval) 3246 3245 dev_info(dev, "can't get clock-frequency\n"); 3247 3246 3248 - dev_dbg(dev, "clk %d, mode %d\n", hwcfg->ext_clk, 3247 + dev_dbg(dev, "clk %u, mode %u\n", hwcfg->ext_clk, 3249 3248 hwcfg->csi_signalling_mode); 3250 3249 3251 3250 if (!bus_cfg.nr_of_link_frequencies) { ··· 3264 3263 3265 3264 for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++) { 3266 3265 hwcfg->op_sys_clock[i] = bus_cfg.link_frequencies[i]; 3267 - dev_dbg(dev, "freq %d: %lld\n", i, hwcfg->op_sys_clock[i]); 3266 + dev_dbg(dev, "freq %u: %lld\n", i, hwcfg->op_sys_clock[i]); 3268 3267 } 3269 3268 3270 3269 v4l2_fwnode_endpoint_free(&bus_cfg);

+1 -1

drivers/media/i2c/dw9714.c

··· 183 183 return 0; 184 184 185 185 err_cleanup: 186 + regulator_disable(dw9714_dev->vcc); 186 187 v4l2_ctrl_handler_free(&dw9714_dev->ctrls_vcm); 187 188 media_entity_cleanup(&dw9714_dev->sd.entity); 188 189 ··· 202 201 if (ret) { 203 202 dev_err(&client->dev, 204 203 "Failed to disable vcc: %d\n", ret); 205 - return ret; 206 204 } 207 205 } 208 206 pm_runtime_set_suspended(&client->dev);

-6

drivers/media/i2c/dw9768.c

··· 469 469 470 470 dw9768->sd.entity.function = MEDIA_ENT_F_LENS; 471 471 472 - /* 473 - * Device is already turned on by i2c-core with ACPI domain PM. 474 - * Attempt to turn off the device to satisfy the privacy LED concerns. 475 - */ 476 - pm_runtime_set_active(dev); 477 472 pm_runtime_enable(dev); 478 473 if (!pm_runtime_enabled(dev)) { 479 474 ret = dw9768_runtime_resume(dev); ··· 483 488 dev_err(dev, "failed to register V4L2 subdev: %d", ret); 484 489 goto err_power_off; 485 490 } 486 - pm_runtime_idle(dev); 487 491 488 492 return 0; 489 493

+2

drivers/media/i2c/dw9807-vcm.c

··· 295 295 296 296 static const struct of_device_id dw9807_of_table[] = { 297 297 { .compatible = "dongwoon,dw9807-vcm" }, 298 + /* Compatibility for older firmware, NEVER USE THIS IN FIRMWARE! */ 299 + { .compatible = "dongwoon,dw9807" }, 298 300 { /* sentinel */ } 299 301 }; 300 302 MODULE_DEVICE_TABLE(of, dw9807_of_table);

+35 -4

drivers/media/i2c/imx412.c

··· 11 11 #include <linux/i2c.h> 12 12 #include <linux/module.h> 13 13 #include <linux/pm_runtime.h> 14 + #include <linux/regulator/consumer.h> 14 15 15 16 #include <media/v4l2-ctrls.h> 16 17 #include <media/v4l2-fwnode.h> ··· 102 101 struct imx412_reg_list reg_list; 103 102 }; 104 103 104 + static const char * const imx412_supply_names[] = { 105 + "dovdd", /* Digital I/O power */ 106 + "avdd", /* Analog power */ 107 + "dvdd", /* Digital core power */ 108 + }; 109 + 105 110 /** 106 111 * struct imx412 - imx412 sensor device structure 107 112 * @dev: Pointer to generic device ··· 116 109 * @pad: Media pad. Only one pad supported 117 110 * @reset_gpio: Sensor reset gpio 118 111 * @inclk: Sensor input clock 112 + * @supplies: Regulator supplies 119 113 * @ctrl_handler: V4L2 control handler 120 114 * @link_freq_ctrl: Pointer to link frequency control 121 115 * @pclk_ctrl: Pointer to pixel clock control ··· 136 128 struct media_pad pad; 137 129 struct gpio_desc *reset_gpio; 138 130 struct clk *inclk; 131 + struct regulator_bulk_data supplies[ARRAY_SIZE(imx412_supply_names)]; 139 132 struct v4l2_ctrl_handler ctrl_handler; 140 133 struct v4l2_ctrl *link_freq_ctrl; 141 134 struct v4l2_ctrl *pclk_ctrl; ··· 955 946 return -EINVAL; 956 947 } 957 948 949 + /* Get optional DT defined regulators */ 950 + for (i = 0; i < ARRAY_SIZE(imx412_supply_names); i++) 951 + imx412->supplies[i].supply = imx412_supply_names[i]; 952 + 953 + ret = devm_regulator_bulk_get(imx412->dev, 954 + ARRAY_SIZE(imx412_supply_names), 955 + imx412->supplies); 956 + if (ret) 957 + return ret; 958 + 958 959 ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 959 960 if (!ep) 960 961 return -ENXIO; ··· 1030 1011 struct imx412 *imx412 = to_imx412(sd); 1031 1012 int ret; 1032 1013 1033 - gpiod_set_value_cansleep(imx412->reset_gpio, 1); 1014 + ret = regulator_bulk_enable(ARRAY_SIZE(imx412_supply_names), 1015 + imx412->supplies); 1016 + if (ret < 0) { 1017 + dev_err(dev, "failed to enable regulators\n"); 1018 + return ret; 1019 + } 1020 + 1021 + gpiod_set_value_cansleep(imx412->reset_gpio, 0); 1034 1022 1035 1023 ret = clk_prepare_enable(imx412->inclk); 1036 1024 if (ret) { ··· 1050 1024 return 0; 1051 1025 1052 1026 error_reset: 1053 - gpiod_set_value_cansleep(imx412->reset_gpio, 0); 1027 + gpiod_set_value_cansleep(imx412->reset_gpio, 1); 1028 + regulator_bulk_disable(ARRAY_SIZE(imx412_supply_names), 1029 + imx412->supplies); 1054 1030 1055 1031 return ret; 1056 1032 } ··· 1068 1040 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1069 1041 struct imx412 *imx412 = to_imx412(sd); 1070 1042 1071 - gpiod_set_value_cansleep(imx412->reset_gpio, 0); 1072 - 1073 1043 clk_disable_unprepare(imx412->inclk); 1044 + 1045 + gpiod_set_value_cansleep(imx412->reset_gpio, 1); 1046 + 1047 + regulator_bulk_disable(ARRAY_SIZE(imx412_supply_names), 1048 + imx412->supplies); 1074 1049 1075 1050 return 0; 1076 1051 }

+7 -12

drivers/media/i2c/max9286.c

··· 1147 1147 return ret; 1148 1148 } 1149 1149 1150 - static int max9286_init(struct device *dev) 1150 + static int max9286_init(struct max9286_priv *priv) 1151 1151 { 1152 - struct max9286_priv *priv; 1153 - struct i2c_client *client; 1152 + struct i2c_client *client = priv->client; 1154 1153 int ret; 1155 - 1156 - client = to_i2c_client(dev); 1157 - priv = i2c_get_clientdata(client); 1158 1154 1159 1155 ret = max9286_poc_enable(priv, true); 1160 1156 if (ret) ··· 1158 1162 1159 1163 ret = max9286_setup(priv); 1160 1164 if (ret) { 1161 - dev_err(dev, "Unable to setup max9286\n"); 1165 + dev_err(&client->dev, "Unable to setup max9286\n"); 1162 1166 goto err_poc_disable; 1163 1167 } 1164 1168 ··· 1168 1172 */ 1169 1173 ret = max9286_v4l2_register(priv); 1170 1174 if (ret) { 1171 - dev_err(dev, "Failed to register with V4L2\n"); 1175 + dev_err(&client->dev, "Failed to register with V4L2\n"); 1172 1176 goto err_poc_disable; 1173 1177 } 1174 1178 1175 1179 ret = max9286_i2c_mux_init(priv); 1176 1180 if (ret) { 1177 - dev_err(dev, "Unable to initialize I2C multiplexer\n"); 1181 + dev_err(&client->dev, "Unable to initialize I2C multiplexer\n"); 1178 1182 goto err_v4l2_register; 1179 1183 } 1180 1184 ··· 1329 1333 mutex_init(&priv->mutex); 1330 1334 1331 1335 priv->client = client; 1332 - i2c_set_clientdata(client, priv); 1333 1336 1334 1337 priv->gpiod_pwdn = devm_gpiod_get_optional(&client->dev, "enable", 1335 1338 GPIOD_OUT_HIGH); ··· 1364 1369 if (ret) 1365 1370 goto err_powerdown; 1366 1371 1367 - ret = max9286_init(&client->dev); 1372 + ret = max9286_init(priv); 1368 1373 if (ret < 0) 1369 1374 goto err_cleanup_dt; 1370 1375 ··· 1380 1385 1381 1386 static int max9286_remove(struct i2c_client *client) 1382 1387 { 1383 - struct max9286_priv *priv = i2c_get_clientdata(client); 1388 + struct max9286_priv *priv = sd_to_max9286(i2c_get_clientdata(client)); 1384 1389 1385 1390 i2c_mux_del_adapters(priv->mux); 1386 1391

+4 -4

drivers/media/i2c/ov5645.c

··· 843 843 if (code->index > 0) 844 844 return -EINVAL; 845 845 846 - code->code = MEDIA_BUS_FMT_UYVY8_2X8; 846 + code->code = MEDIA_BUS_FMT_UYVY8_1X16; 847 847 848 848 return 0; 849 849 } ··· 852 852 struct v4l2_subdev_state *sd_state, 853 853 struct v4l2_subdev_frame_size_enum *fse) 854 854 { 855 - if (fse->code != MEDIA_BUS_FMT_UYVY8_2X8) 855 + if (fse->code != MEDIA_BUS_FMT_UYVY8_1X16) 856 856 return -EINVAL; 857 857 858 858 if (fse->index >= ARRAY_SIZE(ov5645_mode_info_data)) ··· 948 948 format->which); 949 949 __format->width = __crop->width; 950 950 __format->height = __crop->height; 951 - __format->code = MEDIA_BUS_FMT_UYVY8_2X8; 951 + __format->code = MEDIA_BUS_FMT_UYVY8_1X16; 952 952 __format->field = V4L2_FIELD_NONE; 953 953 __format->colorspace = V4L2_COLORSPACE_SRGB; 954 954 ··· 1283 1283 1284 1284 static struct i2c_driver ov5645_i2c_driver = { 1285 1285 .driver = { 1286 - .of_match_table = of_match_ptr(ov5645_of_match), 1286 + .of_match_table = ov5645_of_match, 1287 1287 .name = "ov5645", 1288 1288 }, 1289 1289 .probe_new = ov5645_probe,

+2 -2

drivers/media/i2c/ov5648.c

··· 2498 2498 2499 2499 /* DOVDD: digital I/O */ 2500 2500 sensor->dovdd = devm_regulator_get(dev, "dovdd"); 2501 - if (IS_ERR(sensor->dvdd)) { 2501 + if (IS_ERR(sensor->dovdd)) { 2502 2502 dev_err(dev, "cannot get DOVDD (digital I/O) regulator\n"); 2503 - ret = PTR_ERR(sensor->dvdd); 2503 + ret = PTR_ERR(sensor->dovdd); 2504 2504 goto error_endpoint; 2505 2505 } 2506 2506

+1 -1

drivers/media/i2c/ov5695.c

··· 1122 1122 1123 1123 switch (ctrl->id) { 1124 1124 case V4L2_CID_EXPOSURE: 1125 - /* 4 least significant bits of expsoure are fractional part */ 1125 + /* 4 least significant bits of exposure are fractional part */ 1126 1126 ret = ov5695_write_reg(ov5695->client, OV5695_REG_EXPOSURE, 1127 1127 OV5695_REG_VALUE_24BIT, ctrl->val << 4); 1128 1128 break;

+531 -219

drivers/media/i2c/ov7251.c

··· 14 14 #include <linux/i2c.h> 15 15 #include <linux/init.h> 16 16 #include <linux/module.h> 17 + #include <linux/mod_devicetable.h> 18 + #include <linux/pm_runtime.h> 17 19 #include <linux/regulator/consumer.h> 18 20 #include <linux/slab.h> 19 21 #include <linux/types.h> ··· 43 41 #define OV7251_TIMING_FORMAT2_MIRROR BIT(2) 44 42 #define OV7251_PRE_ISP_00 0x5e00 45 43 #define OV7251_PRE_ISP_00_TEST_PATTERN BIT(7) 44 + #define OV7251_PLL1_PRE_DIV_REG 0x30b4 45 + #define OV7251_PLL1_MULT_REG 0x30b3 46 + #define OV7251_PLL1_DIVIDER_REG 0x30b1 47 + #define OV7251_PLL1_PIX_DIV_REG 0x30b0 48 + #define OV7251_PLL1_MIPI_DIV_REG 0x30b5 49 + #define OV7251_PLL2_PRE_DIV_REG 0x3098 50 + #define OV7251_PLL2_MULT_REG 0x3099 51 + #define OV7251_PLL2_DIVIDER_REG 0x309d 52 + #define OV7251_PLL2_SYS_DIV_REG 0x309a 53 + #define OV7251_PLL2_ADC_DIV_REG 0x309b 54 + 55 + #define OV7251_NATIVE_WIDTH 656 56 + #define OV7251_NATIVE_HEIGHT 496 57 + #define OV7251_ACTIVE_START_LEFT 4 58 + #define OV7251_ACTIVE_START_TOP 4 59 + #define OV7251_ACTIVE_WIDTH 648 60 + #define OV7251_ACTIVE_HEIGHT 488 61 + 62 + #define OV7251_FIXED_PPL 928 63 + #define OV7251_TIMING_VTS_REG 0x380e 64 + #define OV7251_TIMING_MIN_VTS 1 65 + #define OV7251_TIMING_MAX_VTS 0xffff 66 + #define OV7251_INTEGRATION_MARGIN 20 46 67 47 68 struct reg_value { 48 69 u16 reg; ··· 75 50 struct ov7251_mode_info { 76 51 u32 width; 77 52 u32 height; 53 + u32 vts; 78 54 const struct reg_value *data; 79 55 u32 data_size; 80 56 u32 pixel_clock; ··· 83 57 u16 exposure_max; 84 58 u16 exposure_def; 85 59 struct v4l2_fract timeperframe; 60 + }; 61 + 62 + struct ov7251_pll1_cfg { 63 + unsigned int pre_div; 64 + unsigned int mult; 65 + unsigned int div; 66 + unsigned int pix_div; 67 + unsigned int mipi_div; 68 + }; 69 + 70 + struct ov7251_pll2_cfg { 71 + unsigned int pre_div; 72 + unsigned int mult; 73 + unsigned int div; 74 + unsigned int sys_div; 75 + unsigned int adc_div; 76 + }; 77 + 78 + /* 79 + * Rubbish ordering, but only PLL1 needs to have a separate configuration per 80 + * link frequency and the array member needs to be last. 81 + */ 82 + struct ov7251_pll_cfgs { 83 + const struct ov7251_pll2_cfg *pll2; 84 + const struct ov7251_pll1_cfg *pll1[]; 85 + }; 86 + 87 + enum xclk_rate { 88 + OV7251_19_2_MHZ, 89 + OV7251_24_MHZ, 90 + OV7251_NUM_SUPPORTED_RATES 91 + }; 92 + 93 + enum supported_link_freqs { 94 + OV7251_LINK_FREQ_240_MHZ, 95 + OV7251_LINK_FREQ_319_2_MHZ, 96 + OV7251_NUM_SUPPORTED_LINK_FREQS 86 97 }; 87 98 88 99 struct ov7251 { ··· 137 74 struct regulator *core_regulator; 138 75 struct regulator *analog_regulator; 139 76 77 + const struct ov7251_pll_cfgs *pll_cfgs; 78 + enum supported_link_freqs link_freq_idx; 140 79 const struct ov7251_mode_info *current_mode; 141 80 142 81 struct v4l2_ctrl_handler ctrls; ··· 146 81 struct v4l2_ctrl *link_freq; 147 82 struct v4l2_ctrl *exposure; 148 83 struct v4l2_ctrl *gain; 84 + struct v4l2_ctrl *hblank; 85 + struct v4l2_ctrl *vblank; 149 86 150 87 /* Cached register values */ 151 88 u8 aec_pk_manual; ··· 165 98 { 166 99 return container_of(sd, struct ov7251, sd); 167 100 } 101 + 102 + static const struct ov7251_pll1_cfg ov7251_pll1_cfg_19_2_mhz_240_mhz = { 103 + .pre_div = 0x03, 104 + .mult = 0x4b, 105 + .div = 0x01, 106 + .pix_div = 0x0a, 107 + .mipi_div = 0x05, 108 + }; 109 + 110 + static const struct ov7251_pll1_cfg ov7251_pll1_cfg_19_2_mhz_319_2_mhz = { 111 + .pre_div = 0x01, 112 + .mult = 0x85, 113 + .div = 0x04, 114 + .pix_div = 0x0a, 115 + .mipi_div = 0x05, 116 + }; 117 + 118 + static const struct ov7251_pll1_cfg ov7251_pll1_cfg_24_mhz_240_mhz = { 119 + .pre_div = 0x03, 120 + .mult = 0x64, 121 + .div = 0x01, 122 + .pix_div = 0x0a, 123 + .mipi_div = 0x05, 124 + }; 125 + 126 + static const struct ov7251_pll1_cfg ov7251_pll1_cfg_24_mhz_319_2_mhz = { 127 + .pre_div = 0x05, 128 + .mult = 0x85, 129 + .div = 0x02, 130 + .pix_div = 0x0a, 131 + .mipi_div = 0x05, 132 + }; 133 + 134 + static const struct ov7251_pll2_cfg ov7251_pll2_cfg_19_2_mhz = { 135 + .pre_div = 0x04, 136 + .mult = 0x32, 137 + .div = 0x00, 138 + .sys_div = 0x05, 139 + .adc_div = 0x04, 140 + }; 141 + 142 + static const struct ov7251_pll2_cfg ov7251_pll2_cfg_24_mhz = { 143 + .pre_div = 0x04, 144 + .mult = 0x28, 145 + .div = 0x00, 146 + .sys_div = 0x05, 147 + .adc_div = 0x04, 148 + }; 149 + 150 + static const struct ov7251_pll_cfgs ov7251_pll_cfgs_19_2_mhz = { 151 + .pll2 = &ov7251_pll2_cfg_19_2_mhz, 152 + .pll1 = { 153 + [OV7251_LINK_FREQ_240_MHZ] = &ov7251_pll1_cfg_19_2_mhz_240_mhz, 154 + [OV7251_LINK_FREQ_319_2_MHZ] = &ov7251_pll1_cfg_19_2_mhz_319_2_mhz, 155 + }, 156 + }; 157 + 158 + static const struct ov7251_pll_cfgs ov7251_pll_cfgs_24_mhz = { 159 + .pll2 = &ov7251_pll2_cfg_24_mhz, 160 + .pll1 = { 161 + [OV7251_LINK_FREQ_240_MHZ] = &ov7251_pll1_cfg_24_mhz_240_mhz, 162 + [OV7251_LINK_FREQ_319_2_MHZ] = &ov7251_pll1_cfg_24_mhz_319_2_mhz, 163 + }, 164 + }; 165 + 166 + static const struct ov7251_pll_cfgs *ov7251_pll_cfgs[] = { 167 + [OV7251_19_2_MHZ] = &ov7251_pll_cfgs_19_2_mhz, 168 + [OV7251_24_MHZ] = &ov7251_pll_cfgs_24_mhz, 169 + }; 168 170 169 171 static const struct reg_value ov7251_global_init_setting[] = { 170 172 { 0x0103, 0x01 }, ··· 253 117 { 0x301c, 0xf0 }, 254 118 { 0x3023, 0x05 }, 255 119 { 0x3037, 0xf0 }, 256 - { 0x3098, 0x04 }, /* pll2 pre divider */ 257 - { 0x3099, 0x28 }, /* pll2 multiplier */ 258 - { 0x309a, 0x05 }, /* pll2 sys divider */ 259 - { 0x309b, 0x04 }, /* pll2 adc divider */ 260 - { 0x309d, 0x00 }, /* pll2 divider */ 261 - { 0x30b0, 0x0a }, /* pll1 pix divider */ 262 - { 0x30b1, 0x01 }, /* pll1 divider */ 263 - { 0x30b3, 0x64 }, /* pll1 multiplier */ 264 - { 0x30b4, 0x03 }, /* pll1 pre divider */ 265 - { 0x30b5, 0x05 }, /* pll1 mipi divider */ 266 120 { 0x3106, 0xda }, 267 121 { 0x3503, 0x07 }, 268 122 { 0x3509, 0x10 }, ··· 381 255 { 0x301c, 0x00 }, 382 256 { 0x3023, 0x05 }, 383 257 { 0x3037, 0xf0 }, 384 - { 0x3098, 0x04 }, /* pll2 pre divider */ 385 - { 0x3099, 0x28 }, /* pll2 multiplier */ 386 - { 0x309a, 0x05 }, /* pll2 sys divider */ 387 - { 0x309b, 0x04 }, /* pll2 adc divider */ 388 - { 0x309d, 0x00 }, /* pll2 divider */ 389 - { 0x30b0, 0x0a }, /* pll1 pix divider */ 390 - { 0x30b1, 0x01 }, /* pll1 divider */ 391 - { 0x30b3, 0x64 }, /* pll1 multiplier */ 392 - { 0x30b4, 0x03 }, /* pll1 pre divider */ 393 - { 0x30b5, 0x05 }, /* pll1 mipi divider */ 394 258 { 0x3106, 0xda }, 395 259 { 0x3503, 0x07 }, 396 260 { 0x3509, 0x10 }, ··· 509 393 { 0x301c, 0x00 }, 510 394 { 0x3023, 0x05 }, 511 395 { 0x3037, 0xf0 }, 512 - { 0x3098, 0x04 }, /* pll2 pre divider */ 513 - { 0x3099, 0x28 }, /* pll2 multiplier */ 514 - { 0x309a, 0x05 }, /* pll2 sys divider */ 515 - { 0x309b, 0x04 }, /* pll2 adc divider */ 516 - { 0x309d, 0x00 }, /* pll2 divider */ 517 - { 0x30b0, 0x0a }, /* pll1 pix divider */ 518 - { 0x30b1, 0x01 }, /* pll1 divider */ 519 - { 0x30b3, 0x64 }, /* pll1 multiplier */ 520 - { 0x30b4, 0x03 }, /* pll1 pre divider */ 521 - { 0x30b5, 0x05 }, /* pll1 mipi divider */ 522 396 { 0x3106, 0xda }, 523 397 { 0x3503, 0x07 }, 524 398 { 0x3509, 0x10 }, ··· 624 518 { 0x5001, 0x80 }, 625 519 }; 626 520 521 + static const unsigned long supported_xclk_rates[] = { 522 + [OV7251_19_2_MHZ] = 19200000, 523 + [OV7251_24_MHZ] = 24000000, 524 + }; 525 + 627 526 static const s64 link_freq[] = { 628 - 240000000, 527 + [OV7251_LINK_FREQ_240_MHZ] = 240000000, 528 + [OV7251_LINK_FREQ_319_2_MHZ] = 319200000, 529 + }; 530 + 531 + static const s64 pixel_rates[] = { 532 + [OV7251_LINK_FREQ_240_MHZ] = 48000000, 533 + [OV7251_LINK_FREQ_319_2_MHZ] = 63840000, 629 534 }; 630 535 631 536 static const struct ov7251_mode_info ov7251_mode_info_data[] = { 632 537 { 633 538 .width = 640, 634 539 .height = 480, 540 + .vts = 1724, 635 541 .data = ov7251_setting_vga_30fps, 636 542 .data_size = ARRAY_SIZE(ov7251_setting_vga_30fps), 637 - .pixel_clock = 48000000, 638 - .link_freq = 0, /* an index in link_freq[] */ 639 543 .exposure_max = 1704, 640 544 .exposure_def = 504, 641 545 .timeperframe = { ··· 656 540 { 657 541 .width = 640, 658 542 .height = 480, 543 + .vts = 860, 659 544 .data = ov7251_setting_vga_60fps, 660 545 .data_size = ARRAY_SIZE(ov7251_setting_vga_60fps), 661 - .pixel_clock = 48000000, 662 - .link_freq = 0, /* an index in link_freq[] */ 663 546 .exposure_max = 840, 664 547 .exposure_def = 504, 665 548 .timeperframe = { ··· 669 554 { 670 555 .width = 640, 671 556 .height = 480, 557 + .vts = 572, 672 558 .data = ov7251_setting_vga_90fps, 673 559 .data_size = ARRAY_SIZE(ov7251_setting_vga_90fps), 674 - .pixel_clock = 48000000, 675 - .link_freq = 0, /* an index in link_freq[] */ 676 560 .exposure_max = 552, 677 561 .exposure_def = 504, 678 562 .timeperframe = { ··· 805 691 return 0; 806 692 } 807 693 694 + static int ov7251_pll_configure(struct ov7251 *ov7251) 695 + { 696 + const struct ov7251_pll_cfgs *configs; 697 + int ret; 698 + 699 + configs = ov7251->pll_cfgs; 700 + 701 + ret = ov7251_write_reg(ov7251, OV7251_PLL1_PRE_DIV_REG, 702 + configs->pll1[ov7251->link_freq_idx]->pre_div); 703 + if (ret < 0) 704 + return ret; 705 + 706 + ret = ov7251_write_reg(ov7251, OV7251_PLL1_MULT_REG, 707 + configs->pll1[ov7251->link_freq_idx]->mult); 708 + if (ret < 0) 709 + return ret; 710 + ret = ov7251_write_reg(ov7251, OV7251_PLL1_DIVIDER_REG, 711 + configs->pll1[ov7251->link_freq_idx]->div); 712 + if (ret < 0) 713 + return ret; 714 + 715 + ret = ov7251_write_reg(ov7251, OV7251_PLL1_PIX_DIV_REG, 716 + configs->pll1[ov7251->link_freq_idx]->pix_div); 717 + if (ret < 0) 718 + return ret; 719 + 720 + ret = ov7251_write_reg(ov7251, OV7251_PLL1_MIPI_DIV_REG, 721 + configs->pll1[ov7251->link_freq_idx]->mipi_div); 722 + if (ret < 0) 723 + return ret; 724 + 725 + ret = ov7251_write_reg(ov7251, OV7251_PLL2_PRE_DIV_REG, 726 + configs->pll2->pre_div); 727 + if (ret < 0) 728 + return ret; 729 + 730 + ret = ov7251_write_reg(ov7251, OV7251_PLL2_MULT_REG, 731 + configs->pll2->mult); 732 + if (ret < 0) 733 + return ret; 734 + 735 + ret = ov7251_write_reg(ov7251, OV7251_PLL2_DIVIDER_REG, 736 + configs->pll2->div); 737 + if (ret < 0) 738 + return ret; 739 + 740 + ret = ov7251_write_reg(ov7251, OV7251_PLL2_SYS_DIV_REG, 741 + configs->pll2->sys_div); 742 + if (ret < 0) 743 + return ret; 744 + 745 + ret = ov7251_write_reg(ov7251, OV7251_PLL2_ADC_DIV_REG, 746 + configs->pll2->adc_div); 747 + 748 + return ret; 749 + } 750 + 808 751 static int ov7251_set_exposure(struct ov7251 *ov7251, s32 exposure) 809 752 { 810 753 u16 reg; ··· 903 732 return 0; 904 733 } 905 734 906 - static int ov7251_set_power_on(struct ov7251 *ov7251) 735 + static int ov7251_set_power_on(struct device *dev) 907 736 { 737 + struct i2c_client *client = container_of(dev, struct i2c_client, dev); 738 + struct v4l2_subdev *sd = i2c_get_clientdata(client); 739 + struct ov7251 *ov7251 = to_ov7251(sd); 908 740 int ret; 909 741 u32 wait_us; 910 742 ··· 929 755 DIV_ROUND_UP(ov7251->xclk_freq, 1000)); 930 756 usleep_range(wait_us, wait_us + 1000); 931 757 932 - return 0; 758 + ret = ov7251_set_register_array(ov7251, 759 + ov7251_global_init_setting, 760 + ARRAY_SIZE(ov7251_global_init_setting)); 761 + if (ret < 0) { 762 + dev_err(ov7251->dev, "error during global init\n"); 763 + ov7251_regulators_disable(ov7251); 764 + return ret; 765 + } 766 + 767 + return ret; 933 768 } 934 769 935 - static void ov7251_set_power_off(struct ov7251 *ov7251) 770 + static int ov7251_set_power_off(struct device *dev) 936 771 { 772 + struct i2c_client *client = container_of(dev, struct i2c_client, dev); 773 + struct v4l2_subdev *sd = i2c_get_clientdata(client); 774 + struct ov7251 *ov7251 = to_ov7251(sd); 775 + 937 776 clk_disable_unprepare(ov7251->xclk); 938 777 gpiod_set_value_cansleep(ov7251->enable_gpio, 0); 939 778 ov7251_regulators_disable(ov7251); 940 - } 941 779 942 - static int ov7251_s_power(struct v4l2_subdev *sd, int on) 943 - { 944 - struct ov7251 *ov7251 = to_ov7251(sd); 945 - int ret = 0; 946 - 947 - mutex_lock(&ov7251->lock); 948 - 949 - /* If the power state is not modified - no work to do. */ 950 - if (ov7251->power_on == !!on) 951 - goto exit; 952 - 953 - if (on) { 954 - ret = ov7251_set_power_on(ov7251); 955 - if (ret < 0) 956 - goto exit; 957 - 958 - ret = ov7251_set_register_array(ov7251, 959 - ov7251_global_init_setting, 960 - ARRAY_SIZE(ov7251_global_init_setting)); 961 - if (ret < 0) { 962 - dev_err(ov7251->dev, "could not set init registers\n"); 963 - ov7251_set_power_off(ov7251); 964 - goto exit; 965 - } 966 - 967 - ov7251->power_on = true; 968 - } else { 969 - ov7251_set_power_off(ov7251); 970 - ov7251->power_on = false; 971 - } 972 - 973 - exit: 974 - mutex_unlock(&ov7251->lock); 975 - 976 - return ret; 780 + return 0; 977 781 } 978 782 979 783 static int ov7251_set_hflip(struct ov7251 *ov7251, s32 value) ··· 1010 858 "Vertical Pattern Bars", 1011 859 }; 1012 860 861 + static int ov7251_vts_configure(struct ov7251 *ov7251, s32 vblank) 862 + { 863 + u8 vts[2]; 864 + 865 + vts[0] = ((ov7251->current_mode->height + vblank) & 0xff00) >> 8; 866 + vts[1] = ((ov7251->current_mode->height + vblank) & 0x00ff); 867 + 868 + return ov7251_write_seq_regs(ov7251, OV7251_TIMING_VTS_REG, vts, 2); 869 + } 870 + 1013 871 static int ov7251_s_ctrl(struct v4l2_ctrl *ctrl) 1014 872 { 1015 873 struct ov7251 *ov7251 = container_of(ctrl->handler, 1016 874 struct ov7251, ctrls); 1017 875 int ret; 1018 876 877 + /* If VBLANK is altered we need to update exposure to compensate */ 878 + if (ctrl->id == V4L2_CID_VBLANK) { 879 + int exposure_max; 880 + 881 + exposure_max = ov7251->current_mode->height + ctrl->val - 882 + OV7251_INTEGRATION_MARGIN; 883 + __v4l2_ctrl_modify_range(ov7251->exposure, 884 + ov7251->exposure->minimum, 885 + exposure_max, 886 + ov7251->exposure->step, 887 + min(ov7251->exposure->val, 888 + exposure_max)); 889 + } 890 + 1019 891 /* v4l2_ctrl_lock() locks our mutex */ 1020 892 1021 - if (!ov7251->power_on) 893 + if (!pm_runtime_get_if_in_use(ov7251->dev)) 1022 894 return 0; 1023 895 1024 896 switch (ctrl->id) { ··· 1061 885 case V4L2_CID_VFLIP: 1062 886 ret = ov7251_set_vflip(ov7251, ctrl->val); 1063 887 break; 888 + case V4L2_CID_VBLANK: 889 + ret = ov7251_vts_configure(ov7251, ctrl->val); 890 + break; 1064 891 default: 1065 892 ret = -EINVAL; 1066 893 break; 1067 894 } 895 + 896 + pm_runtime_put(ov7251->dev); 1068 897 1069 898 return ret; 1070 899 } ··· 1215 1034 { 1216 1035 struct ov7251 *ov7251 = to_ov7251(sd); 1217 1036 struct v4l2_mbus_framefmt *__format; 1037 + int vblank_max, vblank_def; 1218 1038 struct v4l2_rect *__crop; 1219 1039 const struct ov7251_mode_info *new_mode; 1220 1040 int ret = 0; ··· 1234 1052 __crop->height = new_mode->height; 1235 1053 1236 1054 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 1237 - ret = __v4l2_ctrl_s_ctrl_int64(ov7251->pixel_clock, 1238 - new_mode->pixel_clock); 1239 - if (ret < 0) 1240 - goto exit; 1241 - 1242 - ret = __v4l2_ctrl_s_ctrl(ov7251->link_freq, 1243 - new_mode->link_freq); 1244 - if (ret < 0) 1245 - goto exit; 1246 - 1247 1055 ret = __v4l2_ctrl_modify_range(ov7251->exposure, 1248 1056 1, new_mode->exposure_max, 1249 1057 1, new_mode->exposure_def); ··· 1246 1074 goto exit; 1247 1075 1248 1076 ret = __v4l2_ctrl_s_ctrl(ov7251->gain, 16); 1077 + if (ret < 0) 1078 + goto exit; 1079 + 1080 + vblank_max = OV7251_TIMING_MAX_VTS - new_mode->height; 1081 + vblank_def = new_mode->vts - new_mode->height; 1082 + ret = __v4l2_ctrl_modify_range(ov7251->vblank, 1083 + OV7251_TIMING_MIN_VTS, 1084 + vblank_max, 1, vblank_def); 1249 1085 if (ret < 0) 1250 1086 goto exit; 1251 1087 ··· 1303 1123 { 1304 1124 struct ov7251 *ov7251 = to_ov7251(sd); 1305 1125 1306 - if (sel->target != V4L2_SEL_TGT_CROP) 1307 - return -EINVAL; 1308 - 1126 + switch (sel->target) { 1127 + case V4L2_SEL_TGT_CROP_DEFAULT: 1128 + case V4L2_SEL_TGT_CROP: 1309 1129 mutex_lock(&ov7251->lock); 1310 - sel->r = *__ov7251_get_pad_crop(ov7251, sd_state, sel->pad, 1311 - sel->which); 1312 - mutex_unlock(&ov7251->lock); 1130 + sel->r = *__ov7251_get_pad_crop(ov7251, sd_state, sel->pad, 1131 + sel->which); 1132 + mutex_unlock(&ov7251->lock); 1133 + break; 1134 + case V4L2_SEL_TGT_NATIVE_SIZE: 1135 + sel->r.top = 0; 1136 + sel->r.left = 0; 1137 + sel->r.width = OV7251_NATIVE_WIDTH; 1138 + sel->r.height = OV7251_NATIVE_HEIGHT; 1139 + break; 1140 + case V4L2_SEL_TGT_CROP_BOUNDS: 1141 + sel->r.top = OV7251_ACTIVE_START_TOP; 1142 + sel->r.left = OV7251_ACTIVE_START_LEFT; 1143 + sel->r.width = OV7251_ACTIVE_WIDTH; 1144 + sel->r.height = OV7251_ACTIVE_HEIGHT; 1145 + break; 1146 + default: 1147 + return -EINVAL; 1148 + } 1313 1149 1314 1150 return 0; 1315 1151 } ··· 1338 1142 mutex_lock(&ov7251->lock); 1339 1143 1340 1144 if (enable) { 1145 + ret = pm_runtime_get_sync(ov7251->dev); 1146 + if (ret < 0) 1147 + goto unlock_out; 1148 + 1149 + ret = ov7251_pll_configure(ov7251); 1150 + if (ret) { 1151 + dev_err(ov7251->dev, "error configuring PLLs\n"); 1152 + goto err_power_down; 1153 + } 1154 + 1341 1155 ret = ov7251_set_register_array(ov7251, 1342 1156 ov7251->current_mode->data, 1343 1157 ov7251->current_mode->data_size); ··· 1355 1149 dev_err(ov7251->dev, "could not set mode %dx%d\n", 1356 1150 ov7251->current_mode->width, 1357 1151 ov7251->current_mode->height); 1358 - goto exit; 1152 + goto err_power_down; 1359 1153 } 1360 1154 ret = __v4l2_ctrl_handler_setup(&ov7251->ctrls); 1361 1155 if (ret < 0) { 1362 1156 dev_err(ov7251->dev, "could not sync v4l2 controls\n"); 1363 - goto exit; 1157 + goto err_power_down; 1364 1158 } 1365 1159 ret = ov7251_write_reg(ov7251, OV7251_SC_MODE_SELECT, 1366 1160 OV7251_SC_MODE_SELECT_STREAMING); 1161 + if (ret) 1162 + goto err_power_down; 1367 1163 } else { 1368 1164 ret = ov7251_write_reg(ov7251, OV7251_SC_MODE_SELECT, 1369 1165 OV7251_SC_MODE_SELECT_SW_STANDBY); 1166 + pm_runtime_put(ov7251->dev); 1370 1167 } 1371 1168 1372 - exit: 1169 + unlock_out: 1373 1170 mutex_unlock(&ov7251->lock); 1171 + return ret; 1374 1172 1173 + err_power_down: 1174 + pm_runtime_put_noidle(ov7251->dev); 1175 + mutex_unlock(&ov7251->lock); 1375 1176 return ret; 1376 1177 } 1377 1178 ··· 1405 1192 new_mode = ov7251_find_mode_by_ival(ov7251, &fi->interval); 1406 1193 1407 1194 if (new_mode != ov7251->current_mode) { 1408 - ret = __v4l2_ctrl_s_ctrl_int64(ov7251->pixel_clock, 1409 - new_mode->pixel_clock); 1410 - if (ret < 0) 1411 - goto exit; 1412 - 1413 - ret = __v4l2_ctrl_s_ctrl(ov7251->link_freq, 1414 - new_mode->link_freq); 1415 - if (ret < 0) 1416 - goto exit; 1417 - 1418 1195 ret = __v4l2_ctrl_modify_range(ov7251->exposure, 1419 1196 1, new_mode->exposure_max, 1420 1197 1, new_mode->exposure_def); ··· 1431 1228 return ret; 1432 1229 } 1433 1230 1434 - static const struct v4l2_subdev_core_ops ov7251_core_ops = { 1435 - .s_power = ov7251_s_power, 1436 - }; 1437 - 1438 1231 static const struct v4l2_subdev_video_ops ov7251_video_ops = { 1439 1232 .s_stream = ov7251_s_stream, 1440 1233 .g_frame_interval = ov7251_get_frame_interval, ··· 1448 1249 }; 1449 1250 1450 1251 static const struct v4l2_subdev_ops ov7251_subdev_ops = { 1451 - .core = &ov7251_core_ops, 1452 1252 .video = &ov7251_video_ops, 1453 1253 .pad = &ov7251_subdev_pad_ops, 1454 1254 }; 1455 1255 1256 + static int ov7251_check_hwcfg(struct ov7251 *ov7251) 1257 + { 1258 + struct fwnode_handle *fwnode = dev_fwnode(ov7251->dev); 1259 + struct v4l2_fwnode_endpoint bus_cfg = { 1260 + .bus_type = V4L2_MBUS_CSI2_DPHY, 1261 + }; 1262 + struct fwnode_handle *endpoint; 1263 + unsigned int i, j; 1264 + int ret; 1265 + 1266 + endpoint = fwnode_graph_get_next_endpoint(fwnode, NULL); 1267 + if (!endpoint) 1268 + return -EPROBE_DEFER; /* could be provided by cio2-bridge */ 1269 + 1270 + ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &bus_cfg); 1271 + fwnode_handle_put(endpoint); 1272 + if (ret) 1273 + return dev_err_probe(ov7251->dev, ret, 1274 + "parsing endpoint node failed\n"); 1275 + 1276 + if (!bus_cfg.nr_of_link_frequencies) { 1277 + ret = dev_err_probe(ov7251->dev, -EINVAL, 1278 + "no link frequencies defined\n"); 1279 + goto out_free_bus_cfg; 1280 + } 1281 + 1282 + for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++) { 1283 + for (j = 0; j < ARRAY_SIZE(link_freq); j++) 1284 + if (bus_cfg.link_frequencies[i] == link_freq[j]) 1285 + break; 1286 + 1287 + if (j < ARRAY_SIZE(link_freq)) 1288 + break; 1289 + } 1290 + 1291 + if (i == bus_cfg.nr_of_link_frequencies) { 1292 + ret = dev_err_probe(ov7251->dev, -EINVAL, 1293 + "no supported link freq found\n"); 1294 + goto out_free_bus_cfg; 1295 + } 1296 + 1297 + ov7251->link_freq_idx = i; 1298 + 1299 + out_free_bus_cfg: 1300 + v4l2_fwnode_endpoint_free(&bus_cfg); 1301 + 1302 + return ret; 1303 + } 1304 + 1305 + static int ov7251_detect_chip(struct ov7251 *ov7251) 1306 + { 1307 + u8 chip_id_high, chip_id_low, chip_rev; 1308 + int ret; 1309 + 1310 + ret = ov7251_read_reg(ov7251, OV7251_CHIP_ID_HIGH, &chip_id_high); 1311 + if (ret < 0 || chip_id_high != OV7251_CHIP_ID_HIGH_BYTE) 1312 + return dev_err_probe(ov7251->dev, -ENODEV, 1313 + "could not read ID high\n"); 1314 + 1315 + ret = ov7251_read_reg(ov7251, OV7251_CHIP_ID_LOW, &chip_id_low); 1316 + if (ret < 0 || chip_id_low != OV7251_CHIP_ID_LOW_BYTE) 1317 + return dev_err_probe(ov7251->dev, -ENODEV, 1318 + "could not read ID low\n"); 1319 + 1320 + ret = ov7251_read_reg(ov7251, OV7251_SC_GP_IO_IN1, &chip_rev); 1321 + if (ret < 0) 1322 + return dev_err_probe(ov7251->dev, -ENODEV, 1323 + "could not read revision\n"); 1324 + chip_rev >>= 4; 1325 + 1326 + dev_info(ov7251->dev, 1327 + "OV7251 revision %x (%s) detected at address 0x%02x\n", 1328 + chip_rev, 1329 + chip_rev == 0x4 ? "1A / 1B" : 1330 + chip_rev == 0x5 ? "1C / 1D" : 1331 + chip_rev == 0x6 ? "1E" : 1332 + chip_rev == 0x7 ? "1F" : "unknown", 1333 + ov7251->i2c_client->addr); 1334 + 1335 + return 0; 1336 + } 1337 + 1338 + static int ov7251_init_ctrls(struct ov7251 *ov7251) 1339 + { 1340 + int vblank_max, vblank_def; 1341 + s64 pixel_rate; 1342 + int hblank; 1343 + 1344 + v4l2_ctrl_handler_init(&ov7251->ctrls, 7); 1345 + ov7251->ctrls.lock = &ov7251->lock; 1346 + 1347 + v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops, 1348 + V4L2_CID_HFLIP, 0, 1, 1, 0); 1349 + v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops, 1350 + V4L2_CID_VFLIP, 0, 1, 1, 0); 1351 + ov7251->exposure = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops, 1352 + V4L2_CID_EXPOSURE, 1, 32, 1, 32); 1353 + ov7251->gain = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops, 1354 + V4L2_CID_GAIN, 16, 1023, 1, 16); 1355 + v4l2_ctrl_new_std_menu_items(&ov7251->ctrls, &ov7251_ctrl_ops, 1356 + V4L2_CID_TEST_PATTERN, 1357 + ARRAY_SIZE(ov7251_test_pattern_menu) - 1, 1358 + 0, 0, ov7251_test_pattern_menu); 1359 + 1360 + pixel_rate = pixel_rates[ov7251->link_freq_idx]; 1361 + ov7251->pixel_clock = v4l2_ctrl_new_std(&ov7251->ctrls, 1362 + &ov7251_ctrl_ops, 1363 + V4L2_CID_PIXEL_RATE, 1364 + pixel_rate, INT_MAX, 1365 + pixel_rate, pixel_rate); 1366 + ov7251->link_freq = v4l2_ctrl_new_int_menu(&ov7251->ctrls, 1367 + &ov7251_ctrl_ops, 1368 + V4L2_CID_LINK_FREQ, 1369 + ARRAY_SIZE(link_freq) - 1, 1370 + ov7251->link_freq_idx, 1371 + link_freq); 1372 + if (ov7251->link_freq) 1373 + ov7251->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1374 + if (ov7251->pixel_clock) 1375 + ov7251->pixel_clock->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1376 + 1377 + hblank = OV7251_FIXED_PPL - ov7251->current_mode->width; 1378 + ov7251->hblank = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops, 1379 + V4L2_CID_HBLANK, hblank, hblank, 1, 1380 + hblank); 1381 + if (ov7251->hblank) 1382 + ov7251->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1383 + 1384 + vblank_max = OV7251_TIMING_MAX_VTS - ov7251->current_mode->height; 1385 + vblank_def = ov7251->current_mode->vts - ov7251->current_mode->height; 1386 + ov7251->vblank = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops, 1387 + V4L2_CID_VBLANK, 1388 + OV7251_TIMING_MIN_VTS, vblank_max, 1, 1389 + vblank_def); 1390 + 1391 + ov7251->sd.ctrl_handler = &ov7251->ctrls; 1392 + 1393 + if (ov7251->ctrls.error) { 1394 + v4l2_ctrl_handler_free(&ov7251->ctrls); 1395 + return ov7251->ctrls.error; 1396 + } 1397 + 1398 + return 0; 1399 + } 1400 + 1456 1401 static int ov7251_probe(struct i2c_client *client) 1457 1402 { 1458 1403 struct device *dev = &client->dev; 1459 - struct fwnode_handle *endpoint; 1460 1404 struct ov7251 *ov7251; 1461 - u8 chip_id_high, chip_id_low, chip_rev; 1405 + unsigned int rate = 0, clk_rate = 0; 1462 1406 int ret; 1407 + int i; 1463 1408 1464 1409 ov7251 = devm_kzalloc(dev, sizeof(struct ov7251), GFP_KERNEL); 1465 1410 if (!ov7251) ··· 1612 1269 ov7251->i2c_client = client; 1613 1270 ov7251->dev = dev; 1614 1271 1615 - endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL); 1616 - if (!endpoint) { 1617 - dev_err(dev, "endpoint node not found\n"); 1618 - return -EINVAL; 1619 - } 1620 - 1621 - ret = v4l2_fwnode_endpoint_parse(endpoint, &ov7251->ep); 1622 - fwnode_handle_put(endpoint); 1623 - if (ret < 0) { 1624 - dev_err(dev, "parsing endpoint node failed\n"); 1272 + ret = ov7251_check_hwcfg(ov7251); 1273 + if (ret) 1625 1274 return ret; 1626 - } 1627 - 1628 - if (ov7251->ep.bus_type != V4L2_MBUS_CSI2_DPHY) { 1629 - dev_err(dev, "invalid bus type (%u), must be CSI2 (%u)\n", 1630 - ov7251->ep.bus_type, V4L2_MBUS_CSI2_DPHY); 1631 - return -EINVAL; 1632 - } 1633 1275 1634 1276 /* get system clock (xclk) */ 1635 - ov7251->xclk = devm_clk_get(dev, "xclk"); 1636 - if (IS_ERR(ov7251->xclk)) { 1637 - dev_err(dev, "could not get xclk"); 1638 - return PTR_ERR(ov7251->xclk); 1639 - } 1277 + ov7251->xclk = devm_clk_get_optional(dev, NULL); 1278 + if (IS_ERR(ov7251->xclk)) 1279 + return dev_err_probe(dev, PTR_ERR(ov7251->xclk), 1280 + "could not get xclk"); 1640 1281 1282 + /* 1283 + * We could have either a 24MHz or 19.2MHz clock rate from either DT or 1284 + * ACPI. We also need to support the IPU3 case which will have both an 1285 + * external clock AND a clock-frequency property. 1286 + */ 1641 1287 ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency", 1642 - &ov7251->xclk_freq); 1643 - if (ret) { 1644 - dev_err(dev, "could not get xclk frequency\n"); 1645 - return ret; 1288 + &rate); 1289 + if (ret && !ov7251->xclk) 1290 + return dev_err_probe(dev, ret, "invalid clock config\n"); 1291 + 1292 + clk_rate = clk_get_rate(ov7251->xclk); 1293 + ov7251->xclk_freq = clk_rate ? clk_rate : rate; 1294 + 1295 + if (ov7251->xclk_freq == 0) 1296 + return dev_err_probe(dev, -EINVAL, "invalid clock frequency\n"); 1297 + 1298 + if (!ret && ov7251->xclk) { 1299 + ret = clk_set_rate(ov7251->xclk, rate); 1300 + if (ret) 1301 + return dev_err_probe(dev, ret, 1302 + "failed to set clock rate\n"); 1646 1303 } 1647 1304 1648 - /* external clock must be 24MHz, allow 1% tolerance */ 1649 - if (ov7251->xclk_freq < 23760000 || ov7251->xclk_freq > 24240000) { 1650 - dev_err(dev, "external clock frequency %u is not supported\n", 1651 - ov7251->xclk_freq); 1652 - return -EINVAL; 1653 - } 1305 + for (i = 0; i < ARRAY_SIZE(supported_xclk_rates); i++) 1306 + if (ov7251->xclk_freq == supported_xclk_rates[i]) 1307 + break; 1654 1308 1655 - ret = clk_set_rate(ov7251->xclk, ov7251->xclk_freq); 1656 - if (ret) { 1657 - dev_err(dev, "could not set xclk frequency\n"); 1658 - return ret; 1659 - } 1309 + if (i == ARRAY_SIZE(supported_xclk_rates)) 1310 + return dev_err_probe(dev, -EINVAL, 1311 + "clock rate %u Hz is unsupported\n", 1312 + ov7251->xclk_freq); 1313 + 1314 + ov7251->pll_cfgs = ov7251_pll_cfgs[i]; 1660 1315 1661 1316 ov7251->io_regulator = devm_regulator_get(dev, "vdddo"); 1662 1317 if (IS_ERR(ov7251->io_regulator)) { ··· 1682 1341 1683 1342 mutex_init(&ov7251->lock); 1684 1343 1685 - v4l2_ctrl_handler_init(&ov7251->ctrls, 7); 1686 - ov7251->ctrls.lock = &ov7251->lock; 1687 - 1688 - v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops, 1689 - V4L2_CID_HFLIP, 0, 1, 1, 0); 1690 - v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops, 1691 - V4L2_CID_VFLIP, 0, 1, 1, 0); 1692 - ov7251->exposure = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops, 1693 - V4L2_CID_EXPOSURE, 1, 32, 1, 32); 1694 - ov7251->gain = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops, 1695 - V4L2_CID_GAIN, 16, 1023, 1, 16); 1696 - v4l2_ctrl_new_std_menu_items(&ov7251->ctrls, &ov7251_ctrl_ops, 1697 - V4L2_CID_TEST_PATTERN, 1698 - ARRAY_SIZE(ov7251_test_pattern_menu) - 1, 1699 - 0, 0, ov7251_test_pattern_menu); 1700 - ov7251->pixel_clock = v4l2_ctrl_new_std(&ov7251->ctrls, 1701 - &ov7251_ctrl_ops, 1702 - V4L2_CID_PIXEL_RATE, 1703 - 1, INT_MAX, 1, 1); 1704 - ov7251->link_freq = v4l2_ctrl_new_int_menu(&ov7251->ctrls, 1705 - &ov7251_ctrl_ops, 1706 - V4L2_CID_LINK_FREQ, 1707 - ARRAY_SIZE(link_freq) - 1, 1708 - 0, link_freq); 1709 - if (ov7251->link_freq) 1710 - ov7251->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1711 - 1712 - ov7251->sd.ctrl_handler = &ov7251->ctrls; 1713 - 1714 - if (ov7251->ctrls.error) { 1715 - dev_err(dev, "%s: control initialization error %d\n", 1716 - __func__, ov7251->ctrls.error); 1717 - ret = ov7251->ctrls.error; 1718 - goto free_ctrl; 1344 + ov7251->current_mode = &ov7251_mode_info_data[0]; 1345 + ret = ov7251_init_ctrls(ov7251); 1346 + if (ret) { 1347 + dev_err_probe(dev, ret, "error during v4l2 ctrl init\n"); 1348 + goto destroy_mutex; 1719 1349 } 1720 1350 1721 1351 v4l2_i2c_subdev_init(&ov7251->sd, client, &ov7251_subdev_ops); ··· 1701 1389 goto free_ctrl; 1702 1390 } 1703 1391 1704 - ret = ov7251_s_power(&ov7251->sd, true); 1705 - if (ret < 0) { 1706 - dev_err(dev, "could not power up OV7251\n"); 1392 + ret = ov7251_set_power_on(ov7251->dev); 1393 + if (ret) 1707 1394 goto free_entity; 1708 - } 1709 1395 1710 - ret = ov7251_read_reg(ov7251, OV7251_CHIP_ID_HIGH, &chip_id_high); 1711 - if (ret < 0 || chip_id_high != OV7251_CHIP_ID_HIGH_BYTE) { 1712 - dev_err(dev, "could not read ID high\n"); 1713 - ret = -ENODEV; 1396 + ret = ov7251_detect_chip(ov7251); 1397 + if (ret) 1714 1398 goto power_down; 1715 - } 1716 - ret = ov7251_read_reg(ov7251, OV7251_CHIP_ID_LOW, &chip_id_low); 1717 - if (ret < 0 || chip_id_low != OV7251_CHIP_ID_LOW_BYTE) { 1718 - dev_err(dev, "could not read ID low\n"); 1719 - ret = -ENODEV; 1720 - goto power_down; 1721 - } 1722 1399 1723 - ret = ov7251_read_reg(ov7251, OV7251_SC_GP_IO_IN1, &chip_rev); 1724 - if (ret < 0) { 1725 - dev_err(dev, "could not read revision\n"); 1726 - ret = -ENODEV; 1727 - goto power_down; 1728 - } 1729 - chip_rev >>= 4; 1730 - 1731 - dev_info(dev, "OV7251 revision %x (%s) detected at address 0x%02x\n", 1732 - chip_rev, 1733 - chip_rev == 0x4 ? "1A / 1B" : 1734 - chip_rev == 0x5 ? "1C / 1D" : 1735 - chip_rev == 0x6 ? "1E" : 1736 - chip_rev == 0x7 ? "1F" : "unknown", 1737 - client->addr); 1400 + pm_runtime_set_active(&client->dev); 1401 + pm_runtime_get_noresume(&client->dev); 1402 + pm_runtime_enable(&client->dev); 1738 1403 1739 1404 ret = ov7251_read_reg(ov7251, OV7251_PRE_ISP_00, 1740 1405 &ov7251->pre_isp_00); 1741 1406 if (ret < 0) { 1742 1407 dev_err(dev, "could not read test pattern value\n"); 1743 1408 ret = -ENODEV; 1744 - goto power_down; 1409 + goto err_pm_runtime; 1745 1410 } 1746 1411 1747 1412 ret = ov7251_read_reg(ov7251, OV7251_TIMING_FORMAT1, ··· 1726 1437 if (ret < 0) { 1727 1438 dev_err(dev, "could not read vflip value\n"); 1728 1439 ret = -ENODEV; 1729 - goto power_down; 1440 + goto err_pm_runtime; 1730 1441 } 1731 1442 1732 1443 ret = ov7251_read_reg(ov7251, OV7251_TIMING_FORMAT2, ··· 1734 1445 if (ret < 0) { 1735 1446 dev_err(dev, "could not read hflip value\n"); 1736 1447 ret = -ENODEV; 1737 - goto power_down; 1448 + goto err_pm_runtime; 1738 1449 } 1739 1450 1740 - ov7251_s_power(&ov7251->sd, false); 1451 + pm_runtime_set_autosuspend_delay(&client->dev, 1000); 1452 + pm_runtime_use_autosuspend(&client->dev); 1453 + pm_runtime_put_autosuspend(&client->dev); 1741 1454 1742 1455 ret = v4l2_async_register_subdev(&ov7251->sd); 1743 1456 if (ret < 0) { ··· 1751 1460 1752 1461 return 0; 1753 1462 1463 + err_pm_runtime: 1464 + pm_runtime_disable(ov7251->dev); 1465 + pm_runtime_put_noidle(ov7251->dev); 1754 1466 power_down: 1755 - ov7251_s_power(&ov7251->sd, false); 1467 + ov7251_set_power_off(ov7251->dev); 1756 1468 free_entity: 1757 1469 media_entity_cleanup(&ov7251->sd.entity); 1758 1470 free_ctrl: 1759 1471 v4l2_ctrl_handler_free(&ov7251->ctrls); 1472 + destroy_mutex: 1760 1473 mutex_destroy(&ov7251->lock); 1761 1474 1762 1475 return ret; ··· 1776 1481 v4l2_ctrl_handler_free(&ov7251->ctrls); 1777 1482 mutex_destroy(&ov7251->lock); 1778 1483 1484 + pm_runtime_disable(ov7251->dev); 1485 + if (!pm_runtime_status_suspended(ov7251->dev)) 1486 + ov7251_set_power_off(ov7251->dev); 1487 + pm_runtime_set_suspended(ov7251->dev); 1488 + 1779 1489 return 0; 1780 1490 } 1491 + 1492 + static const struct dev_pm_ops ov7251_pm_ops = { 1493 + SET_RUNTIME_PM_OPS(ov7251_set_power_off, ov7251_set_power_on, NULL) 1494 + }; 1781 1495 1782 1496 static const struct of_device_id ov7251_of_match[] = { 1783 1497 { .compatible = "ovti,ov7251" }, ··· 1794 1490 }; 1795 1491 MODULE_DEVICE_TABLE(of, ov7251_of_match); 1796 1492 1493 + static const struct acpi_device_id ov7251_acpi_match[] = { 1494 + { "INT347E" }, 1495 + { } 1496 + }; 1497 + MODULE_DEVICE_TABLE(acpi, ov7251_acpi_match); 1498 + 1797 1499 static struct i2c_driver ov7251_i2c_driver = { 1798 1500 .driver = { 1799 1501 .of_match_table = ov7251_of_match, 1502 + .acpi_match_table = ov7251_acpi_match, 1800 1503 .name = "ov7251", 1504 + .pm = &ov7251_pm_ops, 1801 1505 }, 1802 1506 .probe_new = ov7251_probe, 1803 1507 .remove = ov7251_remove,

+19 -14

drivers/media/i2c/ov7640.c

··· 13 13 MODULE_DESCRIPTION("OmniVision ov7640 sensor driver"); 14 14 MODULE_LICENSE("GPL v2"); 15 15 16 - static const u8 initial_registers[] = { 17 - 0x12, 0x80, 18 - 0x12, 0x54, 19 - 0x14, 0x24, 20 - 0x15, 0x01, 21 - 0x28, 0x20, 22 - 0x75, 0x82, 23 - 0xFF, 0xFF, /* Terminator (reg 0xFF is unused) */ 16 + struct reg_val { 17 + u8 reg; 18 + u8 val; 24 19 }; 25 20 26 - static int write_regs(struct i2c_client *client, const u8 *regs) 27 - { 28 - int i; 21 + static const struct reg_val regval_init[] = { 22 + {0x12, 0x80}, 23 + {0x12, 0x54}, 24 + {0x14, 0x24}, 25 + {0x15, 0x01}, 26 + {0x28, 0x20}, 27 + {0x75, 0x82}, 28 + }; 29 29 30 - for (i = 0; regs[i] != 0xFF; i += 2) 31 - if (i2c_smbus_write_byte_data(client, regs[i], regs[i + 1]) < 0) 30 + static int write_regs(struct i2c_client *client, 31 + const struct reg_val *rv, int len) 32 + { 33 + while (--len >= 0) { 34 + if (i2c_smbus_write_byte_data(client, rv->reg, rv->val) < 0) 32 35 return -1; 36 + rv++; 37 + } 33 38 return 0; 34 39 } 35 40 ··· 61 56 v4l_info(client, "chip found @ 0x%02x (%s)\n", 62 57 client->addr << 1, client->adapter->name); 63 58 64 - if (write_regs(client, initial_registers) < 0) { 59 + if (write_regs(client, regval_init, ARRAY_SIZE(regval_init)) < 0) { 65 60 v4l_err(client, "error initializing OV7640\n"); 66 61 return -ENODEV; 67 62 }

-1

drivers/media/i2c/ov7670.c

··· 2017 2017 v4l2_async_unregister_subdev(sd); 2018 2018 v4l2_ctrl_handler_free(&info->hdl); 2019 2019 media_entity_cleanup(&info->sd.entity); 2020 - ov7670_power_off(sd); 2021 2020 return 0; 2022 2021 } 2023 2022

+6 -17

drivers/media/i2c/ov8856.c

··· 63 63 #define OV8856_ANAL_GAIN_STEP 1 64 64 65 65 /* Digital gain controls from sensor */ 66 + #define OV8856_REG_DIGITAL_GAIN 0x350a 66 67 #define OV8856_REG_MWB_R_GAIN 0x5019 67 68 #define OV8856_REG_MWB_G_GAIN 0x501b 68 69 #define OV8856_REG_MWB_B_GAIN 0x501d ··· 352 351 {0x484b, 0x05}, 353 352 {0x5000, 0x57}, 354 353 {0x5001, 0x0a}, 355 - {0x5004, 0x04}, 354 + {0x5004, 0x06}, 356 355 {0x502e, 0x03}, 357 356 {0x5030, 0x41}, 358 357 {0x5795, 0x02}, ··· 544 543 {0x484b, 0x05}, 545 544 {0x5000, 0x57}, 546 545 {0x5001, 0x0a}, 547 - {0x5004, 0x04}, 546 + {0x5004, 0x06}, 548 547 {0x502e, 0x03}, 549 548 {0x5030, 0x41}, 550 549 {0x5795, 0x00}, ··· 735 734 {0x484b, 0x05}, 736 735 {0x5000, 0x57}, 737 736 {0x5001, 0x0a}, 738 - {0x5004, 0x04}, 737 + {0x5004, 0x06}, 739 738 {0x502e, 0x03}, 740 739 {0x5030, 0x41}, 741 740 {0x5780, 0x14}, ··· 926 925 {0x484b, 0x05}, 927 926 {0x5000, 0x57}, 928 927 {0x5001, 0x0a}, 929 - {0x5004, 0x04}, 928 + {0x5004, 0x06}, 930 929 {0x502e, 0x03}, 931 930 {0x5030, 0x41}, 932 931 {0x5780, 0x14}, ··· 1756 1755 1757 1756 static int ov8856_update_digital_gain(struct ov8856 *ov8856, u32 d_gain) 1758 1757 { 1759 - int ret; 1760 - 1761 - ret = ov8856_write_reg(ov8856, OV8856_REG_MWB_R_GAIN, 1762 - OV8856_REG_VALUE_16BIT, d_gain); 1763 - if (ret) 1764 - return ret; 1765 - 1766 - ret = ov8856_write_reg(ov8856, OV8856_REG_MWB_G_GAIN, 1767 - OV8856_REG_VALUE_16BIT, d_gain); 1768 - if (ret) 1769 - return ret; 1770 - 1771 - return ov8856_write_reg(ov8856, OV8856_REG_MWB_B_GAIN, 1758 + return ov8856_write_reg(ov8856, OV8856_REG_DIGITAL_GAIN, 1772 1759 OV8856_REG_VALUE_16BIT, d_gain); 1773 1760 } 1774 1761

+5 -5

drivers/media/i2c/rdacm20.c

··· 47 47 #define OV10635_VTS 933 48 48 49 49 /* 50 - * As the drivers supports a single MEDIA_BUS_FMT_UYVY8_2X8 format we 50 + * As the drivers supports a single MEDIA_BUS_FMT_UYVY8_1X16 format we 51 51 * can harcode the pixel rate. 52 52 * 53 53 * PCLK is fed through the system clock, programmed @88MHz. 54 - * MEDIA_BUS_FMT_UYVY8_2X8 format = 2 samples per pixel. 54 + * MEDIA_BUS_FMT_UYVY8_1X16 format = 2 samples per pixel. 55 55 * 56 56 * Pixelrate = PCLK / 2 57 57 * FPS = (OV10635_VTS * OV10635_HTS) / PixelRate ··· 409 409 if (code->pad || code->index > 0) 410 410 return -EINVAL; 411 411 412 - code->code = MEDIA_BUS_FMT_UYVY8_2X8; 412 + code->code = MEDIA_BUS_FMT_UYVY8_1X16; 413 413 414 414 return 0; 415 415 } ··· 425 425 426 426 mf->width = OV10635_WIDTH; 427 427 mf->height = OV10635_HEIGHT; 428 - mf->code = MEDIA_BUS_FMT_UYVY8_2X8; 428 + mf->code = MEDIA_BUS_FMT_UYVY8_1X16; 429 429 mf->colorspace = V4L2_COLORSPACE_RAW; 430 430 mf->field = V4L2_FIELD_NONE; 431 431 mf->ycbcr_enc = V4L2_YCBCR_ENC_601; ··· 611 611 goto error_free_ctrls; 612 612 613 613 dev->pad.flags = MEDIA_PAD_FL_SOURCE; 614 - dev->sd.entity.flags |= MEDIA_ENT_F_CAM_SENSOR; 614 + dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 615 615 ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); 616 616 if (ret < 0) 617 617 goto error_free_ctrls;

+1 -1

drivers/media/i2c/rdacm21.c

··· 583 583 goto error_free_ctrls; 584 584 585 585 dev->pad.flags = MEDIA_PAD_FL_SOURCE; 586 - dev->sd.entity.flags |= MEDIA_ENT_F_CAM_SENSOR; 586 + dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 587 587 ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); 588 588 if (ret < 0) 589 589 goto error_free_ctrls;

+3 -1

drivers/media/i2c/s5k6a3.c

··· 213 213 for (i++; i < S5K6A3_NUM_SUPPLIES; i++) { 214 214 ret = regulator_enable(sensor->supplies[i].consumer); 215 215 if (ret < 0) 216 - goto error_reg_dis; 216 + goto error_clk; 217 217 } 218 218 219 219 gpio_set_value(sensor->gpio_reset, 1); ··· 226 226 msleep(20); 227 227 return 0; 228 228 229 + error_clk: 230 + clk_disable_unprepare(sensor->clock); 229 231 error_reg_dis: 230 232 for (--i; i >= 0; --i) 231 233 regulator_disable(sensor->supplies[i].consumer);

+34 -27

drivers/media/i2c/video-i2c.c

··· 9 9 * - Melexis MLX90640 Thermal Cameras 10 10 */ 11 11 12 + #include <linux/bits.h> 12 13 #include <linux/delay.h> 13 14 #include <linux/freezer.h> 14 15 #include <linux/hwmon.h> ··· 34 33 #include <media/videobuf2-vmalloc.h> 35 34 36 35 #define VIDEO_I2C_DRIVER "video-i2c" 36 + 37 + /* Power control register */ 38 + #define AMG88XX_REG_PCTL 0x00 39 + #define AMG88XX_PCTL_NORMAL 0x00 40 + #define AMG88XX_PCTL_SLEEP 0x10 41 + 42 + /* Reset register */ 43 + #define AMG88XX_REG_RST 0x01 44 + #define AMG88XX_RST_FLAG 0x30 45 + #define AMG88XX_RST_INIT 0x3f 46 + 47 + /* Frame rate register */ 48 + #define AMG88XX_REG_FPSC 0x02 49 + #define AMG88XX_FPSC_1FPS BIT(0) 50 + 51 + /* Thermistor register */ 52 + #define AMG88XX_REG_TTHL 0x0e 53 + 54 + /* Temperature register */ 55 + #define AMG88XX_REG_T01L 0x80 56 + 57 + /* RAM */ 58 + #define MLX90640_RAM_START_ADDR 0x0400 59 + 60 + /* EEPROM */ 61 + #define MLX90640_EEPROM_START_ADDR 0x2400 62 + 63 + /* Control register */ 64 + #define MLX90640_REG_CTL1 0x800d 65 + #define MLX90640_REG_CTL1_MASK GENMASK(9, 7) 66 + #define MLX90640_REG_CTL1_MASK_SHIFT 7 37 67 38 68 struct video_i2c_chip; 39 69 ··· 156 124 { 157 125 struct video_i2c_data *data = priv; 158 126 159 - return regmap_bulk_read(data->regmap, 0x2400 + offset, val, bytes); 127 + return regmap_bulk_read(data->regmap, MLX90640_EEPROM_START_ADDR + offset, val, bytes); 160 128 } 161 129 162 130 static struct nvmem_config mlx90640_nvram_config = { ··· 167 135 .reg_read = mlx90640_nvram_read, 168 136 }; 169 137 170 - /* Power control register */ 171 - #define AMG88XX_REG_PCTL 0x00 172 - #define AMG88XX_PCTL_NORMAL 0x00 173 - #define AMG88XX_PCTL_SLEEP 0x10 174 - 175 - /* Reset register */ 176 - #define AMG88XX_REG_RST 0x01 177 - #define AMG88XX_RST_FLAG 0x30 178 - #define AMG88XX_RST_INIT 0x3f 179 - 180 - /* Frame rate register */ 181 - #define AMG88XX_REG_FPSC 0x02 182 - #define AMG88XX_FPSC_1FPS BIT(0) 183 - 184 - /* Thermistor register */ 185 - #define AMG88XX_REG_TTHL 0x0e 186 - 187 - /* Temperature register */ 188 - #define AMG88XX_REG_T01L 0x80 189 - 190 - /* Control register */ 191 - #define MLX90640_REG_CTL1 0x800d 192 - #define MLX90640_REG_CTL1_MASK 0x0380 193 - #define MLX90640_REG_CTL1_MASK_SHIFT 7 194 - 195 138 static int amg88xx_xfer(struct video_i2c_data *data, char *buf) 196 139 { 197 140 return regmap_bulk_read(data->regmap, AMG88XX_REG_T01L, buf, ··· 175 168 176 169 static int mlx90640_xfer(struct video_i2c_data *data, char *buf) 177 170 { 178 - return regmap_bulk_read(data->regmap, 0x400, buf, 171 + return regmap_bulk_read(data->regmap, MLX90640_RAM_START_ADDR, buf, 179 172 data->chip->buffer_size); 180 173 } 181 174

+4 -17

drivers/media/mc/mc-device.c

··· 604 604 media_gobj_destroy(&entity->graph_obj); 605 605 606 606 /* invoke entity_notify callbacks to handle entity removal?? */ 607 - 608 - entity->graph_obj.mdev = NULL; 609 607 } 610 608 611 - /** 612 - * media_device_register_entity - Register an entity with a media device 613 - * @mdev: The media device 614 - * @entity: The entity 615 - */ 616 609 int __must_check media_device_register_entity(struct media_device *mdev, 617 610 struct media_entity *entity) 618 611 { ··· 684 691 } 685 692 EXPORT_SYMBOL_GPL(media_device_unregister_entity); 686 693 687 - /** 688 - * media_device_init() - initialize a media device 689 - * @mdev: The media device 690 - * 691 - * The caller is responsible for initializing the media device before 692 - * registration. The following fields must be set: 693 - * 694 - * - dev must point to the parent device 695 - * - model must be filled with the device model name 696 - */ 697 694 void media_device_init(struct media_device *mdev) 698 695 { 699 696 INIT_LIST_HEAD(&mdev->entities); ··· 697 714 ida_init(&mdev->entity_internal_idx); 698 715 699 716 atomic_set(&mdev->request_id, 0); 717 + 718 + if (!*mdev->bus_info) 719 + media_set_bus_info(mdev->bus_info, sizeof(mdev->bus_info), 720 + mdev->dev); 700 721 701 722 dev_dbg(mdev->dev, "Media device initialized\n"); 702 723 }

+63 -19

drivers/media/mc/mc-entity.c

··· 44 44 } 45 45 }; 46 46 47 + static inline const char *link_type_name(struct media_link *link) 48 + { 49 + switch (link->flags & MEDIA_LNK_FL_LINK_TYPE) { 50 + case MEDIA_LNK_FL_DATA_LINK: 51 + return "data"; 52 + case MEDIA_LNK_FL_INTERFACE_LINK: 53 + return "interface"; 54 + case MEDIA_LNK_FL_ANCILLARY_LINK: 55 + return "ancillary"; 56 + default: 57 + return "unknown"; 58 + } 59 + } 60 + 47 61 __must_check int __media_entity_enum_init(struct media_entity_enum *ent_enum, 48 62 int idx_max) 49 63 { ··· 103 89 104 90 dev_dbg(gobj->mdev->dev, 105 91 "%s id %u: %s link id %u ==> id %u\n", 106 - event_name, media_id(gobj), 107 - media_type(link->gobj0) == MEDIA_GRAPH_PAD ? 108 - "data" : "interface", 92 + event_name, media_id(gobj), link_type_name(link), 109 93 media_id(link->gobj0), 110 94 media_id(link->gobj1)); 111 95 break; ··· 306 294 struct media_entity *next; 307 295 308 296 link = list_entry(link_top(graph), typeof(*link), list); 297 + 298 + /* If the link is not a data link, don't follow it */ 299 + if ((link->flags & MEDIA_LNK_FL_LINK_TYPE) != MEDIA_LNK_FL_DATA_LINK) { 300 + link_top(graph) = link_top(graph)->next; 301 + return; 302 + } 309 303 310 304 /* The link is not enabled so we do not follow. */ 311 305 if (!(link->flags & MEDIA_LNK_FL_ENABLED)) { ··· 597 579 struct media_link *rlink, *tmp; 598 580 struct media_entity *remote; 599 581 600 - if (link->source->entity == entity) 601 - remote = link->sink->entity; 602 - else 603 - remote = link->source->entity; 604 - 605 - list_for_each_entry_safe(rlink, tmp, &remote->links, list) { 606 - if (rlink != link->reverse) 607 - continue; 608 - 582 + /* Remove the reverse links for a data link. */ 583 + if ((link->flags & MEDIA_LNK_FL_LINK_TYPE) == MEDIA_LNK_FL_DATA_LINK) { 609 584 if (link->source->entity == entity) 610 - remote->num_backlinks--; 585 + remote = link->sink->entity; 586 + else 587 + remote = link->source->entity; 611 588 612 - /* Remove the remote link */ 613 - list_del(&rlink->list); 614 - media_gobj_destroy(&rlink->graph_obj); 615 - kfree(rlink); 589 + list_for_each_entry_safe(rlink, tmp, &remote->links, list) { 590 + if (rlink != link->reverse) 591 + continue; 616 592 617 - if (--remote->num_links == 0) 618 - break; 593 + if (link->source->entity == entity) 594 + remote->num_backlinks--; 595 + 596 + /* Remove the remote link */ 597 + list_del(&rlink->list); 598 + media_gobj_destroy(&rlink->graph_obj); 599 + kfree(rlink); 600 + 601 + if (--remote->num_links == 0) 602 + break; 603 + } 619 604 } 605 + 620 606 list_del(&link->list); 621 607 media_gobj_destroy(&link->graph_obj); 622 608 kfree(link); ··· 1029 1007 mutex_unlock(&mdev->graph_mutex); 1030 1008 } 1031 1009 EXPORT_SYMBOL_GPL(media_remove_intf_links); 1010 + 1011 + struct media_link *media_create_ancillary_link(struct media_entity *primary, 1012 + struct media_entity *ancillary) 1013 + { 1014 + struct media_link *link; 1015 + 1016 + link = media_add_link(&primary->links); 1017 + if (!link) 1018 + return ERR_PTR(-ENOMEM); 1019 + 1020 + link->gobj0 = &primary->graph_obj; 1021 + link->gobj1 = &ancillary->graph_obj; 1022 + link->flags = MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED | 1023 + MEDIA_LNK_FL_ANCILLARY_LINK; 1024 + 1025 + /* Initialize graph object embedded in the new link */ 1026 + media_gobj_create(primary->graph_obj.mdev, MEDIA_GRAPH_LINK, 1027 + &link->graph_obj); 1028 + 1029 + return link; 1030 + } 1031 + EXPORT_SYMBOL_GPL(media_create_ancillary_link);

-2

drivers/media/pci/bt8xx/bttv-driver.c

··· 2435 2435 2436 2436 strscpy(cap->driver, "bttv", sizeof(cap->driver)); 2437 2437 strscpy(cap->card, btv->video_dev.name, sizeof(cap->card)); 2438 - snprintf(cap->bus_info, sizeof(cap->bus_info), 2439 - "PCI:%s", pci_name(btv->c.pci)); 2440 2438 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE | 2441 2439 V4L2_CAP_STREAMING | V4L2_CAP_DEVICE_CAPS; 2442 2440 if (no_overlay <= 0)

-2

drivers/media/pci/cx18/cx18-ioctl.c

··· 389 389 390 390 strscpy(vcap->driver, CX18_DRIVER_NAME, sizeof(vcap->driver)); 391 391 strscpy(vcap->card, cx->card_name, sizeof(vcap->card)); 392 - snprintf(vcap->bus_info, sizeof(vcap->bus_info), 393 - "PCI:%s", pci_name(cx->pci_dev)); 394 392 vcap->capabilities = cx->v4l2_cap | V4L2_CAP_DEVICE_CAPS; 395 393 return 0; 396 394 }

+3 -3

drivers/media/pci/cx23885/cx23885-core.c

··· 2165 2165 err = dma_set_mask(&pci_dev->dev, 0xffffffff); 2166 2166 if (err) { 2167 2167 pr_err("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name); 2168 - goto fail_ctrl; 2168 + goto fail_dma_set_mask; 2169 2169 } 2170 2170 2171 2171 err = request_irq(pci_dev->irq, cx23885_irq, ··· 2173 2173 if (err < 0) { 2174 2174 pr_err("%s: can't get IRQ %d\n", 2175 2175 dev->name, pci_dev->irq); 2176 - goto fail_irq; 2176 + goto fail_dma_set_mask; 2177 2177 } 2178 2178 2179 2179 switch (dev->board) { ··· 2195 2195 2196 2196 return 0; 2197 2197 2198 - fail_irq: 2198 + fail_dma_set_mask: 2199 2199 cx23885_dev_unregister(dev); 2200 2200 fail_ctrl: 2201 2201 v4l2_ctrl_handler_free(hdl);

+2 -2

drivers/media/pci/cx25821/cx25821-alsa.c

··· 728 728 729 729 chip->irq = dev->pci->irq; 730 730 731 - err = request_irq(dev->pci->irq, cx25821_irq, 732 - IRQF_SHARED, chip->dev->name, chip); 731 + err = devm_request_irq(&dev->pci->dev, dev->pci->irq, cx25821_irq, 732 + IRQF_SHARED, chip->dev->name, chip); 733 733 734 734 if (err < 0) { 735 735 pr_err("ERROR %s: can't get IRQ %d for ALSA\n", chip->dev->name,

+1 -1

drivers/media/pci/cx25821/cx25821-core.c

··· 1332 1332 struct cx25821_dev *dev = get_cx25821(v4l2_dev); 1333 1333 1334 1334 cx25821_shutdown(dev); 1335 - pci_disable_device(pci_dev); 1336 1335 1337 1336 /* unregister stuff */ 1338 1337 if (pci_dev->irq) 1339 1338 free_irq(pci_dev->irq, dev); 1339 + pci_disable_device(pci_dev); 1340 1340 1341 1341 cx25821_dev_unregister(dev); 1342 1342 v4l2_device_unregister(v4l2_dev);

-1

drivers/media/pci/cx88/cx88-blackbird.c

··· 796 796 struct cx88_core *core = dev->core; 797 797 798 798 strscpy(cap->driver, "cx88_blackbird", sizeof(cap->driver)); 799 - sprintf(cap->bus_info, "PCI:%s", pci_name(dev->pci)); 800 799 return cx88_querycap(file, core, cap); 801 800 } 802 801

-1

drivers/media/pci/cx88/cx88-video.c

··· 808 808 struct cx88_core *core = dev->core; 809 809 810 810 strscpy(cap->driver, "cx8800", sizeof(cap->driver)); 811 - sprintf(cap->bus_info, "PCI:%s", pci_name(dev->pci)); 812 811 return cx88_querycap(file, core, cap); 813 812 } 814 813

-3

drivers/media/pci/dt3155/dt3155.c

··· 292 292 static int dt3155_querycap(struct file *filp, void *p, 293 293 struct v4l2_capability *cap) 294 294 { 295 - struct dt3155_priv *pd = video_drvdata(filp); 296 - 297 295 strscpy(cap->driver, DT3155_NAME, sizeof(cap->driver)); 298 296 strscpy(cap->card, DT3155_NAME " frame grabber", sizeof(cap->card)); 299 - sprintf(cap->bus_info, "PCI:%s", pci_name(pd->pdev)); 300 297 return 0; 301 298 } 302 299

+2

drivers/media/pci/intel/ipu3/cio2-bridge.c

··· 25 25 CIO2_SENSOR_CONFIG("INT33BE", 1, 419200000), 26 26 /* Omnivision OV8865 */ 27 27 CIO2_SENSOR_CONFIG("INT347A", 1, 360000000), 28 + /* Omnivision OV7251 */ 29 + CIO2_SENSOR_CONFIG("INT347E", 1, 319200000), 28 30 /* Omnivision OV2680 */ 29 31 CIO2_SENSOR_CONFIG("OVTI2680", 0), 30 32 };

+5 -6

drivers/media/pci/intel/ipu3/ipu3-cio2-main.c

··· 65 65 .fourcc = V4L2_PIX_FMT_IPU3_SRGGB10, 66 66 .mipicode = 0x2b, 67 67 .bpp = 10, 68 + }, { 69 + .mbus_code = MEDIA_BUS_FMT_Y10_1X10, 70 + .fourcc = V4L2_PIX_FMT_IPU3_Y10, 71 + .mipicode = 0x2b, 72 + .bpp = 10, 68 73 }, 69 74 }; 70 75 ··· 1051 1046 static int cio2_v4l2_querycap(struct file *file, void *fh, 1052 1047 struct v4l2_capability *cap) 1053 1048 { 1054 - struct cio2_device *cio2 = video_drvdata(file); 1055 - 1056 1049 strscpy(cap->driver, CIO2_NAME, sizeof(cap->driver)); 1057 1050 strscpy(cap->card, CIO2_DEVICE_NAME, sizeof(cap->card)); 1058 - snprintf(cap->bus_info, sizeof(cap->bus_info), 1059 - "PCI:%s", pci_name(cio2->pci_dev)); 1060 1051 1061 1052 return 0; 1062 1053 } ··· 1778 1777 cio2->media_dev.dev = dev; 1779 1778 strscpy(cio2->media_dev.model, CIO2_DEVICE_NAME, 1780 1779 sizeof(cio2->media_dev.model)); 1781 - snprintf(cio2->media_dev.bus_info, sizeof(cio2->media_dev.bus_info), 1782 - "PCI:%s", pci_name(cio2->pci_dev)); 1783 1780 cio2->media_dev.hw_revision = 0; 1784 1781 1785 1782 media_device_init(&cio2->media_dev);

-1

drivers/media/pci/ivtv/ivtv-ioctl.c

··· 732 732 733 733 strscpy(vcap->driver, IVTV_DRIVER_NAME, sizeof(vcap->driver)); 734 734 strscpy(vcap->card, itv->card_name, sizeof(vcap->card)); 735 - snprintf(vcap->bus_info, sizeof(vcap->bus_info), "PCI:%s", pci_name(itv->pdev)); 736 735 vcap->capabilities = itv->v4l2_cap | V4L2_CAP_DEVICE_CAPS; 737 736 return 0; 738 737 }

-1

drivers/media/pci/meye/meye.c

··· 1012 1012 { 1013 1013 strscpy(cap->driver, "meye", sizeof(cap->driver)); 1014 1014 strscpy(cap->card, "meye", sizeof(cap->card)); 1015 - sprintf(cap->bus_info, "PCI:%s", pci_name(meye.mchip_dev)); 1016 1015 return 0; 1017 1016 } 1018 1017

+1 -3

drivers/media/pci/saa7134/saa7134-video.c

··· 1475 1475 strscpy(cap->driver, "saa7134", sizeof(cap->driver)); 1476 1476 strscpy(cap->card, saa7134_boards[dev->board].name, 1477 1477 sizeof(cap->card)); 1478 - sprintf(cap->bus_info, "PCI:%s", pci_name(dev->pci)); 1479 1478 cap->capabilities = V4L2_CAP_READWRITE | V4L2_CAP_STREAMING | 1480 1479 V4L2_CAP_RADIO | V4L2_CAP_VIDEO_CAPTURE | 1481 1480 V4L2_CAP_VBI_CAPTURE | V4L2_CAP_DEVICE_CAPS; ··· 1832 1833 spin_lock_irqsave(&dev->slock, flags); 1833 1834 start_preview(dev); 1834 1835 spin_unlock_irqrestore(&dev->slock, flags); 1835 - } 1836 - if (!on) { 1836 + } else { 1837 1837 if (priv != dev->overlay_owner) 1838 1838 return -EINVAL; 1839 1839 spin_lock_irqsave(&dev->slock, flags);

-1

drivers/media/pci/saa7164/saa7164-encoder.c

··· 490 490 strscpy(cap->driver, dev->name, sizeof(cap->driver)); 491 491 strscpy(cap->card, saa7164_boards[dev->board].name, 492 492 sizeof(cap->card)); 493 - sprintf(cap->bus_info, "PCI:%s", pci_name(dev->pci)); 494 493 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE | 495 494 V4L2_CAP_TUNER | V4L2_CAP_VBI_CAPTURE | 496 495 V4L2_CAP_DEVICE_CAPS;

-1

drivers/media/pci/saa7164/saa7164-vbi.c

··· 201 201 strscpy(cap->driver, dev->name, sizeof(cap->driver)); 202 202 strscpy(cap->card, saa7164_boards[dev->board].name, 203 203 sizeof(cap->card)); 204 - sprintf(cap->bus_info, "PCI:%s", pci_name(dev->pci)); 205 204 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE | 206 205 V4L2_CAP_TUNER | V4L2_CAP_VBI_CAPTURE | 207 206 V4L2_CAP_DEVICE_CAPS;

-3

drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c

··· 764 764 struct v4l2_capability *cap) 765 765 { 766 766 struct solo_enc_dev *solo_enc = video_drvdata(file); 767 - struct solo_dev *solo_dev = solo_enc->solo_dev; 768 767 769 768 strscpy(cap->driver, SOLO6X10_NAME, sizeof(cap->driver)); 770 769 snprintf(cap->card, sizeof(cap->card), "Softlogic 6x10 Enc %d", 771 770 solo_enc->ch); 772 - snprintf(cap->bus_info, sizeof(cap->bus_info), "PCI:%s", 773 - pci_name(solo_dev->pdev)); 774 771 return 0; 775 772 } 776 773

-4

drivers/media/pci/solo6x10/solo6x10-v4l2.c

··· 372 372 static int solo_querycap(struct file *file, void *priv, 373 373 struct v4l2_capability *cap) 374 374 { 375 - struct solo_dev *solo_dev = video_drvdata(file); 376 - 377 375 strscpy(cap->driver, SOLO6X10_NAME, sizeof(cap->driver)); 378 376 strscpy(cap->card, "Softlogic 6x10", sizeof(cap->card)); 379 - snprintf(cap->bus_info, sizeof(cap->bus_info), "PCI:%s", 380 - pci_name(solo_dev->pdev)); 381 377 return 0; 382 378 } 383 379

-4

drivers/media/pci/sta2x11/sta2x11_vip.c

··· 401 401 static int vidioc_querycap(struct file *file, void *priv, 402 402 struct v4l2_capability *cap) 403 403 { 404 - struct sta2x11_vip *vip = video_drvdata(file); 405 - 406 404 strscpy(cap->driver, KBUILD_MODNAME, sizeof(cap->driver)); 407 405 strscpy(cap->card, KBUILD_MODNAME, sizeof(cap->card)); 408 - snprintf(cap->bus_info, sizeof(cap->bus_info), "PCI:%s", 409 - pci_name(vip->pdev)); 410 406 return 0; 411 407 } 412 408

-1

drivers/media/pci/tw5864/tw5864-video.c

··· 604 604 strscpy(cap->driver, "tw5864", sizeof(cap->driver)); 605 605 snprintf(cap->card, sizeof(cap->card), "TW5864 Encoder %d", 606 606 input->nr); 607 - sprintf(cap->bus_info, "PCI:%s", pci_name(input->root->pci)); 608 607 return 0; 609 608 } 610 609

-3

drivers/media/pci/tw68/tw68-video.c

··· 712 712 static int tw68_querycap(struct file *file, void *priv, 713 713 struct v4l2_capability *cap) 714 714 { 715 - struct tw68_dev *dev = video_drvdata(file); 716 - 717 715 strscpy(cap->driver, "tw68", sizeof(cap->driver)); 718 716 strscpy(cap->card, "Techwell Capture Card", 719 717 sizeof(cap->card)); 720 - sprintf(cap->bus_info, "PCI:%s", pci_name(dev->pci)); 721 718 return 0; 722 719 } 723 720

-2

drivers/media/pci/tw686x/tw686x-video.c

··· 762 762 763 763 strscpy(cap->driver, "tw686x", sizeof(cap->driver)); 764 764 strscpy(cap->card, dev->name, sizeof(cap->card)); 765 - snprintf(cap->bus_info, sizeof(cap->bus_info), 766 - "PCI:%s", pci_name(dev->pci_dev)); 767 765 return 0; 768 766 } 769 767

-5

drivers/media/platform/allegro-dvt/allegro-core.c

··· 3249 3249 static int allegro_querycap(struct file *file, void *fh, 3250 3250 struct v4l2_capability *cap) 3251 3251 { 3252 - struct video_device *vdev = video_devdata(file); 3253 - struct allegro_dev *dev = video_get_drvdata(vdev); 3254 - 3255 3252 strscpy(cap->driver, KBUILD_MODNAME, sizeof(cap->driver)); 3256 3253 strscpy(cap->card, "Allegro DVT Video Encoder", sizeof(cap->card)); 3257 - snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", 3258 - dev_name(&dev->plat_dev->dev)); 3259 3254 3260 3255 return 0; 3261 3256 }

+34 -50

drivers/media/platform/amphion/vdec.c

··· 26 26 #include "vpu_cmds.h" 27 27 #include "vpu_rpc.h" 28 28 29 - #define VDEC_FRAME_DEPTH 256 30 29 #define VDEC_MIN_BUFFER_CAP 8 30 + #define VDEC_MIN_BUFFER_OUT 8 31 31 32 32 struct vdec_fs_info { 33 33 char name[8]; ··· 63 63 bool is_source_changed; 64 64 u32 source_change; 65 65 u32 drain; 66 - u32 ts_pre_count; 67 - u32 frame_depth; 68 66 }; 69 67 70 68 static const struct vpu_format vdec_formats[] = { ··· 161 163 V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 2); 162 164 if (ctrl) 163 165 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; 166 + 167 + if (inst->ctrl_handler.error) { 168 + ret = inst->ctrl_handler.error; 169 + v4l2_ctrl_handler_free(&inst->ctrl_handler); 170 + return ret; 171 + } 164 172 165 173 ret = v4l2_ctrl_handler_setup(&inst->ctrl_handler); 166 174 if (ret) { ··· 474 470 if (!vdec->drain) 475 471 return 0; 476 472 477 - if (v4l2_m2m_num_src_bufs_ready(inst->fh.m2m_ctx)) 473 + if (!vpu_is_source_empty(inst)) 478 474 return 0; 479 475 480 476 if (!vdec->params.frame_count) { ··· 593 589 { 594 590 struct vdec_t *vdec = inst->priv; 595 591 596 - if (V4L2_TYPE_IS_OUTPUT(type)) { 597 - if (vdec->ts_pre_count >= vdec->frame_depth) 598 - return false; 592 + if (V4L2_TYPE_IS_OUTPUT(type)) 599 593 return true; 600 - } 601 594 602 595 if (vdec->req_frame_count) 603 596 return true; 604 597 605 598 return false; 599 + } 600 + 601 + static struct vb2_v4l2_buffer *vdec_get_src_buffer(struct vpu_inst *inst, u32 count) 602 + { 603 + if (count > 1) 604 + vpu_skip_frame(inst, count - 1); 605 + 606 + return vpu_next_src_buf(inst); 606 607 } 607 608 608 609 static int vdec_frame_decoded(struct vpu_inst *inst, void *arg) ··· 616 607 struct vpu_dec_pic_info *info = arg; 617 608 struct vpu_vb2_buffer *vpu_buf; 618 609 struct vb2_v4l2_buffer *vbuf; 610 + struct vb2_v4l2_buffer *src_buf; 619 611 int ret = 0; 620 612 621 613 if (!info || info->id >= ARRAY_SIZE(vdec->slots)) ··· 630 620 goto exit; 631 621 } 632 622 vbuf = &vpu_buf->m2m_buf.vb; 623 + src_buf = vdec_get_src_buffer(inst, info->consumed_count); 624 + if (src_buf) { 625 + v4l2_m2m_buf_copy_metadata(src_buf, vbuf, true); 626 + if (info->consumed_count) { 627 + v4l2_m2m_src_buf_remove(inst->fh.m2m_ctx); 628 + vpu_set_buffer_state(src_buf, VPU_BUF_STATE_IDLE); 629 + v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE); 630 + } else { 631 + vpu_set_buffer_state(src_buf, VPU_BUF_STATE_DECODED); 632 + } 633 + } 633 634 if (vpu_get_buffer_state(vbuf) == VPU_BUF_STATE_DECODED) 634 635 dev_info(inst->dev, "[%d] buf[%d] has been decoded\n", inst->id, info->id); 635 636 vpu_set_buffer_state(vbuf, VPU_BUF_STATE_DECODED); 636 637 vdec->decoded_frame_count++; 637 - if (vdec->ts_pre_count >= info->consumed_count) 638 - vdec->ts_pre_count -= info->consumed_count; 639 - else 640 - vdec->ts_pre_count = 0; 641 638 exit: 642 639 vpu_inst_unlock(inst); 643 640 ··· 700 683 vpu_set_buffer_state(vbuf, VPU_BUF_STATE_READY); 701 684 vb2_set_plane_payload(&vbuf->vb2_buf, 0, inst->cap_format.sizeimage[0]); 702 685 vb2_set_plane_payload(&vbuf->vb2_buf, 1, inst->cap_format.sizeimage[1]); 703 - vbuf->vb2_buf.timestamp = frame->timestamp; 704 686 vbuf->field = inst->cap_format.field; 705 687 vbuf->sequence = sequence; 706 - dev_dbg(inst->dev, "[%d][OUTPUT TS]%32lld\n", inst->id, frame->timestamp); 688 + dev_dbg(inst->dev, "[%d][OUTPUT TS]%32lld\n", inst->id, vbuf->vb2_buf.timestamp); 707 689 708 690 v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_DONE); 709 691 vpu_inst_lock(inst); ··· 724 708 vdec->fixed_fmt = false; 725 709 vdec->params.end_flag = 0; 726 710 vdec->drain = 0; 727 - vdec->ts_pre_count = 0; 728 711 vdec->params.frame_count = 0; 729 712 vdec->decoded_frame_count = 0; 730 713 vdec->display_frame_count = 0; ··· 797 782 if (vdec->codec_info.progressive) 798 783 inst->cap_format.field = V4L2_FIELD_NONE; 799 784 else 800 - inst->cap_format.field = V4L2_FIELD_SEQ_BT; 785 + inst->cap_format.field = V4L2_FIELD_SEQ_TB; 801 786 if (vdec->codec_info.color_primaries == V4L2_COLORSPACE_DEFAULT) 802 787 vdec->codec_info.color_primaries = V4L2_COLORSPACE_REC709; 803 788 if (vdec->codec_info.transfer_chars == V4L2_XFER_FUNC_DEFAULT) ··· 1259 1244 if (free_space < vb2_get_plane_payload(vb, 0) + 0x40000) 1260 1245 return -ENOMEM; 1261 1246 1247 + vpu_set_buffer_state(vbuf, VPU_BUF_STATE_INUSE); 1262 1248 ret = vpu_iface_input_frame(inst, vb); 1263 1249 if (ret < 0) 1264 1250 return -ENOMEM; 1265 1251 1266 1252 dev_dbg(inst->dev, "[%d][INPUT TS]%32lld\n", inst->id, vb->timestamp); 1267 - vdec->ts_pre_count++; 1268 1253 vdec->params.frame_count++; 1269 - 1270 - v4l2_m2m_src_buf_remove_by_buf(inst->fh.m2m_ctx, vbuf); 1271 - vpu_set_buffer_state(vbuf, VPU_BUF_STATE_IDLE); 1272 - v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_DONE); 1273 1254 1274 1255 if (vdec->drain) 1275 1256 vdec_drain(inst); ··· 1329 1318 vdec->sequence); 1330 1319 vdec->params.end_flag = 0; 1331 1320 vdec->drain = 0; 1332 - vdec->ts_pre_count = 0; 1333 1321 vdec->params.frame_count = 0; 1334 1322 vdec->decoded_frame_count = 0; 1335 1323 vdec->display_frame_count = 0; ··· 1535 1525 vdec->drain, vdec->eos_received, vdec->source_change); 1536 1526 break; 1537 1527 case 8: 1538 - num = scnprintf(str, size, "ts_pre_count = %d, frame_depth = %d\n", 1539 - vdec->ts_pre_count, vdec->frame_depth); 1540 - break; 1541 - case 9: 1542 1528 num = scnprintf(str, size, "fps = %d/%d\n", 1543 1529 vdec->codec_info.frame_rate.numerator, 1544 1530 vdec->codec_info.frame_rate.denominator); ··· 1568 1562 static void vdec_init(struct file *file) 1569 1563 { 1570 1564 struct vpu_inst *inst = to_inst(file); 1571 - struct vdec_t *vdec; 1572 1565 struct v4l2_format f; 1573 - 1574 - vdec = inst->priv; 1575 - vdec->frame_depth = VDEC_FRAME_DEPTH; 1576 1566 1577 1567 memset(&f, 0, sizeof(f)); 1578 1568 f.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; ··· 1614 1612 1615 1613 vdec->fixed_fmt = false; 1616 1614 inst->min_buffer_cap = VDEC_MIN_BUFFER_CAP; 1615 + inst->min_buffer_out = VDEC_MIN_BUFFER_OUT; 1617 1616 vdec_init(file); 1618 1617 1619 1618 return 0; 1620 - } 1621 - 1622 - static __poll_t vdec_poll(struct file *file, poll_table *wait) 1623 - { 1624 - struct vpu_inst *inst = to_inst(file); 1625 - struct vb2_queue *src_q, *dst_q; 1626 - __poll_t ret; 1627 - 1628 - ret = v4l2_m2m_fop_poll(file, wait); 1629 - src_q = v4l2_m2m_get_src_vq(inst->fh.m2m_ctx); 1630 - dst_q = v4l2_m2m_get_dst_vq(inst->fh.m2m_ctx); 1631 - if (vb2_is_streaming(src_q) && !vb2_is_streaming(dst_q)) 1632 - ret &= (~EPOLLERR); 1633 - if (!src_q->error && !dst_q->error && 1634 - (vb2_is_streaming(src_q) && list_empty(&src_q->queued_list)) && 1635 - (vb2_is_streaming(dst_q) && list_empty(&dst_q->queued_list))) 1636 - ret &= (~EPOLLERR); 1637 - 1638 - return ret; 1639 1619 } 1640 1620 1641 1621 static const struct v4l2_file_operations vdec_fops = { ··· 1625 1641 .open = vdec_open, 1626 1642 .release = vpu_v4l2_close, 1627 1643 .unlocked_ioctl = video_ioctl2, 1628 - .poll = vdec_poll, 1644 + .poll = v4l2_m2m_fop_poll, 1629 1645 .mmap = v4l2_m2m_fop_mmap, 1630 1646 }; 1631 1647

+28 -31

drivers/media/platform/amphion/venc.c

··· 33 33 #define VENC_CAPTURE_ENABLE BIT(1) 34 34 #define VENC_ENABLE_MASK (VENC_OUTPUT_ENABLE | VENC_CAPTURE_ENABLE) 35 35 #define VENC_MAX_BUF_CNT 8 36 + #define VENC_MIN_BUFFER_OUT 6 37 + #define VENC_MIN_BUFFER_CAP 6 36 38 37 39 struct venc_t { 38 40 struct vpu_encode_params params; ··· 283 281 if (!parm) 284 282 return -EINVAL; 285 283 284 + if (!V4L2_TYPE_IS_OUTPUT(parm->type)) 285 + return -EINVAL; 286 + 286 287 if (!vpu_helper_check_type(inst, parm->type)) 287 288 return -EINVAL; 288 289 ··· 305 300 unsigned long n, d; 306 301 307 302 if (!parm) 303 + return -EINVAL; 304 + 305 + if (!V4L2_TYPE_IS_OUTPUT(parm->type)) 308 306 return -EINVAL; 309 307 310 308 if (!vpu_helper_check_type(inst, parm->type)) ··· 431 423 if (inst->state != VPU_CODEC_STATE_DRAIN) 432 424 return 0; 433 425 434 - if (v4l2_m2m_num_src_bufs_ready(inst->fh.m2m_ctx)) 426 + if (!vpu_is_source_empty(inst)) 435 427 return 0; 436 428 437 429 if (!venc->input_ready) ··· 688 680 ~(1 << V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME), 689 681 V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME); 690 682 683 + if (inst->ctrl_handler.error) { 684 + ret = inst->ctrl_handler.error; 685 + v4l2_ctrl_handler_free(&inst->ctrl_handler); 686 + return ret; 687 + } 688 + 691 689 ret = v4l2_ctrl_handler_setup(&inst->ctrl_handler); 692 690 if (ret) { 693 691 dev_err(inst->dev, "[%d] setup ctrls fail, ret = %d\n", inst->id, ret); ··· 789 775 struct vb2_v4l2_buffer *vbuf) 790 776 { 791 777 struct venc_t *venc = inst->priv; 778 + struct vb2_v4l2_buffer *src_buf; 792 779 793 780 if (!vbuf) 794 781 return -EAGAIN; 795 782 783 + src_buf = vpu_find_buf_by_sequence(inst, inst->out_format.type, frame->info.frame_id); 784 + if (src_buf) { 785 + v4l2_m2m_buf_copy_metadata(src_buf, vbuf, true); 786 + vpu_set_buffer_state(src_buf, VPU_BUF_STATE_IDLE); 787 + v4l2_m2m_src_buf_remove_by_buf(inst->fh.m2m_ctx, src_buf); 788 + v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE); 789 + } else { 790 + vbuf->vb2_buf.timestamp = frame->info.timestamp; 791 + } 796 792 if (!venc_get_enable(inst->priv, vbuf->vb2_buf.type)) { 797 793 v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR); 798 794 return 0; ··· 824 800 } 825 801 vb2_set_plane_payload(&vbuf->vb2_buf, 0, frame->bytesused); 826 802 vbuf->sequence = frame->info.frame_id; 827 - vbuf->vb2_buf.timestamp = frame->info.timestamp; 828 803 vbuf->field = inst->cap_format.field; 829 804 vbuf->flags |= frame->info.pic_type; 830 805 vpu_set_buffer_state(vbuf, VPU_BUF_STATE_IDLE); 831 - dev_dbg(inst->dev, "[%d][OUTPUT TS]%32lld\n", inst->id, frame->info.timestamp); 806 + dev_dbg(inst->dev, "[%d][OUTPUT TS]%32lld\n", inst->id, vbuf->vb2_buf.timestamp); 832 807 v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_DONE); 833 808 venc->ready_count++; 834 809 ··· 881 858 vpu_inst_unlock(inst); 882 859 883 860 return ret; 884 - } 885 - 886 - static void venc_buf_done(struct vpu_inst *inst, struct vpu_frame_info *frame) 887 - { 888 - struct vb2_v4l2_buffer *vbuf; 889 - 890 - if (!inst->fh.m2m_ctx) 891 - return; 892 - 893 - vpu_inst_lock(inst); 894 - if (!venc_get_enable(inst->priv, frame->type)) 895 - goto exit; 896 - vbuf = vpu_find_buf_by_sequence(inst, frame->type, frame->sequence); 897 - if (!vbuf) { 898 - dev_err(inst->dev, "[%d] can't find buf: type %d, sequence %d\n", 899 - inst->id, frame->type, frame->sequence); 900 - goto exit; 901 - } 902 - 903 - vpu_set_buffer_state(vbuf, VPU_BUF_STATE_IDLE); 904 - if (V4L2_TYPE_IS_OUTPUT(frame->type)) 905 - v4l2_m2m_src_buf_remove_by_buf(inst->fh.m2m_ctx, vbuf); 906 - else 907 - v4l2_m2m_dst_buf_remove_by_buf(inst->fh.m2m_ctx, vbuf); 908 - v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_DONE); 909 - exit: 910 - vpu_inst_unlock(inst); 911 861 } 912 862 913 863 static void venc_set_last_buffer_dequeued(struct vpu_inst *inst) ··· 1248 1252 .check_ready = venc_check_ready, 1249 1253 .input_done = venc_input_done, 1250 1254 .get_one_frame = venc_frame_encoded, 1251 - .buf_done = venc_buf_done, 1252 1255 .stop_done = venc_stop_done, 1253 1256 .event_notify = venc_event_notify, 1254 1257 .release = venc_release, ··· 1328 1333 if (ret) 1329 1334 return ret; 1330 1335 1336 + inst->min_buffer_out = VENC_MIN_BUFFER_OUT; 1337 + inst->min_buffer_cap = VENC_MIN_BUFFER_CAP; 1331 1338 venc_init(file); 1332 1339 1333 1340 return 0;

-12

drivers/media/platform/amphion/vpu_dbg.c

··· 413 413 vpu->debugfs, 414 414 inst, 415 415 &vpu_dbg_inst_fops); 416 - if (!inst->debugfs) { 417 - dev_err(inst->dev, "vpu create debugfs %s fail\n", name); 418 - return -EINVAL; 419 - } 420 416 421 417 return 0; 422 418 } ··· 447 451 vpu->debugfs, 448 452 core, 449 453 &vpu_dbg_core_fops); 450 - if (!core->debugfs) { 451 - dev_err(core->dev, "vpu create debugfs %s fail\n", name); 452 - return -EINVAL; 453 - } 454 454 } 455 455 if (!core->debugfs_fwlog) { 456 456 scnprintf(name, sizeof(name), "fwlog.%d", core->id); ··· 455 463 vpu->debugfs, 456 464 core, 457 465 &vpu_dbg_fwlog_fops); 458 - if (!core->debugfs_fwlog) { 459 - dev_err(core->dev, "vpu create debugfs %s fail\n", name); 460 - return -EINVAL; 461 - } 462 466 } 463 467 464 468 return 0;

+1 -1

drivers/media/platform/amphion/vpu_defs.h

··· 69 69 VPU_MSG_ID_BS_ERROR, 70 70 VPU_MSG_ID_UNSUPPORTED, 71 71 VPU_MSG_ID_TIMESTAMP_INFO, 72 - 73 72 VPU_MSG_ID_FIRMWARE_XCPT, 73 + VPU_MSG_ID_PIC_SKIPPED, 74 74 }; 75 75 76 76 enum VPU_ENC_MEMORY_RESOURSE {

+3 -1

drivers/media/platform/amphion/vpu_malone.c

··· 170 170 VID_API_EVENT_DEC_CHECK_RES = 0x24, 171 171 VID_API_EVENT_DEC_CFG_INFO = 0x25, 172 172 VID_API_EVENT_UNSUPPORTED_STREAM = 0x26, 173 + VID_API_EVENT_PIC_SKIPPED = 0x27, 173 174 VID_API_EVENT_STR_SUSPENDED = 0x30, 174 175 VID_API_EVENT_SNAPSHOT_DONE = 0x40, 175 176 VID_API_EVENT_FW_STATUS = 0xF0, ··· 704 703 {VPU_MSG_ID_BS_ERROR, VID_API_EVENT_BS_ERROR}, 705 704 {VPU_MSG_ID_UNSUPPORTED, VID_API_EVENT_UNSUPPORTED_STREAM}, 706 705 {VPU_MSG_ID_FIRMWARE_XCPT, VID_API_EVENT_FIRMWARE_XCPT}, 706 + {VPU_MSG_ID_PIC_SKIPPED, VID_API_EVENT_PIC_SKIPPED}, 707 707 }; 708 708 709 709 static void vpu_malone_pack_fs_alloc(struct vpu_rpc_event *pkt, ··· 1558 1556 * merge the data to next frame 1559 1557 */ 1560 1558 vbuf = to_vb2_v4l2_buffer(vb); 1561 - if (vpu_vb_is_codecconfig(vbuf) && (s64)vb->timestamp < 0) { 1559 + if (vpu_vb_is_codecconfig(vbuf)) { 1562 1560 inst->extra_size += size; 1563 1561 return 0; 1564 1562 }

+8

drivers/media/platform/amphion/vpu_msgs.c

··· 166 166 vpu_v4l2_set_error(inst); 167 167 } 168 168 169 + static void vpu_session_handle_pic_skipped(struct vpu_inst *inst, struct vpu_rpc_event *pkt) 170 + { 171 + vpu_inst_lock(inst); 172 + vpu_skip_frame(inst, 1); 173 + vpu_inst_unlock(inst); 174 + } 175 + 169 176 static struct vpu_msg_handler handlers[] = { 170 177 {VPU_MSG_ID_START_DONE, vpu_session_handle_start_done}, 171 178 {VPU_MSG_ID_STOP_DONE, vpu_session_handle_stop_done}, ··· 188 181 {VPU_MSG_ID_PIC_EOS, vpu_session_handle_eos}, 189 182 {VPU_MSG_ID_UNSUPPORTED, vpu_session_handle_error}, 190 183 {VPU_MSG_ID_FIRMWARE_XCPT, vpu_session_handle_firmware_xcpt}, 184 + {VPU_MSG_ID_PIC_SKIPPED, vpu_session_handle_pic_skipped}, 191 185 }; 192 186 193 187 static int vpu_session_handle_msg(struct vpu_inst *inst, struct vpu_rpc_event *msg)

+64 -4

drivers/media/platform/amphion/vpu_v4l2.c

··· 73 73 if (inst->fh.m2m_ctx) { 74 74 src_q = v4l2_m2m_get_src_vq(inst->fh.m2m_ctx); 75 75 dst_q = v4l2_m2m_get_dst_vq(inst->fh.m2m_ctx); 76 - if (src_q) 77 - src_q->error = 1; 78 - if (dst_q) 79 - dst_q->error = 1; 76 + src_q->error = 1; 77 + dst_q->error = 1; 78 + wake_up(&src_q->done_wq); 79 + wake_up(&dst_q->done_wq); 80 80 } 81 81 vpu_inst_unlock(inst); 82 82 } ··· 125 125 wake_up(&q->done_wq); 126 126 vpu_notify_eos(inst); 127 127 return 0; 128 + } 129 + 130 + bool vpu_is_source_empty(struct vpu_inst *inst) 131 + { 132 + struct v4l2_m2m_buffer *buf = NULL; 133 + 134 + if (!inst->fh.m2m_ctx) 135 + return true; 136 + v4l2_m2m_for_each_src_buf(inst->fh.m2m_ctx, buf) { 137 + if (vpu_get_buffer_state(&buf->vb) == VPU_BUF_STATE_IDLE) 138 + return false; 139 + } 140 + return true; 128 141 } 129 142 130 143 const struct vpu_format *vpu_try_fmt_common(struct vpu_inst *inst, struct v4l2_format *f) ··· 245 232 return -EINVAL; 246 233 247 234 return call_vop(inst, process_capture, &vbuf->vb2_buf); 235 + } 236 + 237 + struct vb2_v4l2_buffer *vpu_next_src_buf(struct vpu_inst *inst) 238 + { 239 + struct vb2_v4l2_buffer *src_buf = v4l2_m2m_next_src_buf(inst->fh.m2m_ctx); 240 + 241 + if (!src_buf || vpu_get_buffer_state(src_buf) == VPU_BUF_STATE_IDLE) 242 + return NULL; 243 + 244 + while (vpu_vb_is_codecconfig(src_buf)) { 245 + v4l2_m2m_src_buf_remove(inst->fh.m2m_ctx); 246 + vpu_set_buffer_state(src_buf, VPU_BUF_STATE_IDLE); 247 + v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE); 248 + 249 + src_buf = v4l2_m2m_next_src_buf(inst->fh.m2m_ctx); 250 + if (!src_buf || vpu_get_buffer_state(src_buf) == VPU_BUF_STATE_IDLE) 251 + return NULL; 252 + } 253 + 254 + return src_buf; 255 + } 256 + 257 + void vpu_skip_frame(struct vpu_inst *inst, int count) 258 + { 259 + struct vb2_v4l2_buffer *src_buf; 260 + enum vb2_buffer_state state; 261 + int i = 0; 262 + 263 + if (count <= 0) 264 + return; 265 + 266 + while (i < count) { 267 + src_buf = v4l2_m2m_src_buf_remove(inst->fh.m2m_ctx); 268 + if (!src_buf || vpu_get_buffer_state(src_buf) == VPU_BUF_STATE_IDLE) 269 + return; 270 + if (vpu_get_buffer_state(src_buf) == VPU_BUF_STATE_DECODED) 271 + state = VB2_BUF_STATE_DONE; 272 + else 273 + state = VB2_BUF_STATE_ERROR; 274 + i++; 275 + vpu_set_buffer_state(src_buf, VPU_BUF_STATE_IDLE); 276 + v4l2_m2m_buf_done(src_buf, state); 277 + } 248 278 } 249 279 250 280 struct vb2_v4l2_buffer *vpu_find_buf_by_sequence(struct vpu_inst *inst, u32 type, u32 sequence) ··· 398 342 return 0; 399 343 } 400 344 345 + if (V4L2_TYPE_IS_OUTPUT(vq->type)) 346 + *buf_count = max_t(unsigned int, *buf_count, inst->min_buffer_out); 347 + else 348 + *buf_count = max_t(unsigned int, *buf_count, inst->min_buffer_cap); 401 349 *plane_count = cur_fmt->num_planes; 402 350 for (i = 0; i < cur_fmt->num_planes; i++) 403 351 psize[i] = cur_fmt->sizeimage[i];

+3

drivers/media/platform/amphion/vpu_v4l2.h

··· 19 19 const struct vpu_format *vpu_try_fmt_common(struct vpu_inst *inst, struct v4l2_format *f); 20 20 int vpu_process_output_buffer(struct vpu_inst *inst); 21 21 int vpu_process_capture_buffer(struct vpu_inst *inst); 22 + struct vb2_v4l2_buffer *vpu_next_src_buf(struct vpu_inst *inst); 23 + void vpu_skip_frame(struct vpu_inst *inst, int count); 22 24 struct vb2_v4l2_buffer *vpu_find_buf_by_sequence(struct vpu_inst *inst, u32 type, u32 sequence); 23 25 struct vb2_v4l2_buffer *vpu_find_buf_by_idx(struct vpu_inst *inst, u32 type, u32 idx); 24 26 void vpu_v4l2_set_error(struct vpu_inst *inst); ··· 29 27 int vpu_set_last_buffer_dequeued(struct vpu_inst *inst); 30 28 void vpu_vb2_buffers_return(struct vpu_inst *inst, unsigned int type, enum vb2_buffer_state state); 31 29 int vpu_get_num_buffers(struct vpu_inst *inst, u32 type); 30 + bool vpu_is_source_empty(struct vpu_inst *inst); 32 31 33 32 dma_addr_t vpu_get_vb_phy_addr(struct vb2_buffer *vb, u32 plane_no); 34 33 unsigned int vpu_get_vb_length(struct vb2_buffer *vb, u32 plane_no);

+2 -2

drivers/media/platform/aspeed/aspeed-video.c

··· 1993 1993 1994 1994 rc = aspeed_video_setup_video(video); 1995 1995 if (rc) { 1996 + aspeed_video_free_buf(video, &video->jpeg); 1996 1997 clk_unprepare(video->vclk); 1997 1998 clk_unprepare(video->eclk); 1998 1999 return rc; ··· 2025 2024 2026 2025 v4l2_device_unregister(v4l2_dev); 2027 2026 2028 - dma_free_coherent(video->dev, VE_JPEG_HEADER_SIZE, video->jpeg.virt, 2029 - video->jpeg.dma); 2027 + aspeed_video_free_buf(video, &video->jpeg); 2030 2028 2031 2029 of_reserved_mem_device_release(dev); 2032 2030

+28 -6

drivers/media/platform/atmel/atmel-isc-base.c

··· 401 401 struct isc_buffer *buf; 402 402 int ret; 403 403 404 + mutex_lock(&isc->awb_mutex); 404 405 v4l2_ctrl_activate(isc->do_wb_ctrl, false); 405 406 406 407 isc->stop = true; ··· 410 409 if (isc->cur_frm && !wait_for_completion_timeout(&isc->comp, 5 * HZ)) 411 410 v4l2_err(&isc->v4l2_dev, 412 411 "Timeout waiting for end of the capture\n"); 412 + 413 + mutex_unlock(&isc->awb_mutex); 413 414 414 415 /* Disable DMA interrupt */ 415 416 regmap_write(isc->regmap, ISC_INTDIS, ISC_INT_DDONE); ··· 445 442 446 443 spin_lock_irqsave(&isc->dma_queue_lock, flags); 447 444 if (!isc->cur_frm && list_empty(&isc->dma_queue) && 448 - vb2_is_streaming(vb->vb2_queue)) { 445 + vb2_start_streaming_called(vb->vb2_queue)) { 449 446 isc->cur_frm = buf; 450 447 isc_start_dma(isc); 451 448 } else ··· 1032 1029 { 1033 1030 struct isc_device *isc = video_drvdata(file); 1034 1031 1035 - if (vb2_is_streaming(&isc->vb2_vidq)) 1032 + if (vb2_is_busy(&isc->vb2_vidq)) 1036 1033 return -EBUSY; 1037 1034 1038 1035 return isc_set_fmt(isc, f); ··· 1400 1397 u32 min, max; 1401 1398 int ret; 1402 1399 1403 - /* streaming is not active anymore */ 1404 - if (isc->stop) 1405 - return; 1406 - 1407 1400 if (ctrls->hist_stat != HIST_ENABLED) 1408 1401 return; 1409 1402 ··· 1454 1455 } 1455 1456 regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his, 1456 1457 hist_id | baysel | ISC_HIS_CFG_RAR); 1458 + 1459 + /* 1460 + * We have to make sure the streaming has not stopped meanwhile. 1461 + * ISC requires a frame to clock the internal profile update. 1462 + * To avoid issues, lock the sequence with a mutex 1463 + */ 1464 + mutex_lock(&isc->awb_mutex); 1465 + 1466 + /* streaming is not active anymore */ 1467 + if (isc->stop) { 1468 + mutex_unlock(&isc->awb_mutex); 1469 + return; 1470 + }; 1471 + 1457 1472 isc_update_profile(isc); 1473 + 1474 + mutex_unlock(&isc->awb_mutex); 1475 + 1458 1476 /* if awb has been disabled, we don't need to start another histogram */ 1459 1477 if (ctrls->awb) 1460 1478 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ); ··· 1550 1534 1551 1535 isc_update_awb_ctrls(isc); 1552 1536 1537 + mutex_lock(&isc->awb_mutex); 1553 1538 if (vb2_is_streaming(&isc->vb2_vidq)) { 1554 1539 /* 1555 1540 * If we are streaming, we can update profile to ··· 1565 1548 */ 1566 1549 v4l2_ctrl_activate(isc->do_wb_ctrl, false); 1567 1550 } 1551 + mutex_unlock(&isc->awb_mutex); 1568 1552 1569 1553 /* if we have autowhitebalance on, start histogram procedure */ 1570 1554 if (ctrls->awb == ISC_WB_AUTO && ··· 1747 1729 { 1748 1730 struct isc_device *isc = container_of(notifier->v4l2_dev, 1749 1731 struct isc_device, v4l2_dev); 1732 + mutex_destroy(&isc->awb_mutex); 1750 1733 cancel_work_sync(&isc->awb_work); 1751 1734 video_unregister_device(&isc->video_dev); 1752 1735 v4l2_ctrl_handler_free(&isc->ctrls.handler); ··· 1857 1838 isc->current_subdev = container_of(notifier, 1858 1839 struct isc_subdev_entity, notifier); 1859 1840 mutex_init(&isc->lock); 1841 + mutex_init(&isc->awb_mutex); 1842 + 1860 1843 init_completion(&isc->comp); 1861 1844 1862 1845 /* Initialize videobuf2 queue */ ··· 1927 1906 return 0; 1928 1907 1929 1908 isc_async_complete_err: 1909 + mutex_destroy(&isc->awb_mutex); 1930 1910 mutex_destroy(&isc->lock); 1931 1911 return ret; 1932 1912 }

+5 -3

drivers/media/platform/atmel/atmel-isc.h

··· 218 218 * 219 219 * @lock: lock for serializing userspace file operations 220 220 * with ISC operations 221 + * @awb_mutex: serialize access to streaming status from awb work queue 221 222 * @awb_lock: lock for serializing awb work queue operations 222 223 * with DMA/buffer operations 223 224 * ··· 273 272 struct video_device video_dev; 274 273 275 274 struct vb2_queue vb2_vidq; 276 - spinlock_t dma_queue_lock; /* serialize access to dma queue */ 275 + spinlock_t dma_queue_lock; 277 276 struct list_head dma_queue; 278 277 struct isc_buffer *cur_frm; 279 278 unsigned int sequence; ··· 290 289 struct isc_ctrls ctrls; 291 290 struct work_struct awb_work; 292 291 293 - struct mutex lock; /* serialize access to file operations */ 294 - spinlock_t awb_lock; /* serialize access to DMA buffers from awb work queue */ 292 + struct mutex lock; 293 + struct mutex awb_mutex; 294 + spinlock_t awb_lock; 295 295 296 296 struct regmap_field *pipeline[ISC_PIPE_LINE_NODE_NUM]; 297 297

+22 -36

drivers/media/platform/atmel/atmel-sama5d2-isc.c

··· 60 60 static const struct isc_format sama5d2_controller_formats[] = { 61 61 { 62 62 .fourcc = V4L2_PIX_FMT_ARGB444, 63 - }, 64 - { 63 + }, { 65 64 .fourcc = V4L2_PIX_FMT_ARGB555, 66 - }, 67 - { 65 + }, { 68 66 .fourcc = V4L2_PIX_FMT_RGB565, 69 - }, 70 - { 67 + }, { 71 68 .fourcc = V4L2_PIX_FMT_ABGR32, 72 - }, 73 - { 69 + }, { 74 70 .fourcc = V4L2_PIX_FMT_XBGR32, 75 - }, 76 - { 71 + }, { 77 72 .fourcc = V4L2_PIX_FMT_YUV420, 78 - }, 79 - { 73 + }, { 80 74 .fourcc = V4L2_PIX_FMT_YUYV, 81 - }, 82 - { 75 + }, { 83 76 .fourcc = V4L2_PIX_FMT_YUV422P, 84 - }, 85 - { 77 + }, { 86 78 .fourcc = V4L2_PIX_FMT_GREY, 87 - }, 88 - { 79 + }, { 89 80 .fourcc = V4L2_PIX_FMT_Y10, 90 - }, 91 - { 81 + }, { 92 82 .fourcc = V4L2_PIX_FMT_SBGGR8, 93 - }, 94 - { 83 + }, { 95 84 .fourcc = V4L2_PIX_FMT_SGBRG8, 96 - }, 97 - { 85 + }, { 98 86 .fourcc = V4L2_PIX_FMT_SGRBG8, 99 - }, 100 - { 87 + }, { 101 88 .fourcc = V4L2_PIX_FMT_SRGGB8, 102 - }, 103 - { 89 + }, { 104 90 .fourcc = V4L2_PIX_FMT_SBGGR10, 105 - }, 106 - { 91 + }, { 107 92 .fourcc = V4L2_PIX_FMT_SGBRG10, 108 - }, 109 - { 93 + }, { 110 94 .fourcc = V4L2_PIX_FMT_SGRBG10, 111 - }, 112 - { 95 + }, { 113 96 .fourcc = V4L2_PIX_FMT_SRGGB10, 114 97 }, 115 98 }; ··· 274 291 * Thus, if the YCYC mode is selected, replace it with the 275 292 * sama5d2-compliant mode which is YYCC . 276 293 */ 277 - if ((rlp_mode & ISC_RLP_CFG_MODE_YCYC) == ISC_RLP_CFG_MODE_YCYC) { 294 + if ((rlp_mode & ISC_RLP_CFG_MODE_MASK) == ISC_RLP_CFG_MODE_YCYC) { 278 295 rlp_mode &= ~ISC_RLP_CFG_MODE_MASK; 279 296 rlp_mode |= ISC_RLP_CFG_MODE_YYCC; 280 297 } ··· 545 562 ret = clk_prepare_enable(isc->ispck); 546 563 if (ret) { 547 564 dev_err(dev, "failed to enable ispck: %d\n", ret); 548 - goto cleanup_subdev; 565 + goto disable_pm; 549 566 } 550 567 551 568 /* ispck should be greater or equal to hclock */ ··· 562 579 563 580 unprepare_clk: 564 581 clk_disable_unprepare(isc->ispck); 582 + 583 + disable_pm: 584 + pm_runtime_disable(dev); 565 585 566 586 cleanup_subdev: 567 587 isc_subdev_cleanup(isc);

+20 -41

drivers/media/platform/atmel/atmel-sama7g5-isc.c

··· 63 63 static const struct isc_format sama7g5_controller_formats[] = { 64 64 { 65 65 .fourcc = V4L2_PIX_FMT_ARGB444, 66 - }, 67 - { 66 + }, { 68 67 .fourcc = V4L2_PIX_FMT_ARGB555, 69 - }, 70 - { 68 + }, { 71 69 .fourcc = V4L2_PIX_FMT_RGB565, 72 - }, 73 - { 70 + }, { 74 71 .fourcc = V4L2_PIX_FMT_ABGR32, 75 - }, 76 - { 72 + }, { 77 73 .fourcc = V4L2_PIX_FMT_XBGR32, 78 - }, 79 - { 74 + }, { 80 75 .fourcc = V4L2_PIX_FMT_YUV420, 81 - }, 82 - { 76 + }, { 83 77 .fourcc = V4L2_PIX_FMT_UYVY, 84 - }, 85 - { 78 + }, { 86 79 .fourcc = V4L2_PIX_FMT_VYUY, 87 - }, 88 - { 80 + }, { 89 81 .fourcc = V4L2_PIX_FMT_YUYV, 90 - }, 91 - { 82 + }, { 92 83 .fourcc = V4L2_PIX_FMT_YUV422P, 93 - }, 94 - { 84 + }, { 95 85 .fourcc = V4L2_PIX_FMT_GREY, 96 - }, 97 - { 86 + }, { 98 87 .fourcc = V4L2_PIX_FMT_Y10, 99 - }, 100 - { 88 + }, { 101 89 .fourcc = V4L2_PIX_FMT_Y16, 102 - }, 103 - { 90 + }, { 104 91 .fourcc = V4L2_PIX_FMT_SBGGR8, 105 - }, 106 - { 92 + }, { 107 93 .fourcc = V4L2_PIX_FMT_SGBRG8, 108 - }, 109 - { 94 + }, { 110 95 .fourcc = V4L2_PIX_FMT_SGRBG8, 111 - }, 112 - { 96 + }, { 113 97 .fourcc = V4L2_PIX_FMT_SRGGB8, 114 - }, 115 - { 98 + }, { 116 99 .fourcc = V4L2_PIX_FMT_SBGGR10, 117 - }, 118 - { 100 + }, { 119 101 .fourcc = V4L2_PIX_FMT_SGBRG10, 120 - }, 121 - { 102 + }, { 122 103 .fourcc = V4L2_PIX_FMT_SGRBG10, 123 - }, 124 - { 104 + }, { 125 105 .fourcc = V4L2_PIX_FMT_SRGGB10, 126 106 }, 127 107 }; ··· 205 225 .mbus_code = MEDIA_BUS_FMT_Y10_1X10, 206 226 .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, 207 227 }, 208 - 209 228 }; 210 229 211 230 static void isc_sama7g5_config_csc(struct isc_device *isc)

+5

drivers/media/platform/atmel/microchip-csi2dc.c

··· 454 454 return 0; 455 455 } 456 456 457 + static const struct media_entity_operations csi2dc_entity_ops = { 458 + .link_validate = v4l2_subdev_link_validate, 459 + }; 460 + 457 461 static const struct v4l2_subdev_pad_ops csi2dc_pad_ops = { 458 462 .enum_mbus_code = csi2dc_enum_mbus_code, 459 463 .set_fmt = csi2dc_set_fmt, ··· 687 683 688 684 csi2dc->csi2dc_sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 689 685 csi2dc->csi2dc_sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 686 + csi2dc->csi2dc_sd.entity.ops = &csi2dc_entity_ops; 690 687 691 688 platform_set_drvdata(pdev, csi2dc); 692 689

+3 -2

drivers/media/platform/cadence/cdns-csi2tx.c

··· 15 15 #include <linux/platform_device.h> 16 16 #include <linux/slab.h> 17 17 18 + #include <media/mipi-csi2.h> 18 19 #include <media/v4l2-ctrls.h> 19 20 #include <media/v4l2-device.h> 20 21 #include <media/v4l2-fwnode.h> ··· 122 121 { 123 122 .mbus = MEDIA_BUS_FMT_UYVY8_1X16, 124 123 .bpp = 2, 125 - .dt = 0x1e, 124 + .dt = MIPI_CSI2_DT_YUV422_8B, 126 125 }, 127 126 { 128 127 .mbus = MEDIA_BUS_FMT_RGB888_1X24, 129 128 .bpp = 3, 130 - .dt = 0x24, 129 + .dt = MIPI_CSI2_DT_RGB888, 131 130 }, 132 131 }; 133 132

+2 -2

drivers/media/platform/chips-media/coda-bit.c

··· 326 326 struct coda_buffer_meta *meta; 327 327 u32 start; 328 328 329 + lockdep_assert_held(&ctx->bitstream_mutex); 330 + 329 331 if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG) 330 332 return; 331 333 ··· 2176 2174 (!(ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG))) { 2177 2175 coda_dbg(1, ctx, "bitstream payload: %d, skipping\n", 2178 2176 coda_get_bitstream_payload(ctx)); 2179 - v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx); 2180 2177 return -EAGAIN; 2181 2178 } 2182 2179 ··· 2185 2184 2186 2185 if (ret < 0) { 2187 2186 v4l2_err(&dev->v4l2_dev, "failed to start decoding\n"); 2188 - v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx); 2189 2187 return -EAGAIN; 2190 2188 } else { 2191 2189 ctx->initialized = 1;

+88 -67

drivers/media/platform/chips-media/coda-common.c

··· 657 657 const struct coda_q_data *q_data_src; 658 658 const struct coda_codec *codec; 659 659 struct vb2_queue *src_vq; 660 + int hscale = 0; 661 + int vscale = 0; 660 662 int ret; 661 663 bool use_vdoa; 662 664 ··· 675 673 */ 676 674 src_vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT); 677 675 if (vb2_is_streaming(src_vq)) { 678 - f->fmt.pix.width = q_data_src->width; 679 - f->fmt.pix.height = q_data_src->height; 676 + if (q_data_src->fourcc == V4L2_PIX_FMT_JPEG && 677 + ctx->dev->devtype->product == CODA_960) { 678 + hscale = coda_jpeg_scale(q_data_src->width, f->fmt.pix.width); 679 + vscale = coda_jpeg_scale(q_data_src->height, f->fmt.pix.height); 680 + } 681 + f->fmt.pix.width = q_data_src->width >> hscale; 682 + f->fmt.pix.height = q_data_src->height >> vscale; 680 683 681 684 if (q_data_src->fourcc == V4L2_PIX_FMT_JPEG) { 682 685 if (ctx->params.jpeg_chroma_subsampling == ··· 711 704 712 705 /* The decoders always write complete macroblocks or MCUs */ 713 706 if (ctx->inst_type == CODA_INST_DECODER) { 714 - f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 16); 715 - f->fmt.pix.height = round_up(f->fmt.pix.height, 16); 707 + f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 16 >> hscale); 708 + f->fmt.pix.height = round_up(f->fmt.pix.height, 16 >> vscale); 716 709 if (codec->src_fourcc == V4L2_PIX_FMT_JPEG && 717 710 f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUV422P) { 718 711 f->fmt.pix.sizeimage = f->fmt.pix.bytesperline * ··· 857 850 struct coda_q_data *q_data_src; 858 851 const struct coda_codec *codec; 859 852 struct v4l2_rect r; 853 + int hscale = 0; 854 + int vscale = 0; 860 855 int ret; 856 + 857 + q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT); 858 + 859 + if (q_data_src->fourcc == V4L2_PIX_FMT_JPEG && 860 + ctx->dev->devtype->product == CODA_960) { 861 + hscale = coda_jpeg_scale(q_data_src->width, f->fmt.pix.width); 862 + vscale = coda_jpeg_scale(q_data_src->height, f->fmt.pix.height); 863 + } 861 864 862 865 ret = coda_try_fmt_vid_cap(file, priv, f); 863 866 if (ret) 864 867 return ret; 865 868 866 - q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT); 867 869 r.left = 0; 868 870 r.top = 0; 869 - r.width = q_data_src->width; 870 - r.height = q_data_src->height; 871 + r.width = q_data_src->width >> hscale; 872 + r.height = q_data_src->height >> vscale; 871 873 872 874 ret = coda_s_fmt(ctx, f, &r); 873 875 if (ret) ··· 1107 1091 } 1108 1092 } 1109 1093 1110 - static int coda_try_encoder_cmd(struct file *file, void *fh, 1111 - struct v4l2_encoder_cmd *ec) 1112 - { 1113 - struct coda_ctx *ctx = fh_to_ctx(fh); 1114 - 1115 - if (ctx->inst_type != CODA_INST_ENCODER) 1116 - return -ENOTTY; 1117 - 1118 - return v4l2_m2m_ioctl_try_encoder_cmd(file, fh, ec); 1119 - } 1120 - 1121 1094 static void coda_wake_up_capture_queue(struct coda_ctx *ctx) 1122 1095 { 1123 1096 struct vb2_queue *dst_vq; ··· 1125 1120 struct vb2_v4l2_buffer *buf; 1126 1121 int ret; 1127 1122 1128 - ret = coda_try_encoder_cmd(file, fh, ec); 1123 + ret = v4l2_m2m_ioctl_try_encoder_cmd(file, fh, ec); 1129 1124 if (ret < 0) 1130 1125 return ret; 1131 1126 ··· 1152 1147 mutex_unlock(&ctx->wakeup_mutex); 1153 1148 1154 1149 return 0; 1155 - } 1156 - 1157 - static int coda_try_decoder_cmd(struct file *file, void *fh, 1158 - struct v4l2_decoder_cmd *dc) 1159 - { 1160 - struct coda_ctx *ctx = fh_to_ctx(fh); 1161 - 1162 - if (ctx->inst_type != CODA_INST_DECODER) 1163 - return -ENOTTY; 1164 - 1165 - return v4l2_m2m_ioctl_try_decoder_cmd(file, fh, dc); 1166 1150 } 1167 1151 1168 1152 static bool coda_mark_last_meta(struct coda_ctx *ctx) ··· 1210 1216 bool wakeup; 1211 1217 int ret; 1212 1218 1213 - ret = coda_try_decoder_cmd(file, fh, dc); 1219 + ret = v4l2_m2m_ioctl_try_decoder_cmd(file, fh, dc); 1214 1220 if (ret < 0) 1215 1221 return ret; 1216 1222 ··· 1285 1291 struct coda_q_data *q_data_dst; 1286 1292 const struct coda_codec *codec; 1287 1293 1288 - if (ctx->inst_type != CODA_INST_ENCODER) 1289 - return -ENOTTY; 1290 - 1291 1294 if (fsize->index) 1292 1295 return -EINVAL; 1293 1296 ··· 1315 1324 struct v4l2_frmivalenum *f) 1316 1325 { 1317 1326 struct coda_ctx *ctx = fh_to_ctx(fh); 1318 - int i; 1327 + struct coda_q_data *q_data; 1328 + const struct coda_codec *codec; 1319 1329 1320 1330 if (f->index) 1321 1331 return -EINVAL; ··· 1325 1333 if (!ctx->vdoa && f->pixel_format == V4L2_PIX_FMT_YUYV) 1326 1334 return -EINVAL; 1327 1335 1328 - for (i = 0; i < CODA_MAX_FORMATS; i++) { 1329 - if (f->pixel_format == ctx->cvd->src_formats[i] || 1330 - f->pixel_format == ctx->cvd->dst_formats[i]) 1331 - break; 1336 + if (coda_format_normalize_yuv(f->pixel_format) == V4L2_PIX_FMT_YUV420) { 1337 + q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE); 1338 + codec = coda_find_codec(ctx->dev, f->pixel_format, 1339 + q_data->fourcc); 1340 + } else { 1341 + codec = coda_find_codec(ctx->dev, V4L2_PIX_FMT_YUV420, 1342 + f->pixel_format); 1332 1343 } 1333 - if (i == CODA_MAX_FORMATS) 1344 + if (!codec) 1345 + return -EINVAL; 1346 + 1347 + if (f->width < MIN_W || f->width > codec->max_w || 1348 + f->height < MIN_H || f->height > codec->max_h) 1334 1349 return -EINVAL; 1335 1350 1336 1351 f->type = V4L2_FRMIVAL_TYPE_CONTINUOUS; ··· 1497 1498 .vidioc_g_selection = coda_g_selection, 1498 1499 .vidioc_s_selection = coda_s_selection, 1499 1500 1500 - .vidioc_try_encoder_cmd = coda_try_encoder_cmd, 1501 + .vidioc_try_encoder_cmd = v4l2_m2m_ioctl_try_encoder_cmd, 1501 1502 .vidioc_encoder_cmd = coda_encoder_cmd, 1502 - .vidioc_try_decoder_cmd = coda_try_decoder_cmd, 1503 + .vidioc_try_decoder_cmd = v4l2_m2m_ioctl_try_decoder_cmd, 1503 1504 .vidioc_decoder_cmd = coda_decoder_cmd, 1504 1505 1505 1506 .vidioc_g_parm = coda_g_parm, ··· 1534 1535 mutex_lock(&dev->coda_mutex); 1535 1536 1536 1537 ret = ctx->ops->prepare_run(ctx); 1537 - if (ret < 0 && ctx->inst_type == CODA_INST_DECODER) { 1538 - mutex_unlock(&dev->coda_mutex); 1539 - mutex_unlock(&ctx->buffer_mutex); 1540 - /* job_finish scheduled by prepare_decode */ 1541 - return; 1542 - } 1538 + if (ret < 0 && ctx->inst_type == CODA_INST_DECODER) 1539 + goto out; 1543 1540 1544 1541 if (!wait_for_completion_timeout(&ctx->completion, 1545 1542 msecs_to_jiffies(1000))) { ··· 1557 1562 ctx->ops->seq_end_work) 1558 1563 queue_work(dev->workqueue, &ctx->seq_end_work); 1559 1564 1565 + out: 1560 1566 mutex_unlock(&dev->coda_mutex); 1561 1567 mutex_unlock(&ctx->buffer_mutex); 1562 1568 ··· 1661 1665 csize = coda_estimate_sizeimage(ctx, usize, max_w, max_h); 1662 1666 1663 1667 ctx->params.codec_mode = ctx->codec->mode; 1664 - if (ctx->cvd->src_formats[0] == V4L2_PIX_FMT_JPEG) 1665 - ctx->colorspace = V4L2_COLORSPACE_JPEG; 1666 - else 1668 + if (ctx->cvd->src_formats[0] == V4L2_PIX_FMT_JPEG || 1669 + ctx->cvd->dst_formats[0] == V4L2_PIX_FMT_JPEG) { 1670 + ctx->colorspace = V4L2_COLORSPACE_SRGB; 1671 + ctx->xfer_func = V4L2_XFER_FUNC_SRGB; 1672 + ctx->ycbcr_enc = V4L2_YCBCR_ENC_601; 1673 + ctx->quantization = V4L2_QUANTIZATION_FULL_RANGE; 1674 + } else { 1667 1675 ctx->colorspace = V4L2_COLORSPACE_REC709; 1668 - ctx->xfer_func = V4L2_XFER_FUNC_DEFAULT; 1669 - ctx->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 1670 - ctx->quantization = V4L2_QUANTIZATION_DEFAULT; 1676 + ctx->xfer_func = V4L2_XFER_FUNC_DEFAULT; 1677 + ctx->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 1678 + ctx->quantization = V4L2_QUANTIZATION_DEFAULT; 1679 + } 1671 1680 ctx->params.framerate = 30; 1672 1681 1673 1682 /* Default formats for output and input queues */ ··· 2012 2011 */ 2013 2012 if (q_data_src->fourcc == V4L2_PIX_FMT_JPEG) { 2014 2013 buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); 2015 - ret = coda_jpeg_decode_header(ctx, &buf->vb2_buf); 2016 - if (ret < 0) { 2017 - v4l2_err(v4l2_dev, 2018 - "failed to decode JPEG header: %d\n", 2019 - ret); 2020 - goto err; 2021 - } 2014 + coda_jpeg_decode_header(ctx, &buf->vb2_buf); 2015 + /* 2016 + * We have to start streaming even if the first buffer 2017 + * does not contain a valid JPEG image. The error will 2018 + * be caught during device run and will be signalled 2019 + * via the capture buffer error flag. 2020 + */ 2022 2021 2023 2022 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE); 2024 2023 q_data_dst->width = round_up(q_data_src->width, 16); ··· 2345 2344 V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET, -12, 12, 1, 0); 2346 2345 v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops, 2347 2346 V4L2_CID_MPEG_VIDEO_H264_PROFILE, 2348 - V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, 0x0, 2349 - V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE); 2347 + V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE, 0x0, 2348 + V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE); 2350 2349 if (ctx->dev->devtype->product == CODA_HX4 || 2351 2350 ctx->dev->devtype->product == CODA_7541) { 2352 2351 v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops, ··· 2360 2359 if (ctx->dev->devtype->product == CODA_960) { 2361 2360 v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops, 2362 2361 V4L2_CID_MPEG_VIDEO_H264_LEVEL, 2363 - V4L2_MPEG_VIDEO_H264_LEVEL_4_0, 2364 - ~((1 << V4L2_MPEG_VIDEO_H264_LEVEL_2_0) | 2362 + V4L2_MPEG_VIDEO_H264_LEVEL_4_2, 2363 + ~((1 << V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | 2364 + (1 << V4L2_MPEG_VIDEO_H264_LEVEL_2_0) | 2365 2365 (1 << V4L2_MPEG_VIDEO_H264_LEVEL_3_0) | 2366 2366 (1 << V4L2_MPEG_VIDEO_H264_LEVEL_3_1) | 2367 2367 (1 << V4L2_MPEG_VIDEO_H264_LEVEL_3_2) | 2368 - (1 << V4L2_MPEG_VIDEO_H264_LEVEL_4_0)), 2368 + (1 << V4L2_MPEG_VIDEO_H264_LEVEL_4_0) | 2369 + (1 << V4L2_MPEG_VIDEO_H264_LEVEL_4_1) | 2370 + (1 << V4L2_MPEG_VIDEO_H264_LEVEL_4_2)), 2369 2371 V4L2_MPEG_VIDEO_H264_LEVEL_4_0); 2370 2372 } 2371 2373 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops, ··· 2430 2426 ctx->h264_profile_ctrl = v4l2_ctrl_new_std_menu(&ctx->ctrls, 2431 2427 &coda_ctrl_ops, V4L2_CID_MPEG_VIDEO_H264_PROFILE, 2432 2428 V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, 2433 - ~((1 << V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) | 2429 + ~((1 << V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) | 2434 2430 (1 << V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) | 2435 2431 (1 << V4L2_MPEG_VIDEO_H264_PROFILE_HIGH)), 2436 2432 V4L2_MPEG_VIDEO_H264_PROFILE_HIGH); ··· 2904 2900 v4l2_disable_ioctl(vfd, VIDIOC_CROPCAP); 2905 2901 v4l2_disable_ioctl(vfd, VIDIOC_G_CROP); 2906 2902 v4l2_disable_ioctl(vfd, VIDIOC_S_CROP); 2903 + 2904 + if (dev->devtype->vdevs[i]->type == CODA_INST_ENCODER) { 2905 + v4l2_disable_ioctl(vfd, VIDIOC_DECODER_CMD); 2906 + v4l2_disable_ioctl(vfd, VIDIOC_TRY_DECODER_CMD); 2907 + if (dev->devtype->vdevs[i]->dst_formats[0] == V4L2_PIX_FMT_JPEG) { 2908 + v4l2_disable_ioctl(vfd, VIDIOC_ENUM_FRAMEINTERVALS); 2909 + v4l2_disable_ioctl(vfd, VIDIOC_G_PARM); 2910 + v4l2_disable_ioctl(vfd, VIDIOC_S_PARM); 2911 + } 2912 + } else { 2913 + v4l2_disable_ioctl(vfd, VIDIOC_ENCODER_CMD); 2914 + v4l2_disable_ioctl(vfd, VIDIOC_TRY_ENCODER_CMD); 2915 + v4l2_disable_ioctl(vfd, VIDIOC_ENUM_FRAMESIZES); 2916 + v4l2_disable_ioctl(vfd, VIDIOC_ENUM_FRAMEINTERVALS); 2917 + v4l2_disable_ioctl(vfd, VIDIOC_G_PARM); 2918 + v4l2_disable_ioctl(vfd, VIDIOC_S_PARM); 2919 + } 2907 2920 2908 2921 ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0); 2909 2922 if (!ret)

+13 -11

drivers/media/platform/chips-media/coda-jpeg.c

··· 283 283 284 284 ret = v4l2_jpeg_parse_header(buf, len, &header); 285 285 if (ret < 0) { 286 - v4l2_err(&dev->v4l2_dev, "failed to parse header\n"); 286 + v4l2_err(&dev->v4l2_dev, "failed to parse JPEG header: %pe\n", 287 + ERR_PTR(ret)); 287 288 return ret; 288 289 } 289 290 ··· 1329 1328 struct coda_q_data *q_data_src, *q_data_dst; 1330 1329 struct vb2_v4l2_buffer *src_buf, *dst_buf; 1331 1330 int chroma_interleave; 1331 + int scl_hor_mode, scl_ver_mode; 1332 1332 1333 1333 src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); 1334 1334 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); ··· 1337 1335 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE); 1338 1336 dst_fourcc = q_data_dst->fourcc; 1339 1337 1338 + scl_hor_mode = coda_jpeg_scale(q_data_src->width, q_data_dst->width); 1339 + scl_ver_mode = coda_jpeg_scale(q_data_src->height, q_data_dst->height); 1340 + 1340 1341 if (vb2_get_plane_payload(&src_buf->vb2_buf, 0) == 0) 1341 1342 vb2_set_plane_payload(&src_buf->vb2_buf, 0, 1342 1343 vb2_plane_size(&src_buf->vb2_buf, 0)); 1343 1344 1344 1345 chroma_format = coda9_jpeg_chroma_format(q_data_dst->fourcc); 1345 - if (chroma_format < 0) { 1346 - v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx); 1346 + if (chroma_format < 0) 1347 1347 return chroma_format; 1348 - } 1349 1348 1350 1349 ret = coda_jpeg_decode_header(ctx, &src_buf->vb2_buf); 1351 1350 if (ret < 0) { 1352 - v4l2_err(&dev->v4l2_dev, "failed to decode JPEG header: %d\n", 1353 - ret); 1354 - 1355 1351 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); 1356 1352 dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); 1357 1353 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE); 1358 - v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE); 1354 + v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_ERROR); 1359 1355 1360 - v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx); 1361 1356 return ret; 1362 1357 } 1363 1358 ··· 1385 1386 coda_write(dev, 0, CODA9_REG_JPEG_ROT_INFO); 1386 1387 coda_write(dev, bus_req_num[chroma_format], CODA9_REG_JPEG_OP_INFO); 1387 1388 coda_write(dev, mcu_info[chroma_format], CODA9_REG_JPEG_MCU_INFO); 1388 - coda_write(dev, 0, CODA9_REG_JPEG_SCL_INFO); 1389 + if (scl_hor_mode || scl_ver_mode) 1390 + val = CODA9_JPEG_SCL_ENABLE | (scl_hor_mode << 2) | scl_ver_mode; 1391 + else 1392 + val = 0; 1393 + coda_write(dev, val, CODA9_REG_JPEG_SCL_INFO); 1389 1394 coda_write(dev, chroma_interleave, CODA9_REG_JPEG_DPB_CONFIG); 1390 1395 coda_write(dev, ctx->params.jpeg_restart_interval, 1391 1396 CODA9_REG_JPEG_RST_INTVAL); ··· 1399 1396 if (ret < 0) { 1400 1397 v4l2_err(&dev->v4l2_dev, 1401 1398 "failed to set up Huffman tables: %d\n", ret); 1402 - v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx); 1403 1399 return ret; 1404 1400 } 1405 1401 }

+7

drivers/media/platform/chips-media/coda.h

··· 380 380 void coda_update_profile_level_ctrls(struct coda_ctx *ctx, u8 profile_idc, 381 381 u8 level_idc); 382 382 383 + static inline int coda_jpeg_scale(int src, int dst) 384 + { 385 + return (dst <= src / 8) ? 3 : 386 + (dst <= src / 4) ? 2 : 387 + (dst <= src / 2) ? 1 : 0; 388 + } 389 + 383 390 bool coda_jpeg_check_buffer(struct coda_ctx *ctx, struct vb2_buffer *vb); 384 391 int coda_jpeg_decode_header(struct coda_ctx *ctx, struct vb2_buffer *vb); 385 392 int coda_jpeg_write_tables(struct coda_ctx *ctx);

-1

drivers/media/platform/marvell/cafe-driver.c

··· 497 497 mcam->plat_power_up = cafe_ctlr_power_up; 498 498 mcam->plat_power_down = cafe_ctlr_power_down; 499 499 mcam->dev = &pdev->dev; 500 - snprintf(mcam->bus_info, sizeof(mcam->bus_info), "PCI:%s", pci_name(pdev)); 501 500 /* 502 501 * Vmalloc mode for buffers is traditional with this driver. 503 502 * We *might* be able to run DMA_contig, especially on a system

-2

drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c

··· 137 137 138 138 strscpy(cap->driver, jpeg->variant->dev_name, sizeof(cap->driver)); 139 139 strscpy(cap->card, jpeg->variant->dev_name, sizeof(cap->card)); 140 - snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", 141 - dev_name(jpeg->dev)); 142 140 143 141 return 0; 144 142 }

+1

drivers/media/platform/mediatek/vcodec/Kconfig

··· 22 22 select VIDEO_MEDIATEK_VCODEC_VPU if VIDEO_MEDIATEK_VPU 23 23 select VIDEO_MEDIATEK_VCODEC_SCP if MTK_SCP 24 24 select V4L2_H264 25 + select V4L2_VP9 25 26 select MEDIA_CONTROLLER 26 27 select MEDIA_CONTROLLER_REQUEST_API 27 28 help

+4

drivers/media/platform/mediatek/vcodec/Makefile

··· 7 7 8 8 mtk-vcodec-dec-y := vdec/vdec_h264_if.o \ 9 9 vdec/vdec_vp8_if.o \ 10 + vdec/vdec_vp8_req_if.o \ 10 11 vdec/vdec_vp9_if.o \ 12 + vdec/vdec_vp9_req_lat_if.o \ 11 13 vdec/vdec_h264_req_if.o \ 14 + vdec/vdec_h264_req_common.o \ 15 + vdec/vdec_h264_req_multi_if.o \ 12 16 mtk_vcodec_dec_drv.o \ 13 17 vdec_drv_if.o \ 14 18 vdec_vpu_if.o \

+38 -37

drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec.c

··· 26 26 const struct mtk_video_fmt *fmt; 27 27 unsigned int k; 28 28 29 - for (k = 0; k < dec_pdata->num_formats; k++) { 29 + for (k = 0; k < *dec_pdata->num_formats; k++) { 30 30 fmt = &dec_pdata->vdec_formats[k]; 31 31 if (fmt->fourcc == f->fmt.pix_mp.pixelformat) 32 32 return fmt; ··· 47 47 static int vidioc_try_decoder_cmd(struct file *file, void *priv, 48 48 struct v4l2_decoder_cmd *cmd) 49 49 { 50 - struct mtk_vcodec_ctx *ctx = fh_to_ctx(priv); 51 - 52 - /* Use M2M stateless helper if relevant */ 53 - if (ctx->dev->vdec_pdata->uses_stateless_api) 54 - return v4l2_m2m_ioctl_stateless_try_decoder_cmd(file, priv, 55 - cmd); 56 - else 57 - return v4l2_m2m_ioctl_try_decoder_cmd(file, priv, cmd); 50 + return v4l2_m2m_ioctl_try_decoder_cmd(file, priv, cmd); 58 51 } 59 52 60 53 ··· 61 68 ret = vidioc_try_decoder_cmd(file, priv, cmd); 62 69 if (ret) 63 70 return ret; 64 - 65 - /* Use M2M stateless helper if relevant */ 66 - if (ctx->dev->vdec_pdata->uses_stateless_api) 67 - return v4l2_m2m_ioctl_stateless_decoder_cmd(file, priv, cmd); 68 71 69 72 mtk_v4l2_debug(1, "decoder cmd=%u", cmd->cmd); 70 73 dst_vq = v4l2_m2m_get_vq(ctx->m2m_ctx, ··· 141 152 q_data->coded_height = DFT_CFG_HEIGHT; 142 153 q_data->fmt = ctx->dev->vdec_pdata->default_cap_fmt; 143 154 q_data->field = V4L2_FIELD_NONE; 155 + ctx->max_width = MTK_VDEC_MAX_W; 156 + ctx->max_height = MTK_VDEC_MAX_H; 144 157 145 158 v4l_bound_align_image(&q_data->coded_width, 146 159 MTK_VDEC_MIN_W, 147 - MTK_VDEC_MAX_W, 4, 160 + ctx->max_width, 4, 148 161 &q_data->coded_height, 149 162 MTK_VDEC_MIN_H, 150 - MTK_VDEC_MAX_H, 5, 6); 163 + ctx->max_height, 5, 6); 151 164 152 165 q_data->sizeimage[0] = q_data->coded_width * q_data->coded_height; 153 166 q_data->bytesperline[0] = q_data->coded_width; ··· 208 217 } 209 218 } 210 219 211 - static int vidioc_try_fmt(struct v4l2_format *f, 220 + static int vidioc_try_fmt(struct mtk_vcodec_ctx *ctx, struct v4l2_format *f, 212 221 const struct mtk_video_fmt *fmt) 213 222 { 214 223 struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp; ··· 216 225 pix_fmt_mp->field = V4L2_FIELD_NONE; 217 226 218 227 pix_fmt_mp->width = 219 - clamp(pix_fmt_mp->width, MTK_VDEC_MIN_W, MTK_VDEC_MAX_W); 228 + clamp(pix_fmt_mp->width, MTK_VDEC_MIN_W, ctx->max_width); 220 229 pix_fmt_mp->height = 221 - clamp(pix_fmt_mp->height, MTK_VDEC_MIN_H, MTK_VDEC_MAX_H); 230 + clamp(pix_fmt_mp->height, MTK_VDEC_MIN_H, ctx->max_height); 222 231 223 232 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { 224 233 pix_fmt_mp->num_planes = 1; ··· 236 245 tmp_h = pix_fmt_mp->height; 237 246 v4l_bound_align_image(&pix_fmt_mp->width, 238 247 MTK_VDEC_MIN_W, 239 - MTK_VDEC_MAX_W, 6, 248 + ctx->max_width, 6, 240 249 &pix_fmt_mp->height, 241 250 MTK_VDEC_MIN_H, 242 - MTK_VDEC_MAX_H, 6, 9); 251 + ctx->max_height, 6, 9); 243 252 244 253 if (pix_fmt_mp->width < tmp_w && 245 - (pix_fmt_mp->width + 64) <= MTK_VDEC_MAX_W) 254 + (pix_fmt_mp->width + 64) <= ctx->max_width) 246 255 pix_fmt_mp->width += 64; 247 256 if (pix_fmt_mp->height < tmp_h && 248 - (pix_fmt_mp->height + 64) <= MTK_VDEC_MAX_H) 257 + (pix_fmt_mp->height + 64) <= ctx->max_height) 249 258 pix_fmt_mp->height += 64; 250 259 251 260 mtk_v4l2_debug(0, ··· 285 294 fmt = mtk_vdec_find_format(f, dec_pdata); 286 295 } 287 296 288 - return vidioc_try_fmt(f, fmt); 297 + return vidioc_try_fmt(ctx, f, fmt); 289 298 } 290 299 291 300 static int vidioc_try_fmt_vid_out_mplane(struct file *file, void *priv, ··· 308 317 return -EINVAL; 309 318 } 310 319 311 - return vidioc_try_fmt(f, fmt); 320 + return vidioc_try_fmt(ctx, f, fmt); 312 321 } 313 322 314 323 static int vidioc_vdec_g_selection(struct file *file, void *priv, ··· 435 444 if (fmt == NULL) 436 445 return -EINVAL; 437 446 447 + if (!(ctx->dev->dec_capability & VCODEC_CAPABILITY_4K_DISABLED) && 448 + fmt->fourcc != V4L2_PIX_FMT_VP8_FRAME) { 449 + mtk_v4l2_debug(3, "4K is enabled"); 450 + ctx->max_width = VCODEC_DEC_4K_CODED_WIDTH; 451 + ctx->max_height = VCODEC_DEC_4K_CODED_HEIGHT; 452 + } 453 + 438 454 q_data->fmt = fmt; 439 - vidioc_try_fmt(f, q_data->fmt); 455 + vidioc_try_fmt(ctx, f, q_data->fmt); 440 456 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { 441 457 q_data->sizeimage[0] = pix_mp->plane_fmt[0].sizeimage; 442 458 q_data->coded_width = pix_mp->width; ··· 464 466 } 465 467 ctx->state = MTK_STATE_INIT; 466 468 } 469 + } else { 470 + ctx->capture_fourcc = fmt->fourcc; 467 471 } 468 472 469 473 /* ··· 476 476 ctx->picinfo.pic_w = pix_mp->width; 477 477 ctx->picinfo.pic_h = pix_mp->height; 478 478 479 + /* 480 + * If get pic info fail, need to use the default pic info params, or 481 + * v4l2-compliance will fail 482 + */ 479 483 ret = vdec_if_get_param(ctx, GET_PARAM_PIC_INFO, &ctx->picinfo); 480 484 if (ret) { 481 485 mtk_v4l2_err("[%d]Error!! Get GET_PARAM_PICTURE_INFO Fail", 482 486 ctx->id); 483 - return -EINVAL; 484 487 } 485 488 486 489 ctx->last_decoded_picinfo = ctx->picinfo; ··· 526 523 if (fsize->index != 0) 527 524 return -EINVAL; 528 525 529 - for (i = 0; i < dec_pdata->num_framesizes; ++i) { 526 + for (i = 0; i < *dec_pdata->num_framesizes; ++i) { 530 527 if (fsize->pixel_format != dec_pdata->vdec_framesizes[i].fourcc) 531 528 continue; 532 529 533 530 fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; 534 531 fsize->stepwise = dec_pdata->vdec_framesizes[i].stepwise; 535 - if (!(ctx->dev->dec_capability & 536 - VCODEC_CAPABILITY_4K_DISABLED)) { 537 - mtk_v4l2_debug(3, "4K is enabled"); 538 - fsize->stepwise.max_width = 539 - VCODEC_DEC_4K_CODED_WIDTH; 540 - fsize->stepwise.max_height = 541 - VCODEC_DEC_4K_CODED_HEIGHT; 542 - } 532 + 533 + fsize->stepwise.max_width = ctx->max_width; 534 + fsize->stepwise.max_height = ctx->max_height; 543 535 mtk_v4l2_debug(1, "%x, %d %d %d %d %d %d", 544 536 ctx->dev->dec_capability, 545 537 fsize->stepwise.min_width, ··· 543 545 fsize->stepwise.min_height, 544 546 fsize->stepwise.max_height, 545 547 fsize->stepwise.step_height); 548 + 546 549 return 0; 547 550 } 548 551 ··· 558 559 const struct mtk_video_fmt *fmt; 559 560 int i, j = 0; 560 561 561 - for (i = 0; i < dec_pdata->num_formats; i++) { 562 + for (i = 0; i < *dec_pdata->num_formats; i++) { 562 563 if (output_queue && 563 564 dec_pdata->vdec_formats[i].type != MTK_FMT_DEC) 564 565 continue; ··· 571 572 ++j; 572 573 } 573 574 574 - if (i == dec_pdata->num_formats) 575 + if (i == *dec_pdata->num_formats) 575 576 return -EINVAL; 576 577 577 578 fmt = &dec_pdata->vdec_formats[i]; ··· 736 737 i, vb2_plane_size(vb, i), 737 738 q_data->sizeimage[i]); 738 739 } 740 + if (!V4L2_TYPE_IS_OUTPUT(vb->type)) 741 + vb2_set_plane_payload(vb, i, q_data->sizeimage[i]); 739 742 } 740 743 741 744 return 0;

+1

drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec.h

··· 69 69 extern const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pdata; 70 70 extern const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata; 71 71 extern const struct mtk_vcodec_dec_pdata mtk_lat_sig_core_pdata; 72 + extern const struct mtk_vcodec_dec_pdata mtk_vdec_single_core_pdata; 72 73 73 74 74 75 /*

+9 -6

drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c

··· 193 193 mtk_vcodec_dec_set_default_params(ctx); 194 194 195 195 if (v4l2_fh_is_singular(&ctx->fh)) { 196 - ret = mtk_vcodec_dec_pw_on(dev, MTK_VDEC_LAT0); 197 - if (ret < 0) 198 - goto err_load_fw; 199 196 /* 200 197 * Does nothing if firmware was already loaded. 201 198 */ ··· 249 252 v4l2_m2m_ctx_release(ctx->m2m_ctx); 250 253 mtk_vcodec_dec_release(ctx); 251 254 252 - if (v4l2_fh_is_singular(&ctx->fh)) 253 - mtk_vcodec_dec_pw_off(dev, MTK_VDEC_LAT0); 254 255 v4l2_fh_del(&ctx->fh); 255 256 v4l2_fh_exit(&ctx->fh); 256 257 v4l2_ctrl_handler_free(&ctx->ctrl_hdl); ··· 395 400 } 396 401 397 402 if (dev->vdec_pdata->uses_stateless_api) { 403 + v4l2_disable_ioctl(vfd_dec, VIDIOC_DECODER_CMD); 404 + v4l2_disable_ioctl(vfd_dec, VIDIOC_TRY_DECODER_CMD); 405 + 398 406 dev->mdev_dec.dev = &pdev->dev; 399 407 strscpy(dev->mdev_dec.model, MTK_VCODEC_DEC_NAME, 400 408 sizeof(dev->mdev_dec.model)); ··· 461 463 .compatible = "mediatek,mt8192-vcodec-dec", 462 464 .data = &mtk_lat_sig_core_pdata, 463 465 }, 466 + { 467 + .compatible = "mediatek,mt8186-vcodec-dec", 468 + .data = &mtk_vdec_single_core_pdata, 469 + }, 464 470 {}, 465 471 }; 466 472 ··· 489 487 video_unregister_device(dev->vfd_dec); 490 488 491 489 v4l2_device_unregister(&dev->v4l2_dev); 492 - pm_runtime_disable(dev->pm.dev); 490 + if (!dev->vdec_pdata->is_subdev_supported) 491 + pm_runtime_disable(dev->pm.dev); 493 492 mtk_vcodec_fw_release(dev->fw_handler); 494 493 return 0; 495 494 }

+110 -64

drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_pm.c

··· 57 57 } 58 58 EXPORT_SYMBOL_GPL(mtk_vcodec_init_dec_clk); 59 59 60 - int mtk_vcodec_dec_pw_on(struct mtk_vcodec_dev *vdec_dev, int hw_idx) 60 + static int mtk_vcodec_dec_pw_on(struct mtk_vcodec_pm *pm) 61 61 { 62 - struct mtk_vdec_hw_dev *subdev_dev; 63 - struct mtk_vcodec_pm *pm; 64 62 int ret; 65 - 66 - if (vdec_dev->vdec_pdata->is_subdev_supported) { 67 - subdev_dev = mtk_vcodec_get_hw_dev(vdec_dev, hw_idx); 68 - if (!subdev_dev) { 69 - mtk_v4l2_err("Failed to get hw dev\n"); 70 - return -EINVAL; 71 - } 72 - pm = &subdev_dev->pm; 73 - } else { 74 - pm = &vdec_dev->pm; 75 - } 76 63 77 64 ret = pm_runtime_resume_and_get(pm->dev); 78 65 if (ret) ··· 67 80 68 81 return ret; 69 82 } 70 - EXPORT_SYMBOL_GPL(mtk_vcodec_dec_pw_on); 71 83 72 - void mtk_vcodec_dec_pw_off(struct mtk_vcodec_dev *vdec_dev, int hw_idx) 84 + static void mtk_vcodec_dec_pw_off(struct mtk_vcodec_pm *pm) 73 85 { 74 - struct mtk_vdec_hw_dev *subdev_dev; 75 - struct mtk_vcodec_pm *pm; 76 86 int ret; 77 - 78 - if (vdec_dev->vdec_pdata->is_subdev_supported) { 79 - subdev_dev = mtk_vcodec_get_hw_dev(vdec_dev, hw_idx); 80 - if (!subdev_dev) { 81 - mtk_v4l2_err("Failed to get hw dev\n"); 82 - return; 83 - } 84 - pm = &subdev_dev->pm; 85 - } else { 86 - pm = &vdec_dev->pm; 87 - } 88 87 89 88 ret = pm_runtime_put_sync(pm->dev); 90 89 if (ret) 91 90 mtk_v4l2_err("pm_runtime_put_sync fail %d", ret); 92 91 } 93 - EXPORT_SYMBOL_GPL(mtk_vcodec_dec_pw_off); 94 92 95 - void mtk_vcodec_dec_clock_on(struct mtk_vcodec_dev *vdec_dev, int hw_idx) 93 + static void mtk_vcodec_dec_clock_on(struct mtk_vcodec_pm *pm) 96 94 { 97 - struct mtk_vdec_hw_dev *subdev_dev; 98 - struct mtk_vcodec_pm *pm; 99 95 struct mtk_vcodec_clk *dec_clk; 100 96 int ret, i; 101 - 102 - if (vdec_dev->vdec_pdata->is_subdev_supported) { 103 - subdev_dev = mtk_vcodec_get_hw_dev(vdec_dev, hw_idx); 104 - if (!subdev_dev) { 105 - mtk_v4l2_err("Failed to get hw dev\n"); 106 - return; 107 - } 108 - pm = &subdev_dev->pm; 109 - enable_irq(subdev_dev->dec_irq); 110 - } else { 111 - pm = &vdec_dev->pm; 112 - enable_irq(vdec_dev->dec_irq); 113 - } 114 97 115 98 dec_clk = &pm->vdec_clk; 116 99 for (i = 0; i < dec_clk->clk_num; i++) { ··· 97 140 for (i -= 1; i >= 0; i--) 98 141 clk_disable_unprepare(dec_clk->clk_info[i].vcodec_clk); 99 142 } 100 - EXPORT_SYMBOL_GPL(mtk_vcodec_dec_clock_on); 101 143 102 - void mtk_vcodec_dec_clock_off(struct mtk_vcodec_dev *vdec_dev, int hw_idx) 144 + static void mtk_vcodec_dec_clock_off(struct mtk_vcodec_pm *pm) 103 145 { 104 - struct mtk_vdec_hw_dev *subdev_dev; 105 - struct mtk_vcodec_pm *pm; 106 146 struct mtk_vcodec_clk *dec_clk; 107 147 int i; 108 - 109 - if (vdec_dev->vdec_pdata->is_subdev_supported) { 110 - subdev_dev = mtk_vcodec_get_hw_dev(vdec_dev, hw_idx); 111 - if (!subdev_dev) { 112 - mtk_v4l2_err("Failed to get hw dev\n"); 113 - return; 114 - } 115 - pm = &subdev_dev->pm; 116 - disable_irq(subdev_dev->dec_irq); 117 - } else { 118 - pm = &vdec_dev->pm; 119 - disable_irq(vdec_dev->dec_irq); 120 - } 121 148 122 149 dec_clk = &pm->vdec_clk; 123 150 for (i = dec_clk->clk_num - 1; i >= 0; i--) 124 151 clk_disable_unprepare(dec_clk->clk_info[i].vcodec_clk); 125 152 } 126 - EXPORT_SYMBOL_GPL(mtk_vcodec_dec_clock_off); 153 + 154 + static void mtk_vcodec_dec_enable_irq(struct mtk_vcodec_dev *vdec_dev, int hw_idx) 155 + { 156 + struct mtk_vdec_hw_dev *subdev_dev; 157 + 158 + if (!test_bit(hw_idx, vdec_dev->subdev_bitmap)) 159 + return; 160 + 161 + if (vdec_dev->vdec_pdata->is_subdev_supported) { 162 + subdev_dev = mtk_vcodec_get_hw_dev(vdec_dev, hw_idx); 163 + if (subdev_dev) 164 + enable_irq(subdev_dev->dec_irq); 165 + else 166 + mtk_v4l2_err("Failed to get hw dev\n"); 167 + } else { 168 + enable_irq(vdec_dev->dec_irq); 169 + } 170 + } 171 + 172 + static void mtk_vcodec_dec_disable_irq(struct mtk_vcodec_dev *vdec_dev, int hw_idx) 173 + { 174 + struct mtk_vdec_hw_dev *subdev_dev; 175 + 176 + if (!test_bit(hw_idx, vdec_dev->subdev_bitmap)) 177 + return; 178 + 179 + if (vdec_dev->vdec_pdata->is_subdev_supported) { 180 + subdev_dev = mtk_vcodec_get_hw_dev(vdec_dev, hw_idx); 181 + if (subdev_dev) 182 + disable_irq(subdev_dev->dec_irq); 183 + else 184 + mtk_v4l2_err("Failed to get hw dev\n"); 185 + } else { 186 + disable_irq(vdec_dev->dec_irq); 187 + } 188 + } 189 + 190 + static struct mtk_vcodec_pm *mtk_vcodec_dec_get_pm(struct mtk_vcodec_dev *vdec_dev, 191 + int hw_idx) 192 + { 193 + struct mtk_vdec_hw_dev *subdev_dev; 194 + 195 + if (!test_bit(hw_idx, vdec_dev->subdev_bitmap)) 196 + return NULL; 197 + 198 + if (vdec_dev->vdec_pdata->is_subdev_supported) { 199 + subdev_dev = mtk_vcodec_get_hw_dev(vdec_dev, hw_idx); 200 + if (subdev_dev) 201 + return &subdev_dev->pm; 202 + 203 + mtk_v4l2_err("Failed to get hw dev\n"); 204 + return NULL; 205 + } 206 + 207 + return &vdec_dev->pm; 208 + } 209 + 210 + static void mtk_vcodec_dec_child_dev_on(struct mtk_vcodec_dev *vdec_dev, 211 + int hw_idx) 212 + { 213 + struct mtk_vcodec_pm *pm; 214 + 215 + pm = mtk_vcodec_dec_get_pm(vdec_dev, hw_idx); 216 + if (pm) { 217 + mtk_vcodec_dec_pw_on(pm); 218 + mtk_vcodec_dec_clock_on(pm); 219 + } 220 + } 221 + 222 + static void mtk_vcodec_dec_child_dev_off(struct mtk_vcodec_dev *vdec_dev, 223 + int hw_idx) 224 + { 225 + struct mtk_vcodec_pm *pm; 226 + 227 + pm = mtk_vcodec_dec_get_pm(vdec_dev, hw_idx); 228 + if (pm) { 229 + mtk_vcodec_dec_clock_off(pm); 230 + mtk_vcodec_dec_pw_off(pm); 231 + } 232 + } 233 + 234 + void mtk_vcodec_dec_enable_hardware(struct mtk_vcodec_ctx *ctx, int hw_idx) 235 + { 236 + mutex_lock(&ctx->dev->dec_mutex[hw_idx]); 237 + 238 + if (IS_VDEC_LAT_ARCH(ctx->dev->vdec_pdata->hw_arch) && 239 + hw_idx == MTK_VDEC_CORE) 240 + mtk_vcodec_dec_child_dev_on(ctx->dev, MTK_VDEC_LAT0); 241 + mtk_vcodec_dec_child_dev_on(ctx->dev, hw_idx); 242 + 243 + mtk_vcodec_dec_enable_irq(ctx->dev, hw_idx); 244 + } 245 + EXPORT_SYMBOL_GPL(mtk_vcodec_dec_enable_hardware); 246 + 247 + void mtk_vcodec_dec_disable_hardware(struct mtk_vcodec_ctx *ctx, int hw_idx) 248 + { 249 + mtk_vcodec_dec_disable_irq(ctx->dev, hw_idx); 250 + 251 + mtk_vcodec_dec_child_dev_off(ctx->dev, hw_idx); 252 + if (IS_VDEC_LAT_ARCH(ctx->dev->vdec_pdata->hw_arch) && 253 + hw_idx == MTK_VDEC_CORE) 254 + mtk_vcodec_dec_child_dev_off(ctx->dev, MTK_VDEC_LAT0); 255 + 256 + mutex_unlock(&ctx->dev->dec_mutex[hw_idx]); 257 + } 258 + EXPORT_SYMBOL_GPL(mtk_vcodec_dec_disable_hardware);

+2 -4

drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_pm.h

··· 11 11 12 12 int mtk_vcodec_init_dec_clk(struct platform_device *pdev, struct mtk_vcodec_pm *pm); 13 13 14 - int mtk_vcodec_dec_pw_on(struct mtk_vcodec_dev *vdec_dev, int hw_idx); 15 - void mtk_vcodec_dec_pw_off(struct mtk_vcodec_dev *vdec_dev, int hw_idx); 16 - void mtk_vcodec_dec_clock_on(struct mtk_vcodec_dev *vdec_dev, int hw_idx); 17 - void mtk_vcodec_dec_clock_off(struct mtk_vcodec_dev *vdec_dev, int hw_idx); 14 + void mtk_vcodec_dec_enable_hardware(struct mtk_vcodec_ctx *ctx, int hw_idx); 15 + void mtk_vcodec_dec_disable_hardware(struct mtk_vcodec_ctx *ctx, int hw_idx); 18 16 19 17 #endif /* _MTK_VCODEC_DEC_PM_H_ */

+8 -11

drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateful.c

··· 37 37 }, 38 38 }; 39 39 40 - #define NUM_FORMATS ARRAY_SIZE(mtk_video_formats) 40 + static const unsigned int num_supported_formats = 41 + ARRAY_SIZE(mtk_video_formats); 42 + 41 43 #define DEFAULT_OUT_FMT_IDX 0 42 44 #define DEFAULT_CAP_FMT_IDX 3 43 45 ··· 61 59 }, 62 60 }; 63 61 64 - #define NUM_SUPPORTED_FRAMESIZE ARRAY_SIZE(mtk_vdec_framesizes) 62 + static const unsigned int num_supported_framesize = 63 + ARRAY_SIZE(mtk_vdec_framesizes); 65 64 66 65 /* 67 66 * This function tries to clean all display buffers, the buffers will return ··· 93 90 vb = &dstbuf->m2m_buf.vb; 94 91 mutex_lock(&ctx->lock); 95 92 if (dstbuf->used) { 96 - vb2_set_plane_payload(&vb->vb2_buf, 0, ctx->picinfo.fb_sz[0]); 97 - if (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes == 2) 98 - vb2_set_plane_payload(&vb->vb2_buf, 1, 99 - ctx->picinfo.fb_sz[1]); 100 - 101 93 mtk_v4l2_debug(2, "[%d]status=%x queue id=%d to done_list %d", 102 94 ctx->id, disp_frame_buffer->status, 103 95 vb->vb2_buf.index, dstbuf->queued_in_vb2); ··· 233 235 unsigned int k; 234 236 235 237 dst_q_data = &ctx->q_data[MTK_Q_DATA_DST]; 236 - for (k = 0; k < NUM_FORMATS; k++) { 238 + for (k = 0; k < num_supported_formats; k++) { 237 239 fmt = &mtk_video_formats[k]; 238 240 if (fmt->fourcc == pixelformat) { 239 241 mtk_v4l2_debug(1, "Update cap fourcc(%d -> %d)", ··· 611 613 }; 612 614 613 615 const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pdata = { 614 - .chip = MTK_MT8173, 615 616 .init_vdec_params = mtk_init_vdec_params, 616 617 .ctrls_setup = mtk_vcodec_dec_ctrls_setup, 617 618 .vdec_vb2_ops = &mtk_vdec_frame_vb2_ops, 618 619 .vdec_formats = mtk_video_formats, 619 - .num_formats = NUM_FORMATS, 620 + .num_formats = &num_supported_formats, 620 621 .default_out_fmt = &mtk_video_formats[DEFAULT_OUT_FMT_IDX], 621 622 .default_cap_fmt = &mtk_video_formats[DEFAULT_CAP_FMT_IDX], 622 623 .vdec_framesizes = mtk_vdec_framesizes, 623 - .num_framesizes = NUM_SUPPORTED_FRAMESIZE, 624 + .num_framesizes = &num_supported_framesize, 624 625 .worker = mtk_vdec_worker, 625 626 .flush_decoder = mtk_vdec_flush_decoder, 626 627 .is_subdev_supported = false,

+207 -75

drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c

··· 76 76 .max = V4L2_STATELESS_H264_START_CODE_ANNEX_B, 77 77 }, 78 78 .codec_type = V4L2_PIX_FMT_H264_SLICE, 79 - } 79 + }, 80 + { 81 + .cfg = { 82 + .id = V4L2_CID_STATELESS_VP8_FRAME, 83 + }, 84 + .codec_type = V4L2_PIX_FMT_VP8_FRAME, 85 + }, 86 + { 87 + .cfg = { 88 + .id = V4L2_CID_MPEG_VIDEO_VP8_PROFILE, 89 + .min = V4L2_MPEG_VIDEO_VP8_PROFILE_0, 90 + .def = V4L2_MPEG_VIDEO_VP8_PROFILE_0, 91 + .max = V4L2_MPEG_VIDEO_VP8_PROFILE_3, 92 + }, 93 + .codec_type = V4L2_PIX_FMT_VP8_FRAME, 94 + }, 95 + { 96 + .cfg = { 97 + .id = V4L2_CID_STATELESS_VP9_FRAME, 98 + }, 99 + .codec_type = V4L2_PIX_FMT_VP9_FRAME, 100 + }, 101 + { 102 + .cfg = { 103 + .id = V4L2_CID_MPEG_VIDEO_VP9_PROFILE, 104 + .min = V4L2_MPEG_VIDEO_VP9_PROFILE_0, 105 + .def = V4L2_MPEG_VIDEO_VP9_PROFILE_0, 106 + .max = V4L2_MPEG_VIDEO_VP9_PROFILE_3, 107 + }, 108 + .codec_type = V4L2_PIX_FMT_VP9_FRAME, 109 + }, 80 110 }; 81 111 82 112 #define NUM_CTRLS ARRAY_SIZE(mtk_stateless_controls) 83 113 84 - static const struct mtk_video_fmt mtk_video_formats[] = { 85 - { 86 - .fourcc = V4L2_PIX_FMT_H264_SLICE, 87 - .type = MTK_FMT_DEC, 88 - .num_planes = 1, 89 - }, 90 - { 91 - .fourcc = V4L2_PIX_FMT_MM21, 92 - .type = MTK_FMT_FRAME, 93 - .num_planes = 2, 94 - }, 114 + static struct mtk_video_fmt mtk_video_formats[5]; 115 + static struct mtk_codec_framesizes mtk_vdec_framesizes[3]; 116 + 117 + static struct mtk_video_fmt default_out_format; 118 + static struct mtk_video_fmt default_cap_format; 119 + static unsigned int num_formats; 120 + static unsigned int num_framesizes; 121 + 122 + static struct v4l2_frmsize_stepwise stepwise_fhd = { 123 + .min_width = MTK_VDEC_MIN_W, 124 + .max_width = MTK_VDEC_MAX_W, 125 + .step_width = 16, 126 + .min_height = MTK_VDEC_MIN_H, 127 + .max_height = MTK_VDEC_MAX_H, 128 + .step_height = 16 95 129 }; 96 130 97 - #define NUM_FORMATS ARRAY_SIZE(mtk_video_formats) 98 - #define DEFAULT_OUT_FMT_IDX 0 99 - #define DEFAULT_CAP_FMT_IDX 1 100 - 101 - static const struct mtk_codec_framesizes mtk_vdec_framesizes[] = { 102 - { 103 - .fourcc = V4L2_PIX_FMT_H264_SLICE, 104 - .stepwise = { MTK_VDEC_MIN_W, MTK_VDEC_MAX_W, 16, 105 - MTK_VDEC_MIN_H, MTK_VDEC_MAX_H, 16 }, 106 - }, 107 - }; 108 - 109 - #define NUM_SUPPORTED_FRAMESIZE ARRAY_SIZE(mtk_vdec_framesizes) 110 - 111 - static void mtk_vdec_stateless_set_dst_payload(struct mtk_vcodec_ctx *ctx, 112 - struct vdec_fb *fb) 131 + static void mtk_vdec_stateless_cap_to_disp(struct mtk_vcodec_ctx *ctx, int error, 132 + struct media_request *src_buf_req) 113 133 { 114 - struct mtk_video_dec_buf *vdec_frame_buf = 115 - container_of(fb, struct mtk_video_dec_buf, frame_buffer); 116 - struct vb2_v4l2_buffer *vb = &vdec_frame_buf->m2m_buf.vb; 117 - unsigned int cap_y_size = ctx->q_data[MTK_Q_DATA_DST].sizeimage[0]; 134 + struct vb2_v4l2_buffer *vb2_dst; 135 + enum vb2_buffer_state state; 118 136 119 - vb2_set_plane_payload(&vb->vb2_buf, 0, cap_y_size); 120 - if (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes == 2) { 121 - unsigned int cap_c_size = 122 - ctx->q_data[MTK_Q_DATA_DST].sizeimage[1]; 137 + if (error) 138 + state = VB2_BUF_STATE_ERROR; 139 + else 140 + state = VB2_BUF_STATE_DONE; 123 141 124 - vb2_set_plane_payload(&vb->vb2_buf, 1, cap_c_size); 125 - } 142 + vb2_dst = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx); 143 + v4l2_m2m_buf_done(vb2_dst, state); 144 + 145 + mtk_v4l2_debug(2, "free frame buffer id:%d to done list", 146 + vb2_dst->vb2_buf.index); 147 + 148 + if (src_buf_req) 149 + v4l2_ctrl_request_complete(src_buf_req, &ctx->ctrl_hdl); 126 150 } 127 151 128 - static struct vdec_fb *vdec_get_cap_buffer(struct mtk_vcodec_ctx *ctx, 129 - struct vb2_v4l2_buffer *vb2_v4l2) 152 + static struct vdec_fb *vdec_get_cap_buffer(struct mtk_vcodec_ctx *ctx) 130 153 { 131 - struct mtk_video_dec_buf *framebuf = 132 - container_of(vb2_v4l2, struct mtk_video_dec_buf, m2m_buf.vb); 133 - struct vdec_fb *pfb = &framebuf->frame_buffer; 134 - struct vb2_buffer *dst_buf = &vb2_v4l2->vb2_buf; 154 + struct mtk_video_dec_buf *framebuf; 155 + struct vb2_v4l2_buffer *vb2_v4l2; 156 + struct vb2_buffer *dst_buf; 157 + struct vdec_fb *pfb; 135 158 136 - pfb->base_y.va = NULL; 159 + vb2_v4l2 = v4l2_m2m_next_dst_buf(ctx->m2m_ctx); 160 + if (!vb2_v4l2) { 161 + mtk_v4l2_debug(1, "[%d] dst_buf empty!!", ctx->id); 162 + return NULL; 163 + } 164 + 165 + dst_buf = &vb2_v4l2->vb2_buf; 166 + framebuf = container_of(vb2_v4l2, struct mtk_video_dec_buf, m2m_buf.vb); 167 + 168 + pfb = &framebuf->frame_buffer; 169 + pfb->base_y.va = vb2_plane_vaddr(dst_buf, 0); 137 170 pfb->base_y.dma_addr = vb2_dma_contig_plane_dma_addr(dst_buf, 0); 138 171 pfb->base_y.size = ctx->q_data[MTK_Q_DATA_DST].sizeimage[0]; 139 172 140 173 if (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes == 2) { 141 - pfb->base_c.va = NULL; 174 + pfb->base_c.va = vb2_plane_vaddr(dst_buf, 1); 142 175 pfb->base_c.dma_addr = 143 176 vb2_dma_contig_plane_dma_addr(dst_buf, 1); 144 177 pfb->base_c.size = ctx->q_data[MTK_Q_DATA_DST].sizeimage[1]; ··· 195 162 struct mtk_vcodec_ctx *ctx = 196 163 container_of(work, struct mtk_vcodec_ctx, decode_work); 197 164 struct mtk_vcodec_dev *dev = ctx->dev; 198 - struct vb2_v4l2_buffer *vb2_v4l2_src, *vb2_v4l2_dst; 165 + struct vb2_v4l2_buffer *vb2_v4l2_src; 199 166 struct vb2_buffer *vb2_src; 200 167 struct mtk_vcodec_mem *bs_src; 201 168 struct mtk_video_dec_buf *dec_buf_src; 202 169 struct media_request *src_buf_req; 203 - struct vdec_fb *dst_buf; 170 + enum vb2_buffer_state state; 204 171 bool res_chg = false; 205 172 int ret; 206 173 ··· 208 175 if (!vb2_v4l2_src) { 209 176 v4l2_m2m_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx); 210 177 mtk_v4l2_debug(1, "[%d] no available source buffer", ctx->id); 211 - return; 212 - } 213 - 214 - vb2_v4l2_dst = v4l2_m2m_next_dst_buf(ctx->m2m_ctx); 215 - if (!vb2_v4l2_dst) { 216 - v4l2_m2m_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx); 217 - mtk_v4l2_debug(1, "[%d] no available destination buffer", ctx->id); 218 178 return; 219 179 } 220 180 ··· 219 193 mtk_v4l2_debug(3, "[%d] (%d) id=%d, vb=%p", ctx->id, 220 194 vb2_src->vb2_queue->type, vb2_src->index, vb2_src); 221 195 222 - bs_src->va = NULL; 196 + bs_src->va = vb2_plane_vaddr(vb2_src, 0); 223 197 bs_src->dma_addr = vb2_dma_contig_plane_dma_addr(vb2_src, 0); 224 198 bs_src->size = (size_t)vb2_src->planes[0].bytesused; 199 + if (!bs_src->va) { 200 + v4l2_m2m_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx); 201 + mtk_v4l2_err("[%d] id=%d source buffer is NULL", ctx->id, 202 + vb2_src->index); 203 + return; 204 + } 225 205 226 206 mtk_v4l2_debug(3, "[%d] Bitstream VA=%p DMA=%pad Size=%zx vb=%p", 227 207 ctx->id, bs_src->va, &bs_src->dma_addr, bs_src->size, vb2_src); ··· 238 206 else 239 207 mtk_v4l2_err("vb2 buffer media request is NULL"); 240 208 241 - dst_buf = vdec_get_cap_buffer(ctx, vb2_v4l2_dst); 242 - v4l2_m2m_buf_copy_metadata(vb2_v4l2_src, vb2_v4l2_dst, true); 243 - ret = vdec_if_decode(ctx, bs_src, dst_buf, &res_chg); 209 + ret = vdec_if_decode(ctx, bs_src, NULL, &res_chg); 244 210 if (ret) { 245 211 mtk_v4l2_err(" <===[%d], src_buf[%d] sz=0x%zx pts=%llu vdec_if_decode() ret=%d res_chg=%d===>", 246 212 ctx->id, vb2_src->index, bs_src->size, ··· 250 220 } 251 221 } 252 222 253 - mtk_vdec_stateless_set_dst_payload(ctx, dst_buf); 254 - 255 - v4l2_m2m_buf_done_and_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx, 256 - ret ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE); 257 - 258 - v4l2_ctrl_request_complete(src_buf_req, &ctx->ctrl_hdl); 223 + state = ret ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE; 224 + if (!IS_VDEC_LAT_ARCH(dev->vdec_pdata->hw_arch) || 225 + ctx->current_codec == V4L2_PIX_FMT_VP8_FRAME || ret) { 226 + v4l2_m2m_buf_done_and_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx, state); 227 + if (src_buf_req) 228 + v4l2_ctrl_request_complete(src_buf_req, &ctx->ctrl_hdl); 229 + } else { 230 + v4l2_m2m_src_buf_remove(ctx->m2m_ctx); 231 + v4l2_m2m_buf_done(vb2_v4l2_src, state); 232 + v4l2_m2m_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx); 233 + } 259 234 } 260 235 261 236 static void vb2ops_vdec_stateless_buf_queue(struct vb2_buffer *vb) ··· 342 307 .req_queue = v4l2_m2m_request_queue, 343 308 }; 344 309 310 + static void mtk_vcodec_add_formats(unsigned int fourcc, 311 + struct mtk_vcodec_ctx *ctx) 312 + { 313 + struct mtk_vcodec_dev *dev = ctx->dev; 314 + const struct mtk_vcodec_dec_pdata *pdata = dev->vdec_pdata; 315 + int count_formats = *pdata->num_formats; 316 + int count_framesizes = *pdata->num_framesizes; 317 + 318 + switch (fourcc) { 319 + case V4L2_PIX_FMT_H264_SLICE: 320 + case V4L2_PIX_FMT_VP8_FRAME: 321 + case V4L2_PIX_FMT_VP9_FRAME: 322 + mtk_video_formats[count_formats].fourcc = fourcc; 323 + mtk_video_formats[count_formats].type = MTK_FMT_DEC; 324 + mtk_video_formats[count_formats].num_planes = 1; 325 + 326 + mtk_vdec_framesizes[count_framesizes].fourcc = fourcc; 327 + mtk_vdec_framesizes[count_framesizes].stepwise = stepwise_fhd; 328 + num_framesizes++; 329 + break; 330 + case V4L2_PIX_FMT_MM21: 331 + case V4L2_PIX_FMT_MT21C: 332 + mtk_video_formats[count_formats].fourcc = fourcc; 333 + mtk_video_formats[count_formats].type = MTK_FMT_FRAME; 334 + mtk_video_formats[count_formats].num_planes = 2; 335 + break; 336 + default: 337 + mtk_v4l2_err("Can not add unsupported format type"); 338 + return; 339 + } 340 + 341 + num_formats++; 342 + mtk_v4l2_debug(3, "num_formats: %d num_frames:%d dec_capability: 0x%x", 343 + count_formats, count_framesizes, ctx->dev->dec_capability); 344 + } 345 + 346 + static void mtk_vcodec_get_supported_formats(struct mtk_vcodec_ctx *ctx) 347 + { 348 + int cap_format_count = 0, out_format_count = 0; 349 + 350 + if (num_formats && num_framesizes) 351 + return; 352 + 353 + if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_MM21) { 354 + mtk_vcodec_add_formats(V4L2_PIX_FMT_MM21, ctx); 355 + cap_format_count++; 356 + } 357 + if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_MT21C) { 358 + mtk_vcodec_add_formats(V4L2_PIX_FMT_MT21C, ctx); 359 + cap_format_count++; 360 + } 361 + if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_H264_SLICE) { 362 + mtk_vcodec_add_formats(V4L2_PIX_FMT_H264_SLICE, ctx); 363 + out_format_count++; 364 + } 365 + if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_VP8_FRAME) { 366 + mtk_vcodec_add_formats(V4L2_PIX_FMT_VP8_FRAME, ctx); 367 + out_format_count++; 368 + } 369 + if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_VP9_FRAME) { 370 + mtk_vcodec_add_formats(V4L2_PIX_FMT_VP9_FRAME, ctx); 371 + out_format_count++; 372 + } 373 + 374 + if (cap_format_count) 375 + default_cap_format = mtk_video_formats[cap_format_count - 1]; 376 + if (out_format_count) 377 + default_out_format = 378 + mtk_video_formats[cap_format_count + out_format_count - 1]; 379 + } 380 + 345 381 static void mtk_init_vdec_params(struct mtk_vcodec_ctx *ctx) 346 382 { 347 383 struct vb2_queue *src_vq; 348 384 349 385 src_vq = v4l2_m2m_get_vq(ctx->m2m_ctx, 350 386 V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); 387 + 388 + if (!ctx->dev->vdec_pdata->is_subdev_supported) 389 + ctx->dev->dec_capability |= 390 + MTK_VDEC_FORMAT_H264_SLICE | MTK_VDEC_FORMAT_MM21; 391 + mtk_vcodec_get_supported_formats(ctx); 351 392 352 393 /* Support request api for output plane */ 353 394 src_vq->supports_requests = true; ··· 454 343 }; 455 344 456 345 const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata = { 457 - .chip = MTK_MT8183, 458 346 .init_vdec_params = mtk_init_vdec_params, 459 347 .ctrls_setup = mtk_vcodec_dec_ctrls_setup, 460 348 .vdec_vb2_ops = &mtk_vdec_request_vb2_ops, 461 349 .vdec_formats = mtk_video_formats, 462 - .num_formats = NUM_FORMATS, 463 - .default_out_fmt = &mtk_video_formats[DEFAULT_OUT_FMT_IDX], 464 - .default_cap_fmt = &mtk_video_formats[DEFAULT_CAP_FMT_IDX], 350 + .num_formats = &num_formats, 351 + .default_out_fmt = &default_out_format, 352 + .default_cap_fmt = &default_cap_format, 465 353 .vdec_framesizes = mtk_vdec_framesizes, 466 - .num_framesizes = NUM_SUPPORTED_FRAMESIZE, 354 + .num_framesizes = &num_framesizes, 467 355 .uses_stateless_api = true, 468 356 .worker = mtk_vdec_worker, 469 357 .flush_decoder = mtk_vdec_flush_decoder, 358 + .cap_to_disp = mtk_vdec_stateless_cap_to_disp, 359 + .get_cap_buffer = vdec_get_cap_buffer, 470 360 .is_subdev_supported = false, 471 361 .hw_arch = MTK_VDEC_PURE_SINGLE_CORE, 472 362 }; 473 363 474 364 /* This platform data is used for one lat and one core architecture. */ 475 365 const struct mtk_vcodec_dec_pdata mtk_lat_sig_core_pdata = { 476 - .chip = MTK_MT8192, 477 366 .init_vdec_params = mtk_init_vdec_params, 478 367 .ctrls_setup = mtk_vcodec_dec_ctrls_setup, 479 368 .vdec_vb2_ops = &mtk_vdec_request_vb2_ops, 480 369 .vdec_formats = mtk_video_formats, 481 - .num_formats = NUM_FORMATS, 482 - .default_out_fmt = &mtk_video_formats[DEFAULT_OUT_FMT_IDX], 483 - .default_cap_fmt = &mtk_video_formats[DEFAULT_CAP_FMT_IDX], 370 + .num_formats = &num_formats, 371 + .default_out_fmt = &default_out_format, 372 + .default_cap_fmt = &default_cap_format, 484 373 .vdec_framesizes = mtk_vdec_framesizes, 485 - .num_framesizes = NUM_SUPPORTED_FRAMESIZE, 374 + .num_framesizes = &num_framesizes, 486 375 .uses_stateless_api = true, 487 376 .worker = mtk_vdec_worker, 488 377 .flush_decoder = mtk_vdec_flush_decoder, 378 + .cap_to_disp = mtk_vdec_stateless_cap_to_disp, 379 + .get_cap_buffer = vdec_get_cap_buffer, 489 380 .is_subdev_supported = true, 490 381 .hw_arch = MTK_VDEC_LAT_SINGLE_CORE, 382 + }; 383 + 384 + const struct mtk_vcodec_dec_pdata mtk_vdec_single_core_pdata = { 385 + .init_vdec_params = mtk_init_vdec_params, 386 + .ctrls_setup = mtk_vcodec_dec_ctrls_setup, 387 + .vdec_vb2_ops = &mtk_vdec_request_vb2_ops, 388 + .vdec_formats = mtk_video_formats, 389 + .num_formats = &num_formats, 390 + .default_out_fmt = &default_out_format, 391 + .default_cap_fmt = &default_cap_format, 392 + .vdec_framesizes = mtk_vdec_framesizes, 393 + .num_framesizes = &num_framesizes, 394 + .uses_stateless_api = true, 395 + .worker = mtk_vdec_worker, 396 + .flush_decoder = mtk_vdec_flush_decoder, 397 + .cap_to_disp = mtk_vdec_stateless_cap_to_disp, 398 + .get_cap_buffer = vdec_get_cap_buffer, 399 + .is_subdev_supported = true, 400 + .hw_arch = MTK_VDEC_PURE_SINGLE_CORE, 491 401 };

+25 -16

drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h

··· 274 274 * to be used with encoder and stateful decoder. 275 275 * @is_flushing: set to true if flushing is in progress. 276 276 * @current_codec: current set input codec, in V4L2 pixel format 277 + * @capture_fourcc: capture queue type in V4L2 pixel format 277 278 * 278 279 * @colorspace: enum v4l2_colorspace; supplemental to pixelformat 279 280 * @ycbcr_enc: enum v4l2_ycbcr_encoding, Y'CbCr encoding ··· 285 284 * mtk_video_dec_buf. 286 285 * @hw_id: hardware index used to identify different hardware. 287 286 * 287 + * @max_width: hardware supported max width 288 + * @max_height: hardware supported max height 288 289 * @msg_queue: msg queue used to store lat buffer information. 289 290 */ 290 291 struct mtk_vcodec_ctx { ··· 322 319 bool is_flushing; 323 320 324 321 u32 current_codec; 322 + u32 capture_fourcc; 325 323 326 324 enum v4l2_colorspace colorspace; 327 325 enum v4l2_ycbcr_encoding ycbcr_enc; ··· 333 329 struct mutex lock; 334 330 int hw_id; 335 331 332 + unsigned int max_width; 333 + unsigned int max_height; 336 334 struct vdec_msg_queue msg_queue; 337 - }; 338 - 339 - enum mtk_chip { 340 - MTK_MT8173, 341 - MTK_MT8183, 342 - MTK_MT8192, 343 - MTK_MT8195, 344 335 }; 345 336 346 337 /* ··· 346 347 MTK_VDEC_LAT_SINGLE_CORE, 347 348 }; 348 349 350 + /* 351 + * struct mtk_vdec_format_types - Structure used to get supported 352 + * format types according to decoder capability 353 + */ 354 + enum mtk_vdec_format_types { 355 + MTK_VDEC_FORMAT_MM21 = 0x20, 356 + MTK_VDEC_FORMAT_MT21C = 0x40, 357 + MTK_VDEC_FORMAT_H264_SLICE = 0x100, 358 + MTK_VDEC_FORMAT_VP8_FRAME = 0x200, 359 + MTK_VDEC_FORMAT_VP9_FRAME = 0x400, 360 + }; 361 + 349 362 /** 350 363 * struct mtk_vcodec_dec_pdata - compatible data for each IC 351 364 * @init_vdec_params: init vdec params 352 365 * @ctrls_setup: init vcodec dec ctrls 353 366 * @worker: worker to start a decode job 354 367 * @flush_decoder: function that flushes the decoder 355 - * 368 + * @get_cap_buffer: get capture buffer from capture queue 369 + * @cap_to_disp: put capture buffer to disp list for lat and core arch 356 370 * @vdec_vb2_ops: struct vb2_ops 357 371 * 358 372 * @vdec_formats: supported video decoder formats ··· 376 364 * @vdec_framesizes: supported video decoder frame sizes 377 365 * @num_framesizes: count of video decoder frame sizes 378 366 * 379 - * @chip: chip this decoder is compatible with 380 367 * @hw_arch: hardware arch is used to separate pure_sin_core and lat_sin_core 381 368 * 382 369 * @is_subdev_supported: whether support parent-node architecture(subdev) ··· 387 376 int (*ctrls_setup)(struct mtk_vcodec_ctx *ctx); 388 377 void (*worker)(struct work_struct *work); 389 378 int (*flush_decoder)(struct mtk_vcodec_ctx *ctx); 379 + struct vdec_fb *(*get_cap_buffer)(struct mtk_vcodec_ctx *ctx); 380 + void (*cap_to_disp)(struct mtk_vcodec_ctx *ctx, int error, 381 + struct media_request *src_buf_req); 390 382 391 383 struct vb2_ops *vdec_vb2_ops; 392 384 393 385 const struct mtk_video_fmt *vdec_formats; 394 - const int num_formats; 386 + const int *num_formats; 395 387 const struct mtk_video_fmt *default_out_fmt; 396 388 const struct mtk_video_fmt *default_cap_fmt; 397 389 398 390 const struct mtk_codec_framesizes *vdec_framesizes; 399 - const int num_framesizes; 391 + const int *num_framesizes; 400 392 401 - enum mtk_chip chip; 402 393 enum mtk_vdec_hw_arch hw_arch; 403 394 404 395 bool is_subdev_supported; ··· 409 396 410 397 /** 411 398 * struct mtk_vcodec_enc_pdata - compatible data for each IC 412 - * 413 - * @chip: chip this encoder is compatible with 414 399 * 415 400 * @uses_ext: whether the encoder uses the extended firmware messaging format 416 401 * @min_bitrate: minimum supported encoding bitrate ··· 420 409 * @core_id: stand for h264 or vp8 encode index 421 410 */ 422 411 struct mtk_vcodec_enc_pdata { 423 - enum mtk_chip chip; 424 - 425 412 bool uses_ext; 426 413 unsigned long min_bitrate; 427 414 unsigned long max_bitrate;

-5

drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_drv.c

··· 376 376 } 377 377 378 378 static const struct mtk_vcodec_enc_pdata mt8173_avc_pdata = { 379 - .chip = MTK_MT8173, 380 379 .capture_formats = mtk_video_formats_capture_h264, 381 380 .num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_h264), 382 381 .output_formats = mtk_video_formats_output, ··· 386 387 }; 387 388 388 389 static const struct mtk_vcodec_enc_pdata mt8173_vp8_pdata = { 389 - .chip = MTK_MT8173, 390 390 .capture_formats = mtk_video_formats_capture_vp8, 391 391 .num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_vp8), 392 392 .output_formats = mtk_video_formats_output, ··· 396 398 }; 397 399 398 400 static const struct mtk_vcodec_enc_pdata mt8183_pdata = { 399 - .chip = MTK_MT8183, 400 401 .uses_ext = true, 401 402 .capture_formats = mtk_video_formats_capture_h264, 402 403 .num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_h264), ··· 407 410 }; 408 411 409 412 static const struct mtk_vcodec_enc_pdata mt8192_pdata = { 410 - .chip = MTK_MT8192, 411 413 .uses_ext = true, 412 414 .capture_formats = mtk_video_formats_capture_h264, 413 415 .num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_h264), ··· 418 422 }; 419 423 420 424 static const struct mtk_vcodec_enc_pdata mt8195_pdata = { 421 - .chip = MTK_MT8195, 422 425 .uses_ext = true, 423 426 .capture_formats = mtk_video_formats_capture_h264, 424 427 .num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_h264),

+6

drivers/media/platform/mediatek/vcodec/mtk_vcodec_fw.c

··· 65 65 return fw->ops->ipi_send(fw, id, buf, len, wait); 66 66 } 67 67 EXPORT_SYMBOL_GPL(mtk_vcodec_fw_ipi_send); 68 + 69 + int mtk_vcodec_fw_get_type(struct mtk_vcodec_fw *fw) 70 + { 71 + return fw->type; 72 + } 73 + EXPORT_SYMBOL_GPL(mtk_vcodec_fw_get_type);

+1

drivers/media/platform/mediatek/vcodec/mtk_vcodec_fw.h

··· 39 39 const char *name, void *priv); 40 40 int mtk_vcodec_fw_ipi_send(struct mtk_vcodec_fw *fw, int id, 41 41 void *buf, unsigned int len, unsigned int wait); 42 + int mtk_vcodec_fw_get_type(struct mtk_vcodec_fw *fw); 42 43 43 44 #endif /* _MTK_VCODEC_FW_H_ */

+323

drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_common.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Copyright (c) 2022 MediaTek Inc. 4 + * Author: Yunfei Dong <yunfei.dong@mediatek.com> 5 + */ 6 + 7 + #include "vdec_h264_req_common.h" 8 + 9 + /* get used parameters for sps/pps */ 10 + #define GET_MTK_VDEC_FLAG(cond, flag) \ 11 + { dst_param->cond = ((src_param->flags & flag) ? (1) : (0)); } 12 + #define GET_MTK_VDEC_PARAM(param) \ 13 + { dst_param->param = src_param->param; } 14 + 15 + void mtk_vdec_h264_get_ref_list(u8 *ref_list, 16 + const struct v4l2_h264_reference *v4l2_ref_list, 17 + int num_valid) 18 + { 19 + u32 i; 20 + 21 + /* 22 + * TODO The firmware does not support field decoding. Future 23 + * implementation must use v4l2_ref_list[i].fields to obtain 24 + * the reference field parity. 25 + */ 26 + 27 + for (i = 0; i < num_valid; i++) 28 + ref_list[i] = v4l2_ref_list[i].index; 29 + 30 + /* 31 + * The firmware expects unused reflist entries to have the value 0x20. 32 + */ 33 + memset(&ref_list[num_valid], 0x20, 32 - num_valid); 34 + } 35 + 36 + void *mtk_vdec_h264_get_ctrl_ptr(struct mtk_vcodec_ctx *ctx, int id) 37 + { 38 + struct v4l2_ctrl *ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, id); 39 + 40 + if (!ctrl) 41 + return ERR_PTR(-EINVAL); 42 + 43 + return ctrl->p_cur.p; 44 + } 45 + 46 + void mtk_vdec_h264_fill_dpb_info(struct mtk_vcodec_ctx *ctx, 47 + struct slice_api_h264_decode_param *decode_params, 48 + struct mtk_h264_dpb_info *h264_dpb_info) 49 + { 50 + const struct slice_h264_dpb_entry *dpb; 51 + struct vb2_queue *vq; 52 + struct vb2_buffer *vb; 53 + struct vb2_v4l2_buffer *vb2_v4l2; 54 + int index, vb2_index; 55 + 56 + vq = v4l2_m2m_get_vq(ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); 57 + 58 + for (index = 0; index < V4L2_H264_NUM_DPB_ENTRIES; index++) { 59 + dpb = &decode_params->dpb[index]; 60 + if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) { 61 + h264_dpb_info[index].reference_flag = 0; 62 + continue; 63 + } 64 + 65 + vb2_index = vb2_find_timestamp(vq, dpb->reference_ts, 0); 66 + if (vb2_index < 0) { 67 + dev_err(&ctx->dev->plat_dev->dev, 68 + "Reference invalid: dpb_index(%d) reference_ts(%lld)", 69 + index, dpb->reference_ts); 70 + continue; 71 + } 72 + 73 + /* 1 for short term reference, 2 for long term reference */ 74 + if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)) 75 + h264_dpb_info[index].reference_flag = 1; 76 + else 77 + h264_dpb_info[index].reference_flag = 2; 78 + 79 + vb = vq->bufs[vb2_index]; 80 + vb2_v4l2 = container_of(vb, struct vb2_v4l2_buffer, vb2_buf); 81 + h264_dpb_info[index].field = vb2_v4l2->field; 82 + 83 + h264_dpb_info[index].y_dma_addr = 84 + vb2_dma_contig_plane_dma_addr(vb, 0); 85 + if (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes == 2) 86 + h264_dpb_info[index].c_dma_addr = 87 + vb2_dma_contig_plane_dma_addr(vb, 1); 88 + else 89 + h264_dpb_info[index].c_dma_addr = 90 + h264_dpb_info[index].y_dma_addr + 91 + ctx->picinfo.fb_sz[0]; 92 + } 93 + } 94 + 95 + void mtk_vdec_h264_copy_sps_params(struct mtk_h264_sps_param *dst_param, 96 + const struct v4l2_ctrl_h264_sps *src_param) 97 + { 98 + GET_MTK_VDEC_PARAM(chroma_format_idc); 99 + GET_MTK_VDEC_PARAM(bit_depth_luma_minus8); 100 + GET_MTK_VDEC_PARAM(bit_depth_chroma_minus8); 101 + GET_MTK_VDEC_PARAM(log2_max_frame_num_minus4); 102 + GET_MTK_VDEC_PARAM(pic_order_cnt_type); 103 + GET_MTK_VDEC_PARAM(log2_max_pic_order_cnt_lsb_minus4); 104 + GET_MTK_VDEC_PARAM(max_num_ref_frames); 105 + GET_MTK_VDEC_PARAM(pic_width_in_mbs_minus1); 106 + GET_MTK_VDEC_PARAM(pic_height_in_map_units_minus1); 107 + 108 + GET_MTK_VDEC_FLAG(separate_colour_plane_flag, 109 + V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE); 110 + GET_MTK_VDEC_FLAG(qpprime_y_zero_transform_bypass_flag, 111 + V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS); 112 + GET_MTK_VDEC_FLAG(delta_pic_order_always_zero_flag, 113 + V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO); 114 + GET_MTK_VDEC_FLAG(frame_mbs_only_flag, 115 + V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY); 116 + GET_MTK_VDEC_FLAG(mb_adaptive_frame_field_flag, 117 + V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD); 118 + GET_MTK_VDEC_FLAG(direct_8x8_inference_flag, 119 + V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE); 120 + } 121 + 122 + void mtk_vdec_h264_copy_pps_params(struct mtk_h264_pps_param *dst_param, 123 + const struct v4l2_ctrl_h264_pps *src_param) 124 + { 125 + GET_MTK_VDEC_PARAM(num_ref_idx_l0_default_active_minus1); 126 + GET_MTK_VDEC_PARAM(num_ref_idx_l1_default_active_minus1); 127 + GET_MTK_VDEC_PARAM(weighted_bipred_idc); 128 + GET_MTK_VDEC_PARAM(pic_init_qp_minus26); 129 + GET_MTK_VDEC_PARAM(chroma_qp_index_offset); 130 + GET_MTK_VDEC_PARAM(second_chroma_qp_index_offset); 131 + 132 + GET_MTK_VDEC_FLAG(entropy_coding_mode_flag, 133 + V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE); 134 + GET_MTK_VDEC_FLAG(pic_order_present_flag, 135 + V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT); 136 + GET_MTK_VDEC_FLAG(weighted_pred_flag, 137 + V4L2_H264_PPS_FLAG_WEIGHTED_PRED); 138 + GET_MTK_VDEC_FLAG(deblocking_filter_control_present_flag, 139 + V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT); 140 + GET_MTK_VDEC_FLAG(constrained_intra_pred_flag, 141 + V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED); 142 + GET_MTK_VDEC_FLAG(redundant_pic_cnt_present_flag, 143 + V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT); 144 + GET_MTK_VDEC_FLAG(transform_8x8_mode_flag, 145 + V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE); 146 + GET_MTK_VDEC_FLAG(scaling_matrix_present_flag, 147 + V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT); 148 + } 149 + 150 + void mtk_vdec_h264_copy_slice_hd_params(struct mtk_h264_slice_hd_param *dst_param, 151 + const struct v4l2_ctrl_h264_slice_params *src_param, 152 + const struct v4l2_ctrl_h264_decode_params *dec_param) 153 + { 154 + int temp; 155 + 156 + GET_MTK_VDEC_PARAM(first_mb_in_slice); 157 + GET_MTK_VDEC_PARAM(slice_type); 158 + GET_MTK_VDEC_PARAM(cabac_init_idc); 159 + GET_MTK_VDEC_PARAM(slice_qp_delta); 160 + GET_MTK_VDEC_PARAM(disable_deblocking_filter_idc); 161 + GET_MTK_VDEC_PARAM(slice_alpha_c0_offset_div2); 162 + GET_MTK_VDEC_PARAM(slice_beta_offset_div2); 163 + GET_MTK_VDEC_PARAM(num_ref_idx_l0_active_minus1); 164 + GET_MTK_VDEC_PARAM(num_ref_idx_l1_active_minus1); 165 + 166 + dst_param->frame_num = dec_param->frame_num; 167 + dst_param->pic_order_cnt_lsb = dec_param->pic_order_cnt_lsb; 168 + 169 + dst_param->delta_pic_order_cnt_bottom = 170 + dec_param->delta_pic_order_cnt_bottom; 171 + dst_param->delta_pic_order_cnt0 = 172 + dec_param->delta_pic_order_cnt0; 173 + dst_param->delta_pic_order_cnt1 = 174 + dec_param->delta_pic_order_cnt1; 175 + 176 + temp = dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC; 177 + dst_param->field_pic_flag = temp ? 1 : 0; 178 + 179 + temp = dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD; 180 + dst_param->bottom_field_flag = temp ? 1 : 0; 181 + 182 + GET_MTK_VDEC_FLAG(direct_spatial_mv_pred_flag, 183 + V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED); 184 + } 185 + 186 + void mtk_vdec_h264_copy_scaling_matrix(struct slice_api_h264_scaling_matrix *dst_matrix, 187 + const struct v4l2_ctrl_h264_scaling_matrix *src_matrix) 188 + { 189 + memcpy(dst_matrix->scaling_list_4x4, src_matrix->scaling_list_4x4, 190 + sizeof(dst_matrix->scaling_list_4x4)); 191 + 192 + memcpy(dst_matrix->scaling_list_8x8, src_matrix->scaling_list_8x8, 193 + sizeof(dst_matrix->scaling_list_8x8)); 194 + } 195 + 196 + void 197 + mtk_vdec_h264_copy_decode_params(struct slice_api_h264_decode_param *dst_params, 198 + const struct v4l2_ctrl_h264_decode_params *src_params, 199 + const struct v4l2_h264_dpb_entry dpb[V4L2_H264_NUM_DPB_ENTRIES]) 200 + { 201 + struct slice_h264_dpb_entry *dst_entry; 202 + const struct v4l2_h264_dpb_entry *src_entry; 203 + int i; 204 + 205 + for (i = 0; i < ARRAY_SIZE(dst_params->dpb); i++) { 206 + dst_entry = &dst_params->dpb[i]; 207 + src_entry = &dpb[i]; 208 + 209 + dst_entry->reference_ts = src_entry->reference_ts; 210 + dst_entry->frame_num = src_entry->frame_num; 211 + dst_entry->pic_num = src_entry->pic_num; 212 + dst_entry->top_field_order_cnt = src_entry->top_field_order_cnt; 213 + dst_entry->bottom_field_order_cnt = 214 + src_entry->bottom_field_order_cnt; 215 + dst_entry->flags = src_entry->flags; 216 + } 217 + 218 + /* num_slices is a leftover from the old H.264 support and is ignored 219 + * by the firmware. 220 + */ 221 + dst_params->num_slices = 0; 222 + dst_params->nal_ref_idc = src_params->nal_ref_idc; 223 + dst_params->top_field_order_cnt = src_params->top_field_order_cnt; 224 + dst_params->bottom_field_order_cnt = src_params->bottom_field_order_cnt; 225 + dst_params->flags = src_params->flags; 226 + } 227 + 228 + static bool mtk_vdec_h264_dpb_entry_match(const struct v4l2_h264_dpb_entry *a, 229 + const struct v4l2_h264_dpb_entry *b) 230 + { 231 + return a->top_field_order_cnt == b->top_field_order_cnt && 232 + a->bottom_field_order_cnt == b->bottom_field_order_cnt; 233 + } 234 + 235 + /* 236 + * Move DPB entries of dec_param that refer to a frame already existing in dpb 237 + * into the already existing slot in dpb, and move other entries into new slots. 238 + * 239 + * This function is an adaptation of the similarly-named function in 240 + * hantro_h264.c. 241 + */ 242 + void mtk_vdec_h264_update_dpb(const struct v4l2_ctrl_h264_decode_params *dec_param, 243 + struct v4l2_h264_dpb_entry *dpb) 244 + { 245 + DECLARE_BITMAP(new, ARRAY_SIZE(dec_param->dpb)) = { 0, }; 246 + DECLARE_BITMAP(in_use, ARRAY_SIZE(dec_param->dpb)) = { 0, }; 247 + DECLARE_BITMAP(used, ARRAY_SIZE(dec_param->dpb)) = { 0, }; 248 + unsigned int i, j; 249 + 250 + /* Disable all entries by default, and mark the ones in use. */ 251 + for (i = 0; i < ARRAY_SIZE(dec_param->dpb); i++) { 252 + if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) 253 + set_bit(i, in_use); 254 + dpb[i].flags &= ~V4L2_H264_DPB_ENTRY_FLAG_ACTIVE; 255 + } 256 + 257 + /* Try to match new DPB entries with existing ones by their POCs. */ 258 + for (i = 0; i < ARRAY_SIZE(dec_param->dpb); i++) { 259 + const struct v4l2_h264_dpb_entry *ndpb = &dec_param->dpb[i]; 260 + 261 + if (!(ndpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) 262 + continue; 263 + 264 + /* 265 + * To cut off some comparisons, iterate only on target DPB 266 + * entries were already used. 267 + */ 268 + for_each_set_bit(j, in_use, ARRAY_SIZE(dec_param->dpb)) { 269 + struct v4l2_h264_dpb_entry *cdpb; 270 + 271 + cdpb = &dpb[j]; 272 + if (!mtk_vdec_h264_dpb_entry_match(cdpb, ndpb)) 273 + continue; 274 + 275 + *cdpb = *ndpb; 276 + set_bit(j, used); 277 + /* Don't reiterate on this one. */ 278 + clear_bit(j, in_use); 279 + break; 280 + } 281 + 282 + if (j == ARRAY_SIZE(dec_param->dpb)) 283 + set_bit(i, new); 284 + } 285 + 286 + /* For entries that could not be matched, use remaining free slots. */ 287 + for_each_set_bit(i, new, ARRAY_SIZE(dec_param->dpb)) { 288 + const struct v4l2_h264_dpb_entry *ndpb = &dec_param->dpb[i]; 289 + struct v4l2_h264_dpb_entry *cdpb; 290 + 291 + /* 292 + * Both arrays are of the same sizes, so there is no way 293 + * we can end up with no space in target array, unless 294 + * something is buggy. 295 + */ 296 + j = find_first_zero_bit(used, ARRAY_SIZE(dec_param->dpb)); 297 + if (WARN_ON(j >= ARRAY_SIZE(dec_param->dpb))) 298 + return; 299 + 300 + cdpb = &dpb[j]; 301 + *cdpb = *ndpb; 302 + set_bit(j, used); 303 + } 304 + } 305 + 306 + unsigned int mtk_vdec_h264_get_mv_buf_size(unsigned int width, unsigned int height) 307 + { 308 + int unit_size = (width / MB_UNIT_LEN) * (height / MB_UNIT_LEN) + 8; 309 + 310 + return HW_MB_STORE_SZ * unit_size; 311 + } 312 + 313 + int mtk_vdec_h264_find_start_code(unsigned char *data, unsigned int data_sz) 314 + { 315 + if (data_sz > 3 && data[0] == 0 && data[1] == 0 && data[2] == 1) 316 + return 3; 317 + 318 + if (data_sz > 4 && data[0] == 0 && data[1] == 0 && data[2] == 0 && 319 + data[3] == 1) 320 + return 4; 321 + 322 + return -1; 323 + }

+277

drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_common.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Copyright (c) 2022 MediaTek Inc. 4 + * Author: Yunfei Dong <yunfei.dong@mediatek.com> 5 + */ 6 + 7 + #ifndef _VDEC_H264_REQ_COMMON_H_ 8 + #define _VDEC_H264_REQ_COMMON_H_ 9 + 10 + #include <linux/module.h> 11 + #include <linux/slab.h> 12 + #include <media/v4l2-h264.h> 13 + #include <media/v4l2-mem2mem.h> 14 + #include <media/videobuf2-dma-contig.h> 15 + 16 + #include "../mtk_vcodec_drv.h" 17 + 18 + #define NAL_NON_IDR_SLICE 0x01 19 + #define NAL_IDR_SLICE 0x05 20 + #define NAL_TYPE(value) ((value) & 0x1F) 21 + 22 + #define BUF_PREDICTION_SZ (64 * 4096) 23 + #define MB_UNIT_LEN 16 24 + 25 + /* motion vector size (bytes) for every macro block */ 26 + #define HW_MB_STORE_SZ 64 27 + 28 + #define H264_MAX_MV_NUM 32 29 + 30 + /** 31 + * struct mtk_h264_dpb_info - h264 dpb information 32 + * 33 + * @y_dma_addr: Y bitstream physical address 34 + * @c_dma_addr: CbCr bitstream physical address 35 + * @reference_flag: reference picture flag (short/long term reference picture) 36 + * @field: field picture flag 37 + */ 38 + struct mtk_h264_dpb_info { 39 + dma_addr_t y_dma_addr; 40 + dma_addr_t c_dma_addr; 41 + int reference_flag; 42 + int field; 43 + }; 44 + 45 + /* 46 + * struct mtk_h264_sps_param - parameters for sps 47 + */ 48 + struct mtk_h264_sps_param { 49 + unsigned char chroma_format_idc; 50 + unsigned char bit_depth_luma_minus8; 51 + unsigned char bit_depth_chroma_minus8; 52 + unsigned char log2_max_frame_num_minus4; 53 + unsigned char pic_order_cnt_type; 54 + unsigned char log2_max_pic_order_cnt_lsb_minus4; 55 + unsigned char max_num_ref_frames; 56 + unsigned char separate_colour_plane_flag; 57 + unsigned short pic_width_in_mbs_minus1; 58 + unsigned short pic_height_in_map_units_minus1; 59 + unsigned int max_frame_nums; 60 + unsigned char qpprime_y_zero_transform_bypass_flag; 61 + unsigned char delta_pic_order_always_zero_flag; 62 + unsigned char frame_mbs_only_flag; 63 + unsigned char mb_adaptive_frame_field_flag; 64 + unsigned char direct_8x8_inference_flag; 65 + unsigned char reserved[3]; 66 + }; 67 + 68 + /* 69 + * struct mtk_h264_pps_param - parameters for pps 70 + */ 71 + struct mtk_h264_pps_param { 72 + unsigned char num_ref_idx_l0_default_active_minus1; 73 + unsigned char num_ref_idx_l1_default_active_minus1; 74 + unsigned char weighted_bipred_idc; 75 + char pic_init_qp_minus26; 76 + char chroma_qp_index_offset; 77 + char second_chroma_qp_index_offset; 78 + unsigned char entropy_coding_mode_flag; 79 + unsigned char pic_order_present_flag; 80 + unsigned char deblocking_filter_control_present_flag; 81 + unsigned char constrained_intra_pred_flag; 82 + unsigned char weighted_pred_flag; 83 + unsigned char redundant_pic_cnt_present_flag; 84 + unsigned char transform_8x8_mode_flag; 85 + unsigned char scaling_matrix_present_flag; 86 + unsigned char reserved[2]; 87 + }; 88 + 89 + /* 90 + * struct mtk_h264_slice_hd_param - parameters for slice header 91 + */ 92 + struct mtk_h264_slice_hd_param { 93 + unsigned int first_mb_in_slice; 94 + unsigned int field_pic_flag; 95 + unsigned int slice_type; 96 + unsigned int frame_num; 97 + int pic_order_cnt_lsb; 98 + int delta_pic_order_cnt_bottom; 99 + unsigned int bottom_field_flag; 100 + unsigned int direct_spatial_mv_pred_flag; 101 + int delta_pic_order_cnt0; 102 + int delta_pic_order_cnt1; 103 + unsigned int cabac_init_idc; 104 + int slice_qp_delta; 105 + unsigned int disable_deblocking_filter_idc; 106 + int slice_alpha_c0_offset_div2; 107 + int slice_beta_offset_div2; 108 + unsigned int num_ref_idx_l0_active_minus1; 109 + unsigned int num_ref_idx_l1_active_minus1; 110 + unsigned int reserved; 111 + }; 112 + 113 + /* 114 + * struct slice_api_h264_scaling_matrix - parameters for scaling list 115 + */ 116 + struct slice_api_h264_scaling_matrix { 117 + unsigned char scaling_list_4x4[6][16]; 118 + unsigned char scaling_list_8x8[6][64]; 119 + }; 120 + 121 + /* 122 + * struct slice_h264_dpb_entry - each dpb information 123 + */ 124 + struct slice_h264_dpb_entry { 125 + unsigned long long reference_ts; 126 + unsigned short frame_num; 127 + unsigned short pic_num; 128 + /* Note that field is indicated by v4l2_buffer.field */ 129 + int top_field_order_cnt; 130 + int bottom_field_order_cnt; 131 + unsigned int flags; 132 + }; 133 + 134 + /* 135 + * struct slice_api_h264_decode_param - parameters for decode. 136 + */ 137 + struct slice_api_h264_decode_param { 138 + struct slice_h264_dpb_entry dpb[V4L2_H264_NUM_DPB_ENTRIES]; 139 + unsigned short num_slices; 140 + unsigned short nal_ref_idc; 141 + unsigned char ref_pic_list_p0[32]; 142 + unsigned char ref_pic_list_b0[32]; 143 + unsigned char ref_pic_list_b1[32]; 144 + int top_field_order_cnt; 145 + int bottom_field_order_cnt; 146 + unsigned int flags; 147 + }; 148 + 149 + /** 150 + * struct h264_fb - h264 decode frame buffer information 151 + * 152 + * @vdec_fb_va: virtual address of struct vdec_fb 153 + * @y_fb_dma: dma address of Y frame buffer (luma) 154 + * @c_fb_dma: dma address of C frame buffer (chroma) 155 + * @poc: picture order count of frame buffer 156 + * @reserved: for 8 bytes alignment 157 + */ 158 + struct h264_fb { 159 + u64 vdec_fb_va; 160 + u64 y_fb_dma; 161 + u64 c_fb_dma; 162 + s32 poc; 163 + u32 reserved; 164 + }; 165 + 166 + /** 167 + * mtk_vdec_h264_get_ref_list - translate V4L2 reference list 168 + * 169 + * @ref_list: Mediatek reference picture list 170 + * @v4l2_ref_list: V4L2 reference picture list 171 + * @num_valid: used reference number 172 + */ 173 + void mtk_vdec_h264_get_ref_list(u8 *ref_list, 174 + const struct v4l2_h264_reference *v4l2_ref_list, 175 + int num_valid); 176 + 177 + /** 178 + * mtk_vdec_h264_get_ctrl_ptr - get each CID contrl address. 179 + * 180 + * @ctx: v4l2 ctx 181 + * @id: CID control ID 182 + * 183 + * Return: returns CID ctrl address. 184 + */ 185 + void *mtk_vdec_h264_get_ctrl_ptr(struct mtk_vcodec_ctx *ctx, int id); 186 + 187 + /** 188 + * mtk_vdec_h264_fill_dpb_info - get each CID contrl address. 189 + * 190 + * @ctx: v4l2 ctx 191 + * @decode_params: slice decode params 192 + * @h264_dpb_info: dpb buffer information 193 + */ 194 + void mtk_vdec_h264_fill_dpb_info(struct mtk_vcodec_ctx *ctx, 195 + struct slice_api_h264_decode_param *decode_params, 196 + struct mtk_h264_dpb_info *h264_dpb_info); 197 + 198 + /** 199 + * mtk_vdec_h264_copy_sps_params - get sps params. 200 + * 201 + * @dst_param: sps params for hw decoder 202 + * @src_param: sps params from user driver 203 + */ 204 + void mtk_vdec_h264_copy_sps_params(struct mtk_h264_sps_param *dst_param, 205 + const struct v4l2_ctrl_h264_sps *src_param); 206 + 207 + /** 208 + * mtk_vdec_h264_copy_pps_params - get pps params. 209 + * 210 + * @dst_param: pps params for hw decoder 211 + * @src_param: pps params from user driver 212 + */ 213 + void mtk_vdec_h264_copy_pps_params(struct mtk_h264_pps_param *dst_param, 214 + const struct v4l2_ctrl_h264_pps *src_param); 215 + 216 + /** 217 + * mtk_vdec_h264_copy_slice_hd_params - get slice header params. 218 + * 219 + * @dst_param: slice params for hw decoder 220 + * @src_param: slice params from user driver 221 + * @dec_param: decode params from user driver 222 + */ 223 + void mtk_vdec_h264_copy_slice_hd_params(struct mtk_h264_slice_hd_param *dst_param, 224 + const struct v4l2_ctrl_h264_slice_params *src_param, 225 + const struct v4l2_ctrl_h264_decode_params *dec_param); 226 + 227 + /** 228 + * mtk_vdec_h264_copy_scaling_matrix - get each CID contrl address. 229 + * 230 + * @dst_matrix: scaling list params for hw decoder 231 + * @src_matrix: scaling list params from user driver 232 + */ 233 + void mtk_vdec_h264_copy_scaling_matrix(struct slice_api_h264_scaling_matrix *dst_matrix, 234 + const struct v4l2_ctrl_h264_scaling_matrix *src_matrix); 235 + 236 + /** 237 + * mtk_vdec_h264_copy_decode_params - get decode params. 238 + * 239 + * @dst_params: dst params for hw decoder 240 + * @src_params: decode params from user driver 241 + * @dpb: dpb information 242 + */ 243 + void 244 + mtk_vdec_h264_copy_decode_params(struct slice_api_h264_decode_param *dst_params, 245 + const struct v4l2_ctrl_h264_decode_params *src_params, 246 + const struct v4l2_h264_dpb_entry dpb[V4L2_H264_NUM_DPB_ENTRIES]); 247 + 248 + /** 249 + * mtk_vdec_h264_update_dpb - updata dpb list. 250 + * 251 + * @dec_param: v4l2 control decode params 252 + * @dpb: dpb entry informaton 253 + */ 254 + void mtk_vdec_h264_update_dpb(const struct v4l2_ctrl_h264_decode_params *dec_param, 255 + struct v4l2_h264_dpb_entry *dpb); 256 + 257 + /** 258 + * mtk_vdec_h264_find_start_code - find h264 start code using sofeware. 259 + * 260 + * @data: input buffer address 261 + * @data_sz: input buffer size 262 + * 263 + * Return: returns start code position. 264 + */ 265 + int mtk_vdec_h264_find_start_code(unsigned char *data, unsigned int data_sz); 266 + 267 + /** 268 + * mtk_vdec_h264_get_mv_buf_size - get mv buffer size. 269 + * 270 + * @width: picture width 271 + * @height: picture height 272 + * 273 + * Return: returns mv buffer size. 274 + */ 275 + unsigned int mtk_vdec_h264_get_mv_buf_size(unsigned int width, unsigned int height); 276 + 277 + #endif

+61 -386

drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_if.c

··· 12 12 #include "../vdec_drv_base.h" 13 13 #include "../vdec_drv_if.h" 14 14 #include "../vdec_vpu_if.h" 15 - 16 - #define BUF_PREDICTION_SZ (64 * 4096) 17 - #define MB_UNIT_LEN 16 18 - 19 - /* get used parameters for sps/pps */ 20 - #define GET_MTK_VDEC_FLAG(cond, flag) \ 21 - { dst_param->cond = ((src_param->flags & (flag)) ? (1) : (0)); } 22 - #define GET_MTK_VDEC_PARAM(param) \ 23 - { dst_param->param = src_param->param; } 24 - /* motion vector size (bytes) for every macro block */ 25 - #define HW_MB_STORE_SZ 64 26 - 27 - #define H264_MAX_FB_NUM 17 28 - #define H264_MAX_MV_NUM 32 29 - #define HDR_PARSING_BUF_SZ 1024 30 - 31 - /** 32 - * struct mtk_h264_dpb_info - h264 dpb information 33 - * @y_dma_addr: Y bitstream physical address 34 - * @c_dma_addr: CbCr bitstream physical address 35 - * @reference_flag: reference picture flag (short/long term reference picture) 36 - * @field: field picture flag 37 - */ 38 - struct mtk_h264_dpb_info { 39 - dma_addr_t y_dma_addr; 40 - dma_addr_t c_dma_addr; 41 - int reference_flag; 42 - int field; 43 - }; 44 - 45 - /* 46 - * struct mtk_h264_sps_param - parameters for sps 47 - */ 48 - struct mtk_h264_sps_param { 49 - unsigned char chroma_format_idc; 50 - unsigned char bit_depth_luma_minus8; 51 - unsigned char bit_depth_chroma_minus8; 52 - unsigned char log2_max_frame_num_minus4; 53 - unsigned char pic_order_cnt_type; 54 - unsigned char log2_max_pic_order_cnt_lsb_minus4; 55 - unsigned char max_num_ref_frames; 56 - unsigned char separate_colour_plane_flag; 57 - unsigned short pic_width_in_mbs_minus1; 58 - unsigned short pic_height_in_map_units_minus1; 59 - unsigned int max_frame_nums; 60 - unsigned char qpprime_y_zero_transform_bypass_flag; 61 - unsigned char delta_pic_order_always_zero_flag; 62 - unsigned char frame_mbs_only_flag; 63 - unsigned char mb_adaptive_frame_field_flag; 64 - unsigned char direct_8x8_inference_flag; 65 - unsigned char reserved[3]; 66 - }; 67 - 68 - /* 69 - * struct mtk_h264_pps_param - parameters for pps 70 - */ 71 - struct mtk_h264_pps_param { 72 - unsigned char num_ref_idx_l0_default_active_minus1; 73 - unsigned char num_ref_idx_l1_default_active_minus1; 74 - unsigned char weighted_bipred_idc; 75 - char pic_init_qp_minus26; 76 - char chroma_qp_index_offset; 77 - char second_chroma_qp_index_offset; 78 - unsigned char entropy_coding_mode_flag; 79 - unsigned char pic_order_present_flag; 80 - unsigned char deblocking_filter_control_present_flag; 81 - unsigned char constrained_intra_pred_flag; 82 - unsigned char weighted_pred_flag; 83 - unsigned char redundant_pic_cnt_present_flag; 84 - unsigned char transform_8x8_mode_flag; 85 - unsigned char scaling_matrix_present_flag; 86 - unsigned char reserved[2]; 87 - }; 88 - 89 - struct slice_api_h264_scaling_matrix { 90 - unsigned char scaling_list_4x4[6][16]; 91 - unsigned char scaling_list_8x8[6][64]; 92 - }; 93 - 94 - struct slice_h264_dpb_entry { 95 - unsigned long long reference_ts; 96 - unsigned short frame_num; 97 - unsigned short pic_num; 98 - /* Note that field is indicated by v4l2_buffer.field */ 99 - int top_field_order_cnt; 100 - int bottom_field_order_cnt; 101 - unsigned int flags; /* V4L2_H264_DPB_ENTRY_FLAG_* */ 102 - }; 103 - 104 - /* 105 - * struct slice_api_h264_decode_param - parameters for decode. 106 - */ 107 - struct slice_api_h264_decode_param { 108 - struct slice_h264_dpb_entry dpb[16]; 109 - unsigned short num_slices; 110 - unsigned short nal_ref_idc; 111 - unsigned char ref_pic_list_p0[32]; 112 - unsigned char ref_pic_list_b0[32]; 113 - unsigned char ref_pic_list_b1[32]; 114 - int top_field_order_cnt; 115 - int bottom_field_order_cnt; 116 - unsigned int flags; /* V4L2_H264_DECODE_PARAM_FLAG_* */ 117 - }; 15 + #include "vdec_h264_req_common.h" 118 16 119 17 /* 120 18 * struct mtk_h264_dec_slice_param - parameters for decode current frame ··· 23 125 struct slice_api_h264_scaling_matrix scaling_matrix; 24 126 struct slice_api_h264_decode_param decode_params; 25 127 struct mtk_h264_dpb_info h264_dpb_info[16]; 26 - }; 27 - 28 - /** 29 - * struct h264_fb - h264 decode frame buffer information 30 - * @vdec_fb_va : virtual address of struct vdec_fb 31 - * @y_fb_dma : dma address of Y frame buffer (luma) 32 - * @c_fb_dma : dma address of C frame buffer (chroma) 33 - * @poc : picture order count of frame buffer 34 - * @reserved : for 8 bytes alignment 35 - */ 36 - struct h264_fb { 37 - u64 vdec_fb_va; 38 - u64 y_fb_dma; 39 - u64 c_fb_dma; 40 - s32 poc; 41 - u32 reserved; 42 128 }; 43 129 44 130 /** ··· 94 212 struct v4l2_h264_dpb_entry dpb[16]; 95 213 }; 96 214 97 - static void *get_ctrl_ptr(struct mtk_vcodec_ctx *ctx, int id) 215 + static int get_vdec_decode_parameters(struct vdec_h264_slice_inst *inst) 98 216 { 99 - struct v4l2_ctrl *ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, id); 100 - 101 - return ctrl->p_cur.p; 102 - } 103 - 104 - static void get_h264_dpb_list(struct vdec_h264_slice_inst *inst, 105 - struct mtk_h264_dec_slice_param *slice_param) 106 - { 107 - struct vb2_queue *vq; 108 - struct vb2_buffer *vb; 109 - struct vb2_v4l2_buffer *vb2_v4l2; 110 - u64 index; 111 - 112 - vq = v4l2_m2m_get_vq(inst->ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); 113 - 114 - for (index = 0; index < ARRAY_SIZE(slice_param->decode_params.dpb); index++) { 115 - const struct slice_h264_dpb_entry *dpb; 116 - int vb2_index; 117 - 118 - dpb = &slice_param->decode_params.dpb[index]; 119 - if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) { 120 - slice_param->h264_dpb_info[index].reference_flag = 0; 121 - continue; 122 - } 123 - 124 - vb2_index = vb2_find_timestamp(vq, dpb->reference_ts, 0); 125 - if (vb2_index < 0) { 126 - mtk_vcodec_err(inst, "Reference invalid: dpb_index(%lld) reference_ts(%lld)", 127 - index, dpb->reference_ts); 128 - continue; 129 - } 130 - /* 1 for short term reference, 2 for long term reference */ 131 - if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)) 132 - slice_param->h264_dpb_info[index].reference_flag = 1; 133 - else 134 - slice_param->h264_dpb_info[index].reference_flag = 2; 135 - 136 - vb = vq->bufs[vb2_index]; 137 - vb2_v4l2 = container_of(vb, struct vb2_v4l2_buffer, vb2_buf); 138 - slice_param->h264_dpb_info[index].field = vb2_v4l2->field; 139 - 140 - slice_param->h264_dpb_info[index].y_dma_addr = 141 - vb2_dma_contig_plane_dma_addr(vb, 0); 142 - if (inst->ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes == 2) { 143 - slice_param->h264_dpb_info[index].c_dma_addr = 144 - vb2_dma_contig_plane_dma_addr(vb, 1); 145 - } 146 - } 147 - } 148 - 149 - static void get_h264_sps_parameters(struct mtk_h264_sps_param *dst_param, 150 - const struct v4l2_ctrl_h264_sps *src_param) 151 - { 152 - GET_MTK_VDEC_PARAM(chroma_format_idc); 153 - GET_MTK_VDEC_PARAM(bit_depth_luma_minus8); 154 - GET_MTK_VDEC_PARAM(bit_depth_chroma_minus8); 155 - GET_MTK_VDEC_PARAM(log2_max_frame_num_minus4); 156 - GET_MTK_VDEC_PARAM(pic_order_cnt_type); 157 - GET_MTK_VDEC_PARAM(log2_max_pic_order_cnt_lsb_minus4); 158 - GET_MTK_VDEC_PARAM(max_num_ref_frames); 159 - GET_MTK_VDEC_PARAM(pic_width_in_mbs_minus1); 160 - GET_MTK_VDEC_PARAM(pic_height_in_map_units_minus1); 161 - 162 - GET_MTK_VDEC_FLAG(separate_colour_plane_flag, 163 - V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE); 164 - GET_MTK_VDEC_FLAG(qpprime_y_zero_transform_bypass_flag, 165 - V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS); 166 - GET_MTK_VDEC_FLAG(delta_pic_order_always_zero_flag, 167 - V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO); 168 - GET_MTK_VDEC_FLAG(frame_mbs_only_flag, 169 - V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY); 170 - GET_MTK_VDEC_FLAG(mb_adaptive_frame_field_flag, 171 - V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD); 172 - GET_MTK_VDEC_FLAG(direct_8x8_inference_flag, 173 - V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE); 174 - } 175 - 176 - static void get_h264_pps_parameters(struct mtk_h264_pps_param *dst_param, 177 - const struct v4l2_ctrl_h264_pps *src_param) 178 - { 179 - GET_MTK_VDEC_PARAM(num_ref_idx_l0_default_active_minus1); 180 - GET_MTK_VDEC_PARAM(num_ref_idx_l1_default_active_minus1); 181 - GET_MTK_VDEC_PARAM(weighted_bipred_idc); 182 - GET_MTK_VDEC_PARAM(pic_init_qp_minus26); 183 - GET_MTK_VDEC_PARAM(chroma_qp_index_offset); 184 - GET_MTK_VDEC_PARAM(second_chroma_qp_index_offset); 185 - 186 - GET_MTK_VDEC_FLAG(entropy_coding_mode_flag, 187 - V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE); 188 - GET_MTK_VDEC_FLAG(pic_order_present_flag, 189 - V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT); 190 - GET_MTK_VDEC_FLAG(weighted_pred_flag, 191 - V4L2_H264_PPS_FLAG_WEIGHTED_PRED); 192 - GET_MTK_VDEC_FLAG(deblocking_filter_control_present_flag, 193 - V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT); 194 - GET_MTK_VDEC_FLAG(constrained_intra_pred_flag, 195 - V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED); 196 - GET_MTK_VDEC_FLAG(redundant_pic_cnt_present_flag, 197 - V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT); 198 - GET_MTK_VDEC_FLAG(transform_8x8_mode_flag, 199 - V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE); 200 - GET_MTK_VDEC_FLAG(scaling_matrix_present_flag, 201 - V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT); 202 - } 203 - 204 - static void 205 - get_h264_scaling_matrix(struct slice_api_h264_scaling_matrix *dst_matrix, 206 - const struct v4l2_ctrl_h264_scaling_matrix *src_matrix) 207 - { 208 - memcpy(dst_matrix->scaling_list_4x4, src_matrix->scaling_list_4x4, 209 - sizeof(dst_matrix->scaling_list_4x4)); 210 - 211 - memcpy(dst_matrix->scaling_list_8x8, src_matrix->scaling_list_8x8, 212 - sizeof(dst_matrix->scaling_list_8x8)); 213 - } 214 - 215 - static void 216 - get_h264_decode_parameters(struct slice_api_h264_decode_param *dst_params, 217 - const struct v4l2_ctrl_h264_decode_params *src_params, 218 - const struct v4l2_h264_dpb_entry dpb[V4L2_H264_NUM_DPB_ENTRIES]) 219 - { 220 - int i; 221 - 222 - for (i = 0; i < ARRAY_SIZE(dst_params->dpb); i++) { 223 - struct slice_h264_dpb_entry *dst_entry = &dst_params->dpb[i]; 224 - const struct v4l2_h264_dpb_entry *src_entry = &dpb[i]; 225 - 226 - dst_entry->reference_ts = src_entry->reference_ts; 227 - dst_entry->frame_num = src_entry->frame_num; 228 - dst_entry->pic_num = src_entry->pic_num; 229 - dst_entry->top_field_order_cnt = src_entry->top_field_order_cnt; 230 - dst_entry->bottom_field_order_cnt = 231 - src_entry->bottom_field_order_cnt; 232 - dst_entry->flags = src_entry->flags; 233 - } 234 - 235 - /* 236 - * num_slices is a leftover from the old H.264 support and is ignored 237 - * by the firmware. 238 - */ 239 - dst_params->num_slices = 0; 240 - dst_params->nal_ref_idc = src_params->nal_ref_idc; 241 - dst_params->top_field_order_cnt = src_params->top_field_order_cnt; 242 - dst_params->bottom_field_order_cnt = src_params->bottom_field_order_cnt; 243 - dst_params->flags = src_params->flags; 244 - } 245 - 246 - static bool dpb_entry_match(const struct v4l2_h264_dpb_entry *a, 247 - const struct v4l2_h264_dpb_entry *b) 248 - { 249 - return a->top_field_order_cnt == b->top_field_order_cnt && 250 - a->bottom_field_order_cnt == b->bottom_field_order_cnt; 251 - } 252 - 253 - /* 254 - * Move DPB entries of dec_param that refer to a frame already existing in dpb 255 - * into the already existing slot in dpb, and move other entries into new slots. 256 - * 257 - * This function is an adaptation of the similarly-named function in 258 - * hantro_h264.c. 259 - */ 260 - static void update_dpb(const struct v4l2_ctrl_h264_decode_params *dec_param, 261 - struct v4l2_h264_dpb_entry *dpb) 262 - { 263 - DECLARE_BITMAP(new, ARRAY_SIZE(dec_param->dpb)) = { 0, }; 264 - DECLARE_BITMAP(in_use, ARRAY_SIZE(dec_param->dpb)) = { 0, }; 265 - DECLARE_BITMAP(used, ARRAY_SIZE(dec_param->dpb)) = { 0, }; 266 - unsigned int i, j; 267 - 268 - /* Disable all entries by default, and mark the ones in use. */ 269 - for (i = 0; i < ARRAY_SIZE(dec_param->dpb); i++) { 270 - if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) 271 - set_bit(i, in_use); 272 - dpb[i].flags &= ~V4L2_H264_DPB_ENTRY_FLAG_ACTIVE; 273 - } 274 - 275 - /* Try to match new DPB entries with existing ones by their POCs. */ 276 - for (i = 0; i < ARRAY_SIZE(dec_param->dpb); i++) { 277 - const struct v4l2_h264_dpb_entry *ndpb = &dec_param->dpb[i]; 278 - 279 - if (!(ndpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) 280 - continue; 281 - 282 - /* 283 - * To cut off some comparisons, iterate only on target DPB 284 - * entries were already used. 285 - */ 286 - for_each_set_bit(j, in_use, ARRAY_SIZE(dec_param->dpb)) { 287 - struct v4l2_h264_dpb_entry *cdpb; 288 - 289 - cdpb = &dpb[j]; 290 - if (!dpb_entry_match(cdpb, ndpb)) 291 - continue; 292 - 293 - *cdpb = *ndpb; 294 - set_bit(j, used); 295 - /* Don't reiterate on this one. */ 296 - clear_bit(j, in_use); 297 - break; 298 - } 299 - 300 - if (j == ARRAY_SIZE(dec_param->dpb)) 301 - set_bit(i, new); 302 - } 303 - 304 - /* For entries that could not be matched, use remaining free slots. */ 305 - for_each_set_bit(i, new, ARRAY_SIZE(dec_param->dpb)) { 306 - const struct v4l2_h264_dpb_entry *ndpb = &dec_param->dpb[i]; 307 - struct v4l2_h264_dpb_entry *cdpb; 308 - 309 - /* 310 - * Both arrays are of the same sizes, so there is no way 311 - * we can end up with no space in target array, unless 312 - * something is buggy. 313 - */ 314 - j = find_first_zero_bit(used, ARRAY_SIZE(dec_param->dpb)); 315 - if (WARN_ON(j >= ARRAY_SIZE(dec_param->dpb))) 316 - return; 317 - 318 - cdpb = &dpb[j]; 319 - *cdpb = *ndpb; 320 - set_bit(j, used); 321 - } 322 - } 323 - 324 - /* 325 - * The firmware expects unused reflist entries to have the value 0x20. 326 - */ 327 - static void fixup_ref_list(u8 *ref_list, size_t num_valid) 328 - { 329 - memset(&ref_list[num_valid], 0x20, 32 - num_valid); 330 - } 331 - 332 - static void get_vdec_decode_parameters(struct vdec_h264_slice_inst *inst) 333 - { 334 - const struct v4l2_ctrl_h264_decode_params *dec_params = 335 - get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_DECODE_PARAMS); 336 - const struct v4l2_ctrl_h264_sps *sps = 337 - get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_SPS); 338 - const struct v4l2_ctrl_h264_pps *pps = 339 - get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_PPS); 340 - const struct v4l2_ctrl_h264_scaling_matrix *scaling_matrix = 341 - get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_SCALING_MATRIX); 217 + const struct v4l2_ctrl_h264_decode_params *dec_params; 218 + const struct v4l2_ctrl_h264_sps *sps; 219 + const struct v4l2_ctrl_h264_pps *pps; 220 + const struct v4l2_ctrl_h264_scaling_matrix *scaling_matrix; 342 221 struct mtk_h264_dec_slice_param *slice_param = &inst->h264_slice_param; 343 222 struct v4l2_h264_reflist_builder reflist_builder; 223 + struct v4l2_h264_reference v4l2_p0_reflist[V4L2_H264_REF_LIST_LEN]; 224 + struct v4l2_h264_reference v4l2_b0_reflist[V4L2_H264_REF_LIST_LEN]; 225 + struct v4l2_h264_reference v4l2_b1_reflist[V4L2_H264_REF_LIST_LEN]; 344 226 u8 *p0_reflist = slice_param->decode_params.ref_pic_list_p0; 345 227 u8 *b0_reflist = slice_param->decode_params.ref_pic_list_b0; 346 228 u8 *b1_reflist = slice_param->decode_params.ref_pic_list_b1; 347 229 348 - update_dpb(dec_params, inst->dpb); 230 + dec_params = 231 + mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_DECODE_PARAMS); 232 + if (IS_ERR(dec_params)) 233 + return PTR_ERR(dec_params); 349 234 350 - get_h264_sps_parameters(&slice_param->sps, sps); 351 - get_h264_pps_parameters(&slice_param->pps, pps); 352 - get_h264_scaling_matrix(&slice_param->scaling_matrix, scaling_matrix); 353 - get_h264_decode_parameters(&slice_param->decode_params, dec_params, 354 - inst->dpb); 355 - get_h264_dpb_list(inst, slice_param); 235 + sps = mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_SPS); 236 + if (IS_ERR(sps)) 237 + return PTR_ERR(sps); 238 + 239 + pps = mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_PPS); 240 + if (IS_ERR(pps)) 241 + return PTR_ERR(pps); 242 + 243 + scaling_matrix = 244 + mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_SCALING_MATRIX); 245 + if (IS_ERR(scaling_matrix)) 246 + return PTR_ERR(scaling_matrix); 247 + 248 + mtk_vdec_h264_update_dpb(dec_params, inst->dpb); 249 + 250 + mtk_vdec_h264_copy_sps_params(&slice_param->sps, sps); 251 + mtk_vdec_h264_copy_pps_params(&slice_param->pps, pps); 252 + mtk_vdec_h264_copy_scaling_matrix(&slice_param->scaling_matrix, scaling_matrix); 253 + mtk_vdec_h264_copy_decode_params(&slice_param->decode_params, 254 + dec_params, inst->dpb); 255 + mtk_vdec_h264_fill_dpb_info(inst->ctx, &slice_param->decode_params, 256 + slice_param->h264_dpb_info); 356 257 357 258 /* Build the reference lists */ 358 259 v4l2_h264_init_reflist_builder(&reflist_builder, dec_params, sps, 359 260 inst->dpb); 360 - v4l2_h264_build_p_ref_list(&reflist_builder, p0_reflist); 361 - v4l2_h264_build_b_ref_lists(&reflist_builder, b0_reflist, b1_reflist); 261 + v4l2_h264_build_p_ref_list(&reflist_builder, v4l2_p0_reflist); 262 + v4l2_h264_build_b_ref_lists(&reflist_builder, v4l2_b0_reflist, 263 + v4l2_b1_reflist); 264 + 362 265 /* Adapt the built lists to the firmware's expectations */ 363 - fixup_ref_list(p0_reflist, reflist_builder.num_valid); 364 - fixup_ref_list(b0_reflist, reflist_builder.num_valid); 365 - fixup_ref_list(b1_reflist, reflist_builder.num_valid); 266 + mtk_vdec_h264_get_ref_list(p0_reflist, v4l2_p0_reflist, reflist_builder.num_valid); 267 + mtk_vdec_h264_get_ref_list(b0_reflist, v4l2_b0_reflist, reflist_builder.num_valid); 268 + mtk_vdec_h264_get_ref_list(b1_reflist, v4l2_b1_reflist, reflist_builder.num_valid); 366 269 367 270 memcpy(&inst->vsi_ctx.h264_slice_params, slice_param, 368 271 sizeof(inst->vsi_ctx.h264_slice_params)); 369 - } 370 272 371 - static unsigned int get_mv_buf_size(unsigned int width, unsigned int height) 372 - { 373 - int unit_size = (width / MB_UNIT_LEN) * (height / MB_UNIT_LEN) + 8; 374 - 375 - return HW_MB_STORE_SZ * unit_size; 273 + return 0; 376 274 } 377 275 378 276 static int allocate_predication_buf(struct vdec_h264_slice_inst *inst) ··· 187 525 int i; 188 526 int err; 189 527 struct mtk_vcodec_mem *mem = NULL; 190 - unsigned int buf_sz = get_mv_buf_size(pic->buf_w, pic->buf_h); 528 + unsigned int buf_sz = mtk_vdec_h264_get_mv_buf_size(pic->buf_w, pic->buf_h); 191 529 192 530 mtk_v4l2_debug(3, "size = 0x%x", buf_sz); 193 531 for (i = 0; i < H264_MAX_MV_NUM; i++) { ··· 332 670 } 333 671 334 672 static int vdec_h264_slice_decode(void *h_vdec, struct mtk_vcodec_mem *bs, 335 - struct vdec_fb *fb, bool *res_chg) 673 + struct vdec_fb *unused, bool *res_chg) 336 674 { 337 675 struct vdec_h264_slice_inst *inst = h_vdec; 338 676 const struct v4l2_ctrl_h264_decode_params *dec_params = 339 - get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_DECODE_PARAMS); 677 + mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_DECODE_PARAMS); 340 678 struct vdec_vpu_inst *vpu = &inst->vpu; 679 + struct mtk_video_dec_buf *src_buf_info; 680 + struct mtk_video_dec_buf *dst_buf_info; 681 + struct vdec_fb *fb; 341 682 u32 data[2]; 342 683 u64 y_fb_dma; 343 684 u64 c_fb_dma; 344 685 int err; 345 686 687 + inst->num_nalu++; 346 688 /* bs NULL means flush decoder */ 347 689 if (!bs) 348 690 return vpu_dec_reset(vpu); 691 + 692 + fb = inst->ctx->dev->vdec_pdata->get_cap_buffer(inst->ctx); 693 + src_buf_info = container_of(bs, struct mtk_video_dec_buf, bs_buffer); 694 + dst_buf_info = container_of(fb, struct mtk_video_dec_buf, frame_buffer); 349 695 350 696 y_fb_dma = fb ? (u64)fb->base_y.dma_addr : 0; 351 697 c_fb_dma = fb ? (u64)fb->base_c.dma_addr : 0; 352 698 353 699 mtk_vcodec_debug(inst, "+ [%d] FB y_dma=%llx c_dma=%llx va=%p", 354 - ++inst->num_nalu, y_fb_dma, c_fb_dma, fb); 700 + inst->num_nalu, y_fb_dma, c_fb_dma, fb); 355 701 356 702 inst->vsi_ctx.dec.bs_dma = (uint64_t)bs->dma_addr; 357 703 inst->vsi_ctx.dec.y_fb_dma = y_fb_dma; 358 704 inst->vsi_ctx.dec.c_fb_dma = c_fb_dma; 359 705 inst->vsi_ctx.dec.vdec_fb_va = (u64)(uintptr_t)fb; 360 706 361 - get_vdec_decode_parameters(inst); 707 + v4l2_m2m_buf_copy_metadata(&src_buf_info->m2m_buf.vb, 708 + &dst_buf_info->m2m_buf.vb, true); 709 + err = get_vdec_decode_parameters(inst); 710 + if (err) 711 + goto err_free_fb_out; 712 + 362 713 data[0] = bs->size; 363 714 /* 364 715 * Reconstruct the first byte of the NAL unit, as the firmware requests

+808

drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_multi_if.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Copyright (c) 2022 MediaTek Inc. 4 + * Author: Yunfei Dong <yunfei.dong@mediatek.com> 5 + */ 6 + 7 + #include <linux/module.h> 8 + #include <linux/slab.h> 9 + #include <media/v4l2-h264.h> 10 + #include <media/v4l2-mem2mem.h> 11 + #include <media/videobuf2-dma-contig.h> 12 + 13 + #include "../mtk_vcodec_util.h" 14 + #include "../mtk_vcodec_dec.h" 15 + #include "../mtk_vcodec_intr.h" 16 + #include "../vdec_drv_base.h" 17 + #include "../vdec_drv_if.h" 18 + #include "../vdec_vpu_if.h" 19 + #include "vdec_h264_req_common.h" 20 + 21 + /** 22 + * enum vdec_h264_core_dec_err_type - core decode error type 23 + * 24 + * @TRANS_BUFFER_FULL: trans buffer is full 25 + * @SLICE_HEADER_FULL: slice header buffer is full 26 + */ 27 + enum vdec_h264_core_dec_err_type { 28 + TRANS_BUFFER_FULL = 1, 29 + SLICE_HEADER_FULL, 30 + }; 31 + 32 + /** 33 + * struct vdec_h264_slice_lat_dec_param - parameters for decode current frame 34 + * 35 + * @sps: h264 sps syntax parameters 36 + * @pps: h264 pps syntax parameters 37 + * @slice_header: h264 slice header syntax parameters 38 + * @scaling_matrix: h264 scaling list parameters 39 + * @decode_params: decoder parameters of each frame used for hardware decode 40 + * @h264_dpb_info: dpb reference list 41 + */ 42 + struct vdec_h264_slice_lat_dec_param { 43 + struct mtk_h264_sps_param sps; 44 + struct mtk_h264_pps_param pps; 45 + struct mtk_h264_slice_hd_param slice_header; 46 + struct slice_api_h264_scaling_matrix scaling_matrix; 47 + struct slice_api_h264_decode_param decode_params; 48 + struct mtk_h264_dpb_info h264_dpb_info[V4L2_H264_NUM_DPB_ENTRIES]; 49 + }; 50 + 51 + /** 52 + * struct vdec_h264_slice_info - decode information 53 + * 54 + * @nal_info: nal info of current picture 55 + * @timeout: Decode timeout: 1 timeout, 0 no timeount 56 + * @bs_buf_size: bitstream size 57 + * @bs_buf_addr: bitstream buffer dma address 58 + * @y_fb_dma: Y frame buffer dma address 59 + * @c_fb_dma: C frame buffer dma address 60 + * @vdec_fb_va: VDEC frame buffer struct virtual address 61 + * @crc: Used to check whether hardware's status is right 62 + */ 63 + struct vdec_h264_slice_info { 64 + u16 nal_info; 65 + u16 timeout; 66 + u32 bs_buf_size; 67 + u64 bs_buf_addr; 68 + u64 y_fb_dma; 69 + u64 c_fb_dma; 70 + u64 vdec_fb_va; 71 + u32 crc[8]; 72 + }; 73 + 74 + /** 75 + * struct vdec_h264_slice_vsi - shared memory for decode information exchange 76 + * between SCP and Host. 77 + * 78 + * @wdma_err_addr: wdma error dma address 79 + * @wdma_start_addr: wdma start dma address 80 + * @wdma_end_addr: wdma end dma address 81 + * @slice_bc_start_addr: slice bc start dma address 82 + * @slice_bc_end_addr: slice bc end dma address 83 + * @row_info_start_addr: row info start dma address 84 + * @row_info_end_addr: row info end dma address 85 + * @trans_start: trans start dma address 86 + * @trans_end: trans end dma address 87 + * @wdma_end_addr_offset: wdma end address offset 88 + * 89 + * @mv_buf_dma: HW working motion vector buffer 90 + * dma address (AP-W, VPU-R) 91 + * @dec: decode information (AP-R, VPU-W) 92 + * @h264_slice_params: decode parameters for hw used 93 + */ 94 + struct vdec_h264_slice_vsi { 95 + /* LAT dec addr */ 96 + u64 wdma_err_addr; 97 + u64 wdma_start_addr; 98 + u64 wdma_end_addr; 99 + u64 slice_bc_start_addr; 100 + u64 slice_bc_end_addr; 101 + u64 row_info_start_addr; 102 + u64 row_info_end_addr; 103 + u64 trans_start; 104 + u64 trans_end; 105 + u64 wdma_end_addr_offset; 106 + 107 + u64 mv_buf_dma[H264_MAX_MV_NUM]; 108 + struct vdec_h264_slice_info dec; 109 + struct vdec_h264_slice_lat_dec_param h264_slice_params; 110 + }; 111 + 112 + /** 113 + * struct vdec_h264_slice_share_info - shared information used to exchange 114 + * message between lat and core 115 + * 116 + * @sps: sequence header information from user space 117 + * @dec_params: decoder params from user space 118 + * @h264_slice_params: decoder params used for hardware 119 + * @trans_start: trans start dma address 120 + * @trans_end: trans end dma address 121 + * @nal_info: nal info of current picture 122 + */ 123 + struct vdec_h264_slice_share_info { 124 + struct v4l2_ctrl_h264_sps sps; 125 + struct v4l2_ctrl_h264_decode_params dec_params; 126 + struct vdec_h264_slice_lat_dec_param h264_slice_params; 127 + u64 trans_start; 128 + u64 trans_end; 129 + u16 nal_info; 130 + }; 131 + 132 + /** 133 + * struct vdec_h264_slice_inst - h264 decoder instance 134 + * 135 + * @slice_dec_num: how many picture be decoded 136 + * @ctx: point to mtk_vcodec_ctx 137 + * @pred_buf: HW working predication buffer 138 + * @mv_buf: HW working motion vector buffer 139 + * @vpu: VPU instance 140 + * @vsi: vsi used for lat 141 + * @vsi_core: vsi used for core 142 + * 143 + * @vsi_ctx: Local VSI data for this decoding context 144 + * @h264_slice_param: the parameters that hardware use to decode 145 + * 146 + * @resolution_changed:resolution changed 147 + * @realloc_mv_buf: reallocate mv buffer 148 + * @cap_num_planes: number of capture queue plane 149 + * 150 + * @dpb: decoded picture buffer used to store reference 151 + * buffer information 152 + *@is_field_bitstream: is field bitstream 153 + */ 154 + struct vdec_h264_slice_inst { 155 + unsigned int slice_dec_num; 156 + struct mtk_vcodec_ctx *ctx; 157 + struct mtk_vcodec_mem pred_buf; 158 + struct mtk_vcodec_mem mv_buf[H264_MAX_MV_NUM]; 159 + struct vdec_vpu_inst vpu; 160 + struct vdec_h264_slice_vsi *vsi; 161 + struct vdec_h264_slice_vsi *vsi_core; 162 + 163 + struct vdec_h264_slice_vsi vsi_ctx; 164 + struct vdec_h264_slice_lat_dec_param h264_slice_param; 165 + 166 + unsigned int resolution_changed; 167 + unsigned int realloc_mv_buf; 168 + unsigned int cap_num_planes; 169 + 170 + struct v4l2_h264_dpb_entry dpb[16]; 171 + bool is_field_bitstream; 172 + }; 173 + 174 + static int vdec_h264_slice_fill_decode_parameters(struct vdec_h264_slice_inst *inst, 175 + struct vdec_h264_slice_share_info *share_info) 176 + { 177 + struct vdec_h264_slice_lat_dec_param *slice_param = &inst->vsi->h264_slice_params; 178 + const struct v4l2_ctrl_h264_decode_params *dec_params; 179 + const struct v4l2_ctrl_h264_scaling_matrix *src_matrix; 180 + const struct v4l2_ctrl_h264_sps *sps; 181 + const struct v4l2_ctrl_h264_pps *pps; 182 + 183 + dec_params = 184 + mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_DECODE_PARAMS); 185 + if (IS_ERR(dec_params)) 186 + return PTR_ERR(dec_params); 187 + 188 + src_matrix = 189 + mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_SCALING_MATRIX); 190 + if (IS_ERR(src_matrix)) 191 + return PTR_ERR(src_matrix); 192 + 193 + sps = mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_SPS); 194 + if (IS_ERR(sps)) 195 + return PTR_ERR(sps); 196 + 197 + pps = mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_PPS); 198 + if (IS_ERR(pps)) 199 + return PTR_ERR(pps); 200 + 201 + if (dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC) { 202 + mtk_vcodec_err(inst, "No support for H.264 field decoding."); 203 + inst->is_field_bitstream = true; 204 + return -EINVAL; 205 + } 206 + 207 + mtk_vdec_h264_copy_sps_params(&slice_param->sps, sps); 208 + mtk_vdec_h264_copy_pps_params(&slice_param->pps, pps); 209 + mtk_vdec_h264_copy_scaling_matrix(&slice_param->scaling_matrix, src_matrix); 210 + 211 + memcpy(&share_info->sps, sps, sizeof(*sps)); 212 + memcpy(&share_info->dec_params, dec_params, sizeof(*dec_params)); 213 + 214 + return 0; 215 + } 216 + 217 + static int get_vdec_sig_decode_parameters(struct vdec_h264_slice_inst *inst) 218 + { 219 + const struct v4l2_ctrl_h264_decode_params *dec_params; 220 + const struct v4l2_ctrl_h264_sps *sps; 221 + const struct v4l2_ctrl_h264_pps *pps; 222 + const struct v4l2_ctrl_h264_scaling_matrix *scaling_matrix; 223 + struct vdec_h264_slice_lat_dec_param *slice_param = &inst->h264_slice_param; 224 + struct v4l2_h264_reflist_builder reflist_builder; 225 + struct v4l2_h264_reference v4l2_p0_reflist[V4L2_H264_REF_LIST_LEN]; 226 + struct v4l2_h264_reference v4l2_b0_reflist[V4L2_H264_REF_LIST_LEN]; 227 + struct v4l2_h264_reference v4l2_b1_reflist[V4L2_H264_REF_LIST_LEN]; 228 + u8 *p0_reflist = slice_param->decode_params.ref_pic_list_p0; 229 + u8 *b0_reflist = slice_param->decode_params.ref_pic_list_b0; 230 + u8 *b1_reflist = slice_param->decode_params.ref_pic_list_b1; 231 + 232 + dec_params = 233 + mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_DECODE_PARAMS); 234 + if (IS_ERR(dec_params)) 235 + return PTR_ERR(dec_params); 236 + 237 + sps = mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_SPS); 238 + if (IS_ERR(sps)) 239 + return PTR_ERR(sps); 240 + 241 + pps = mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_PPS); 242 + if (IS_ERR(pps)) 243 + return PTR_ERR(pps); 244 + 245 + scaling_matrix = 246 + mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_SCALING_MATRIX); 247 + if (IS_ERR(scaling_matrix)) 248 + return PTR_ERR(scaling_matrix); 249 + 250 + mtk_vdec_h264_update_dpb(dec_params, inst->dpb); 251 + 252 + mtk_vdec_h264_copy_sps_params(&slice_param->sps, sps); 253 + mtk_vdec_h264_copy_pps_params(&slice_param->pps, pps); 254 + mtk_vdec_h264_copy_scaling_matrix(&slice_param->scaling_matrix, scaling_matrix); 255 + 256 + mtk_vdec_h264_copy_decode_params(&slice_param->decode_params, dec_params, inst->dpb); 257 + mtk_vdec_h264_fill_dpb_info(inst->ctx, &slice_param->decode_params, 258 + slice_param->h264_dpb_info); 259 + 260 + /* Build the reference lists */ 261 + v4l2_h264_init_reflist_builder(&reflist_builder, dec_params, sps, inst->dpb); 262 + v4l2_h264_build_p_ref_list(&reflist_builder, v4l2_p0_reflist); 263 + v4l2_h264_build_b_ref_lists(&reflist_builder, v4l2_b0_reflist, v4l2_b1_reflist); 264 + 265 + /* Adapt the built lists to the firmware's expectations */ 266 + mtk_vdec_h264_get_ref_list(p0_reflist, v4l2_p0_reflist, reflist_builder.num_valid); 267 + mtk_vdec_h264_get_ref_list(b0_reflist, v4l2_b0_reflist, reflist_builder.num_valid); 268 + mtk_vdec_h264_get_ref_list(b1_reflist, v4l2_b1_reflist, reflist_builder.num_valid); 269 + 270 + memcpy(&inst->vsi_ctx.h264_slice_params, slice_param, 271 + sizeof(inst->vsi_ctx.h264_slice_params)); 272 + 273 + return 0; 274 + } 275 + 276 + static void vdec_h264_slice_fill_decode_reflist(struct vdec_h264_slice_inst *inst, 277 + struct vdec_h264_slice_lat_dec_param *slice_param, 278 + struct vdec_h264_slice_share_info *share_info) 279 + { 280 + struct v4l2_ctrl_h264_decode_params *dec_params = &share_info->dec_params; 281 + struct v4l2_ctrl_h264_sps *sps = &share_info->sps; 282 + struct v4l2_h264_reflist_builder reflist_builder; 283 + struct v4l2_h264_reference v4l2_p0_reflist[V4L2_H264_REF_LIST_LEN]; 284 + struct v4l2_h264_reference v4l2_b0_reflist[V4L2_H264_REF_LIST_LEN]; 285 + struct v4l2_h264_reference v4l2_b1_reflist[V4L2_H264_REF_LIST_LEN]; 286 + u8 *p0_reflist = slice_param->decode_params.ref_pic_list_p0; 287 + u8 *b0_reflist = slice_param->decode_params.ref_pic_list_b0; 288 + u8 *b1_reflist = slice_param->decode_params.ref_pic_list_b1; 289 + 290 + mtk_vdec_h264_update_dpb(dec_params, inst->dpb); 291 + 292 + mtk_vdec_h264_copy_decode_params(&slice_param->decode_params, dec_params, 293 + inst->dpb); 294 + mtk_vdec_h264_fill_dpb_info(inst->ctx, &slice_param->decode_params, 295 + slice_param->h264_dpb_info); 296 + 297 + mtk_v4l2_debug(3, "cur poc = %d\n", dec_params->bottom_field_order_cnt); 298 + /* Build the reference lists */ 299 + v4l2_h264_init_reflist_builder(&reflist_builder, dec_params, sps, 300 + inst->dpb); 301 + v4l2_h264_build_p_ref_list(&reflist_builder, v4l2_p0_reflist); 302 + v4l2_h264_build_b_ref_lists(&reflist_builder, v4l2_b0_reflist, v4l2_b1_reflist); 303 + 304 + /* Adapt the built lists to the firmware's expectations */ 305 + mtk_vdec_h264_get_ref_list(p0_reflist, v4l2_p0_reflist, reflist_builder.num_valid); 306 + mtk_vdec_h264_get_ref_list(b0_reflist, v4l2_b0_reflist, reflist_builder.num_valid); 307 + mtk_vdec_h264_get_ref_list(b1_reflist, v4l2_b1_reflist, reflist_builder.num_valid); 308 + } 309 + 310 + static int vdec_h264_slice_alloc_mv_buf(struct vdec_h264_slice_inst *inst, 311 + struct vdec_pic_info *pic) 312 + { 313 + unsigned int buf_sz = mtk_vdec_h264_get_mv_buf_size(pic->buf_w, pic->buf_h); 314 + struct mtk_vcodec_mem *mem; 315 + int i, err; 316 + 317 + mtk_v4l2_debug(3, "size = 0x%x", buf_sz); 318 + for (i = 0; i < H264_MAX_MV_NUM; i++) { 319 + mem = &inst->mv_buf[i]; 320 + if (mem->va) 321 + mtk_vcodec_mem_free(inst->ctx, mem); 322 + mem->size = buf_sz; 323 + err = mtk_vcodec_mem_alloc(inst->ctx, mem); 324 + if (err) { 325 + mtk_vcodec_err(inst, "failed to allocate mv buf"); 326 + return err; 327 + } 328 + } 329 + 330 + return 0; 331 + } 332 + 333 + static void vdec_h264_slice_free_mv_buf(struct vdec_h264_slice_inst *inst) 334 + { 335 + int i; 336 + struct mtk_vcodec_mem *mem; 337 + 338 + for (i = 0; i < H264_MAX_MV_NUM; i++) { 339 + mem = &inst->mv_buf[i]; 340 + if (mem->va) 341 + mtk_vcodec_mem_free(inst->ctx, mem); 342 + } 343 + } 344 + 345 + static void vdec_h264_slice_get_pic_info(struct vdec_h264_slice_inst *inst) 346 + { 347 + struct mtk_vcodec_ctx *ctx = inst->ctx; 348 + u32 data[3]; 349 + 350 + data[0] = ctx->picinfo.pic_w; 351 + data[1] = ctx->picinfo.pic_h; 352 + data[2] = ctx->capture_fourcc; 353 + vpu_dec_get_param(&inst->vpu, data, 3, GET_PARAM_PIC_INFO); 354 + 355 + ctx->picinfo.buf_w = ALIGN(ctx->picinfo.pic_w, VCODEC_DEC_ALIGNED_64); 356 + ctx->picinfo.buf_h = ALIGN(ctx->picinfo.pic_h, VCODEC_DEC_ALIGNED_64); 357 + ctx->picinfo.fb_sz[0] = inst->vpu.fb_sz[0]; 358 + ctx->picinfo.fb_sz[1] = inst->vpu.fb_sz[1]; 359 + inst->cap_num_planes = 360 + ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes; 361 + 362 + mtk_vcodec_debug(inst, "pic(%d, %d), buf(%d, %d)", 363 + ctx->picinfo.pic_w, ctx->picinfo.pic_h, 364 + ctx->picinfo.buf_w, ctx->picinfo.buf_h); 365 + mtk_vcodec_debug(inst, "Y/C(%d, %d)", ctx->picinfo.fb_sz[0], 366 + ctx->picinfo.fb_sz[1]); 367 + 368 + if (ctx->last_decoded_picinfo.pic_w != ctx->picinfo.pic_w || 369 + ctx->last_decoded_picinfo.pic_h != ctx->picinfo.pic_h) { 370 + inst->resolution_changed = true; 371 + if (ctx->last_decoded_picinfo.buf_w != ctx->picinfo.buf_w || 372 + ctx->last_decoded_picinfo.buf_h != ctx->picinfo.buf_h) 373 + inst->realloc_mv_buf = true; 374 + 375 + mtk_v4l2_debug(1, "resChg: (%d %d) : old(%d, %d) -> new(%d, %d)", 376 + inst->resolution_changed, 377 + inst->realloc_mv_buf, 378 + ctx->last_decoded_picinfo.pic_w, 379 + ctx->last_decoded_picinfo.pic_h, 380 + ctx->picinfo.pic_w, ctx->picinfo.pic_h); 381 + } 382 + } 383 + 384 + static void vdec_h264_slice_get_crop_info(struct vdec_h264_slice_inst *inst, 385 + struct v4l2_rect *cr) 386 + { 387 + cr->left = 0; 388 + cr->top = 0; 389 + cr->width = inst->ctx->picinfo.pic_w; 390 + cr->height = inst->ctx->picinfo.pic_h; 391 + 392 + mtk_vcodec_debug(inst, "l=%d, t=%d, w=%d, h=%d", 393 + cr->left, cr->top, cr->width, cr->height); 394 + } 395 + 396 + static int vdec_h264_slice_init(struct mtk_vcodec_ctx *ctx) 397 + { 398 + struct vdec_h264_slice_inst *inst; 399 + int err, vsi_size; 400 + 401 + inst = kzalloc(sizeof(*inst), GFP_KERNEL); 402 + if (!inst) 403 + return -ENOMEM; 404 + 405 + inst->ctx = ctx; 406 + 407 + inst->vpu.id = SCP_IPI_VDEC_LAT; 408 + inst->vpu.core_id = SCP_IPI_VDEC_CORE; 409 + inst->vpu.ctx = ctx; 410 + inst->vpu.codec_type = ctx->current_codec; 411 + inst->vpu.capture_type = ctx->capture_fourcc; 412 + 413 + err = vpu_dec_init(&inst->vpu); 414 + if (err) { 415 + mtk_vcodec_err(inst, "vdec_h264 init err=%d", err); 416 + goto error_free_inst; 417 + } 418 + 419 + vsi_size = round_up(sizeof(struct vdec_h264_slice_vsi), VCODEC_DEC_ALIGNED_64); 420 + inst->vsi = inst->vpu.vsi; 421 + inst->vsi_core = 422 + (struct vdec_h264_slice_vsi *)(((char *)inst->vpu.vsi) + vsi_size); 423 + inst->resolution_changed = true; 424 + inst->realloc_mv_buf = true; 425 + 426 + mtk_vcodec_debug(inst, "lat struct size = %d,%d,%d,%d vsi: %d\n", 427 + (int)sizeof(struct mtk_h264_sps_param), 428 + (int)sizeof(struct mtk_h264_pps_param), 429 + (int)sizeof(struct vdec_h264_slice_lat_dec_param), 430 + (int)sizeof(struct mtk_h264_dpb_info), 431 + vsi_size); 432 + mtk_vcodec_debug(inst, "lat H264 instance >> %p, codec_type = 0x%x", 433 + inst, inst->vpu.codec_type); 434 + 435 + ctx->drv_handle = inst; 436 + return 0; 437 + 438 + error_free_inst: 439 + kfree(inst); 440 + return err; 441 + } 442 + 443 + static void vdec_h264_slice_deinit(void *h_vdec) 444 + { 445 + struct vdec_h264_slice_inst *inst = h_vdec; 446 + 447 + mtk_vcodec_debug_enter(inst); 448 + 449 + vpu_dec_deinit(&inst->vpu); 450 + vdec_h264_slice_free_mv_buf(inst); 451 + vdec_msg_queue_deinit(&inst->ctx->msg_queue, inst->ctx); 452 + 453 + kfree(inst); 454 + } 455 + 456 + static int vdec_h264_slice_core_decode(struct vdec_lat_buf *lat_buf) 457 + { 458 + struct vdec_fb *fb; 459 + u64 vdec_fb_va; 460 + u64 y_fb_dma, c_fb_dma; 461 + int err, timeout, i; 462 + struct mtk_vcodec_ctx *ctx = lat_buf->ctx; 463 + struct vdec_h264_slice_inst *inst = ctx->drv_handle; 464 + struct vb2_v4l2_buffer *vb2_v4l2; 465 + struct vdec_h264_slice_share_info *share_info = lat_buf->private_data; 466 + struct mtk_vcodec_mem *mem; 467 + struct vdec_vpu_inst *vpu = &inst->vpu; 468 + 469 + mtk_vcodec_debug(inst, "[h264-core] vdec_h264 core decode"); 470 + memcpy(&inst->vsi_core->h264_slice_params, &share_info->h264_slice_params, 471 + sizeof(share_info->h264_slice_params)); 472 + 473 + fb = ctx->dev->vdec_pdata->get_cap_buffer(ctx); 474 + y_fb_dma = fb ? (u64)fb->base_y.dma_addr : 0; 475 + vdec_fb_va = (unsigned long)fb; 476 + 477 + if (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes == 1) 478 + c_fb_dma = 479 + y_fb_dma + inst->ctx->picinfo.buf_w * inst->ctx->picinfo.buf_h; 480 + else 481 + c_fb_dma = fb ? (u64)fb->base_c.dma_addr : 0; 482 + 483 + mtk_vcodec_debug(inst, "[h264-core] y/c addr = 0x%llx 0x%llx", y_fb_dma, 484 + c_fb_dma); 485 + 486 + inst->vsi_core->dec.y_fb_dma = y_fb_dma; 487 + inst->vsi_core->dec.c_fb_dma = c_fb_dma; 488 + inst->vsi_core->dec.vdec_fb_va = vdec_fb_va; 489 + inst->vsi_core->dec.nal_info = share_info->nal_info; 490 + inst->vsi_core->wdma_start_addr = 491 + lat_buf->ctx->msg_queue.wdma_addr.dma_addr; 492 + inst->vsi_core->wdma_end_addr = 493 + lat_buf->ctx->msg_queue.wdma_addr.dma_addr + 494 + lat_buf->ctx->msg_queue.wdma_addr.size; 495 + inst->vsi_core->wdma_err_addr = lat_buf->wdma_err_addr.dma_addr; 496 + inst->vsi_core->slice_bc_start_addr = lat_buf->slice_bc_addr.dma_addr; 497 + inst->vsi_core->slice_bc_end_addr = lat_buf->slice_bc_addr.dma_addr + 498 + lat_buf->slice_bc_addr.size; 499 + inst->vsi_core->trans_start = share_info->trans_start; 500 + inst->vsi_core->trans_end = share_info->trans_end; 501 + for (i = 0; i < H264_MAX_MV_NUM; i++) { 502 + mem = &inst->mv_buf[i]; 503 + inst->vsi_core->mv_buf_dma[i] = mem->dma_addr; 504 + } 505 + 506 + vb2_v4l2 = v4l2_m2m_next_dst_buf(ctx->m2m_ctx); 507 + v4l2_m2m_buf_copy_metadata(&lat_buf->ts_info, vb2_v4l2, true); 508 + 509 + vdec_h264_slice_fill_decode_reflist(inst, &inst->vsi_core->h264_slice_params, 510 + share_info); 511 + 512 + err = vpu_dec_core(vpu); 513 + if (err) { 514 + mtk_vcodec_err(inst, "core decode err=%d", err); 515 + goto vdec_dec_end; 516 + } 517 + 518 + /* wait decoder done interrupt */ 519 + timeout = mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED, 520 + WAIT_INTR_TIMEOUT_MS, MTK_VDEC_CORE); 521 + if (timeout) 522 + mtk_vcodec_err(inst, "core decode timeout: pic_%d", 523 + ctx->decoded_frame_cnt); 524 + inst->vsi_core->dec.timeout = !!timeout; 525 + 526 + vpu_dec_core_end(vpu); 527 + mtk_vcodec_debug(inst, "pic[%d] crc: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x", 528 + ctx->decoded_frame_cnt, 529 + inst->vsi_core->dec.crc[0], inst->vsi_core->dec.crc[1], 530 + inst->vsi_core->dec.crc[2], inst->vsi_core->dec.crc[3], 531 + inst->vsi_core->dec.crc[4], inst->vsi_core->dec.crc[5], 532 + inst->vsi_core->dec.crc[6], inst->vsi_core->dec.crc[7]); 533 + 534 + vdec_dec_end: 535 + vdec_msg_queue_update_ube_rptr(&lat_buf->ctx->msg_queue, share_info->trans_end); 536 + ctx->dev->vdec_pdata->cap_to_disp(ctx, !!err, lat_buf->src_buf_req); 537 + mtk_vcodec_debug(inst, "core decode done err=%d", err); 538 + ctx->decoded_frame_cnt++; 539 + return 0; 540 + } 541 + 542 + static int vdec_h264_slice_lat_decode(void *h_vdec, struct mtk_vcodec_mem *bs, 543 + struct vdec_fb *fb, bool *res_chg) 544 + { 545 + struct vdec_h264_slice_inst *inst = h_vdec; 546 + struct vdec_vpu_inst *vpu = &inst->vpu; 547 + struct mtk_video_dec_buf *src_buf_info; 548 + int nal_start_idx, err, timeout = 0, i; 549 + unsigned int data[2]; 550 + struct vdec_lat_buf *lat_buf; 551 + struct vdec_h264_slice_share_info *share_info; 552 + unsigned char *buf; 553 + struct mtk_vcodec_mem *mem; 554 + 555 + if (vdec_msg_queue_init(&inst->ctx->msg_queue, inst->ctx, 556 + vdec_h264_slice_core_decode, 557 + sizeof(*share_info))) 558 + return -ENOMEM; 559 + 560 + /* bs NULL means flush decoder */ 561 + if (!bs) { 562 + vdec_msg_queue_wait_lat_buf_full(&inst->ctx->msg_queue); 563 + return vpu_dec_reset(vpu); 564 + } 565 + 566 + if (inst->is_field_bitstream) 567 + return -EINVAL; 568 + 569 + lat_buf = vdec_msg_queue_dqbuf(&inst->ctx->msg_queue.lat_ctx); 570 + if (!lat_buf) { 571 + mtk_vcodec_err(inst, "failed to get lat buffer"); 572 + return -EINVAL; 573 + } 574 + share_info = lat_buf->private_data; 575 + src_buf_info = container_of(bs, struct mtk_video_dec_buf, bs_buffer); 576 + 577 + buf = (unsigned char *)bs->va; 578 + nal_start_idx = mtk_vdec_h264_find_start_code(buf, bs->size); 579 + if (nal_start_idx < 0) { 580 + err = -EINVAL; 581 + goto err_free_fb_out; 582 + } 583 + 584 + inst->vsi->dec.nal_info = buf[nal_start_idx]; 585 + inst->vsi->dec.bs_buf_addr = (u64)bs->dma_addr; 586 + inst->vsi->dec.bs_buf_size = bs->size; 587 + 588 + lat_buf->src_buf_req = src_buf_info->m2m_buf.vb.vb2_buf.req_obj.req; 589 + v4l2_m2m_buf_copy_metadata(&src_buf_info->m2m_buf.vb, &lat_buf->ts_info, true); 590 + 591 + err = vdec_h264_slice_fill_decode_parameters(inst, share_info); 592 + if (err) 593 + goto err_free_fb_out; 594 + 595 + *res_chg = inst->resolution_changed; 596 + if (inst->resolution_changed) { 597 + mtk_vcodec_debug(inst, "- resolution changed -"); 598 + if (inst->realloc_mv_buf) { 599 + err = vdec_h264_slice_alloc_mv_buf(inst, &inst->ctx->picinfo); 600 + inst->realloc_mv_buf = false; 601 + if (err) 602 + goto err_free_fb_out; 603 + } 604 + inst->resolution_changed = false; 605 + } 606 + for (i = 0; i < H264_MAX_MV_NUM; i++) { 607 + mem = &inst->mv_buf[i]; 608 + inst->vsi->mv_buf_dma[i] = mem->dma_addr; 609 + } 610 + inst->vsi->wdma_start_addr = lat_buf->ctx->msg_queue.wdma_addr.dma_addr; 611 + inst->vsi->wdma_end_addr = lat_buf->ctx->msg_queue.wdma_addr.dma_addr + 612 + lat_buf->ctx->msg_queue.wdma_addr.size; 613 + inst->vsi->wdma_err_addr = lat_buf->wdma_err_addr.dma_addr; 614 + inst->vsi->slice_bc_start_addr = lat_buf->slice_bc_addr.dma_addr; 615 + inst->vsi->slice_bc_end_addr = lat_buf->slice_bc_addr.dma_addr + 616 + lat_buf->slice_bc_addr.size; 617 + 618 + inst->vsi->trans_end = inst->ctx->msg_queue.wdma_rptr_addr; 619 + inst->vsi->trans_start = inst->ctx->msg_queue.wdma_wptr_addr; 620 + mtk_vcodec_debug(inst, "lat:trans(0x%llx 0x%llx) err:0x%llx", 621 + inst->vsi->wdma_start_addr, 622 + inst->vsi->wdma_end_addr, 623 + inst->vsi->wdma_err_addr); 624 + 625 + mtk_vcodec_debug(inst, "slice(0x%llx 0x%llx) rprt((0x%llx 0x%llx))", 626 + inst->vsi->slice_bc_start_addr, 627 + inst->vsi->slice_bc_end_addr, 628 + inst->vsi->trans_start, 629 + inst->vsi->trans_end); 630 + err = vpu_dec_start(vpu, data, 2); 631 + if (err) { 632 + mtk_vcodec_debug(inst, "lat decode err: %d", err); 633 + goto err_scp_decode; 634 + } 635 + 636 + /* wait decoder done interrupt */ 637 + timeout = mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED, 638 + WAIT_INTR_TIMEOUT_MS, MTK_VDEC_LAT0); 639 + inst->vsi->dec.timeout = !!timeout; 640 + 641 + err = vpu_dec_end(vpu); 642 + if (err == SLICE_HEADER_FULL || timeout || err == TRANS_BUFFER_FULL) { 643 + err = -EINVAL; 644 + goto err_scp_decode; 645 + } 646 + 647 + share_info->trans_end = inst->ctx->msg_queue.wdma_addr.dma_addr + 648 + inst->vsi->wdma_end_addr_offset; 649 + share_info->trans_start = inst->ctx->msg_queue.wdma_wptr_addr; 650 + share_info->nal_info = inst->vsi->dec.nal_info; 651 + vdec_msg_queue_update_ube_wptr(&lat_buf->ctx->msg_queue, share_info->trans_end); 652 + 653 + memcpy(&share_info->h264_slice_params, &inst->vsi->h264_slice_params, 654 + sizeof(share_info->h264_slice_params)); 655 + vdec_msg_queue_qbuf(&inst->ctx->dev->msg_queue_core_ctx, lat_buf); 656 + 657 + inst->slice_dec_num++; 658 + return 0; 659 + 660 + err_scp_decode: 661 + err_free_fb_out: 662 + vdec_msg_queue_qbuf(&inst->ctx->msg_queue.lat_ctx, lat_buf); 663 + mtk_vcodec_err(inst, "slice dec number: %d err: %d", inst->slice_dec_num, err); 664 + return err; 665 + } 666 + 667 + static int vdec_h264_slice_single_decode(void *h_vdec, struct mtk_vcodec_mem *bs, 668 + struct vdec_fb *unused, bool *res_chg) 669 + { 670 + struct vdec_h264_slice_inst *inst = h_vdec; 671 + struct vdec_vpu_inst *vpu = &inst->vpu; 672 + struct mtk_video_dec_buf *src_buf_info, *dst_buf_info; 673 + struct vdec_fb *fb; 674 + unsigned char *buf; 675 + unsigned int data[2], i; 676 + u64 y_fb_dma, c_fb_dma; 677 + struct mtk_vcodec_mem *mem; 678 + int err, nal_start_idx; 679 + 680 + /* bs NULL means flush decoder */ 681 + if (!bs) 682 + return vpu_dec_reset(vpu); 683 + 684 + fb = inst->ctx->dev->vdec_pdata->get_cap_buffer(inst->ctx); 685 + src_buf_info = container_of(bs, struct mtk_video_dec_buf, bs_buffer); 686 + dst_buf_info = container_of(fb, struct mtk_video_dec_buf, frame_buffer); 687 + 688 + y_fb_dma = fb ? (u64)fb->base_y.dma_addr : 0; 689 + c_fb_dma = fb ? (u64)fb->base_c.dma_addr : 0; 690 + mtk_vcodec_debug(inst, "[h264-dec] [%d] y_dma=%llx c_dma=%llx", 691 + inst->ctx->decoded_frame_cnt, y_fb_dma, c_fb_dma); 692 + 693 + inst->vsi_ctx.dec.bs_buf_addr = (u64)bs->dma_addr; 694 + inst->vsi_ctx.dec.bs_buf_size = bs->size; 695 + inst->vsi_ctx.dec.y_fb_dma = y_fb_dma; 696 + inst->vsi_ctx.dec.c_fb_dma = c_fb_dma; 697 + inst->vsi_ctx.dec.vdec_fb_va = (u64)(uintptr_t)fb; 698 + 699 + v4l2_m2m_buf_copy_metadata(&src_buf_info->m2m_buf.vb, 700 + &dst_buf_info->m2m_buf.vb, true); 701 + err = get_vdec_sig_decode_parameters(inst); 702 + if (err) 703 + goto err_free_fb_out; 704 + 705 + buf = (unsigned char *)bs->va; 706 + nal_start_idx = mtk_vdec_h264_find_start_code(buf, bs->size); 707 + if (nal_start_idx < 0) { 708 + err = -EINVAL; 709 + goto err_free_fb_out; 710 + } 711 + inst->vsi_ctx.dec.nal_info = buf[nal_start_idx]; 712 + 713 + *res_chg = inst->resolution_changed; 714 + if (inst->resolution_changed) { 715 + mtk_vcodec_debug(inst, "- resolution changed -"); 716 + if (inst->realloc_mv_buf) { 717 + err = vdec_h264_slice_alloc_mv_buf(inst, &inst->ctx->picinfo); 718 + inst->realloc_mv_buf = false; 719 + if (err) 720 + goto err_free_fb_out; 721 + } 722 + inst->resolution_changed = false; 723 + 724 + for (i = 0; i < H264_MAX_MV_NUM; i++) { 725 + mem = &inst->mv_buf[i]; 726 + inst->vsi_ctx.mv_buf_dma[i] = mem->dma_addr; 727 + } 728 + } 729 + 730 + memcpy(inst->vpu.vsi, &inst->vsi_ctx, sizeof(inst->vsi_ctx)); 731 + err = vpu_dec_start(vpu, data, 2); 732 + if (err) 733 + goto err_free_fb_out; 734 + 735 + /* wait decoder done interrupt */ 736 + err = mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED, 737 + WAIT_INTR_TIMEOUT_MS, MTK_VDEC_CORE); 738 + if (err) 739 + mtk_vcodec_err(inst, "decode timeout: pic_%d", 740 + inst->ctx->decoded_frame_cnt); 741 + 742 + inst->vsi->dec.timeout = !!err; 743 + err = vpu_dec_end(vpu); 744 + if (err) 745 + goto err_free_fb_out; 746 + 747 + memcpy(&inst->vsi_ctx, inst->vpu.vsi, sizeof(inst->vsi_ctx)); 748 + mtk_vcodec_debug(inst, "pic[%d] crc: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x", 749 + inst->ctx->decoded_frame_cnt, 750 + inst->vsi_ctx.dec.crc[0], inst->vsi_ctx.dec.crc[1], 751 + inst->vsi_ctx.dec.crc[2], inst->vsi_ctx.dec.crc[3], 752 + inst->vsi_ctx.dec.crc[4], inst->vsi_ctx.dec.crc[5], 753 + inst->vsi_ctx.dec.crc[6], inst->vsi_ctx.dec.crc[7]); 754 + 755 + inst->ctx->decoded_frame_cnt++; 756 + return 0; 757 + 758 + err_free_fb_out: 759 + mtk_vcodec_err(inst, "dec frame number: %d err: %d", 760 + inst->ctx->decoded_frame_cnt, err); 761 + return err; 762 + } 763 + 764 + static int vdec_h264_slice_decode(void *h_vdec, struct mtk_vcodec_mem *bs, 765 + struct vdec_fb *unused, bool *res_chg) 766 + { 767 + struct vdec_h264_slice_inst *inst = h_vdec; 768 + int ret; 769 + 770 + if (!h_vdec) 771 + return -EINVAL; 772 + 773 + if (inst->ctx->dev->vdec_pdata->hw_arch == MTK_VDEC_PURE_SINGLE_CORE) 774 + ret = vdec_h264_slice_single_decode(h_vdec, bs, unused, res_chg); 775 + else 776 + ret = vdec_h264_slice_lat_decode(h_vdec, bs, unused, res_chg); 777 + 778 + return ret; 779 + } 780 + 781 + static int vdec_h264_slice_get_param(void *h_vdec, enum vdec_get_param_type type, 782 + void *out) 783 + { 784 + struct vdec_h264_slice_inst *inst = h_vdec; 785 + 786 + switch (type) { 787 + case GET_PARAM_PIC_INFO: 788 + vdec_h264_slice_get_pic_info(inst); 789 + break; 790 + case GET_PARAM_DPB_SIZE: 791 + *(unsigned int *)out = 6; 792 + break; 793 + case GET_PARAM_CROP_INFO: 794 + vdec_h264_slice_get_crop_info(inst, out); 795 + break; 796 + default: 797 + mtk_vcodec_err(inst, "invalid get parameter type=%d", type); 798 + return -EINVAL; 799 + } 800 + return 0; 801 + } 802 + 803 + const struct vdec_common_if vdec_h264_slice_multi_if = { 804 + .init = vdec_h264_slice_init, 805 + .decode = vdec_h264_slice_decode, 806 + .get_param = vdec_h264_slice_get_param, 807 + .deinit = vdec_h264_slice_deinit, 808 + };

+437

drivers/media/platform/mediatek/vcodec/vdec/vdec_vp8_req_if.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Copyright (c) 2021 MediaTek Inc. 4 + * Author: Yunfei Dong <yunfei.dong@mediatek.com> 5 + */ 6 + 7 + #include <linux/slab.h> 8 + #include <media/v4l2-mem2mem.h> 9 + #include <media/videobuf2-dma-contig.h> 10 + #include <uapi/linux/v4l2-controls.h> 11 + 12 + #include "../mtk_vcodec_util.h" 13 + #include "../mtk_vcodec_dec.h" 14 + #include "../mtk_vcodec_intr.h" 15 + #include "../vdec_drv_base.h" 16 + #include "../vdec_drv_if.h" 17 + #include "../vdec_vpu_if.h" 18 + 19 + /* Decoding picture buffer size (3 reference frames plus current frame) */ 20 + #define VP8_DPB_SIZE 4 21 + 22 + /* HW working buffer size (bytes) */ 23 + #define VP8_SEG_ID_SZ SZ_256K 24 + #define VP8_PP_WRAPY_SZ SZ_64K 25 + #define VP8_PP_WRAPC_SZ SZ_64K 26 + #define VP8_VLD_PRED_SZ SZ_64K 27 + 28 + /** 29 + * struct vdec_vp8_slice_info - decode misc information 30 + * 31 + * @vld_wrapper_dma: vld wrapper dma address 32 + * @seg_id_buf_dma: seg id dma address 33 + * @wrap_y_dma: wrap y dma address 34 + * @wrap_c_dma: wrap y dma address 35 + * @cur_y_fb_dma: current plane Y frame buffer dma address 36 + * @cur_c_fb_dma: current plane C frame buffer dma address 37 + * @bs_dma: bitstream dma address 38 + * @bs_sz: bitstream size 39 + * @resolution_changed:resolution change flag 1 - changed, 0 - not change 40 + * @frame_header_type: current frame header type 41 + * @wait_key_frame: wait key frame coming 42 + * @crc: used to check whether hardware's status is right 43 + * @reserved: reserved, currently unused 44 + */ 45 + struct vdec_vp8_slice_info { 46 + u64 vld_wrapper_dma; 47 + u64 seg_id_buf_dma; 48 + u64 wrap_y_dma; 49 + u64 wrap_c_dma; 50 + u64 cur_y_fb_dma; 51 + u64 cur_c_fb_dma; 52 + u64 bs_dma; 53 + u32 bs_sz; 54 + u32 resolution_changed; 55 + u32 frame_header_type; 56 + u32 crc[8]; 57 + u32 reserved; 58 + }; 59 + 60 + /** 61 + * struct vdec_vp8_slice_dpb_info - vp8 reference information 62 + * 63 + * @y_dma_addr: Y bitstream physical address 64 + * @c_dma_addr: CbCr bitstream physical address 65 + * @reference_flag: reference picture flag 66 + * @reserved: 64bit align 67 + */ 68 + struct vdec_vp8_slice_dpb_info { 69 + dma_addr_t y_dma_addr; 70 + dma_addr_t c_dma_addr; 71 + int reference_flag; 72 + int reserved; 73 + }; 74 + 75 + /** 76 + * struct vdec_vp8_slice_vsi - VPU shared information 77 + * 78 + * @dec: decoding information 79 + * @pic: picture information 80 + * @vp8_dpb_info: reference buffer information 81 + */ 82 + struct vdec_vp8_slice_vsi { 83 + struct vdec_vp8_slice_info dec; 84 + struct vdec_pic_info pic; 85 + struct vdec_vp8_slice_dpb_info vp8_dpb_info[3]; 86 + }; 87 + 88 + /** 89 + * struct vdec_vp8_slice_inst - VP8 decoder instance 90 + * 91 + * @seg_id_buf: seg buffer 92 + * @wrap_y_buf: wrapper y buffer 93 + * @wrap_c_buf: wrapper c buffer 94 + * @vld_wrapper_buf: vld wrapper buffer 95 + * @ctx: V4L2 context 96 + * @vpu: VPU instance for decoder 97 + * @vsi: VPU share information 98 + */ 99 + struct vdec_vp8_slice_inst { 100 + struct mtk_vcodec_mem seg_id_buf; 101 + struct mtk_vcodec_mem wrap_y_buf; 102 + struct mtk_vcodec_mem wrap_c_buf; 103 + struct mtk_vcodec_mem vld_wrapper_buf; 104 + struct mtk_vcodec_ctx *ctx; 105 + struct vdec_vpu_inst vpu; 106 + struct vdec_vp8_slice_vsi *vsi; 107 + }; 108 + 109 + static void *vdec_vp8_slice_get_ctrl_ptr(struct mtk_vcodec_ctx *ctx, int id) 110 + { 111 + struct v4l2_ctrl *ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, id); 112 + 113 + if (!ctrl) 114 + return ERR_PTR(-EINVAL); 115 + 116 + return ctrl->p_cur.p; 117 + } 118 + 119 + static void vdec_vp8_slice_get_pic_info(struct vdec_vp8_slice_inst *inst) 120 + { 121 + struct mtk_vcodec_ctx *ctx = inst->ctx; 122 + unsigned int data[3]; 123 + 124 + data[0] = ctx->picinfo.pic_w; 125 + data[1] = ctx->picinfo.pic_h; 126 + data[2] = ctx->capture_fourcc; 127 + vpu_dec_get_param(&inst->vpu, data, 3, GET_PARAM_PIC_INFO); 128 + 129 + ctx->picinfo.buf_w = ALIGN(ctx->picinfo.pic_w, 64); 130 + ctx->picinfo.buf_h = ALIGN(ctx->picinfo.pic_h, 64); 131 + ctx->picinfo.fb_sz[0] = inst->vpu.fb_sz[0]; 132 + ctx->picinfo.fb_sz[1] = inst->vpu.fb_sz[1]; 133 + 134 + inst->vsi->pic.pic_w = ctx->picinfo.pic_w; 135 + inst->vsi->pic.pic_h = ctx->picinfo.pic_h; 136 + inst->vsi->pic.buf_w = ctx->picinfo.buf_w; 137 + inst->vsi->pic.buf_h = ctx->picinfo.buf_h; 138 + inst->vsi->pic.fb_sz[0] = ctx->picinfo.fb_sz[0]; 139 + inst->vsi->pic.fb_sz[1] = ctx->picinfo.fb_sz[1]; 140 + mtk_vcodec_debug(inst, "pic(%d, %d), buf(%d, %d)", 141 + ctx->picinfo.pic_w, ctx->picinfo.pic_h, 142 + ctx->picinfo.buf_w, ctx->picinfo.buf_h); 143 + mtk_vcodec_debug(inst, "fb size: Y(%d), C(%d)", 144 + ctx->picinfo.fb_sz[0], ctx->picinfo.fb_sz[1]); 145 + } 146 + 147 + static int vdec_vp8_slice_alloc_working_buf(struct vdec_vp8_slice_inst *inst) 148 + { 149 + int err; 150 + struct mtk_vcodec_mem *mem; 151 + 152 + mem = &inst->seg_id_buf; 153 + mem->size = VP8_SEG_ID_SZ; 154 + err = mtk_vcodec_mem_alloc(inst->ctx, mem); 155 + if (err) { 156 + mtk_vcodec_err(inst, "Cannot allocate working buffer"); 157 + return err; 158 + } 159 + inst->vsi->dec.seg_id_buf_dma = (u64)mem->dma_addr; 160 + 161 + mem = &inst->wrap_y_buf; 162 + mem->size = VP8_PP_WRAPY_SZ; 163 + err = mtk_vcodec_mem_alloc(inst->ctx, mem); 164 + if (err) { 165 + mtk_vcodec_err(inst, "cannot allocate WRAP Y buffer"); 166 + return err; 167 + } 168 + inst->vsi->dec.wrap_y_dma = (u64)mem->dma_addr; 169 + 170 + mem = &inst->wrap_c_buf; 171 + mem->size = VP8_PP_WRAPC_SZ; 172 + err = mtk_vcodec_mem_alloc(inst->ctx, mem); 173 + if (err) { 174 + mtk_vcodec_err(inst, "cannot allocate WRAP C buffer"); 175 + return err; 176 + } 177 + inst->vsi->dec.wrap_c_dma = (u64)mem->dma_addr; 178 + 179 + mem = &inst->vld_wrapper_buf; 180 + mem->size = VP8_VLD_PRED_SZ; 181 + err = mtk_vcodec_mem_alloc(inst->ctx, mem); 182 + if (err) { 183 + mtk_vcodec_err(inst, "cannot allocate vld wrapper buffer"); 184 + return err; 185 + } 186 + inst->vsi->dec.vld_wrapper_dma = (u64)mem->dma_addr; 187 + 188 + return 0; 189 + } 190 + 191 + static void vdec_vp8_slice_free_working_buf(struct vdec_vp8_slice_inst *inst) 192 + { 193 + struct mtk_vcodec_mem *mem; 194 + 195 + mem = &inst->seg_id_buf; 196 + if (mem->va) 197 + mtk_vcodec_mem_free(inst->ctx, mem); 198 + inst->vsi->dec.seg_id_buf_dma = 0; 199 + 200 + mem = &inst->wrap_y_buf; 201 + if (mem->va) 202 + mtk_vcodec_mem_free(inst->ctx, mem); 203 + inst->vsi->dec.wrap_y_dma = 0; 204 + 205 + mem = &inst->wrap_c_buf; 206 + if (mem->va) 207 + mtk_vcodec_mem_free(inst->ctx, mem); 208 + inst->vsi->dec.wrap_c_dma = 0; 209 + 210 + mem = &inst->vld_wrapper_buf; 211 + if (mem->va) 212 + mtk_vcodec_mem_free(inst->ctx, mem); 213 + inst->vsi->dec.vld_wrapper_dma = 0; 214 + } 215 + 216 + static u64 vdec_vp8_slice_get_ref_by_ts(const struct v4l2_ctrl_vp8_frame *frame_header, 217 + int index) 218 + { 219 + switch (index) { 220 + case 0: 221 + return frame_header->last_frame_ts; 222 + case 1: 223 + return frame_header->golden_frame_ts; 224 + case 2: 225 + return frame_header->alt_frame_ts; 226 + default: 227 + break; 228 + } 229 + 230 + return -1; 231 + } 232 + 233 + static int vdec_vp8_slice_get_decode_parameters(struct vdec_vp8_slice_inst *inst) 234 + { 235 + const struct v4l2_ctrl_vp8_frame *frame_header; 236 + struct mtk_vcodec_ctx *ctx = inst->ctx; 237 + struct vb2_queue *vq; 238 + struct vb2_buffer *vb; 239 + u64 referenct_ts; 240 + int index, vb2_index; 241 + 242 + frame_header = vdec_vp8_slice_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_VP8_FRAME); 243 + if (IS_ERR(frame_header)) 244 + return PTR_ERR(frame_header); 245 + 246 + vq = v4l2_m2m_get_vq(ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); 247 + for (index = 0; index < 3; index++) { 248 + referenct_ts = vdec_vp8_slice_get_ref_by_ts(frame_header, index); 249 + vb2_index = vb2_find_timestamp(vq, referenct_ts, 0); 250 + if (vb2_index < 0) { 251 + if (!V4L2_VP8_FRAME_IS_KEY_FRAME(frame_header)) 252 + mtk_vcodec_err(inst, "reference invalid: index(%d) ts(%lld)", 253 + index, referenct_ts); 254 + inst->vsi->vp8_dpb_info[index].reference_flag = 0; 255 + continue; 256 + } 257 + inst->vsi->vp8_dpb_info[index].reference_flag = 1; 258 + 259 + vb = vq->bufs[vb2_index]; 260 + inst->vsi->vp8_dpb_info[index].y_dma_addr = 261 + vb2_dma_contig_plane_dma_addr(vb, 0); 262 + if (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes == 2) 263 + inst->vsi->vp8_dpb_info[index].c_dma_addr = 264 + vb2_dma_contig_plane_dma_addr(vb, 1); 265 + else 266 + inst->vsi->vp8_dpb_info[index].c_dma_addr = 267 + inst->vsi->vp8_dpb_info[index].y_dma_addr + 268 + ctx->picinfo.fb_sz[0]; 269 + } 270 + 271 + inst->vsi->dec.frame_header_type = frame_header->flags >> 1; 272 + 273 + return 0; 274 + } 275 + 276 + static int vdec_vp8_slice_init(struct mtk_vcodec_ctx *ctx) 277 + { 278 + struct vdec_vp8_slice_inst *inst; 279 + int err; 280 + 281 + inst = kzalloc(sizeof(*inst), GFP_KERNEL); 282 + if (!inst) 283 + return -ENOMEM; 284 + 285 + inst->ctx = ctx; 286 + 287 + inst->vpu.id = SCP_IPI_VDEC_LAT; 288 + inst->vpu.core_id = SCP_IPI_VDEC_CORE; 289 + inst->vpu.ctx = ctx; 290 + inst->vpu.codec_type = ctx->current_codec; 291 + inst->vpu.capture_type = ctx->capture_fourcc; 292 + 293 + err = vpu_dec_init(&inst->vpu); 294 + if (err) { 295 + mtk_vcodec_err(inst, "vdec_vp8 init err=%d", err); 296 + goto error_free_inst; 297 + } 298 + 299 + inst->vsi = inst->vpu.vsi; 300 + err = vdec_vp8_slice_alloc_working_buf(inst); 301 + if (err) 302 + goto error_deinit; 303 + 304 + mtk_vcodec_debug(inst, "vp8 struct size = %d vsi: %d\n", 305 + (int)sizeof(struct v4l2_ctrl_vp8_frame), 306 + (int)sizeof(struct vdec_vp8_slice_vsi)); 307 + mtk_vcodec_debug(inst, "vp8:%p, codec_type = 0x%x vsi: 0x%p", 308 + inst, inst->vpu.codec_type, inst->vpu.vsi); 309 + 310 + ctx->drv_handle = inst; 311 + return 0; 312 + 313 + error_deinit: 314 + vpu_dec_deinit(&inst->vpu); 315 + error_free_inst: 316 + kfree(inst); 317 + return err; 318 + } 319 + 320 + static int vdec_vp8_slice_decode(void *h_vdec, struct mtk_vcodec_mem *bs, 321 + struct vdec_fb *fb, bool *res_chg) 322 + { 323 + struct vdec_vp8_slice_inst *inst = h_vdec; 324 + struct vdec_vpu_inst *vpu = &inst->vpu; 325 + struct mtk_video_dec_buf *src_buf_info, *dst_buf_info; 326 + unsigned int data; 327 + u64 y_fb_dma, c_fb_dma; 328 + int err, timeout; 329 + 330 + /* Resolution changes are never initiated by us */ 331 + *res_chg = false; 332 + 333 + /* bs NULL means flush decoder */ 334 + if (!bs) 335 + return vpu_dec_reset(vpu); 336 + 337 + src_buf_info = container_of(bs, struct mtk_video_dec_buf, bs_buffer); 338 + 339 + fb = inst->ctx->dev->vdec_pdata->get_cap_buffer(inst->ctx); 340 + dst_buf_info = container_of(fb, struct mtk_video_dec_buf, frame_buffer); 341 + 342 + y_fb_dma = fb ? (u64)fb->base_y.dma_addr : 0; 343 + if (inst->ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes == 1) 344 + c_fb_dma = y_fb_dma + 345 + inst->ctx->picinfo.buf_w * inst->ctx->picinfo.buf_h; 346 + else 347 + c_fb_dma = fb ? (u64)fb->base_c.dma_addr : 0; 348 + 349 + inst->vsi->dec.bs_dma = (u64)bs->dma_addr; 350 + inst->vsi->dec.bs_sz = bs->size; 351 + inst->vsi->dec.cur_y_fb_dma = y_fb_dma; 352 + inst->vsi->dec.cur_c_fb_dma = c_fb_dma; 353 + 354 + mtk_vcodec_debug(inst, "frame[%d] bs(%zu 0x%llx) y/c(0x%llx 0x%llx)", 355 + inst->ctx->decoded_frame_cnt, 356 + bs->size, (u64)bs->dma_addr, 357 + y_fb_dma, c_fb_dma); 358 + 359 + v4l2_m2m_buf_copy_metadata(&src_buf_info->m2m_buf.vb, 360 + &dst_buf_info->m2m_buf.vb, true); 361 + 362 + err = vdec_vp8_slice_get_decode_parameters(inst); 363 + if (err) 364 + goto error; 365 + 366 + err = vpu_dec_start(vpu, &data, 1); 367 + if (err) { 368 + mtk_vcodec_debug(inst, "vp8 dec start err!"); 369 + goto error; 370 + } 371 + 372 + if (inst->vsi->dec.resolution_changed) { 373 + mtk_vcodec_debug(inst, "- resolution_changed -"); 374 + *res_chg = true; 375 + return 0; 376 + } 377 + 378 + /* wait decode done interrupt */ 379 + timeout = mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED, 380 + 50, MTK_VDEC_CORE); 381 + 382 + err = vpu_dec_end(vpu); 383 + if (err || timeout) 384 + mtk_vcodec_debug(inst, "vp8 dec error timeout:%d err: %d pic_%d", 385 + timeout, err, inst->ctx->decoded_frame_cnt); 386 + 387 + mtk_vcodec_debug(inst, "pic[%d] crc: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x", 388 + inst->ctx->decoded_frame_cnt, 389 + inst->vsi->dec.crc[0], inst->vsi->dec.crc[1], 390 + inst->vsi->dec.crc[2], inst->vsi->dec.crc[3], 391 + inst->vsi->dec.crc[4], inst->vsi->dec.crc[5], 392 + inst->vsi->dec.crc[6], inst->vsi->dec.crc[7]); 393 + 394 + inst->ctx->decoded_frame_cnt++; 395 + error: 396 + return err; 397 + } 398 + 399 + static int vdec_vp8_slice_get_param(void *h_vdec, enum vdec_get_param_type type, void *out) 400 + { 401 + struct vdec_vp8_slice_inst *inst = h_vdec; 402 + 403 + switch (type) { 404 + case GET_PARAM_PIC_INFO: 405 + vdec_vp8_slice_get_pic_info(inst); 406 + break; 407 + case GET_PARAM_CROP_INFO: 408 + mtk_vcodec_debug(inst, "No need to get vp8 crop information."); 409 + break; 410 + case GET_PARAM_DPB_SIZE: 411 + *((unsigned int *)out) = VP8_DPB_SIZE; 412 + break; 413 + default: 414 + mtk_vcodec_err(inst, "invalid get parameter type=%d", type); 415 + return -EINVAL; 416 + } 417 + 418 + return 0; 419 + } 420 + 421 + static void vdec_vp8_slice_deinit(void *h_vdec) 422 + { 423 + struct vdec_vp8_slice_inst *inst = h_vdec; 424 + 425 + mtk_vcodec_debug_enter(inst); 426 + 427 + vpu_dec_deinit(&inst->vpu); 428 + vdec_vp8_slice_free_working_buf(inst); 429 + kfree(inst); 430 + } 431 + 432 + const struct vdec_common_if vdec_vp8_slice_if = { 433 + .init = vdec_vp8_slice_init, 434 + .decode = vdec_vp8_slice_decode, 435 + .get_param = vdec_vp8_slice_get_param, 436 + .deinit = vdec_vp8_slice_deinit, 437 + };

+2030

drivers/media/platform/mediatek/vcodec/vdec/vdec_vp9_req_lat_if.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Copyright (c) 2021 MediaTek Inc. 4 + * Author: George Sun <george.sun@mediatek.com> 5 + */ 6 + 7 + #include <linux/module.h> 8 + #include <linux/slab.h> 9 + #include <media/videobuf2-dma-contig.h> 10 + #include <media/v4l2-vp9.h> 11 + 12 + #include "../mtk_vcodec_util.h" 13 + #include "../mtk_vcodec_dec.h" 14 + #include "../mtk_vcodec_intr.h" 15 + #include "../vdec_drv_base.h" 16 + #include "../vdec_drv_if.h" 17 + #include "../vdec_vpu_if.h" 18 + 19 + /* reset_frame_context defined in VP9 spec */ 20 + #define VP9_RESET_FRAME_CONTEXT_NONE0 0 21 + #define VP9_RESET_FRAME_CONTEXT_NONE1 1 22 + #define VP9_RESET_FRAME_CONTEXT_SPEC 2 23 + #define VP9_RESET_FRAME_CONTEXT_ALL 3 24 + 25 + #define VP9_TILE_BUF_SIZE 4096 26 + #define VP9_PROB_BUF_SIZE 2560 27 + #define VP9_COUNTS_BUF_SIZE 16384 28 + 29 + #define HDR_FLAG(x) (!!((hdr)->flags & V4L2_VP9_FRAME_FLAG_##x)) 30 + #define LF_FLAG(x) (!!((lf)->flags & V4L2_VP9_LOOP_FILTER_FLAG_##x)) 31 + #define SEG_FLAG(x) (!!((seg)->flags & V4L2_VP9_SEGMENTATION_FLAG_##x)) 32 + #define VP9_BAND_6(band) ((band) == 0 ? 3 : 6) 33 + 34 + /* 35 + * struct vdec_vp9_slice_frame_ctx - vp9 prob tables footprint 36 + */ 37 + struct vdec_vp9_slice_frame_ctx { 38 + struct { 39 + u8 probs[6][3]; 40 + u8 padding[2]; 41 + } coef_probs[4][2][2][6]; 42 + 43 + u8 y_mode_prob[4][16]; 44 + u8 switch_interp_prob[4][16]; 45 + u8 seg[32]; /* ignore */ 46 + u8 comp_inter_prob[16]; 47 + u8 comp_ref_prob[16]; 48 + u8 single_ref_prob[5][2]; 49 + u8 single_ref_prob_padding[6]; 50 + 51 + u8 joint[3]; 52 + u8 joint_padding[13]; 53 + struct { 54 + u8 sign; 55 + u8 classes[10]; 56 + u8 padding[5]; 57 + } sign_classes[2]; 58 + struct { 59 + u8 class0[1]; 60 + u8 bits[10]; 61 + u8 padding[5]; 62 + } class0_bits[2]; 63 + struct { 64 + u8 class0_fp[2][3]; 65 + u8 fp[3]; 66 + u8 class0_hp; 67 + u8 hp; 68 + u8 padding[5]; 69 + } class0_fp_hp[2]; 70 + 71 + u8 uv_mode_prob[10][16]; 72 + u8 uv_mode_prob_padding[2][16]; 73 + 74 + u8 partition_prob[16][4]; 75 + 76 + u8 inter_mode_probs[7][4]; 77 + u8 skip_probs[4]; 78 + 79 + u8 tx_p8x8[2][4]; 80 + u8 tx_p16x16[2][4]; 81 + u8 tx_p32x32[2][4]; 82 + u8 intra_inter_prob[8]; 83 + }; 84 + 85 + /* 86 + * struct vdec_vp9_slice_frame_counts - vp9 counts tables footprint 87 + */ 88 + struct vdec_vp9_slice_frame_counts { 89 + union { 90 + struct { 91 + u32 band_0[3]; 92 + u32 padding0[1]; 93 + u32 band_1_5[5][6]; 94 + u32 padding1[2]; 95 + } eob_branch[4][2][2]; 96 + u32 eob_branch_space[256 * 4]; 97 + }; 98 + 99 + struct { 100 + u32 band_0[3][4]; 101 + u32 band_1_5[5][6][4]; 102 + } coef_probs[4][2][2]; 103 + 104 + u32 intra_inter[4][2]; 105 + u32 comp_inter[5][2]; 106 + u32 comp_inter_padding[2]; 107 + u32 comp_ref[5][2]; 108 + u32 comp_ref_padding[2]; 109 + u32 single_ref[5][2][2]; 110 + u32 inter_mode[7][4]; 111 + u32 y_mode[4][12]; 112 + u32 uv_mode[10][10]; 113 + u32 partition[16][4]; 114 + u32 switchable_interp[4][4]; 115 + 116 + u32 tx_p8x8[2][2]; 117 + u32 tx_p16x16[2][4]; 118 + u32 tx_p32x32[2][4]; 119 + 120 + u32 skip[3][4]; 121 + 122 + u32 joint[4]; 123 + 124 + struct { 125 + u32 sign[2]; 126 + u32 class0[2]; 127 + u32 classes[12]; 128 + u32 bits[10][2]; 129 + u32 padding[4]; 130 + u32 class0_fp[2][4]; 131 + u32 fp[4]; 132 + u32 class0_hp[2]; 133 + u32 hp[2]; 134 + } mvcomp[2]; 135 + 136 + u32 reserved[126][4]; 137 + }; 138 + 139 + /** 140 + * struct vdec_vp9_slice_counts_map - vp9 counts tables to map 141 + * v4l2_vp9_frame_symbol_counts 142 + * @skip: skip counts. 143 + * @y_mode: Y prediction mode counts. 144 + * @filter: interpolation filter counts. 145 + * @mv_joint: motion vector joint counts. 146 + * @sign: motion vector sign counts. 147 + * @classes: motion vector class counts. 148 + * @class0: motion vector class0 bit counts. 149 + * @bits: motion vector bits counts. 150 + * @class0_fp: motion vector class0 fractional bit counts. 151 + * @fp: motion vector fractional bit counts. 152 + * @class0_hp: motion vector class0 high precision fractional bit counts. 153 + * @hp: motion vector high precision fractional bit counts. 154 + */ 155 + struct vdec_vp9_slice_counts_map { 156 + u32 skip[3][2]; 157 + u32 y_mode[4][10]; 158 + u32 filter[4][3]; 159 + u32 sign[2][2]; 160 + u32 classes[2][11]; 161 + u32 class0[2][2]; 162 + u32 bits[2][10][2]; 163 + u32 class0_fp[2][2][4]; 164 + u32 fp[2][4]; 165 + u32 class0_hp[2][2]; 166 + u32 hp[2][2]; 167 + }; 168 + 169 + /* 170 + * struct vdec_vp9_slice_uncompressed_header - vp9 uncompressed header syntax 171 + * used for decoding 172 + */ 173 + struct vdec_vp9_slice_uncompressed_header { 174 + u8 profile; 175 + u8 last_frame_type; 176 + u8 frame_type; 177 + 178 + u8 last_show_frame; 179 + u8 show_frame; 180 + u8 error_resilient_mode; 181 + 182 + u8 bit_depth; 183 + u8 padding0[1]; 184 + u16 last_frame_width; 185 + u16 last_frame_height; 186 + u16 frame_width; 187 + u16 frame_height; 188 + 189 + u8 intra_only; 190 + u8 reset_frame_context; 191 + u8 ref_frame_sign_bias[4]; 192 + u8 allow_high_precision_mv; 193 + u8 interpolation_filter; 194 + 195 + u8 refresh_frame_context; 196 + u8 frame_parallel_decoding_mode; 197 + u8 frame_context_idx; 198 + 199 + /* loop_filter_params */ 200 + u8 loop_filter_level; 201 + u8 loop_filter_sharpness; 202 + u8 loop_filter_delta_enabled; 203 + s8 loop_filter_ref_deltas[4]; 204 + s8 loop_filter_mode_deltas[2]; 205 + 206 + /* quantization_params */ 207 + u8 base_q_idx; 208 + s8 delta_q_y_dc; 209 + s8 delta_q_uv_dc; 210 + s8 delta_q_uv_ac; 211 + 212 + /* segmentation_params */ 213 + u8 segmentation_enabled; 214 + u8 segmentation_update_map; 215 + u8 segmentation_tree_probs[7]; 216 + u8 padding1[1]; 217 + u8 segmentation_temporal_udpate; 218 + u8 segmentation_pred_prob[3]; 219 + u8 segmentation_update_data; 220 + u8 segmentation_abs_or_delta_update; 221 + u8 feature_enabled[8]; 222 + s16 feature_value[8][4]; 223 + 224 + /* tile_info */ 225 + u8 tile_cols_log2; 226 + u8 tile_rows_log2; 227 + u8 padding2[2]; 228 + 229 + u16 uncompressed_header_size; 230 + u16 header_size_in_bytes; 231 + 232 + /* LAT OUT, CORE IN */ 233 + u32 dequant[8][4]; 234 + }; 235 + 236 + /* 237 + * struct vdec_vp9_slice_compressed_header - vp9 compressed header syntax 238 + * used for decoding. 239 + */ 240 + struct vdec_vp9_slice_compressed_header { 241 + u8 tx_mode; 242 + u8 ref_mode; 243 + u8 comp_fixed_ref; 244 + u8 comp_var_ref[2]; 245 + u8 padding[3]; 246 + }; 247 + 248 + /* 249 + * struct vdec_vp9_slice_tiles - vp9 tile syntax 250 + */ 251 + struct vdec_vp9_slice_tiles { 252 + u32 size[4][64]; 253 + u32 mi_rows[4]; 254 + u32 mi_cols[64]; 255 + u8 actual_rows; 256 + u8 padding[7]; 257 + }; 258 + 259 + /* 260 + * struct vdec_vp9_slice_reference - vp9 reference frame information 261 + */ 262 + struct vdec_vp9_slice_reference { 263 + u16 frame_width; 264 + u16 frame_height; 265 + u8 bit_depth; 266 + u8 subsampling_x; 267 + u8 subsampling_y; 268 + u8 padding; 269 + }; 270 + 271 + /* 272 + * struct vdec_vp9_slice_frame - vp9 syntax used for decoding 273 + */ 274 + struct vdec_vp9_slice_frame { 275 + struct vdec_vp9_slice_uncompressed_header uh; 276 + struct vdec_vp9_slice_compressed_header ch; 277 + struct vdec_vp9_slice_tiles tiles; 278 + struct vdec_vp9_slice_reference ref[3]; 279 + }; 280 + 281 + /* 282 + * struct vdec_vp9_slice_init_vsi - VSI used to initialize instance 283 + */ 284 + struct vdec_vp9_slice_init_vsi { 285 + unsigned int architecture; 286 + unsigned int reserved; 287 + u64 core_vsi; 288 + /* default frame context's position in MicroP */ 289 + u64 default_frame_ctx; 290 + }; 291 + 292 + /* 293 + * struct vdec_vp9_slice_mem - memory address and size 294 + */ 295 + struct vdec_vp9_slice_mem { 296 + union { 297 + u64 buf; 298 + dma_addr_t dma_addr; 299 + }; 300 + union { 301 + size_t size; 302 + dma_addr_t dma_addr_end; 303 + u64 padding; 304 + }; 305 + }; 306 + 307 + /* 308 + * struct vdec_vp9_slice_bs - input buffer for decoding 309 + */ 310 + struct vdec_vp9_slice_bs { 311 + struct vdec_vp9_slice_mem buf; 312 + struct vdec_vp9_slice_mem frame; 313 + }; 314 + 315 + /* 316 + * struct vdec_vp9_slice_fb - frame buffer for decoding 317 + */ 318 + struct vdec_vp9_slice_fb { 319 + struct vdec_vp9_slice_mem y; 320 + struct vdec_vp9_slice_mem c; 321 + }; 322 + 323 + /* 324 + * struct vdec_vp9_slice_state - decoding state 325 + */ 326 + struct vdec_vp9_slice_state { 327 + int err; 328 + unsigned int full; 329 + unsigned int timeout; 330 + unsigned int perf; 331 + 332 + unsigned int crc[12]; 333 + }; 334 + 335 + /** 336 + * struct vdec_vp9_slice_vsi - exchange decoding information 337 + * between Main CPU and MicroP 338 + * 339 + * @bs: input buffer 340 + * @fb: output buffer 341 + * @ref: 3 reference buffers 342 + * @mv: mv working buffer 343 + * @seg: segmentation working buffer 344 + * @tile: tile buffer 345 + * @prob: prob table buffer, used to set/update prob table 346 + * @counts: counts table buffer, used to update prob table 347 + * @ube: general buffer 348 + * @trans: trans buffer position in general buffer 349 + * @err_map: error buffer 350 + * @row_info: row info buffer 351 + * @frame: decoding syntax 352 + * @state: decoding state 353 + */ 354 + struct vdec_vp9_slice_vsi { 355 + /* used in LAT stage */ 356 + struct vdec_vp9_slice_bs bs; 357 + /* used in Core stage */ 358 + struct vdec_vp9_slice_fb fb; 359 + struct vdec_vp9_slice_fb ref[3]; 360 + 361 + struct vdec_vp9_slice_mem mv[2]; 362 + struct vdec_vp9_slice_mem seg[2]; 363 + struct vdec_vp9_slice_mem tile; 364 + struct vdec_vp9_slice_mem prob; 365 + struct vdec_vp9_slice_mem counts; 366 + 367 + /* LAT stage's output, Core stage's input */ 368 + struct vdec_vp9_slice_mem ube; 369 + struct vdec_vp9_slice_mem trans; 370 + struct vdec_vp9_slice_mem err_map; 371 + struct vdec_vp9_slice_mem row_info; 372 + 373 + /* decoding parameters */ 374 + struct vdec_vp9_slice_frame frame; 375 + 376 + struct vdec_vp9_slice_state state; 377 + }; 378 + 379 + /** 380 + * struct vdec_vp9_slice_pfc - per-frame context that contains a local vsi. 381 + * pass it from lat to core 382 + * 383 + * @vsi: local vsi. copy to/from remote vsi before/after decoding 384 + * @ref_idx: reference buffer index 385 + * @seq: picture sequence 386 + * @state: decoding state 387 + */ 388 + struct vdec_vp9_slice_pfc { 389 + struct vdec_vp9_slice_vsi vsi; 390 + 391 + u64 ref_idx[3]; 392 + 393 + int seq; 394 + 395 + /* LAT/Core CRC */ 396 + struct vdec_vp9_slice_state state[2]; 397 + }; 398 + 399 + /* 400 + * enum vdec_vp9_slice_resolution_level 401 + */ 402 + enum vdec_vp9_slice_resolution_level { 403 + VP9_RES_NONE, 404 + VP9_RES_FHD, 405 + VP9_RES_4K, 406 + VP9_RES_8K, 407 + }; 408 + 409 + /* 410 + * struct vdec_vp9_slice_ref - picture's width & height should kept 411 + * for later decoding as reference picture 412 + */ 413 + struct vdec_vp9_slice_ref { 414 + unsigned int width; 415 + unsigned int height; 416 + }; 417 + 418 + /** 419 + * struct vdec_vp9_slice_instance - represent one vp9 instance 420 + * 421 + * @ctx: pointer to codec's context 422 + * @vpu: VPU instance 423 + * @seq: global picture sequence 424 + * @level: level of current resolution 425 + * @width: width of last picture 426 + * @height: height of last picture 427 + * @frame_type: frame_type of last picture 428 + * @irq: irq to Main CPU or MicroP 429 + * @show_frame: show_frame of last picture 430 + * @dpb: picture information (width/height) for reference 431 + * @mv: mv working buffer 432 + * @seg: segmentation working buffer 433 + * @tile: tile buffer 434 + * @prob: prob table buffer, used to set/update prob table 435 + * @counts: counts table buffer, used to update prob table 436 + * @frame_ctx: 4 frame context according to VP9 Spec 437 + * @frame_ctx_helper: 4 frame context according to newest kernel spec 438 + * @dirty: state of each frame context 439 + * @init_vsi: vsi used for initialized VP9 instance 440 + * @vsi: vsi used for decoding/flush ... 441 + * @core_vsi: vsi used for Core stage 442 + * @counts_map: used map to counts_helper 443 + * @counts_helper: counts table according to newest kernel spec 444 + */ 445 + struct vdec_vp9_slice_instance { 446 + struct mtk_vcodec_ctx *ctx; 447 + struct vdec_vpu_inst vpu; 448 + 449 + int seq; 450 + 451 + enum vdec_vp9_slice_resolution_level level; 452 + 453 + /* for resolution change and get_pic_info */ 454 + unsigned int width; 455 + unsigned int height; 456 + 457 + /* for last_frame_type */ 458 + unsigned int frame_type; 459 + unsigned int irq; 460 + 461 + unsigned int show_frame; 462 + 463 + /* maintain vp9 reference frame state */ 464 + struct vdec_vp9_slice_ref dpb[VB2_MAX_FRAME]; 465 + 466 + /* 467 + * normal working buffers 468 + * mv[0]/seg[0]/tile/prob/counts is used for LAT 469 + * mv[1]/seg[1] is used for CORE 470 + */ 471 + struct mtk_vcodec_mem mv[2]; 472 + struct mtk_vcodec_mem seg[2]; 473 + struct mtk_vcodec_mem tile; 474 + struct mtk_vcodec_mem prob; 475 + struct mtk_vcodec_mem counts; 476 + 477 + /* 4 prob tables */ 478 + struct vdec_vp9_slice_frame_ctx frame_ctx[4]; 479 + /*4 helper tables */ 480 + struct v4l2_vp9_frame_context frame_ctx_helper; 481 + unsigned char dirty[4]; 482 + 483 + /* MicroP vsi */ 484 + union { 485 + struct vdec_vp9_slice_init_vsi *init_vsi; 486 + struct vdec_vp9_slice_vsi *vsi; 487 + }; 488 + struct vdec_vp9_slice_vsi *core_vsi; 489 + 490 + struct vdec_vp9_slice_counts_map counts_map; 491 + struct v4l2_vp9_frame_symbol_counts counts_helper; 492 + }; 493 + 494 + /* 495 + * all VP9 instances could share this default frame context. 496 + */ 497 + static struct vdec_vp9_slice_frame_ctx *vdec_vp9_slice_default_frame_ctx; 498 + static DEFINE_MUTEX(vdec_vp9_slice_frame_ctx_lock); 499 + 500 + static int vdec_vp9_slice_core_decode(struct vdec_lat_buf *lat_buf); 501 + 502 + static int vdec_vp9_slice_init_default_frame_ctx(struct vdec_vp9_slice_instance *instance) 503 + { 504 + struct vdec_vp9_slice_frame_ctx *remote_frame_ctx; 505 + struct vdec_vp9_slice_frame_ctx *frame_ctx; 506 + struct mtk_vcodec_ctx *ctx; 507 + struct vdec_vp9_slice_init_vsi *vsi; 508 + int ret = 0; 509 + 510 + ctx = instance->ctx; 511 + vsi = instance->vpu.vsi; 512 + if (!ctx || !vsi) 513 + return -EINVAL; 514 + 515 + remote_frame_ctx = mtk_vcodec_fw_map_dm_addr(ctx->dev->fw_handler, 516 + (u32)vsi->default_frame_ctx); 517 + if (!remote_frame_ctx) { 518 + mtk_vcodec_err(instance, "failed to map default frame ctx\n"); 519 + return -EINVAL; 520 + } 521 + 522 + mutex_lock(&vdec_vp9_slice_frame_ctx_lock); 523 + if (vdec_vp9_slice_default_frame_ctx) 524 + goto out; 525 + 526 + frame_ctx = kmalloc(sizeof(*frame_ctx), GFP_KERNEL); 527 + if (!frame_ctx) { 528 + ret = -ENOMEM; 529 + goto out; 530 + } 531 + 532 + memcpy(frame_ctx, remote_frame_ctx, sizeof(*frame_ctx)); 533 + vdec_vp9_slice_default_frame_ctx = frame_ctx; 534 + 535 + out: 536 + mutex_unlock(&vdec_vp9_slice_frame_ctx_lock); 537 + 538 + return ret; 539 + } 540 + 541 + static int vdec_vp9_slice_alloc_working_buffer(struct vdec_vp9_slice_instance *instance, 542 + struct vdec_vp9_slice_vsi *vsi) 543 + { 544 + struct mtk_vcodec_ctx *ctx = instance->ctx; 545 + enum vdec_vp9_slice_resolution_level level; 546 + /* super blocks */ 547 + unsigned int max_sb_w; 548 + unsigned int max_sb_h; 549 + unsigned int max_w; 550 + unsigned int max_h; 551 + unsigned int w; 552 + unsigned int h; 553 + size_t size; 554 + int ret; 555 + int i; 556 + 557 + w = vsi->frame.uh.frame_width; 558 + h = vsi->frame.uh.frame_height; 559 + 560 + if (w > VCODEC_DEC_4K_CODED_WIDTH || 561 + h > VCODEC_DEC_4K_CODED_HEIGHT) { 562 + return -EINVAL; 563 + } else if (w > MTK_VDEC_MAX_W || h > MTK_VDEC_MAX_H) { 564 + /* 4K */ 565 + level = VP9_RES_4K; 566 + max_w = VCODEC_DEC_4K_CODED_WIDTH; 567 + max_h = VCODEC_DEC_4K_CODED_HEIGHT; 568 + } else { 569 + /* FHD */ 570 + level = VP9_RES_FHD; 571 + max_w = MTK_VDEC_MAX_W; 572 + max_h = MTK_VDEC_MAX_H; 573 + } 574 + 575 + if (level == instance->level) 576 + return 0; 577 + 578 + mtk_vcodec_debug(instance, "resolution level changed, from %u to %u, %ux%u", 579 + instance->level, level, w, h); 580 + 581 + max_sb_w = DIV_ROUND_UP(max_w, 64); 582 + max_sb_h = DIV_ROUND_UP(max_h, 64); 583 + ret = -ENOMEM; 584 + 585 + /* 586 + * Lat-flush must wait core idle, otherwise core will 587 + * use released buffers 588 + */ 589 + 590 + size = (max_sb_w * max_sb_h + 2) * 576; 591 + for (i = 0; i < 2; i++) { 592 + if (instance->mv[i].va) 593 + mtk_vcodec_mem_free(ctx, &instance->mv[i]); 594 + instance->mv[i].size = size; 595 + if (mtk_vcodec_mem_alloc(ctx, &instance->mv[i])) 596 + goto err; 597 + } 598 + 599 + size = (max_sb_w * max_sb_h * 32) + 256; 600 + for (i = 0; i < 2; i++) { 601 + if (instance->seg[i].va) 602 + mtk_vcodec_mem_free(ctx, &instance->seg[i]); 603 + instance->seg[i].size = size; 604 + if (mtk_vcodec_mem_alloc(ctx, &instance->seg[i])) 605 + goto err; 606 + } 607 + 608 + if (!instance->tile.va) { 609 + instance->tile.size = VP9_TILE_BUF_SIZE; 610 + if (mtk_vcodec_mem_alloc(ctx, &instance->tile)) 611 + goto err; 612 + } 613 + 614 + if (!instance->prob.va) { 615 + instance->prob.size = VP9_PROB_BUF_SIZE; 616 + if (mtk_vcodec_mem_alloc(ctx, &instance->prob)) 617 + goto err; 618 + } 619 + 620 + if (!instance->counts.va) { 621 + instance->counts.size = VP9_COUNTS_BUF_SIZE; 622 + if (mtk_vcodec_mem_alloc(ctx, &instance->counts)) 623 + goto err; 624 + } 625 + 626 + instance->level = level; 627 + return 0; 628 + 629 + err: 630 + instance->level = VP9_RES_NONE; 631 + return ret; 632 + } 633 + 634 + static void vdec_vp9_slice_free_working_buffer(struct vdec_vp9_slice_instance *instance) 635 + { 636 + struct mtk_vcodec_ctx *ctx = instance->ctx; 637 + int i; 638 + 639 + for (i = 0; i < ARRAY_SIZE(instance->mv); i++) { 640 + if (instance->mv[i].va) 641 + mtk_vcodec_mem_free(ctx, &instance->mv[i]); 642 + } 643 + for (i = 0; i < ARRAY_SIZE(instance->seg); i++) { 644 + if (instance->seg[i].va) 645 + mtk_vcodec_mem_free(ctx, &instance->seg[i]); 646 + } 647 + if (instance->tile.va) 648 + mtk_vcodec_mem_free(ctx, &instance->tile); 649 + if (instance->prob.va) 650 + mtk_vcodec_mem_free(ctx, &instance->prob); 651 + if (instance->counts.va) 652 + mtk_vcodec_mem_free(ctx, &instance->counts); 653 + 654 + instance->level = VP9_RES_NONE; 655 + } 656 + 657 + static void vdec_vp9_slice_vsi_from_remote(struct vdec_vp9_slice_vsi *vsi, 658 + struct vdec_vp9_slice_vsi *remote_vsi, 659 + int skip) 660 + { 661 + struct vdec_vp9_slice_frame *rf; 662 + struct vdec_vp9_slice_frame *f; 663 + 664 + /* 665 + * compressed header 666 + * dequant 667 + * buffer position 668 + * decode state 669 + */ 670 + if (!skip) { 671 + rf = &remote_vsi->frame; 672 + f = &vsi->frame; 673 + memcpy(&f->ch, &rf->ch, sizeof(f->ch)); 674 + memcpy(&f->uh.dequant, &rf->uh.dequant, sizeof(f->uh.dequant)); 675 + memcpy(&vsi->trans, &remote_vsi->trans, sizeof(vsi->trans)); 676 + } 677 + 678 + memcpy(&vsi->state, &remote_vsi->state, sizeof(vsi->state)); 679 + } 680 + 681 + static void vdec_vp9_slice_vsi_to_remote(struct vdec_vp9_slice_vsi *vsi, 682 + struct vdec_vp9_slice_vsi *remote_vsi) 683 + { 684 + memcpy(remote_vsi, vsi, sizeof(*vsi)); 685 + } 686 + 687 + static int vdec_vp9_slice_tile_offset(int idx, int mi_num, int tile_log2) 688 + { 689 + int sbs = (mi_num + 7) >> 3; 690 + int offset = ((idx * sbs) >> tile_log2) << 3; 691 + 692 + return offset < mi_num ? offset : mi_num; 693 + } 694 + 695 + static int vdec_vp9_slice_setup_lat_from_src_buf(struct vdec_vp9_slice_instance *instance, 696 + struct vdec_lat_buf *lat_buf) 697 + { 698 + struct vb2_v4l2_buffer *src; 699 + struct vb2_v4l2_buffer *dst; 700 + 701 + src = v4l2_m2m_next_src_buf(instance->ctx->m2m_ctx); 702 + if (!src) 703 + return -EINVAL; 704 + 705 + lat_buf->src_buf_req = src->vb2_buf.req_obj.req; 706 + 707 + dst = &lat_buf->ts_info; 708 + v4l2_m2m_buf_copy_metadata(src, dst, true); 709 + return 0; 710 + } 711 + 712 + static void vdec_vp9_slice_setup_hdr(struct vdec_vp9_slice_instance *instance, 713 + struct vdec_vp9_slice_uncompressed_header *uh, 714 + struct v4l2_ctrl_vp9_frame *hdr) 715 + { 716 + int i; 717 + 718 + uh->profile = hdr->profile; 719 + uh->last_frame_type = instance->frame_type; 720 + uh->frame_type = !HDR_FLAG(KEY_FRAME); 721 + uh->last_show_frame = instance->show_frame; 722 + uh->show_frame = HDR_FLAG(SHOW_FRAME); 723 + uh->error_resilient_mode = HDR_FLAG(ERROR_RESILIENT); 724 + uh->bit_depth = hdr->bit_depth; 725 + uh->last_frame_width = instance->width; 726 + uh->last_frame_height = instance->height; 727 + uh->frame_width = hdr->frame_width_minus_1 + 1; 728 + uh->frame_height = hdr->frame_height_minus_1 + 1; 729 + uh->intra_only = HDR_FLAG(INTRA_ONLY); 730 + /* map v4l2 enum to values defined in VP9 spec for firmware */ 731 + switch (hdr->reset_frame_context) { 732 + case V4L2_VP9_RESET_FRAME_CTX_NONE: 733 + uh->reset_frame_context = VP9_RESET_FRAME_CONTEXT_NONE0; 734 + break; 735 + case V4L2_VP9_RESET_FRAME_CTX_SPEC: 736 + uh->reset_frame_context = VP9_RESET_FRAME_CONTEXT_SPEC; 737 + break; 738 + case V4L2_VP9_RESET_FRAME_CTX_ALL: 739 + uh->reset_frame_context = VP9_RESET_FRAME_CONTEXT_ALL; 740 + break; 741 + default: 742 + uh->reset_frame_context = VP9_RESET_FRAME_CONTEXT_NONE0; 743 + break; 744 + } 745 + /* 746 + * ref_frame_sign_bias specifies the intended direction 747 + * of the motion vector in time for each reference frame. 748 + * - INTRA_FRAME = 0, 749 + * - LAST_FRAME = 1, 750 + * - GOLDEN_FRAME = 2, 751 + * - ALTREF_FRAME = 3, 752 + * ref_frame_sign_bias[INTRA_FRAME] is always 0 753 + * and VDA only passes another 3 directions 754 + */ 755 + uh->ref_frame_sign_bias[0] = 0; 756 + for (i = 0; i < 3; i++) 757 + uh->ref_frame_sign_bias[i + 1] = 758 + !!(hdr->ref_frame_sign_bias & (1 << i)); 759 + uh->allow_high_precision_mv = HDR_FLAG(ALLOW_HIGH_PREC_MV); 760 + uh->interpolation_filter = hdr->interpolation_filter; 761 + uh->refresh_frame_context = HDR_FLAG(REFRESH_FRAME_CTX); 762 + uh->frame_parallel_decoding_mode = HDR_FLAG(PARALLEL_DEC_MODE); 763 + uh->frame_context_idx = hdr->frame_context_idx; 764 + 765 + /* tile info */ 766 + uh->tile_cols_log2 = hdr->tile_cols_log2; 767 + uh->tile_rows_log2 = hdr->tile_rows_log2; 768 + 769 + uh->uncompressed_header_size = hdr->uncompressed_header_size; 770 + uh->header_size_in_bytes = hdr->compressed_header_size; 771 + } 772 + 773 + static void vdec_vp9_slice_setup_frame_ctx(struct vdec_vp9_slice_instance *instance, 774 + struct vdec_vp9_slice_uncompressed_header *uh, 775 + struct v4l2_ctrl_vp9_frame *hdr) 776 + { 777 + int error_resilient_mode; 778 + int reset_frame_context; 779 + int key_frame; 780 + int intra_only; 781 + int i; 782 + 783 + key_frame = HDR_FLAG(KEY_FRAME); 784 + intra_only = HDR_FLAG(INTRA_ONLY); 785 + error_resilient_mode = HDR_FLAG(ERROR_RESILIENT); 786 + reset_frame_context = uh->reset_frame_context; 787 + 788 + /* 789 + * according to "6.2 Uncompressed header syntax" in 790 + * "VP9 Bitstream & Decoding Process Specification", 791 + * reset @frame_context_idx when (FrameIsIntra || error_resilient_mode) 792 + */ 793 + if (key_frame || intra_only || error_resilient_mode) { 794 + /* 795 + * @reset_frame_context specifies 796 + * whether the frame context should be 797 + * reset to default values: 798 + * 0 or 1 means do not reset any frame context 799 + * 2 resets just the context specified in the frame header 800 + * 3 resets all contexts 801 + */ 802 + if (key_frame || error_resilient_mode || 803 + reset_frame_context == 3) { 804 + /* use default table */ 805 + for (i = 0; i < 4; i++) 806 + instance->dirty[i] = 0; 807 + } else if (reset_frame_context == 2) { 808 + instance->dirty[uh->frame_context_idx] = 0; 809 + } 810 + uh->frame_context_idx = 0; 811 + } 812 + } 813 + 814 + static void vdec_vp9_slice_setup_loop_filter(struct vdec_vp9_slice_uncompressed_header *uh, 815 + struct v4l2_vp9_loop_filter *lf) 816 + { 817 + int i; 818 + 819 + uh->loop_filter_level = lf->level; 820 + uh->loop_filter_sharpness = lf->sharpness; 821 + uh->loop_filter_delta_enabled = LF_FLAG(DELTA_ENABLED); 822 + for (i = 0; i < 4; i++) 823 + uh->loop_filter_ref_deltas[i] = lf->ref_deltas[i]; 824 + for (i = 0; i < 2; i++) 825 + uh->loop_filter_mode_deltas[i] = lf->mode_deltas[i]; 826 + } 827 + 828 + static void vdec_vp9_slice_setup_quantization(struct vdec_vp9_slice_uncompressed_header *uh, 829 + struct v4l2_vp9_quantization *quant) 830 + { 831 + uh->base_q_idx = quant->base_q_idx; 832 + uh->delta_q_y_dc = quant->delta_q_y_dc; 833 + uh->delta_q_uv_dc = quant->delta_q_uv_dc; 834 + uh->delta_q_uv_ac = quant->delta_q_uv_ac; 835 + } 836 + 837 + static void vdec_vp9_slice_setup_segmentation(struct vdec_vp9_slice_uncompressed_header *uh, 838 + struct v4l2_vp9_segmentation *seg) 839 + { 840 + int i; 841 + int j; 842 + 843 + uh->segmentation_enabled = SEG_FLAG(ENABLED); 844 + uh->segmentation_update_map = SEG_FLAG(UPDATE_MAP); 845 + for (i = 0; i < 7; i++) 846 + uh->segmentation_tree_probs[i] = seg->tree_probs[i]; 847 + uh->segmentation_temporal_udpate = SEG_FLAG(TEMPORAL_UPDATE); 848 + for (i = 0; i < 3; i++) 849 + uh->segmentation_pred_prob[i] = seg->pred_probs[i]; 850 + uh->segmentation_update_data = SEG_FLAG(UPDATE_DATA); 851 + uh->segmentation_abs_or_delta_update = SEG_FLAG(ABS_OR_DELTA_UPDATE); 852 + for (i = 0; i < 8; i++) { 853 + uh->feature_enabled[i] = seg->feature_enabled[i]; 854 + for (j = 0; j < 4; j++) 855 + uh->feature_value[i][j] = seg->feature_data[i][j]; 856 + } 857 + } 858 + 859 + static int vdec_vp9_slice_setup_tile(struct vdec_vp9_slice_vsi *vsi, 860 + struct v4l2_ctrl_vp9_frame *hdr) 861 + { 862 + unsigned int rows_log2; 863 + unsigned int cols_log2; 864 + unsigned int rows; 865 + unsigned int cols; 866 + unsigned int mi_rows; 867 + unsigned int mi_cols; 868 + struct vdec_vp9_slice_tiles *tiles; 869 + int offset; 870 + int start; 871 + int end; 872 + int i; 873 + 874 + rows_log2 = hdr->tile_rows_log2; 875 + cols_log2 = hdr->tile_cols_log2; 876 + rows = 1 << rows_log2; 877 + cols = 1 << cols_log2; 878 + tiles = &vsi->frame.tiles; 879 + tiles->actual_rows = 0; 880 + 881 + if (rows > 4 || cols > 64) 882 + return -EINVAL; 883 + 884 + /* setup mi rows/cols information */ 885 + mi_rows = (hdr->frame_height_minus_1 + 1 + 7) >> 3; 886 + mi_cols = (hdr->frame_width_minus_1 + 1 + 7) >> 3; 887 + 888 + for (i = 0; i < rows; i++) { 889 + start = vdec_vp9_slice_tile_offset(i, mi_rows, rows_log2); 890 + end = vdec_vp9_slice_tile_offset(i + 1, mi_rows, rows_log2); 891 + offset = end - start; 892 + tiles->mi_rows[i] = (offset + 7) >> 3; 893 + if (tiles->mi_rows[i]) 894 + tiles->actual_rows++; 895 + } 896 + 897 + for (i = 0; i < cols; i++) { 898 + start = vdec_vp9_slice_tile_offset(i, mi_cols, cols_log2); 899 + end = vdec_vp9_slice_tile_offset(i + 1, mi_cols, cols_log2); 900 + offset = end - start; 901 + tiles->mi_cols[i] = (offset + 7) >> 3; 902 + } 903 + 904 + return 0; 905 + } 906 + 907 + static void vdec_vp9_slice_setup_state(struct vdec_vp9_slice_vsi *vsi) 908 + { 909 + memset(&vsi->state, 0, sizeof(vsi->state)); 910 + } 911 + 912 + static void vdec_vp9_slice_setup_ref_idx(struct vdec_vp9_slice_pfc *pfc, 913 + struct v4l2_ctrl_vp9_frame *hdr) 914 + { 915 + pfc->ref_idx[0] = hdr->last_frame_ts; 916 + pfc->ref_idx[1] = hdr->golden_frame_ts; 917 + pfc->ref_idx[2] = hdr->alt_frame_ts; 918 + } 919 + 920 + static int vdec_vp9_slice_setup_pfc(struct vdec_vp9_slice_instance *instance, 921 + struct vdec_vp9_slice_pfc *pfc) 922 + { 923 + struct v4l2_ctrl_vp9_frame *hdr; 924 + struct vdec_vp9_slice_uncompressed_header *uh; 925 + struct v4l2_ctrl *hdr_ctrl; 926 + struct vdec_vp9_slice_vsi *vsi; 927 + int ret; 928 + 929 + /* frame header */ 930 + hdr_ctrl = v4l2_ctrl_find(&instance->ctx->ctrl_hdl, V4L2_CID_STATELESS_VP9_FRAME); 931 + if (!hdr_ctrl || !hdr_ctrl->p_cur.p) 932 + return -EINVAL; 933 + 934 + hdr = hdr_ctrl->p_cur.p; 935 + vsi = &pfc->vsi; 936 + uh = &vsi->frame.uh; 937 + 938 + /* setup vsi information */ 939 + vdec_vp9_slice_setup_hdr(instance, uh, hdr); 940 + vdec_vp9_slice_setup_frame_ctx(instance, uh, hdr); 941 + vdec_vp9_slice_setup_loop_filter(uh, &hdr->lf); 942 + vdec_vp9_slice_setup_quantization(uh, &hdr->quant); 943 + vdec_vp9_slice_setup_segmentation(uh, &hdr->seg); 944 + ret = vdec_vp9_slice_setup_tile(vsi, hdr); 945 + if (ret) 946 + return ret; 947 + vdec_vp9_slice_setup_state(vsi); 948 + 949 + /* core stage needs buffer index to get ref y/c ... */ 950 + vdec_vp9_slice_setup_ref_idx(pfc, hdr); 951 + 952 + pfc->seq = instance->seq; 953 + instance->seq++; 954 + 955 + return 0; 956 + } 957 + 958 + static int vdec_vp9_slice_setup_lat_buffer(struct vdec_vp9_slice_instance *instance, 959 + struct vdec_vp9_slice_vsi *vsi, 960 + struct mtk_vcodec_mem *bs, 961 + struct vdec_lat_buf *lat_buf) 962 + { 963 + int i; 964 + 965 + vsi->bs.buf.dma_addr = bs->dma_addr; 966 + vsi->bs.buf.size = bs->size; 967 + vsi->bs.frame.dma_addr = bs->dma_addr; 968 + vsi->bs.frame.size = bs->size; 969 + 970 + for (i = 0; i < 2; i++) { 971 + vsi->mv[i].dma_addr = instance->mv[i].dma_addr; 972 + vsi->mv[i].size = instance->mv[i].size; 973 + } 974 + for (i = 0; i < 2; i++) { 975 + vsi->seg[i].dma_addr = instance->seg[i].dma_addr; 976 + vsi->seg[i].size = instance->seg[i].size; 977 + } 978 + vsi->tile.dma_addr = instance->tile.dma_addr; 979 + vsi->tile.size = instance->tile.size; 980 + vsi->prob.dma_addr = instance->prob.dma_addr; 981 + vsi->prob.size = instance->prob.size; 982 + vsi->counts.dma_addr = instance->counts.dma_addr; 983 + vsi->counts.size = instance->counts.size; 984 + 985 + vsi->ube.dma_addr = lat_buf->ctx->msg_queue.wdma_addr.dma_addr; 986 + vsi->ube.size = lat_buf->ctx->msg_queue.wdma_addr.size; 987 + vsi->trans.dma_addr = lat_buf->ctx->msg_queue.wdma_wptr_addr; 988 + /* used to store trans end */ 989 + vsi->trans.dma_addr_end = lat_buf->ctx->msg_queue.wdma_rptr_addr; 990 + vsi->err_map.dma_addr = lat_buf->wdma_err_addr.dma_addr; 991 + vsi->err_map.size = lat_buf->wdma_err_addr.size; 992 + 993 + vsi->row_info.buf = 0; 994 + vsi->row_info.size = 0; 995 + 996 + return 0; 997 + } 998 + 999 + static int vdec_vp9_slice_setup_prob_buffer(struct vdec_vp9_slice_instance *instance, 1000 + struct vdec_vp9_slice_vsi *vsi) 1001 + { 1002 + struct vdec_vp9_slice_frame_ctx *frame_ctx; 1003 + struct vdec_vp9_slice_uncompressed_header *uh; 1004 + 1005 + uh = &vsi->frame.uh; 1006 + 1007 + mtk_vcodec_debug(instance, "ctx dirty %u idx %d\n", 1008 + instance->dirty[uh->frame_context_idx], 1009 + uh->frame_context_idx); 1010 + 1011 + if (instance->dirty[uh->frame_context_idx]) 1012 + frame_ctx = &instance->frame_ctx[uh->frame_context_idx]; 1013 + else 1014 + frame_ctx = vdec_vp9_slice_default_frame_ctx; 1015 + memcpy(instance->prob.va, frame_ctx, sizeof(*frame_ctx)); 1016 + 1017 + return 0; 1018 + } 1019 + 1020 + static void vdec_vp9_slice_setup_seg_buffer(struct vdec_vp9_slice_instance *instance, 1021 + struct vdec_vp9_slice_vsi *vsi, 1022 + struct mtk_vcodec_mem *buf) 1023 + { 1024 + struct vdec_vp9_slice_uncompressed_header *uh; 1025 + 1026 + /* reset segment buffer */ 1027 + uh = &vsi->frame.uh; 1028 + if (uh->frame_type == 0 || 1029 + uh->intra_only || 1030 + uh->error_resilient_mode || 1031 + uh->frame_width != instance->width || 1032 + uh->frame_height != instance->height) { 1033 + mtk_vcodec_debug(instance, "reset seg\n"); 1034 + memset(buf->va, 0, buf->size); 1035 + } 1036 + } 1037 + 1038 + /* 1039 + * parse tiles according to `6.4 Decode tiles syntax` 1040 + * in "vp9-bitstream-specification" 1041 + * 1042 + * frame contains uncompress header, compressed header and several tiles. 1043 + * this function parses tiles' position and size, stores them to tile buffer 1044 + * for decoding. 1045 + */ 1046 + static int vdec_vp9_slice_setup_tile_buffer(struct vdec_vp9_slice_instance *instance, 1047 + struct vdec_vp9_slice_vsi *vsi, 1048 + struct mtk_vcodec_mem *bs) 1049 + { 1050 + struct vdec_vp9_slice_uncompressed_header *uh; 1051 + unsigned int rows_log2; 1052 + unsigned int cols_log2; 1053 + unsigned int rows; 1054 + unsigned int cols; 1055 + unsigned int mi_row; 1056 + unsigned int mi_col; 1057 + unsigned int offset; 1058 + unsigned int pa; 1059 + unsigned int size; 1060 + struct vdec_vp9_slice_tiles *tiles; 1061 + unsigned char *pos; 1062 + unsigned char *end; 1063 + unsigned char *va; 1064 + unsigned int *tb; 1065 + int i; 1066 + int j; 1067 + 1068 + uh = &vsi->frame.uh; 1069 + rows_log2 = uh->tile_rows_log2; 1070 + cols_log2 = uh->tile_cols_log2; 1071 + rows = 1 << rows_log2; 1072 + cols = 1 << cols_log2; 1073 + 1074 + if (rows > 4 || cols > 64) { 1075 + mtk_vcodec_err(instance, "tile_rows %u tile_cols %u\n", 1076 + rows, cols); 1077 + return -EINVAL; 1078 + } 1079 + 1080 + offset = uh->uncompressed_header_size + 1081 + uh->header_size_in_bytes; 1082 + if (bs->size <= offset) { 1083 + mtk_vcodec_err(instance, "bs size %zu tile offset %u\n", 1084 + bs->size, offset); 1085 + return -EINVAL; 1086 + } 1087 + 1088 + tiles = &vsi->frame.tiles; 1089 + /* setup tile buffer */ 1090 + 1091 + va = (unsigned char *)bs->va; 1092 + pos = va + offset; 1093 + end = va + bs->size; 1094 + /* truncated */ 1095 + pa = (unsigned int)bs->dma_addr + offset; 1096 + tb = instance->tile.va; 1097 + for (i = 0; i < rows; i++) { 1098 + for (j = 0; j < cols; j++) { 1099 + if (i == rows - 1 && 1100 + j == cols - 1) { 1101 + size = (unsigned int)(end - pos); 1102 + } else { 1103 + if (end - pos < 4) 1104 + return -EINVAL; 1105 + 1106 + size = (pos[0] << 24) | (pos[1] << 16) | 1107 + (pos[2] << 8) | pos[3]; 1108 + pos += 4; 1109 + pa += 4; 1110 + offset += 4; 1111 + if (end - pos < size) 1112 + return -EINVAL; 1113 + } 1114 + tiles->size[i][j] = size; 1115 + if (tiles->mi_rows[i]) { 1116 + *tb++ = (size << 3) + ((offset << 3) & 0x7f); 1117 + *tb++ = pa & ~0xf; 1118 + *tb++ = (pa << 3) & 0x7f; 1119 + mi_row = (tiles->mi_rows[i] - 1) & 0x1ff; 1120 + mi_col = (tiles->mi_cols[j] - 1) & 0x3f; 1121 + *tb++ = (mi_row << 6) + mi_col; 1122 + } 1123 + pos += size; 1124 + pa += size; 1125 + offset += size; 1126 + } 1127 + } 1128 + 1129 + return 0; 1130 + } 1131 + 1132 + static int vdec_vp9_slice_setup_lat(struct vdec_vp9_slice_instance *instance, 1133 + struct mtk_vcodec_mem *bs, 1134 + struct vdec_lat_buf *lat_buf, 1135 + struct vdec_vp9_slice_pfc *pfc) 1136 + { 1137 + struct vdec_vp9_slice_vsi *vsi = &pfc->vsi; 1138 + int ret; 1139 + 1140 + ret = vdec_vp9_slice_setup_lat_from_src_buf(instance, lat_buf); 1141 + if (ret) 1142 + goto err; 1143 + 1144 + ret = vdec_vp9_slice_setup_pfc(instance, pfc); 1145 + if (ret) 1146 + goto err; 1147 + 1148 + ret = vdec_vp9_slice_alloc_working_buffer(instance, vsi); 1149 + if (ret) 1150 + goto err; 1151 + 1152 + ret = vdec_vp9_slice_setup_lat_buffer(instance, vsi, bs, lat_buf); 1153 + if (ret) 1154 + goto err; 1155 + 1156 + vdec_vp9_slice_setup_seg_buffer(instance, vsi, &instance->seg[0]); 1157 + 1158 + /* setup prob/tile buffers for LAT */ 1159 + 1160 + ret = vdec_vp9_slice_setup_prob_buffer(instance, vsi); 1161 + if (ret) 1162 + goto err; 1163 + 1164 + ret = vdec_vp9_slice_setup_tile_buffer(instance, vsi, bs); 1165 + if (ret) 1166 + goto err; 1167 + 1168 + return 0; 1169 + 1170 + err: 1171 + return ret; 1172 + } 1173 + 1174 + static 1175 + void vdec_vp9_slice_map_counts_eob_coef(unsigned int i, unsigned int j, unsigned int k, 1176 + struct vdec_vp9_slice_frame_counts *counts, 1177 + struct v4l2_vp9_frame_symbol_counts *counts_helper) 1178 + { 1179 + u32 l = 0, m; 1180 + 1181 + /* 1182 + * helper eo -> mtk eo 1183 + * helpre e1 -> mtk c3 1184 + * helper c0 -> c0 1185 + * helper c1 -> c1 1186 + * helper c2 -> c2 1187 + */ 1188 + for (m = 0; m < 3; m++) { 1189 + counts_helper->coeff[i][j][k][l][m] = 1190 + (u32 (*)[3]) & counts->coef_probs[i][j][k].band_0[m]; 1191 + counts_helper->eob[i][j][k][l][m][0] = 1192 + &counts->eob_branch[i][j][k].band_0[m]; 1193 + counts_helper->eob[i][j][k][l][m][1] = 1194 + &counts->coef_probs[i][j][k].band_0[m][3]; 1195 + } 1196 + 1197 + for (l = 1; l < 6; l++) { 1198 + for (m = 0; m < 6; m++) { 1199 + counts_helper->coeff[i][j][k][l][m] = 1200 + (u32 (*)[3]) & counts->coef_probs[i][j][k].band_1_5[l - 1][m]; 1201 + counts_helper->eob[i][j][k][l][m][0] = 1202 + &counts->eob_branch[i][j][k].band_1_5[l - 1][m]; 1203 + counts_helper->eob[i][j][k][l][m][1] = 1204 + &counts->coef_probs[i][j][k].band_1_5[l - 1][m][3]; 1205 + } 1206 + } 1207 + } 1208 + 1209 + static void vdec_vp9_slice_counts_map_helper(struct vdec_vp9_slice_counts_map *counts_map, 1210 + struct vdec_vp9_slice_frame_counts *counts, 1211 + struct v4l2_vp9_frame_symbol_counts *counts_helper) 1212 + { 1213 + int i, j, k; 1214 + 1215 + counts_helper->partition = &counts->partition; 1216 + counts_helper->intra_inter = &counts->intra_inter; 1217 + counts_helper->tx32p = &counts->tx_p32x32; 1218 + counts_helper->tx16p = &counts->tx_p16x16; 1219 + counts_helper->tx8p = &counts->tx_p8x8; 1220 + counts_helper->uv_mode = &counts->uv_mode; 1221 + 1222 + counts_helper->comp = &counts->comp_inter; 1223 + counts_helper->comp_ref = &counts->comp_ref; 1224 + counts_helper->single_ref = &counts->single_ref; 1225 + counts_helper->mv_mode = &counts->inter_mode; 1226 + counts_helper->mv_joint = &counts->joint; 1227 + 1228 + for (i = 0; i < ARRAY_SIZE(counts_map->skip); i++) 1229 + memcpy(counts_map->skip[i], counts->skip[i], 1230 + sizeof(counts_map->skip[0])); 1231 + counts_helper->skip = &counts_map->skip; 1232 + 1233 + for (i = 0; i < ARRAY_SIZE(counts_map->y_mode); i++) 1234 + memcpy(counts_map->y_mode[i], counts->y_mode[i], 1235 + sizeof(counts_map->y_mode[0])); 1236 + counts_helper->y_mode = &counts_map->y_mode; 1237 + 1238 + for (i = 0; i < ARRAY_SIZE(counts_map->filter); i++) 1239 + memcpy(counts_map->filter[i], counts->switchable_interp[i], 1240 + sizeof(counts_map->filter[0])); 1241 + counts_helper->filter = &counts_map->filter; 1242 + 1243 + for (i = 0; i < ARRAY_SIZE(counts_map->sign); i++) 1244 + memcpy(counts_map->sign[i], counts->mvcomp[i].sign, 1245 + sizeof(counts_map->sign[0])); 1246 + counts_helper->sign = &counts_map->sign; 1247 + 1248 + for (i = 0; i < ARRAY_SIZE(counts_map->classes); i++) 1249 + memcpy(counts_map->classes[i], counts->mvcomp[i].classes, 1250 + sizeof(counts_map->classes[0])); 1251 + counts_helper->classes = &counts_map->classes; 1252 + 1253 + for (i = 0; i < ARRAY_SIZE(counts_map->class0); i++) 1254 + memcpy(counts_map->class0[i], counts->mvcomp[i].class0, 1255 + sizeof(counts_map->class0[0])); 1256 + counts_helper->class0 = &counts_map->class0; 1257 + 1258 + for (i = 0; i < ARRAY_SIZE(counts_map->bits); i++) 1259 + for (j = 0; j < ARRAY_SIZE(counts_map->bits[0]); j++) 1260 + memcpy(counts_map->bits[i][j], counts->mvcomp[i].bits[j], 1261 + sizeof(counts_map->bits[0][0])); 1262 + counts_helper->bits = &counts_map->bits; 1263 + 1264 + for (i = 0; i < ARRAY_SIZE(counts_map->class0_fp); i++) 1265 + for (j = 0; j < ARRAY_SIZE(counts_map->class0_fp[0]); j++) 1266 + memcpy(counts_map->class0_fp[i][j], counts->mvcomp[i].class0_fp[j], 1267 + sizeof(counts_map->class0_fp[0][0])); 1268 + counts_helper->class0_fp = &counts_map->class0_fp; 1269 + 1270 + for (i = 0; i < ARRAY_SIZE(counts_map->fp); i++) 1271 + memcpy(counts_map->fp[i], counts->mvcomp[i].fp, 1272 + sizeof(counts_map->fp[0])); 1273 + counts_helper->fp = &counts_map->fp; 1274 + 1275 + for (i = 0; i < ARRAY_SIZE(counts_map->class0_hp); i++) 1276 + memcpy(counts_map->class0_hp[i], counts->mvcomp[i].class0_hp, 1277 + sizeof(counts_map->class0_hp[0])); 1278 + counts_helper->class0_hp = &counts_map->class0_hp; 1279 + 1280 + for (i = 0; i < ARRAY_SIZE(counts_map->hp); i++) 1281 + memcpy(counts_map->hp[i], counts->mvcomp[i].hp, sizeof(counts_map->hp[0])); 1282 + 1283 + counts_helper->hp = &counts_map->hp; 1284 + 1285 + for (i = 0; i < 4; i++) 1286 + for (j = 0; j < 2; j++) 1287 + for (k = 0; k < 2; k++) 1288 + vdec_vp9_slice_map_counts_eob_coef(i, j, k, counts, counts_helper); 1289 + } 1290 + 1291 + static void vdec_vp9_slice_map_to_coef(unsigned int i, unsigned int j, unsigned int k, 1292 + struct vdec_vp9_slice_frame_ctx *frame_ctx, 1293 + struct v4l2_vp9_frame_context *frame_ctx_helper) 1294 + { 1295 + u32 l, m; 1296 + 1297 + for (l = 0; l < ARRAY_SIZE(frame_ctx_helper->coef[0][0][0]); l++) { 1298 + for (m = 0; m < VP9_BAND_6(l); m++) { 1299 + memcpy(frame_ctx_helper->coef[i][j][k][l][m], 1300 + frame_ctx->coef_probs[i][j][k][l].probs[m], 1301 + sizeof(frame_ctx_helper->coef[i][j][k][l][0])); 1302 + } 1303 + } 1304 + } 1305 + 1306 + static void vdec_vp9_slice_map_from_coef(unsigned int i, unsigned int j, unsigned int k, 1307 + struct vdec_vp9_slice_frame_ctx *frame_ctx, 1308 + struct v4l2_vp9_frame_context *frame_ctx_helper) 1309 + { 1310 + u32 l, m; 1311 + 1312 + for (l = 0; l < ARRAY_SIZE(frame_ctx_helper->coef[0][0][0]); l++) { 1313 + for (m = 0; m < VP9_BAND_6(l); m++) { 1314 + memcpy(frame_ctx->coef_probs[i][j][k][l].probs[m], 1315 + frame_ctx_helper->coef[i][j][k][l][m], 1316 + sizeof(frame_ctx_helper->coef[i][j][k][l][0])); 1317 + } 1318 + } 1319 + } 1320 + 1321 + static 1322 + void vdec_vp9_slice_framectx_map_helper(bool frame_is_intra, 1323 + struct vdec_vp9_slice_frame_ctx *pre_frame_ctx, 1324 + struct vdec_vp9_slice_frame_ctx *frame_ctx, 1325 + struct v4l2_vp9_frame_context *frame_ctx_helper) 1326 + { 1327 + struct v4l2_vp9_frame_mv_context *mv = &frame_ctx_helper->mv; 1328 + u32 i, j, k; 1329 + 1330 + for (i = 0; i < ARRAY_SIZE(frame_ctx_helper->coef); i++) 1331 + for (j = 0; j < ARRAY_SIZE(frame_ctx_helper->coef[0]); j++) 1332 + for (k = 0; k < ARRAY_SIZE(frame_ctx_helper->coef[0][0]); k++) 1333 + vdec_vp9_slice_map_to_coef(i, j, k, pre_frame_ctx, 1334 + frame_ctx_helper); 1335 + 1336 + /* 1337 + * use previous prob when frame is not intra or 1338 + * we should use the prob updated by the compressed header parse 1339 + */ 1340 + if (!frame_is_intra) 1341 + frame_ctx = pre_frame_ctx; 1342 + 1343 + for (i = 0; i < ARRAY_SIZE(frame_ctx_helper->tx8); i++) 1344 + memcpy(frame_ctx_helper->tx8[i], frame_ctx->tx_p8x8[i], 1345 + sizeof(frame_ctx_helper->tx8[0])); 1346 + 1347 + for (i = 0; i < ARRAY_SIZE(frame_ctx_helper->tx16); i++) 1348 + memcpy(frame_ctx_helper->tx16[i], frame_ctx->tx_p16x16[i], 1349 + sizeof(frame_ctx_helper->tx16[0])); 1350 + 1351 + for (i = 0; i < ARRAY_SIZE(frame_ctx_helper->tx32); i++) 1352 + memcpy(frame_ctx_helper->tx32[i], frame_ctx->tx_p32x32[i], 1353 + sizeof(frame_ctx_helper->tx32[0])); 1354 + 1355 + memcpy(frame_ctx_helper->skip, frame_ctx->skip_probs, sizeof(frame_ctx_helper->skip)); 1356 + 1357 + for (i = 0; i < ARRAY_SIZE(frame_ctx_helper->inter_mode); i++) 1358 + memcpy(frame_ctx_helper->inter_mode[i], frame_ctx->inter_mode_probs[i], 1359 + sizeof(frame_ctx_helper->inter_mode[0])); 1360 + 1361 + for (i = 0; i < ARRAY_SIZE(frame_ctx_helper->interp_filter); i++) 1362 + memcpy(frame_ctx_helper->interp_filter[i], frame_ctx->switch_interp_prob[i], 1363 + sizeof(frame_ctx_helper->interp_filter[0])); 1364 + 1365 + memcpy(frame_ctx_helper->is_inter, frame_ctx->intra_inter_prob, 1366 + sizeof(frame_ctx_helper->is_inter)); 1367 + 1368 + memcpy(frame_ctx_helper->comp_mode, frame_ctx->comp_inter_prob, 1369 + sizeof(frame_ctx_helper->comp_mode)); 1370 + 1371 + for (i = 0; i < ARRAY_SIZE(frame_ctx_helper->single_ref); i++) 1372 + memcpy(frame_ctx_helper->single_ref[i], frame_ctx->single_ref_prob[i], 1373 + sizeof(frame_ctx_helper->single_ref[0])); 1374 + 1375 + memcpy(frame_ctx_helper->comp_ref, frame_ctx->comp_ref_prob, 1376 + sizeof(frame_ctx_helper->comp_ref)); 1377 + 1378 + for (i = 0; i < ARRAY_SIZE(frame_ctx_helper->y_mode); i++) 1379 + memcpy(frame_ctx_helper->y_mode[i], frame_ctx->y_mode_prob[i], 1380 + sizeof(frame_ctx_helper->y_mode[0])); 1381 + 1382 + for (i = 0; i < ARRAY_SIZE(frame_ctx_helper->uv_mode); i++) 1383 + memcpy(frame_ctx_helper->uv_mode[i], frame_ctx->uv_mode_prob[i], 1384 + sizeof(frame_ctx_helper->uv_mode[0])); 1385 + 1386 + for (i = 0; i < ARRAY_SIZE(frame_ctx_helper->partition); i++) 1387 + memcpy(frame_ctx_helper->partition[i], frame_ctx->partition_prob[i], 1388 + sizeof(frame_ctx_helper->partition[0])); 1389 + 1390 + memcpy(mv->joint, frame_ctx->joint, sizeof(mv->joint)); 1391 + 1392 + for (i = 0; i < ARRAY_SIZE(mv->sign); i++) 1393 + mv->sign[i] = frame_ctx->sign_classes[i].sign; 1394 + 1395 + for (i = 0; i < ARRAY_SIZE(mv->classes); i++) 1396 + memcpy(mv->classes[i], frame_ctx->sign_classes[i].classes, 1397 + sizeof(mv->classes[i])); 1398 + 1399 + for (i = 0; i < ARRAY_SIZE(mv->class0_bit); i++) 1400 + mv->class0_bit[i] = frame_ctx->class0_bits[i].class0[0]; 1401 + 1402 + for (i = 0; i < ARRAY_SIZE(mv->bits); i++) 1403 + memcpy(mv->bits[i], frame_ctx->class0_bits[i].bits, sizeof(mv->bits[0])); 1404 + 1405 + for (i = 0; i < ARRAY_SIZE(mv->class0_fr); i++) 1406 + for (j = 0; j < ARRAY_SIZE(mv->class0_fr[0]); j++) 1407 + memcpy(mv->class0_fr[i][j], frame_ctx->class0_fp_hp[i].class0_fp[j], 1408 + sizeof(mv->class0_fr[0][0])); 1409 + 1410 + for (i = 0; i < ARRAY_SIZE(mv->fr); i++) 1411 + memcpy(mv->fr[i], frame_ctx->class0_fp_hp[i].fp, sizeof(mv->fr[0])); 1412 + 1413 + for (i = 0; i < ARRAY_SIZE(mv->class0_hp); i++) 1414 + mv->class0_hp[i] = frame_ctx->class0_fp_hp[i].class0_hp; 1415 + 1416 + for (i = 0; i < ARRAY_SIZE(mv->hp); i++) 1417 + mv->hp[i] = frame_ctx->class0_fp_hp[i].hp; 1418 + } 1419 + 1420 + static void vdec_vp9_slice_helper_map_framectx(struct v4l2_vp9_frame_context *frame_ctx_helper, 1421 + struct vdec_vp9_slice_frame_ctx *frame_ctx) 1422 + { 1423 + struct v4l2_vp9_frame_mv_context *mv = &frame_ctx_helper->mv; 1424 + u32 i, j, k; 1425 + 1426 + for (i = 0; i < ARRAY_SIZE(frame_ctx_helper->tx8); i++) 1427 + memcpy(frame_ctx->tx_p8x8[i], frame_ctx_helper->tx8[i], 1428 + sizeof(frame_ctx_helper->tx8[0])); 1429 + 1430 + for (i = 0; i < ARRAY_SIZE(frame_ctx_helper->tx16); i++) 1431 + memcpy(frame_ctx->tx_p16x16[i], frame_ctx_helper->tx16[i], 1432 + sizeof(frame_ctx_helper->tx16[0])); 1433 + 1434 + for (i = 0; i < ARRAY_SIZE(frame_ctx_helper->tx32); i++) 1435 + memcpy(frame_ctx->tx_p32x32[i], frame_ctx_helper->tx32[i], 1436 + sizeof(frame_ctx_helper->tx32[0])); 1437 + 1438 + for (i = 0; i < ARRAY_SIZE(frame_ctx_helper->coef); i++) 1439 + for (j = 0; j < ARRAY_SIZE(frame_ctx_helper->coef[0]); j++) 1440 + for (k = 0; k < ARRAY_SIZE(frame_ctx_helper->coef[0][0]); k++) 1441 + vdec_vp9_slice_map_from_coef(i, j, k, frame_ctx, 1442 + frame_ctx_helper); 1443 + 1444 + memcpy(frame_ctx->skip_probs, frame_ctx_helper->skip, sizeof(frame_ctx_helper->skip)); 1445 + 1446 + for (i = 0; i < ARRAY_SIZE(frame_ctx_helper->inter_mode); i++) 1447 + memcpy(frame_ctx->inter_mode_probs[i], frame_ctx_helper->inter_mode[i], 1448 + sizeof(frame_ctx_helper->inter_mode[0])); 1449 + 1450 + for (i = 0; i < ARRAY_SIZE(frame_ctx_helper->interp_filter); i++) 1451 + memcpy(frame_ctx->switch_interp_prob[i], frame_ctx_helper->interp_filter[i], 1452 + sizeof(frame_ctx_helper->interp_filter[0])); 1453 + 1454 + memcpy(frame_ctx->intra_inter_prob, frame_ctx_helper->is_inter, 1455 + sizeof(frame_ctx_helper->is_inter)); 1456 + 1457 + memcpy(frame_ctx->comp_inter_prob, frame_ctx_helper->comp_mode, 1458 + sizeof(frame_ctx_helper->comp_mode)); 1459 + 1460 + for (i = 0; i < ARRAY_SIZE(frame_ctx_helper->single_ref); i++) 1461 + memcpy(frame_ctx->single_ref_prob[i], frame_ctx_helper->single_ref[i], 1462 + sizeof(frame_ctx_helper->single_ref[0])); 1463 + 1464 + memcpy(frame_ctx->comp_ref_prob, frame_ctx_helper->comp_ref, 1465 + sizeof(frame_ctx_helper->comp_ref)); 1466 + 1467 + for (i = 0; i < ARRAY_SIZE(frame_ctx_helper->y_mode); i++) 1468 + memcpy(frame_ctx->y_mode_prob[i], frame_ctx_helper->y_mode[i], 1469 + sizeof(frame_ctx_helper->y_mode[0])); 1470 + 1471 + for (i = 0; i < ARRAY_SIZE(frame_ctx_helper->uv_mode); i++) 1472 + memcpy(frame_ctx->uv_mode_prob[i], frame_ctx_helper->uv_mode[i], 1473 + sizeof(frame_ctx_helper->uv_mode[0])); 1474 + 1475 + for (i = 0; i < ARRAY_SIZE(frame_ctx_helper->partition); i++) 1476 + memcpy(frame_ctx->partition_prob[i], frame_ctx_helper->partition[i], 1477 + sizeof(frame_ctx_helper->partition[0])); 1478 + 1479 + memcpy(frame_ctx->joint, mv->joint, sizeof(mv->joint)); 1480 + 1481 + for (i = 0; i < ARRAY_SIZE(mv->sign); i++) 1482 + frame_ctx->sign_classes[i].sign = mv->sign[i]; 1483 + 1484 + for (i = 0; i < ARRAY_SIZE(mv->classes); i++) 1485 + memcpy(frame_ctx->sign_classes[i].classes, mv->classes[i], 1486 + sizeof(mv->classes[i])); 1487 + 1488 + for (i = 0; i < ARRAY_SIZE(mv->class0_bit); i++) 1489 + frame_ctx->class0_bits[i].class0[0] = mv->class0_bit[i]; 1490 + 1491 + for (i = 0; i < ARRAY_SIZE(mv->bits); i++) 1492 + memcpy(frame_ctx->class0_bits[i].bits, mv->bits[i], sizeof(mv->bits[0])); 1493 + 1494 + for (i = 0; i < ARRAY_SIZE(mv->class0_fr); i++) 1495 + for (j = 0; j < ARRAY_SIZE(mv->class0_fr[0]); j++) 1496 + memcpy(frame_ctx->class0_fp_hp[i].class0_fp[j], mv->class0_fr[i][j], 1497 + sizeof(mv->class0_fr[0][0])); 1498 + 1499 + for (i = 0; i < ARRAY_SIZE(mv->fr); i++) 1500 + memcpy(frame_ctx->class0_fp_hp[i].fp, mv->fr[i], sizeof(mv->fr[0])); 1501 + 1502 + for (i = 0; i < ARRAY_SIZE(mv->class0_hp); i++) 1503 + frame_ctx->class0_fp_hp[i].class0_hp = mv->class0_hp[i]; 1504 + 1505 + for (i = 0; i < ARRAY_SIZE(mv->hp); i++) 1506 + frame_ctx->class0_fp_hp[i].hp = mv->hp[i]; 1507 + } 1508 + 1509 + static int vdec_vp9_slice_update_prob(struct vdec_vp9_slice_instance *instance, 1510 + struct vdec_vp9_slice_vsi *vsi) 1511 + { 1512 + struct vdec_vp9_slice_frame_ctx *pre_frame_ctx; 1513 + struct v4l2_vp9_frame_context *pre_frame_ctx_helper; 1514 + struct vdec_vp9_slice_frame_ctx *frame_ctx; 1515 + struct vdec_vp9_slice_frame_counts *counts; 1516 + struct v4l2_vp9_frame_symbol_counts *counts_helper; 1517 + struct vdec_vp9_slice_uncompressed_header *uh; 1518 + bool frame_is_intra; 1519 + bool use_128; 1520 + 1521 + uh = &vsi->frame.uh; 1522 + pre_frame_ctx = &instance->frame_ctx[uh->frame_context_idx]; 1523 + pre_frame_ctx_helper = &instance->frame_ctx_helper; 1524 + frame_ctx = (struct vdec_vp9_slice_frame_ctx *)instance->prob.va; 1525 + counts = (struct vdec_vp9_slice_frame_counts *)instance->counts.va; 1526 + counts_helper = &instance->counts_helper; 1527 + 1528 + if (!uh->refresh_frame_context) 1529 + return 0; 1530 + 1531 + if (!uh->frame_parallel_decoding_mode) { 1532 + vdec_vp9_slice_counts_map_helper(&instance->counts_map, counts, counts_helper); 1533 + 1534 + frame_is_intra = !vsi->frame.uh.frame_type || vsi->frame.uh.intra_only; 1535 + /* check default prob */ 1536 + if (!instance->dirty[uh->frame_context_idx]) 1537 + vdec_vp9_slice_framectx_map_helper(frame_is_intra, 1538 + vdec_vp9_slice_default_frame_ctx, 1539 + frame_ctx, 1540 + pre_frame_ctx_helper); 1541 + else 1542 + vdec_vp9_slice_framectx_map_helper(frame_is_intra, 1543 + pre_frame_ctx, 1544 + frame_ctx, 1545 + pre_frame_ctx_helper); 1546 + 1547 + use_128 = !frame_is_intra && !vsi->frame.uh.last_frame_type; 1548 + v4l2_vp9_adapt_coef_probs(pre_frame_ctx_helper, 1549 + counts_helper, 1550 + use_128, 1551 + frame_is_intra); 1552 + if (!frame_is_intra) 1553 + v4l2_vp9_adapt_noncoef_probs(pre_frame_ctx_helper, 1554 + counts_helper, 1555 + V4L2_VP9_REFERENCE_MODE_SINGLE_REFERENCE, 1556 + vsi->frame.uh.interpolation_filter, 1557 + vsi->frame.ch.tx_mode, 1558 + vsi->frame.uh.allow_high_precision_mv ? 1559 + V4L2_VP9_FRAME_FLAG_ALLOW_HIGH_PREC_MV : 0); 1560 + vdec_vp9_slice_helper_map_framectx(pre_frame_ctx_helper, pre_frame_ctx); 1561 + } else { 1562 + memcpy(pre_frame_ctx, frame_ctx, sizeof(*frame_ctx)); 1563 + } 1564 + 1565 + instance->dirty[uh->frame_context_idx] = 1; 1566 + 1567 + return 0; 1568 + } 1569 + 1570 + static int vdec_vp9_slice_update_lat(struct vdec_vp9_slice_instance *instance, 1571 + struct vdec_lat_buf *lat_buf, 1572 + struct vdec_vp9_slice_pfc *pfc) 1573 + { 1574 + struct vdec_vp9_slice_vsi *vsi; 1575 + 1576 + vsi = &pfc->vsi; 1577 + memcpy(&pfc->state[0], &vsi->state, sizeof(vsi->state)); 1578 + 1579 + mtk_vcodec_debug(instance, "Frame %u LAT CRC 0x%08x %lx %lx\n", 1580 + pfc->seq, vsi->state.crc[0], 1581 + (unsigned long)vsi->trans.dma_addr, 1582 + (unsigned long)vsi->trans.dma_addr_end); 1583 + 1584 + /* buffer full, need to re-decode */ 1585 + if (vsi->state.full) { 1586 + /* buffer not enough */ 1587 + if (vsi->trans.dma_addr_end - vsi->trans.dma_addr == 1588 + vsi->ube.size) 1589 + return -ENOMEM; 1590 + return -EAGAIN; 1591 + } 1592 + 1593 + vdec_vp9_slice_update_prob(instance, vsi); 1594 + 1595 + instance->width = vsi->frame.uh.frame_width; 1596 + instance->height = vsi->frame.uh.frame_height; 1597 + instance->frame_type = vsi->frame.uh.frame_type; 1598 + instance->show_frame = vsi->frame.uh.show_frame; 1599 + 1600 + return 0; 1601 + } 1602 + 1603 + static int vdec_vp9_slice_setup_core_to_dst_buf(struct vdec_vp9_slice_instance *instance, 1604 + struct vdec_lat_buf *lat_buf) 1605 + { 1606 + struct vb2_v4l2_buffer *dst; 1607 + 1608 + dst = v4l2_m2m_next_dst_buf(instance->ctx->m2m_ctx); 1609 + if (!dst) 1610 + return -EINVAL; 1611 + 1612 + v4l2_m2m_buf_copy_metadata(&lat_buf->ts_info, dst, true); 1613 + return 0; 1614 + } 1615 + 1616 + static int vdec_vp9_slice_setup_core_buffer(struct vdec_vp9_slice_instance *instance, 1617 + struct vdec_vp9_slice_pfc *pfc, 1618 + struct vdec_vp9_slice_vsi *vsi, 1619 + struct vdec_fb *fb, 1620 + struct vdec_lat_buf *lat_buf) 1621 + { 1622 + struct vb2_buffer *vb; 1623 + struct vb2_queue *vq; 1624 + struct vdec_vp9_slice_reference *ref; 1625 + int plane; 1626 + int size; 1627 + int idx; 1628 + int w; 1629 + int h; 1630 + int i; 1631 + 1632 + plane = instance->ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes; 1633 + w = vsi->frame.uh.frame_width; 1634 + h = vsi->frame.uh.frame_height; 1635 + size = ALIGN(w, 64) * ALIGN(h, 64); 1636 + 1637 + /* frame buffer */ 1638 + vsi->fb.y.dma_addr = fb->base_y.dma_addr; 1639 + if (plane == 1) 1640 + vsi->fb.c.dma_addr = fb->base_y.dma_addr + size; 1641 + else 1642 + vsi->fb.c.dma_addr = fb->base_c.dma_addr; 1643 + 1644 + /* reference buffers */ 1645 + vq = v4l2_m2m_get_vq(instance->ctx->m2m_ctx, 1646 + V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); 1647 + if (!vq) 1648 + return -EINVAL; 1649 + 1650 + /* get current output buffer */ 1651 + vb = &v4l2_m2m_next_dst_buf(instance->ctx->m2m_ctx)->vb2_buf; 1652 + if (!vb) 1653 + return -EINVAL; 1654 + 1655 + /* update internal buffer's width/height */ 1656 + for (i = 0; i < vq->num_buffers; i++) { 1657 + if (vb == vq->bufs[i]) { 1658 + instance->dpb[i].width = w; 1659 + instance->dpb[i].height = h; 1660 + break; 1661 + } 1662 + } 1663 + 1664 + /* 1665 + * get buffer's width/height from instance 1666 + * get buffer address from vb2buf 1667 + */ 1668 + for (i = 0; i < 3; i++) { 1669 + ref = &vsi->frame.ref[i]; 1670 + idx = vb2_find_timestamp(vq, pfc->ref_idx[i], 0); 1671 + if (idx < 0) { 1672 + ref->frame_width = w; 1673 + ref->frame_height = h; 1674 + memset(&vsi->ref[i], 0, sizeof(vsi->ref[i])); 1675 + } else { 1676 + ref->frame_width = instance->dpb[idx].width; 1677 + ref->frame_height = instance->dpb[idx].height; 1678 + vb = vq->bufs[idx]; 1679 + vsi->ref[i].y.dma_addr = 1680 + vb2_dma_contig_plane_dma_addr(vb, 0); 1681 + if (plane == 1) 1682 + vsi->ref[i].c.dma_addr = 1683 + vsi->ref[i].y.dma_addr + size; 1684 + else 1685 + vsi->ref[i].c.dma_addr = 1686 + vb2_dma_contig_plane_dma_addr(vb, 1); 1687 + } 1688 + } 1689 + 1690 + return 0; 1691 + } 1692 + 1693 + static int vdec_vp9_slice_setup_core(struct vdec_vp9_slice_instance *instance, 1694 + struct vdec_fb *fb, 1695 + struct vdec_lat_buf *lat_buf, 1696 + struct vdec_vp9_slice_pfc *pfc) 1697 + { 1698 + struct vdec_vp9_slice_vsi *vsi = &pfc->vsi; 1699 + int ret; 1700 + 1701 + vdec_vp9_slice_setup_state(vsi); 1702 + 1703 + ret = vdec_vp9_slice_setup_core_to_dst_buf(instance, lat_buf); 1704 + if (ret) 1705 + goto err; 1706 + 1707 + ret = vdec_vp9_slice_setup_core_buffer(instance, pfc, vsi, fb, lat_buf); 1708 + if (ret) 1709 + goto err; 1710 + 1711 + vdec_vp9_slice_setup_seg_buffer(instance, vsi, &instance->seg[1]); 1712 + 1713 + return 0; 1714 + 1715 + err: 1716 + return ret; 1717 + } 1718 + 1719 + static int vdec_vp9_slice_update_core(struct vdec_vp9_slice_instance *instance, 1720 + struct vdec_lat_buf *lat_buf, 1721 + struct vdec_vp9_slice_pfc *pfc) 1722 + { 1723 + struct vdec_vp9_slice_vsi *vsi; 1724 + 1725 + vsi = &pfc->vsi; 1726 + memcpy(&pfc->state[1], &vsi->state, sizeof(vsi->state)); 1727 + 1728 + mtk_vcodec_debug(instance, "Frame %u Y_CRC %08x %08x %08x %08x\n", 1729 + pfc->seq, 1730 + vsi->state.crc[0], vsi->state.crc[1], 1731 + vsi->state.crc[2], vsi->state.crc[3]); 1732 + mtk_vcodec_debug(instance, "Frame %u C_CRC %08x %08x %08x %08x\n", 1733 + pfc->seq, 1734 + vsi->state.crc[4], vsi->state.crc[5], 1735 + vsi->state.crc[6], vsi->state.crc[7]); 1736 + 1737 + return 0; 1738 + } 1739 + 1740 + static int vdec_vp9_slice_init(struct mtk_vcodec_ctx *ctx) 1741 + { 1742 + struct vdec_vp9_slice_instance *instance; 1743 + struct vdec_vp9_slice_init_vsi *vsi; 1744 + int ret; 1745 + 1746 + instance = kzalloc(sizeof(*instance), GFP_KERNEL); 1747 + if (!instance) 1748 + return -ENOMEM; 1749 + 1750 + instance->ctx = ctx; 1751 + instance->vpu.id = SCP_IPI_VDEC_LAT; 1752 + instance->vpu.core_id = SCP_IPI_VDEC_CORE; 1753 + instance->vpu.ctx = ctx; 1754 + instance->vpu.codec_type = ctx->current_codec; 1755 + 1756 + ret = vpu_dec_init(&instance->vpu); 1757 + if (ret) { 1758 + mtk_vcodec_err(instance, "failed to init vpu dec, ret %d\n", ret); 1759 + goto error_vpu_init; 1760 + } 1761 + 1762 + /* init vsi and global flags */ 1763 + 1764 + vsi = instance->vpu.vsi; 1765 + if (!vsi) { 1766 + mtk_vcodec_err(instance, "failed to get VP9 vsi\n"); 1767 + ret = -EINVAL; 1768 + goto error_vsi; 1769 + } 1770 + instance->init_vsi = vsi; 1771 + instance->core_vsi = mtk_vcodec_fw_map_dm_addr(ctx->dev->fw_handler, 1772 + (u32)vsi->core_vsi); 1773 + if (!instance->core_vsi) { 1774 + mtk_vcodec_err(instance, "failed to get VP9 core vsi\n"); 1775 + ret = -EINVAL; 1776 + goto error_vsi; 1777 + } 1778 + 1779 + instance->irq = 1; 1780 + 1781 + ret = vdec_vp9_slice_init_default_frame_ctx(instance); 1782 + if (ret) 1783 + goto error_default_frame_ctx; 1784 + 1785 + ctx->drv_handle = instance; 1786 + 1787 + return 0; 1788 + 1789 + error_default_frame_ctx: 1790 + error_vsi: 1791 + vpu_dec_deinit(&instance->vpu); 1792 + error_vpu_init: 1793 + kfree(instance); 1794 + return ret; 1795 + } 1796 + 1797 + static void vdec_vp9_slice_deinit(void *h_vdec) 1798 + { 1799 + struct vdec_vp9_slice_instance *instance = h_vdec; 1800 + 1801 + if (!instance) 1802 + return; 1803 + 1804 + vpu_dec_deinit(&instance->vpu); 1805 + vdec_vp9_slice_free_working_buffer(instance); 1806 + vdec_msg_queue_deinit(&instance->ctx->msg_queue, instance->ctx); 1807 + kfree(instance); 1808 + } 1809 + 1810 + static int vdec_vp9_slice_flush(void *h_vdec, struct mtk_vcodec_mem *bs, 1811 + struct vdec_fb *fb, bool *res_chg) 1812 + { 1813 + struct vdec_vp9_slice_instance *instance = h_vdec; 1814 + 1815 + mtk_vcodec_debug(instance, "flush ...\n"); 1816 + 1817 + vdec_msg_queue_wait_lat_buf_full(&instance->ctx->msg_queue); 1818 + return vpu_dec_reset(&instance->vpu); 1819 + } 1820 + 1821 + static void vdec_vp9_slice_get_pic_info(struct vdec_vp9_slice_instance *instance) 1822 + { 1823 + struct mtk_vcodec_ctx *ctx = instance->ctx; 1824 + unsigned int data[3]; 1825 + 1826 + mtk_vcodec_debug(instance, "w %u h %u\n", 1827 + ctx->picinfo.pic_w, ctx->picinfo.pic_h); 1828 + 1829 + data[0] = ctx->picinfo.pic_w; 1830 + data[1] = ctx->picinfo.pic_h; 1831 + data[2] = ctx->capture_fourcc; 1832 + vpu_dec_get_param(&instance->vpu, data, 3, GET_PARAM_PIC_INFO); 1833 + 1834 + ctx->picinfo.buf_w = ALIGN(ctx->picinfo.pic_w, 64); 1835 + ctx->picinfo.buf_h = ALIGN(ctx->picinfo.pic_h, 64); 1836 + ctx->picinfo.fb_sz[0] = instance->vpu.fb_sz[0]; 1837 + ctx->picinfo.fb_sz[1] = instance->vpu.fb_sz[1]; 1838 + } 1839 + 1840 + static void vdec_vp9_slice_get_dpb_size(struct vdec_vp9_slice_instance *instance, 1841 + unsigned int *dpb_sz) 1842 + { 1843 + /* refer VP9 specification */ 1844 + *dpb_sz = 9; 1845 + } 1846 + 1847 + static int vdec_vp9_slice_get_param(void *h_vdec, enum vdec_get_param_type type, void *out) 1848 + { 1849 + struct vdec_vp9_slice_instance *instance = h_vdec; 1850 + 1851 + switch (type) { 1852 + case GET_PARAM_PIC_INFO: 1853 + vdec_vp9_slice_get_pic_info(instance); 1854 + break; 1855 + case GET_PARAM_DPB_SIZE: 1856 + vdec_vp9_slice_get_dpb_size(instance, out); 1857 + break; 1858 + case GET_PARAM_CROP_INFO: 1859 + mtk_vcodec_debug(instance, "No need to get vp9 crop information."); 1860 + break; 1861 + default: 1862 + mtk_vcodec_err(instance, "invalid get parameter type=%d\n", 1863 + type); 1864 + return -EINVAL; 1865 + } 1866 + 1867 + return 0; 1868 + } 1869 + 1870 + static int vdec_vp9_slice_lat_decode(void *h_vdec, struct mtk_vcodec_mem *bs, 1871 + struct vdec_fb *fb, bool *res_chg) 1872 + { 1873 + struct vdec_vp9_slice_instance *instance = h_vdec; 1874 + struct vdec_lat_buf *lat_buf; 1875 + struct vdec_vp9_slice_pfc *pfc; 1876 + struct vdec_vp9_slice_vsi *vsi; 1877 + struct mtk_vcodec_ctx *ctx; 1878 + int ret; 1879 + 1880 + if (!instance || !instance->ctx) 1881 + return -EINVAL; 1882 + ctx = instance->ctx; 1883 + 1884 + /* init msgQ for the first time */ 1885 + if (vdec_msg_queue_init(&ctx->msg_queue, ctx, 1886 + vdec_vp9_slice_core_decode, 1887 + sizeof(*pfc))) 1888 + return -ENOMEM; 1889 + 1890 + /* bs NULL means flush decoder */ 1891 + if (!bs) 1892 + return vdec_vp9_slice_flush(h_vdec, bs, fb, res_chg); 1893 + 1894 + lat_buf = vdec_msg_queue_dqbuf(&instance->ctx->msg_queue.lat_ctx); 1895 + if (!lat_buf) { 1896 + mtk_vcodec_err(instance, "Failed to get VP9 lat buf\n"); 1897 + return -EBUSY; 1898 + } 1899 + pfc = (struct vdec_vp9_slice_pfc *)lat_buf->private_data; 1900 + if (!pfc) 1901 + return -EINVAL; 1902 + vsi = &pfc->vsi; 1903 + 1904 + ret = vdec_vp9_slice_setup_lat(instance, bs, lat_buf, pfc); 1905 + if (ret) { 1906 + mtk_vcodec_err(instance, "Failed to setup VP9 lat ret %d\n", ret); 1907 + return ret; 1908 + } 1909 + vdec_vp9_slice_vsi_to_remote(vsi, instance->vsi); 1910 + 1911 + ret = vpu_dec_start(&instance->vpu, NULL, 0); 1912 + if (ret) { 1913 + mtk_vcodec_err(instance, "Failed to dec VP9 ret %d\n", ret); 1914 + return ret; 1915 + } 1916 + 1917 + if (instance->irq) { 1918 + ret = mtk_vcodec_wait_for_done_ctx(ctx, MTK_INST_IRQ_RECEIVED, 1919 + WAIT_INTR_TIMEOUT_MS, MTK_VDEC_LAT0); 1920 + /* update remote vsi if decode timeout */ 1921 + if (ret) { 1922 + mtk_vcodec_err(instance, "VP9 decode timeout %d pic %d\n", ret, pfc->seq); 1923 + WRITE_ONCE(instance->vsi->state.timeout, 1); 1924 + } 1925 + vpu_dec_end(&instance->vpu); 1926 + } 1927 + 1928 + vdec_vp9_slice_vsi_from_remote(vsi, instance->vsi, 0); 1929 + ret = vdec_vp9_slice_update_lat(instance, lat_buf, pfc); 1930 + 1931 + /* LAT trans full, no more UBE or decode timeout */ 1932 + if (ret) { 1933 + mtk_vcodec_err(instance, "VP9 decode error: %d\n", ret); 1934 + return ret; 1935 + } 1936 + 1937 + mtk_vcodec_debug(instance, "lat dma addr: 0x%lx 0x%lx\n", 1938 + (unsigned long)pfc->vsi.trans.dma_addr, 1939 + (unsigned long)pfc->vsi.trans.dma_addr_end); 1940 + 1941 + vdec_msg_queue_update_ube_wptr(&ctx->msg_queue, 1942 + vsi->trans.dma_addr_end + 1943 + ctx->msg_queue.wdma_addr.dma_addr); 1944 + vdec_msg_queue_qbuf(&ctx->dev->msg_queue_core_ctx, lat_buf); 1945 + 1946 + return 0; 1947 + } 1948 + 1949 + static int vdec_vp9_slice_core_decode(struct vdec_lat_buf *lat_buf) 1950 + { 1951 + struct vdec_vp9_slice_instance *instance; 1952 + struct vdec_vp9_slice_pfc *pfc; 1953 + struct mtk_vcodec_ctx *ctx = NULL; 1954 + struct vdec_fb *fb = NULL; 1955 + int ret = -EINVAL; 1956 + 1957 + if (!lat_buf) 1958 + goto err; 1959 + 1960 + pfc = lat_buf->private_data; 1961 + ctx = lat_buf->ctx; 1962 + if (!pfc || !ctx) 1963 + goto err; 1964 + 1965 + instance = ctx->drv_handle; 1966 + if (!instance) 1967 + goto err; 1968 + 1969 + fb = ctx->dev->vdec_pdata->get_cap_buffer(ctx); 1970 + if (!fb) { 1971 + ret = -EBUSY; 1972 + goto err; 1973 + } 1974 + 1975 + ret = vdec_vp9_slice_setup_core(instance, fb, lat_buf, pfc); 1976 + if (ret) { 1977 + mtk_vcodec_err(instance, "vdec_vp9_slice_setup_core\n"); 1978 + goto err; 1979 + } 1980 + vdec_vp9_slice_vsi_to_remote(&pfc->vsi, instance->core_vsi); 1981 + 1982 + ret = vpu_dec_core(&instance->vpu); 1983 + if (ret) { 1984 + mtk_vcodec_err(instance, "vpu_dec_core\n"); 1985 + goto err; 1986 + } 1987 + 1988 + if (instance->irq) { 1989 + ret = mtk_vcodec_wait_for_done_ctx(ctx, MTK_INST_IRQ_RECEIVED, 1990 + WAIT_INTR_TIMEOUT_MS, MTK_VDEC_CORE); 1991 + /* update remote vsi if decode timeout */ 1992 + if (ret) { 1993 + mtk_vcodec_err(instance, "VP9 core timeout pic %d\n", pfc->seq); 1994 + WRITE_ONCE(instance->core_vsi->state.timeout, 1); 1995 + } 1996 + vpu_dec_core_end(&instance->vpu); 1997 + } 1998 + 1999 + vdec_vp9_slice_vsi_from_remote(&pfc->vsi, instance->core_vsi, 1); 2000 + ret = vdec_vp9_slice_update_core(instance, lat_buf, pfc); 2001 + if (ret) { 2002 + mtk_vcodec_err(instance, "vdec_vp9_slice_update_core\n"); 2003 + goto err; 2004 + } 2005 + 2006 + pfc->vsi.trans.dma_addr_end += ctx->msg_queue.wdma_addr.dma_addr; 2007 + mtk_vcodec_debug(instance, "core dma_addr_end 0x%lx\n", 2008 + (unsigned long)pfc->vsi.trans.dma_addr_end); 2009 + vdec_msg_queue_update_ube_rptr(&ctx->msg_queue, pfc->vsi.trans.dma_addr_end); 2010 + ctx->dev->vdec_pdata->cap_to_disp(ctx, 0, lat_buf->src_buf_req); 2011 + 2012 + return 0; 2013 + 2014 + err: 2015 + if (ctx && pfc) { 2016 + /* always update read pointer */ 2017 + vdec_msg_queue_update_ube_rptr(&ctx->msg_queue, pfc->vsi.trans.dma_addr_end); 2018 + 2019 + if (fb) 2020 + ctx->dev->vdec_pdata->cap_to_disp(ctx, 1, lat_buf->src_buf_req); 2021 + } 2022 + return ret; 2023 + } 2024 + 2025 + const struct vdec_common_if vdec_vp9_slice_lat_if = { 2026 + .init = vdec_vp9_slice_init, 2027 + .decode = vdec_vp9_slice_lat_decode, 2028 + .get_param = vdec_vp9_slice_get_param, 2029 + .deinit = vdec_vp9_slice_deinit, 2030 + };

+22 -15

drivers/media/platform/mediatek/vcodec/vdec_drv_if.c

··· 16 16 17 17 int vdec_if_init(struct mtk_vcodec_ctx *ctx, unsigned int fourcc) 18 18 { 19 + enum mtk_vdec_hw_arch hw_arch = ctx->dev->vdec_pdata->hw_arch; 19 20 int ret = 0; 20 21 21 22 switch (fourcc) { 22 23 case V4L2_PIX_FMT_H264_SLICE: 23 - ctx->dec_if = &vdec_h264_slice_if; 24 + if (!ctx->dev->vdec_pdata->is_subdev_supported) { 25 + ctx->dec_if = &vdec_h264_slice_if; 26 + ctx->hw_id = MTK_VDEC_CORE; 27 + } else { 28 + ctx->dec_if = &vdec_h264_slice_multi_if; 29 + ctx->hw_id = IS_VDEC_LAT_ARCH(hw_arch) ? MTK_VDEC_LAT0 : MTK_VDEC_CORE; 30 + } 24 31 break; 25 32 case V4L2_PIX_FMT_H264: 26 33 ctx->dec_if = &vdec_h264_if; 34 + ctx->hw_id = MTK_VDEC_CORE; 35 + break; 36 + case V4L2_PIX_FMT_VP8_FRAME: 37 + ctx->dec_if = &vdec_vp8_slice_if; 27 38 ctx->hw_id = MTK_VDEC_CORE; 28 39 break; 29 40 case V4L2_PIX_FMT_VP8: ··· 45 34 ctx->dec_if = &vdec_vp9_if; 46 35 ctx->hw_id = MTK_VDEC_CORE; 47 36 break; 37 + case V4L2_PIX_FMT_VP9_FRAME: 38 + ctx->dec_if = &vdec_vp9_slice_lat_if; 39 + ctx->hw_id = MTK_VDEC_LAT0; 40 + break; 48 41 default: 49 42 return -EINVAL; 50 43 } 51 44 52 - mtk_vdec_lock(ctx); 53 - mtk_vcodec_dec_clock_on(ctx->dev, ctx->hw_id); 45 + mtk_vcodec_dec_enable_hardware(ctx, ctx->hw_id); 54 46 ret = ctx->dec_if->init(ctx); 55 - mtk_vcodec_dec_clock_off(ctx->dev, ctx->hw_id); 56 - mtk_vdec_unlock(ctx); 47 + mtk_vcodec_dec_disable_hardware(ctx, ctx->hw_id); 57 48 58 49 return ret; 59 50 } ··· 83 70 if (!ctx->drv_handle) 84 71 return -EIO; 85 72 86 - mtk_vdec_lock(ctx); 87 - 73 + mtk_vcodec_dec_enable_hardware(ctx, ctx->hw_id); 88 74 mtk_vcodec_set_curr_ctx(ctx->dev, ctx, ctx->hw_id); 89 - mtk_vcodec_dec_clock_on(ctx->dev, ctx->hw_id); 90 75 ret = ctx->dec_if->decode(ctx->drv_handle, bs, fb, res_chg); 91 - mtk_vcodec_dec_clock_off(ctx->dev, ctx->hw_id); 92 76 mtk_vcodec_set_curr_ctx(ctx->dev, NULL, ctx->hw_id); 93 - 94 - mtk_vdec_unlock(ctx); 77 + mtk_vcodec_dec_disable_hardware(ctx, ctx->hw_id); 95 78 96 79 return ret; 97 80 } ··· 112 103 if (!ctx->drv_handle) 113 104 return; 114 105 115 - mtk_vdec_lock(ctx); 116 - mtk_vcodec_dec_clock_on(ctx->dev, ctx->hw_id); 106 + mtk_vcodec_dec_enable_hardware(ctx, ctx->hw_id); 117 107 ctx->dec_if->deinit(ctx->drv_handle); 118 - mtk_vcodec_dec_clock_off(ctx->dev, ctx->hw_id); 119 - mtk_vdec_unlock(ctx); 108 + mtk_vcodec_dec_disable_hardware(ctx, ctx->hw_id); 120 109 121 110 ctx->drv_handle = NULL; 122 111 }

+3

drivers/media/platform/mediatek/vcodec/vdec_drv_if.h

··· 56 56 57 57 extern const struct vdec_common_if vdec_h264_if; 58 58 extern const struct vdec_common_if vdec_h264_slice_if; 59 + extern const struct vdec_common_if vdec_h264_slice_multi_if; 59 60 extern const struct vdec_common_if vdec_vp8_if; 61 + extern const struct vdec_common_if vdec_vp8_slice_if; 60 62 extern const struct vdec_common_if vdec_vp9_if; 63 + extern const struct vdec_common_if vdec_vp9_slice_lat_if; 61 64 62 65 /** 63 66 * vdec_if_init() - initialize decode driver

+36

drivers/media/platform/mediatek/vcodec/vdec_ipi_msg.h

··· 20 20 AP_IPIMSG_DEC_RESET = 0xA004, 21 21 AP_IPIMSG_DEC_CORE = 0xA005, 22 22 AP_IPIMSG_DEC_CORE_END = 0xA006, 23 + AP_IPIMSG_DEC_GET_PARAM = 0xA007, 23 24 24 25 VPU_IPIMSG_DEC_INIT_ACK = 0xB000, 25 26 VPU_IPIMSG_DEC_START_ACK = 0xB001, ··· 29 28 VPU_IPIMSG_DEC_RESET_ACK = 0xB004, 30 29 VPU_IPIMSG_DEC_CORE_ACK = 0xB005, 31 30 VPU_IPIMSG_DEC_CORE_END_ACK = 0xB006, 31 + VPU_IPIMSG_DEC_GET_PARAM_ACK = 0xB007, 32 32 }; 33 33 34 34 /** ··· 114 112 uint32_t vpu_inst_addr; 115 113 uint32_t vdec_abi_version; 116 114 uint32_t inst_id; 115 + }; 116 + 117 + /** 118 + * struct vdec_ap_ipi_get_param - for AP_IPIMSG_DEC_GET_PARAM 119 + * @msg_id : AP_IPIMSG_DEC_GET_PARAM 120 + * @inst_id : instance ID. Used if the ABI version >= 2. 121 + * @data : picture information 122 + * @param_type : get param type 123 + * @codec_type : Codec fourcc 124 + */ 125 + struct vdec_ap_ipi_get_param { 126 + u32 msg_id; 127 + u32 inst_id; 128 + u32 data[4]; 129 + u32 param_type; 130 + u32 codec_type; 131 + }; 132 + 133 + /** 134 + * struct vdec_vpu_ipi_get_param_ack - for VPU_IPIMSG_DEC_GET_PARAM_ACK 135 + * @msg_id : VPU_IPIMSG_DEC_GET_PARAM_ACK 136 + * @status : VPU execution result 137 + * @ap_inst_addr : AP vcodec_vpu_inst instance address 138 + * @data : picture information from SCP. 139 + * @param_type : get param type 140 + * @reserved : reserved param 141 + */ 142 + struct vdec_vpu_ipi_get_param_ack { 143 + u32 msg_id; 144 + s32 status; 145 + u64 ap_inst_addr; 146 + u32 data[4]; 147 + u32 param_type; 148 + u32 reserved; 117 149 }; 118 150 119 151 #endif

+2

drivers/media/platform/mediatek/vcodec/vdec_msg_queue.c

··· 212 212 return; 213 213 214 214 ctx = lat_buf->ctx; 215 + mtk_vcodec_dec_enable_hardware(ctx, MTK_VDEC_CORE); 215 216 mtk_vcodec_set_curr_ctx(dev, ctx, MTK_VDEC_CORE); 216 217 217 218 lat_buf->core_decode(lat_buf); 218 219 219 220 mtk_vcodec_set_curr_ctx(dev, NULL, MTK_VDEC_CORE); 221 + mtk_vcodec_dec_disable_hardware(ctx, MTK_VDEC_CORE); 220 222 vdec_msg_queue_qbuf(&ctx->msg_queue.lat_ctx, lat_buf); 221 223 222 224 if (!list_empty(&ctx->msg_queue.lat_ctx.ready_queue)) {

+2

drivers/media/platform/mediatek/vcodec/vdec_msg_queue.h

··· 43 43 * @wdma_err_addr: wdma error address used for lat hardware 44 44 * @slice_bc_addr: slice bc address used for lat hardware 45 45 * @ts_info: need to set timestamp from output to capture 46 + * @src_buf_req: output buffer media request object 46 47 * 47 48 * @private_data: shared information used to lat and core hardware 48 49 * @ctx: mtk vcodec context information ··· 55 54 struct mtk_vcodec_mem wdma_err_addr; 56 55 struct mtk_vcodec_mem slice_bc_addr; 57 56 struct vb2_v4l2_buffer ts_info; 57 + struct media_request *src_buf_req; 58 58 59 59 void *private_data; 60 60 struct mtk_vcodec_ctx *ctx;

+51 -2

drivers/media/platform/mediatek/vcodec/vdec_vpu_if.c

··· 6 6 7 7 #include "mtk_vcodec_drv.h" 8 8 #include "mtk_vcodec_util.h" 9 + #include "vdec_drv_if.h" 9 10 #include "vdec_ipi_msg.h" 10 11 #include "vdec_vpu_if.h" 11 12 #include "mtk_vcodec_fw.h" ··· 34 33 */ 35 34 vpu->inst_id = 0xdeadbeef; 36 35 37 - /* Firmware version field does not exist on MT8173. */ 38 - if (vpu->ctx->dev->vdec_pdata->chip == MTK_MT8173) 36 + /* VPU firmware does not contain a version field. */ 37 + if (mtk_vcodec_fw_get_type(vpu->ctx->dev->fw_handler) == VPU) 39 38 return; 40 39 41 40 /* Check firmware version. */ ··· 50 49 default: 51 50 mtk_vcodec_err(vpu, "unhandled firmware version 0x%x\n", 52 51 vpu->fw_abi_version); 52 + vpu->failure = 1; 53 + break; 54 + } 55 + } 56 + 57 + static void handle_get_param_msg_ack(const struct vdec_vpu_ipi_get_param_ack *msg) 58 + { 59 + struct vdec_vpu_inst *vpu = (struct vdec_vpu_inst *) 60 + (unsigned long)msg->ap_inst_addr; 61 + 62 + mtk_vcodec_debug(vpu, "+ ap_inst_addr = 0x%llx", msg->ap_inst_addr); 63 + 64 + /* param_type is enum vdec_get_param_type */ 65 + switch (msg->param_type) { 66 + case GET_PARAM_PIC_INFO: 67 + vpu->fb_sz[0] = msg->data[0]; 68 + vpu->fb_sz[1] = msg->data[1]; 69 + break; 70 + default: 71 + mtk_vcodec_err(vpu, "invalid get param type=%d", msg->param_type); 53 72 vpu->failure = 1; 54 73 break; 55 74 } ··· 110 89 case VPU_IPIMSG_DEC_CORE_END_ACK: 111 90 break; 112 91 92 + case VPU_IPIMSG_DEC_GET_PARAM_ACK: 93 + handle_get_param_msg_ack(data); 94 + break; 113 95 default: 114 96 mtk_vcodec_err(vpu, "invalid msg=%X", msg->msg_id); 115 97 break; ··· 234 210 235 211 for (i = 0; i < len; i++) 236 212 msg.data[i] = data[i]; 213 + msg.codec_type = vpu->codec_type; 214 + 215 + err = vcodec_vpu_send_msg(vpu, (void *)&msg, sizeof(msg)); 216 + mtk_vcodec_debug(vpu, "- ret=%d", err); 217 + return err; 218 + } 219 + 220 + int vpu_dec_get_param(struct vdec_vpu_inst *vpu, uint32_t *data, 221 + unsigned int len, unsigned int param_type) 222 + { 223 + struct vdec_ap_ipi_get_param msg; 224 + int err; 225 + 226 + mtk_vcodec_debug_enter(vpu); 227 + 228 + if (len > ARRAY_SIZE(msg.data)) { 229 + mtk_vcodec_err(vpu, "invalid len = %d\n", len); 230 + return -EINVAL; 231 + } 232 + 233 + memset(&msg, 0, sizeof(msg)); 234 + msg.msg_id = AP_IPIMSG_DEC_GET_PARAM; 235 + msg.inst_id = vpu->inst_id; 236 + memcpy(msg.data, data, sizeof(unsigned int) * len); 237 + msg.param_type = param_type; 237 238 msg.codec_type = vpu->codec_type; 238 239 239 240 err = vcodec_vpu_send_msg(vpu, (void *)&msg, sizeof(msg));

+15

drivers/media/platform/mediatek/vcodec/vdec_vpu_if.h

··· 28 28 * @wq : wait queue to wait VPU message ack 29 29 * @handler : ipi handler for each decoder 30 30 * @codec_type : use codec type to separate different codecs 31 + * @capture_type: used capture type to separate different capture format 32 + * @fb_sz : frame buffer size of each plane 31 33 */ 32 34 struct vdec_vpu_inst { 33 35 int id; ··· 44 42 wait_queue_head_t wq; 45 43 mtk_vcodec_ipi_handler handler; 46 44 unsigned int codec_type; 45 + unsigned int capture_type; 46 + unsigned int fb_sz[2]; 47 47 }; 48 48 49 49 /** ··· 107 103 * @vpu : instance for vdec_vpu_inst 108 104 */ 109 105 int vpu_dec_core_end(struct vdec_vpu_inst *vpu); 106 + 107 + /** 108 + * vpu_dec_get_param - get param from scp 109 + * 110 + * @vpu : instance for vdec_vpu_inst 111 + * @data: meta data to pass bitstream info to VPU decoder 112 + * @len : meta data length 113 + * @param_type : get param type 114 + */ 115 + int vpu_dec_get_param(struct vdec_vpu_inst *vpu, uint32_t *data, 116 + unsigned int len, unsigned int param_type); 110 117 111 118 #endif

+1 -1

drivers/media/platform/mediatek/vcodec/venc_vpu_if.c

··· 18 18 msg->vpu_inst_addr); 19 19 20 20 /* Firmware version field value is unspecified on MT8173. */ 21 - if (vpu->ctx->dev->venc_pdata->chip == MTK_MT8173) 21 + if (mtk_vcodec_fw_get_type(vpu->ctx->dev->fw_handler) == VPU) 22 22 return; 23 23 24 24 /* Check firmware version. */

+12 -7

drivers/media/platform/nvidia/tegra-vde/h264.c

··· 45 45 }; 46 46 47 47 struct h264_reflists { 48 - u8 p[V4L2_H264_NUM_DPB_ENTRIES]; 49 - u8 b0[V4L2_H264_NUM_DPB_ENTRIES]; 50 - u8 b1[V4L2_H264_NUM_DPB_ENTRIES]; 48 + struct v4l2_h264_reference p[V4L2_H264_NUM_DPB_ENTRIES]; 49 + struct v4l2_h264_reference b0[V4L2_H264_NUM_DPB_ENTRIES]; 50 + struct v4l2_h264_reference b1[V4L2_H264_NUM_DPB_ENTRIES]; 51 51 }; 52 52 53 53 static int tegra_vde_wait_mbe(struct tegra_vde *vde) ··· 765 765 struct tegra_m2m_buffer *tb = vb_to_tegra_buf(&dst->vb2_buf); 766 766 struct tegra_ctx_h264 *h = &ctx->h264; 767 767 struct v4l2_h264_reflist_builder b; 768 + struct v4l2_h264_reference *dpb_id; 768 769 struct h264_reflists reflists; 769 770 struct vb2_buffer *ref; 770 771 unsigned int i; 771 - u8 *dpb_id; 772 772 int err; 773 773 774 774 /* ··· 811 811 } 812 812 813 813 for (i = 0; i < b.num_valid; i++) { 814 - ref = get_ref_buf(ctx, dst, dpb_id[i]); 814 + int dpb_idx = dpb_id[i].index; 815 815 816 - err = tegra_vde_h264_setup_frame(ctx, h264, &b, ref, dpb_id[i], 816 + ref = get_ref_buf(ctx, dst, dpb_idx); 817 + 818 + err = tegra_vde_h264_setup_frame(ctx, h264, &b, ref, dpb_idx, 817 819 h264->dpb_frames_nb++); 818 820 if (err) 819 821 return err; 820 822 821 - if (b.refs[dpb_id[i]].pic_order_count < b.cur_pic_order_count) 823 + if (b.refs[dpb_idx].top_field_order_cnt < b.cur_pic_order_count) 822 824 h264->dpb_ref_frames_with_earlier_poc_nb++; 823 825 } 824 826 ··· 880 878 881 879 /* CABAC unsupported by hardware, requires software preprocessing */ 882 880 if (h->pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) 881 + return -EOPNOTSUPP; 882 + 883 + if (h->decode_params->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC) 883 884 return -EOPNOTSUPP; 884 885 885 886 if (h->sps->profile_idc == 66)

-2

drivers/media/platform/nxp/Kconfig

··· 11 11 select MEDIA_CONTROLLER 12 12 select V4L2_FWNODE 13 13 select VIDEO_V4L2_SUBDEV_API 14 - default n 15 14 help 16 15 Video4Linux2 sub-device driver for the MIPI CSI-2 CSIS receiver 17 16 v3.3/v3.6.3 found on some i.MX7 and i.MX8 SoCs. ··· 20 21 depends on V4L_PLATFORM_DRIVERS 21 22 depends on VIDEO_DEV && (PPC_MPC512x || COMPILE_TEST) && I2C 22 23 select VIDEOBUF_DMA_CONTIG 23 - default y 24 24 help 25 25 Support for Freescale VIU video driver. This device captures 26 26 video data, or overlays video on DIU frame buffer.

+2 -2

drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.h

··· 102 102 MXC_JPEG_INVALID = -1, 103 103 MXC_JPEG_YUV420 = 0x0, /* 2 Plannar, Y=1st plane UV=2nd plane */ 104 104 MXC_JPEG_YUV422 = 0x1, /* 1 Plannar, YUYV sequence */ 105 - MXC_JPEG_RGB = 0x2, /* RGBRGB packed format */ 105 + MXC_JPEG_BGR = 0x2, /* BGR packed format */ 106 106 MXC_JPEG_YUV444 = 0x3, /* 1 Plannar, YUVYUV sequence */ 107 107 MXC_JPEG_GRAY = 0x4, /* Y8 or Y12 or Single Component */ 108 108 MXC_JPEG_RESERVED = 0x5, 109 - MXC_JPEG_ARGB = 0x6, 109 + MXC_JPEG_ABGR = 0x6, 110 110 }; 111 111 112 112 #include "mxc-jpeg.h"

+214 -101

drivers/media/platform/nxp/imx-jpeg/mxc-jpeg.c

··· 8 8 * Baseline and extended sequential jpeg decoding is supported. 9 9 * Progressive jpeg decoding is not supported by the IP. 10 10 * Supports encode and decode of various formats: 11 - * YUV444, YUV422, YUV420, RGB, ARGB, Gray 11 + * YUV444, YUV422, YUV420, BGR, ABGR, Gray 12 12 * YUV420 is the only multi-planar format supported. 13 13 * Minimum resolution is 64 x 64, maximum 8192 x 8192. 14 14 * To achieve 8192 x 8192, modify in defconfig: CONFIG_CMA_SIZE_MBYTES=320 ··· 73 73 .flags = MXC_JPEG_FMT_TYPE_ENC, 74 74 }, 75 75 { 76 - .name = "RGB", /*RGBRGB packed format*/ 77 - .fourcc = V4L2_PIX_FMT_RGB24, 76 + .name = "BGR", /*BGR packed format*/ 77 + .fourcc = V4L2_PIX_FMT_BGR24, 78 78 .subsampling = V4L2_JPEG_CHROMA_SUBSAMPLING_444, 79 79 .nc = 3, 80 80 .depth = 24, ··· 82 82 .h_align = 3, 83 83 .v_align = 3, 84 84 .flags = MXC_JPEG_FMT_TYPE_RAW, 85 + .precision = 8, 85 86 }, 86 87 { 87 - .name = "ARGB", /* ARGBARGB packed format */ 88 - .fourcc = V4L2_PIX_FMT_ARGB32, 88 + .name = "ABGR", /* ABGR packed format */ 89 + .fourcc = V4L2_PIX_FMT_ABGR32, 89 90 .subsampling = V4L2_JPEG_CHROMA_SUBSAMPLING_444, 90 91 .nc = 4, 91 92 .depth = 32, ··· 94 93 .h_align = 3, 95 94 .v_align = 3, 96 95 .flags = MXC_JPEG_FMT_TYPE_RAW, 96 + .precision = 8, 97 97 }, 98 98 { 99 99 .name = "YUV420", /* 1st plane = Y, 2nd plane = UV */ ··· 106 104 .h_align = 4, 107 105 .v_align = 4, 108 106 .flags = MXC_JPEG_FMT_TYPE_RAW, 107 + .precision = 8, 109 108 }, 110 109 { 111 110 .name = "YUV422", /* YUYV */ ··· 118 115 .h_align = 4, 119 116 .v_align = 3, 120 117 .flags = MXC_JPEG_FMT_TYPE_RAW, 118 + .precision = 8, 121 119 }, 122 120 { 123 121 .name = "YUV444", /* YUVYUV */ ··· 130 126 .h_align = 3, 131 127 .v_align = 3, 132 128 .flags = MXC_JPEG_FMT_TYPE_RAW, 129 + .precision = 8, 133 130 }, 134 131 { 135 132 .name = "Gray", /* Gray (Y8/Y12) or Single Comp */ ··· 142 137 .h_align = 3, 143 138 .v_align = 3, 144 139 .flags = MXC_JPEG_FMT_TYPE_RAW, 140 + .precision = 8, 145 141 }, 146 142 }; 147 143 ··· 315 309 /* mxc-jpeg specific */ 316 310 bool dht_needed; 317 311 bool jpeg_parse_error; 312 + const struct mxc_jpeg_fmt *fmt; 313 + int w; 314 + int h; 318 315 }; 319 316 320 317 static inline struct mxc_jpeg_src_buf *vb2_to_mxc_buf(struct vb2_buffer *vb) ··· 329 320 static unsigned int debug; 330 321 module_param(debug, int, 0644); 331 322 MODULE_PARM_DESC(debug, "Debug level (0-3)"); 323 + 324 + static void mxc_jpeg_bytesperline(struct mxc_jpeg_q_data *q, u32 precision); 325 + static void mxc_jpeg_sizeimage(struct mxc_jpeg_q_data *q); 332 326 333 327 static void _bswap16(u16 *a) 334 328 { ··· 420 408 return MXC_JPEG_YUV420; 421 409 case V4L2_PIX_FMT_YUV24: 422 410 return MXC_JPEG_YUV444; 423 - case V4L2_PIX_FMT_RGB24: 424 - return MXC_JPEG_RGB; 425 - case V4L2_PIX_FMT_ARGB32: 426 - return MXC_JPEG_ARGB; 411 + case V4L2_PIX_FMT_BGR24: 412 + return MXC_JPEG_BGR; 413 + case V4L2_PIX_FMT_ABGR32: 414 + return MXC_JPEG_ABGR; 427 415 default: 428 416 return MXC_JPEG_INVALID; 429 417 } ··· 696 684 sof->comp[0].h = 0x2; 697 685 break; 698 686 case V4L2_PIX_FMT_YUV24: 699 - case V4L2_PIX_FMT_RGB24: 687 + case V4L2_PIX_FMT_BGR24: 700 688 default: 701 689 sof->components_no = 3; 702 690 break; 703 - case V4L2_PIX_FMT_ARGB32: 691 + case V4L2_PIX_FMT_ABGR32: 704 692 sof->components_no = 4; 705 693 break; 706 694 case V4L2_PIX_FMT_GREY: ··· 728 716 sos->components_no = 3; 729 717 break; 730 718 case V4L2_PIX_FMT_YUV24: 731 - case V4L2_PIX_FMT_RGB24: 719 + case V4L2_PIX_FMT_BGR24: 732 720 default: 733 721 sos->components_no = 3; 734 722 break; 735 - case V4L2_PIX_FMT_ARGB32: 723 + case V4L2_PIX_FMT_ABGR32: 736 724 sos->components_no = 4; 737 725 break; 738 726 case V4L2_PIX_FMT_GREY: ··· 763 751 memcpy(cfg + offset, jpeg_soi, ARRAY_SIZE(jpeg_soi)); 764 752 offset += ARRAY_SIZE(jpeg_soi); 765 753 766 - if (fourcc == V4L2_PIX_FMT_RGB24 || 767 - fourcc == V4L2_PIX_FMT_ARGB32) { 754 + if (fourcc == V4L2_PIX_FMT_BGR24 || 755 + fourcc == V4L2_PIX_FMT_ABGR32) { 768 756 memcpy(cfg + offset, jpeg_app14, sizeof(jpeg_app14)); 769 757 offset += sizeof(jpeg_app14); 770 758 } else { ··· 928 916 mxc_jpeg_set_desc(cfg_desc_handle, reg, slot); 929 917 } 930 918 919 + static bool mxc_jpeg_source_change(struct mxc_jpeg_ctx *ctx, 920 + struct mxc_jpeg_src_buf *jpeg_src_buf) 921 + { 922 + struct device *dev = ctx->mxc_jpeg->dev; 923 + struct mxc_jpeg_q_data *q_data_cap; 924 + 925 + if (!jpeg_src_buf->fmt) 926 + return false; 927 + 928 + q_data_cap = mxc_jpeg_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE); 929 + if (q_data_cap->fmt != jpeg_src_buf->fmt || 930 + q_data_cap->w != jpeg_src_buf->w || 931 + q_data_cap->h != jpeg_src_buf->h) { 932 + dev_dbg(dev, "Detected jpeg res=(%dx%d)->(%dx%d), pixfmt=%c%c%c%c\n", 933 + q_data_cap->w, q_data_cap->h, 934 + jpeg_src_buf->w, jpeg_src_buf->h, 935 + (jpeg_src_buf->fmt->fourcc & 0xff), 936 + (jpeg_src_buf->fmt->fourcc >> 8) & 0xff, 937 + (jpeg_src_buf->fmt->fourcc >> 16) & 0xff, 938 + (jpeg_src_buf->fmt->fourcc >> 24) & 0xff); 939 + 940 + /* 941 + * set-up the capture queue with the pixelformat and resolution 942 + * detected from the jpeg output stream 943 + */ 944 + q_data_cap->w = jpeg_src_buf->w; 945 + q_data_cap->h = jpeg_src_buf->h; 946 + q_data_cap->fmt = jpeg_src_buf->fmt; 947 + q_data_cap->w_adjusted = q_data_cap->w; 948 + q_data_cap->h_adjusted = q_data_cap->h; 949 + 950 + /* 951 + * align up the resolution for CAST IP, 952 + * but leave the buffer resolution unchanged 953 + */ 954 + v4l_bound_align_image(&q_data_cap->w_adjusted, 955 + q_data_cap->w_adjusted, /* adjust up */ 956 + MXC_JPEG_MAX_WIDTH, 957 + q_data_cap->fmt->h_align, 958 + &q_data_cap->h_adjusted, 959 + q_data_cap->h_adjusted, /* adjust up */ 960 + MXC_JPEG_MAX_HEIGHT, 961 + q_data_cap->fmt->v_align, 962 + 0); 963 + 964 + /* setup bytesperline/sizeimage for capture queue */ 965 + mxc_jpeg_bytesperline(q_data_cap, jpeg_src_buf->fmt->precision); 966 + mxc_jpeg_sizeimage(q_data_cap); 967 + notify_src_chg(ctx); 968 + ctx->source_change = 1; 969 + } 970 + return ctx->source_change ? true : false; 971 + } 972 + 973 + static int mxc_jpeg_job_ready(void *priv) 974 + { 975 + struct mxc_jpeg_ctx *ctx = priv; 976 + 977 + return ctx->source_change ? 0 : 1; 978 + } 979 + 931 980 static void mxc_jpeg_device_run(void *priv) 932 981 { 933 982 struct mxc_jpeg_ctx *ctx = priv; ··· 1036 963 1037 964 return; 1038 965 } 966 + if (ctx->mxc_jpeg->mode == MXC_JPEG_DECODE) { 967 + if (ctx->source_change || mxc_jpeg_source_change(ctx, jpeg_src_buf)) { 968 + spin_unlock_irqrestore(&ctx->mxc_jpeg->hw_lock, flags); 969 + v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx); 970 + return; 971 + } 972 + } 1039 973 1040 974 mxc_jpeg_enable(reg); 1041 975 mxc_jpeg_set_l_endian(reg, 1); ··· 1089 1009 q->last_buffer_dequeued = true; 1090 1010 wake_up(&q->done_wq); 1091 1011 ctx->stopped = 0; 1012 + ctx->header_parsed = false; 1092 1013 } 1093 1014 1094 1015 static int mxc_jpeg_decoder_cmd(struct file *file, void *priv, ··· 1162 1081 1163 1082 /* Handle CREATE_BUFS situation - *nplanes != 0 */ 1164 1083 if (*nplanes) { 1084 + if (*nplanes != q_data->fmt->colplanes) 1085 + return -EINVAL; 1165 1086 for (i = 0; i < *nplanes; i++) { 1166 1087 if (sizes[i] < q_data->sizeimage[i]) 1167 1088 return -EINVAL; ··· 1185 1102 struct mxc_jpeg_q_data *q_data = mxc_jpeg_get_q_data(ctx, q->type); 1186 1103 int ret; 1187 1104 1105 + if (ctx->mxc_jpeg->mode == MXC_JPEG_DECODE && V4L2_TYPE_IS_CAPTURE(q->type)) 1106 + ctx->source_change = 0; 1188 1107 dev_dbg(ctx->mxc_jpeg->dev, "Start streaming ctx=%p", ctx); 1189 1108 q_data->sequence = 0; 1190 1109 ··· 1260 1175 1261 1176 for (i = 0; i < MXC_JPEG_NUM_FORMATS; i++) 1262 1177 if (mxc_formats[i].subsampling == header->frame.subsampling && 1263 - mxc_formats[i].nc == header->frame.num_components) { 1178 + mxc_formats[i].nc == header->frame.num_components && 1179 + mxc_formats[i].precision == header->frame.precision) { 1264 1180 fourcc = mxc_formats[i].fourcc; 1265 1181 break; 1266 1182 } 1267 1183 if (fourcc == 0) { 1268 - dev_err(dev, "Could not identify image format nc=%d, subsampling=%d\n", 1184 + dev_err(dev, 1185 + "Could not identify image format nc=%d, subsampling=%d, precision=%d\n", 1269 1186 header->frame.num_components, 1270 - header->frame.subsampling); 1187 + header->frame.subsampling, 1188 + header->frame.precision); 1271 1189 return fourcc; 1272 1190 } 1273 1191 /* ··· 1278 1190 * encoded with 3 components have RGB colorspace, see Recommendation 1279 1191 * ITU-T T.872 chapter 6.5.3 APP14 marker segment for colour encoding 1280 1192 */ 1281 - if (fourcc == V4L2_PIX_FMT_YUV24 || fourcc == V4L2_PIX_FMT_RGB24) { 1193 + if (fourcc == V4L2_PIX_FMT_YUV24 || fourcc == V4L2_PIX_FMT_BGR24) { 1282 1194 if (header->app14_tf == V4L2_JPEG_APP14_TF_CMYK_RGB) 1283 - fourcc = V4L2_PIX_FMT_RGB24; 1195 + fourcc = V4L2_PIX_FMT_BGR24; 1284 1196 else 1285 1197 fourcc = V4L2_PIX_FMT_YUV24; 1286 1198 } ··· 1288 1200 return fourcc; 1289 1201 } 1290 1202 1291 - static void mxc_jpeg_bytesperline(struct mxc_jpeg_q_data *q, 1292 - u32 precision) 1203 + static void mxc_jpeg_bytesperline(struct mxc_jpeg_q_data *q, u32 precision) 1293 1204 { 1294 1205 /* Bytes distance between the leftmost pixels in two adjacent lines */ 1295 1206 if (q->fmt->fourcc == V4L2_PIX_FMT_JPEG) { 1296 1207 /* bytesperline unused for compressed formats */ 1297 1208 q->bytesperline[0] = 0; 1298 1209 q->bytesperline[1] = 0; 1299 - } else if (q->fmt->fourcc == V4L2_PIX_FMT_NV12M) { 1210 + } else if (q->fmt->subsampling == V4L2_JPEG_CHROMA_SUBSAMPLING_420) { 1300 1211 /* When the image format is planar the bytesperline value 1301 1212 * applies to the first plane and is divided by the same factor 1302 1213 * as the width field for the other planes 1303 1214 */ 1304 - q->bytesperline[0] = q->w * (precision / 8) * 1305 - (q->fmt->depth / 8); 1215 + q->bytesperline[0] = q->w * DIV_ROUND_UP(precision, 8); 1306 1216 q->bytesperline[1] = q->bytesperline[0]; 1217 + } else if (q->fmt->subsampling == V4L2_JPEG_CHROMA_SUBSAMPLING_422) { 1218 + q->bytesperline[0] = q->w * DIV_ROUND_UP(precision, 8) * 2; 1219 + q->bytesperline[1] = 0; 1220 + } else if (q->fmt->subsampling == V4L2_JPEG_CHROMA_SUBSAMPLING_444) { 1221 + q->bytesperline[0] = q->w * DIV_ROUND_UP(precision, 8) * q->fmt->nc; 1222 + q->bytesperline[1] = 0; 1307 1223 } else { 1308 - /* single plane formats */ 1309 - q->bytesperline[0] = q->w * (precision / 8) * 1310 - (q->fmt->depth / 8); 1224 + /* grayscale */ 1225 + q->bytesperline[0] = q->w * DIV_ROUND_UP(precision, 8); 1311 1226 q->bytesperline[1] = 0; 1312 1227 } 1313 1228 } ··· 1336 1245 } 1337 1246 } 1338 1247 1339 - static int mxc_jpeg_parse(struct mxc_jpeg_ctx *ctx, 1340 - u8 *src_addr, u32 size, bool *dht_needed) 1248 + static int mxc_jpeg_parse(struct mxc_jpeg_ctx *ctx, struct vb2_buffer *vb) 1341 1249 { 1342 1250 struct device *dev = ctx->mxc_jpeg->dev; 1343 - struct mxc_jpeg_q_data *q_data_out, *q_data_cap; 1344 - enum v4l2_buf_type cap_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 1345 - bool src_chg = false; 1251 + struct mxc_jpeg_q_data *q_data_out; 1346 1252 u32 fourcc; 1347 1253 struct v4l2_jpeg_header header; 1348 1254 struct mxc_jpeg_sof *psof = NULL; 1349 1255 struct mxc_jpeg_sos *psos = NULL; 1256 + struct mxc_jpeg_src_buf *jpeg_src_buf = vb2_to_mxc_buf(vb); 1257 + u8 *src_addr = (u8 *)vb2_plane_vaddr(vb, 0); 1258 + u32 size = vb2_get_plane_payload(vb, 0); 1350 1259 int ret; 1351 1260 1352 1261 memset(&header, 0, sizeof(header)); ··· 1357 1266 } 1358 1267 1359 1268 /* if DHT marker present, no need to inject default one */ 1360 - *dht_needed = (header.num_dht == 0); 1269 + jpeg_src_buf->dht_needed = (header.num_dht == 0); 1361 1270 1362 1271 q_data_out = mxc_jpeg_get_q_data(ctx, 1363 1272 V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); ··· 1365 1274 dev_warn(dev, "Invalid user resolution 0x0"); 1366 1275 dev_warn(dev, "Keeping resolution from JPEG: %dx%d", 1367 1276 header.frame.width, header.frame.height); 1368 - q_data_out->w = header.frame.width; 1369 - q_data_out->h = header.frame.height; 1370 1277 } else if (header.frame.width != q_data_out->w || 1371 1278 header.frame.height != q_data_out->h) { 1372 1279 dev_err(dev, 1373 1280 "Resolution mismatch: %dx%d (JPEG) versus %dx%d(user)", 1374 1281 header.frame.width, header.frame.height, 1375 1282 q_data_out->w, q_data_out->h); 1376 - return -EINVAL; 1377 1283 } 1284 + q_data_out->w = header.frame.width; 1285 + q_data_out->h = header.frame.height; 1378 1286 if (header.frame.width % 8 != 0 || header.frame.height % 8 != 0) { 1379 1287 dev_err(dev, "JPEG width or height not multiple of 8: %dx%d\n", 1380 1288 header.frame.width, header.frame.height); ··· 1406 1316 if (fourcc == 0) 1407 1317 return -EINVAL; 1408 1318 1409 - /* 1410 - * set-up the capture queue with the pixelformat and resolution 1411 - * detected from the jpeg output stream 1412 - */ 1413 - q_data_cap = mxc_jpeg_get_q_data(ctx, cap_type); 1414 - if (q_data_cap->w != header.frame.width || 1415 - q_data_cap->h != header.frame.height) 1416 - src_chg = true; 1417 - q_data_cap->w = header.frame.width; 1418 - q_data_cap->h = header.frame.height; 1419 - q_data_cap->fmt = mxc_jpeg_find_format(ctx, fourcc); 1420 - q_data_cap->w_adjusted = q_data_cap->w; 1421 - q_data_cap->h_adjusted = q_data_cap->h; 1422 - /* 1423 - * align up the resolution for CAST IP, 1424 - * but leave the buffer resolution unchanged 1425 - */ 1426 - v4l_bound_align_image(&q_data_cap->w_adjusted, 1427 - q_data_cap->w_adjusted, /* adjust up */ 1428 - MXC_JPEG_MAX_WIDTH, 1429 - q_data_cap->fmt->h_align, 1430 - &q_data_cap->h_adjusted, 1431 - q_data_cap->h_adjusted, /* adjust up */ 1432 - MXC_JPEG_MAX_HEIGHT, 1433 - q_data_cap->fmt->v_align, 1434 - 0); 1435 - dev_dbg(dev, "Detected jpeg res=(%dx%d)->(%dx%d), pixfmt=%c%c%c%c\n", 1436 - q_data_cap->w, q_data_cap->h, 1437 - q_data_cap->w_adjusted, q_data_cap->h_adjusted, 1438 - (fourcc & 0xff), 1439 - (fourcc >> 8) & 0xff, 1440 - (fourcc >> 16) & 0xff, 1441 - (fourcc >> 24) & 0xff); 1319 + jpeg_src_buf->fmt = mxc_jpeg_find_format(ctx, fourcc); 1320 + jpeg_src_buf->w = header.frame.width; 1321 + jpeg_src_buf->h = header.frame.height; 1322 + ctx->header_parsed = true; 1442 1323 1443 - /* setup bytesperline/sizeimage for capture queue */ 1444 - mxc_jpeg_bytesperline(q_data_cap, header.frame.precision); 1445 - mxc_jpeg_sizeimage(q_data_cap); 1446 - 1447 - /* 1448 - * if the CAPTURE format was updated with new values, regardless of 1449 - * whether they match the values set by the client or not, signal 1450 - * a source change event 1451 - */ 1452 - if (src_chg) 1453 - notify_src_chg(ctx); 1324 + if (!v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx)) 1325 + mxc_jpeg_source_change(ctx, jpeg_src_buf); 1454 1326 1455 1327 return 0; 1456 1328 } ··· 1433 1381 1434 1382 jpeg_src_buf = vb2_to_mxc_buf(vb); 1435 1383 jpeg_src_buf->jpeg_parse_error = false; 1436 - ret = mxc_jpeg_parse(ctx, 1437 - (u8 *)vb2_plane_vaddr(vb, 0), 1438 - vb2_get_plane_payload(vb, 0), 1439 - &jpeg_src_buf->dht_needed); 1384 + ret = mxc_jpeg_parse(ctx, vb); 1440 1385 if (ret) 1441 1386 jpeg_src_buf->jpeg_parse_error = true; 1442 1387 ··· 1471 1422 i, vb2_plane_size(vb, i), sizeimage); 1472 1423 return -EINVAL; 1473 1424 } 1474 - vb2_set_plane_payload(vb, i, sizeimage); 1475 1425 } 1476 1426 return 0; 1477 1427 } ··· 1488 1440 if (list_empty(&q->done_list)) { 1489 1441 vbuf->flags |= V4L2_BUF_FLAG_LAST; 1490 1442 ctx->stopped = 0; 1443 + ctx->header_parsed = false; 1491 1444 } 1492 1445 } 1493 1446 ··· 1519 1470 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; 1520 1471 src_vq->lock = &ctx->mxc_jpeg->lock; 1521 1472 src_vq->dev = ctx->mxc_jpeg->dev; 1522 - src_vq->allow_zero_bytesused = 1; /* keep old userspace apps working */ 1523 1473 1524 1474 ret = vb2_queue_init(src_vq); 1525 1475 if (ret) ··· 1558 1510 q[i]->h = MXC_JPEG_DEFAULT_HEIGHT; 1559 1511 q[i]->w_adjusted = MXC_JPEG_DEFAULT_WIDTH; 1560 1512 q[i]->h_adjusted = MXC_JPEG_DEFAULT_HEIGHT; 1561 - mxc_jpeg_bytesperline(q[i], 8); 1513 + mxc_jpeg_bytesperline(q[i], q[i]->fmt->precision); 1562 1514 mxc_jpeg_sizeimage(q[i]); 1563 1515 } 1564 1516 } ··· 1617 1569 static int mxc_jpeg_querycap(struct file *file, void *priv, 1618 1570 struct v4l2_capability *cap) 1619 1571 { 1620 - struct mxc_jpeg_dev *mxc_jpeg = video_drvdata(file); 1621 - 1622 1572 strscpy(cap->driver, MXC_JPEG_NAME " codec", sizeof(cap->driver)); 1623 1573 strscpy(cap->card, MXC_JPEG_NAME " codec", sizeof(cap->card)); 1624 - snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", 1625 - dev_name(mxc_jpeg->dev)); 1626 1574 cap->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_M2M_MPLANE; 1627 1575 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; 1628 1576 ··· 1629 1585 struct v4l2_fmtdesc *f) 1630 1586 { 1631 1587 struct mxc_jpeg_ctx *ctx = mxc_jpeg_fh_to_ctx(priv); 1588 + struct mxc_jpeg_q_data *q_data = mxc_jpeg_get_q_data(ctx, f->type); 1632 1589 1633 - if (ctx->mxc_jpeg->mode == MXC_JPEG_ENCODE) 1590 + if (ctx->mxc_jpeg->mode == MXC_JPEG_ENCODE) { 1634 1591 return enum_fmt(mxc_formats, MXC_JPEG_NUM_FORMATS, f, 1635 1592 MXC_JPEG_FMT_TYPE_ENC); 1636 - else 1593 + } else if (!ctx->header_parsed) { 1637 1594 return enum_fmt(mxc_formats, MXC_JPEG_NUM_FORMATS, f, 1638 1595 MXC_JPEG_FMT_TYPE_RAW); 1596 + } else { 1597 + /* For the decoder CAPTURE queue, only enumerate the raw formats 1598 + * supported for the format currently active on OUTPUT 1599 + * (more precisely what was propagated on capture queue 1600 + * after jpeg parse on the output buffer) 1601 + */ 1602 + if (f->index) 1603 + return -EINVAL; 1604 + f->pixelformat = q_data->fmt->fourcc; 1605 + strscpy(f->description, q_data->fmt->name, sizeof(f->description)); 1606 + return 0; 1607 + } 1639 1608 } 1640 1609 1641 1610 static int mxc_jpeg_enum_fmt_vid_out(struct file *file, void *priv, 1642 1611 struct v4l2_fmtdesc *f) 1643 1612 { 1644 1613 struct mxc_jpeg_ctx *ctx = mxc_jpeg_fh_to_ctx(priv); 1614 + u32 type = ctx->mxc_jpeg->mode == MXC_JPEG_DECODE ? MXC_JPEG_FMT_TYPE_ENC : 1615 + MXC_JPEG_FMT_TYPE_RAW; 1616 + int ret; 1645 1617 1618 + ret = enum_fmt(mxc_formats, MXC_JPEG_NUM_FORMATS, f, type); 1619 + if (ret) 1620 + return ret; 1646 1621 if (ctx->mxc_jpeg->mode == MXC_JPEG_DECODE) 1647 - return enum_fmt(mxc_formats, MXC_JPEG_NUM_FORMATS, f, 1648 - MXC_JPEG_FMT_TYPE_ENC); 1649 - else 1650 - return enum_fmt(mxc_formats, MXC_JPEG_NUM_FORMATS, f, 1651 - MXC_JPEG_FMT_TYPE_RAW); 1622 + f->flags = V4L2_FMT_FLAG_DYN_RESOLUTION; 1623 + return 0; 1652 1624 } 1653 1625 1654 1626 static int mxc_jpeg_try_fmt(struct v4l2_format *f, const struct mxc_jpeg_fmt *fmt, ··· 1712 1652 } 1713 1653 1714 1654 /* calculate bytesperline & sizeimage into the tmp_q */ 1715 - mxc_jpeg_bytesperline(&tmp_q, 8); 1655 + mxc_jpeg_bytesperline(&tmp_q, fmt->precision); 1716 1656 mxc_jpeg_sizeimage(&tmp_q); 1717 1657 1718 1658 /* adjust user format according to our calculations */ ··· 1879 1819 struct v4l2_format *f) 1880 1820 { 1881 1821 int ret; 1822 + struct mxc_jpeg_ctx *ctx = mxc_jpeg_fh_to_ctx(priv); 1823 + struct vb2_queue *dst_vq; 1824 + struct mxc_jpeg_q_data *q_data_cap; 1825 + enum v4l2_buf_type cap_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 1826 + struct v4l2_format fc; 1882 1827 1883 1828 ret = mxc_jpeg_try_fmt_vid_out(file, priv, f); 1884 1829 if (ret) 1885 1830 return ret; 1886 1831 1887 - return mxc_jpeg_s_fmt(mxc_jpeg_fh_to_ctx(priv), f); 1832 + ret = mxc_jpeg_s_fmt(mxc_jpeg_fh_to_ctx(priv), f); 1833 + if (ret) 1834 + return ret; 1835 + 1836 + if (ctx->mxc_jpeg->mode != MXC_JPEG_DECODE) 1837 + return 0; 1838 + 1839 + dst_vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, cap_type); 1840 + if (!dst_vq) 1841 + return -EINVAL; 1842 + 1843 + if (vb2_is_busy(dst_vq)) 1844 + return 0; 1845 + 1846 + q_data_cap = mxc_jpeg_get_q_data(ctx, cap_type); 1847 + if (q_data_cap->w == f->fmt.pix_mp.width && q_data_cap->h == f->fmt.pix_mp.height) 1848 + return 0; 1849 + memset(&fc, 0, sizeof(fc)); 1850 + fc.type = cap_type; 1851 + fc.fmt.pix_mp.pixelformat = q_data_cap->fmt->fourcc; 1852 + fc.fmt.pix_mp.width = f->fmt.pix_mp.width; 1853 + fc.fmt.pix_mp.height = f->fmt.pix_mp.height; 1854 + 1855 + return mxc_jpeg_s_fmt_vid_cap(file, priv, &fc); 1888 1856 } 1889 1857 1890 1858 static int mxc_jpeg_g_fmt_vid(struct file *file, void *priv, ··· 2050 1962 }; 2051 1963 2052 1964 static const struct v4l2_m2m_ops mxc_jpeg_m2m_ops = { 1965 + .job_ready = mxc_jpeg_job_ready, 2053 1966 .device_run = mxc_jpeg_device_run, 2054 1967 }; 2055 1968 ··· 2302 2213 } 2303 2214 #endif 2304 2215 2216 + #ifdef CONFIG_PM_SLEEP 2217 + static int mxc_jpeg_suspend(struct device *dev) 2218 + { 2219 + struct mxc_jpeg_dev *jpeg = dev_get_drvdata(dev); 2220 + 2221 + v4l2_m2m_suspend(jpeg->m2m_dev); 2222 + return pm_runtime_force_suspend(dev); 2223 + } 2224 + 2225 + static int mxc_jpeg_resume(struct device *dev) 2226 + { 2227 + struct mxc_jpeg_dev *jpeg = dev_get_drvdata(dev); 2228 + int ret; 2229 + 2230 + ret = pm_runtime_force_resume(dev); 2231 + if (ret < 0) 2232 + return ret; 2233 + 2234 + v4l2_m2m_resume(jpeg->m2m_dev); 2235 + return ret; 2236 + } 2237 + #endif 2238 + 2305 2239 static const struct dev_pm_ops mxc_jpeg_pm_ops = { 2306 2240 SET_RUNTIME_PM_OPS(mxc_jpeg_runtime_suspend, 2307 2241 mxc_jpeg_runtime_resume, NULL) 2242 + SET_SYSTEM_SLEEP_PM_OPS(mxc_jpeg_suspend, mxc_jpeg_resume) 2308 2243 }; 2309 2244 2310 2245 static int mxc_jpeg_remove(struct platform_device *pdev)

+5 -1

drivers/media/platform/nxp/imx-jpeg/mxc-jpeg.h

··· 17 17 #define MXC_JPEG_FMT_TYPE_RAW 1 18 18 #define MXC_JPEG_DEFAULT_WIDTH 1280 19 19 #define MXC_JPEG_DEFAULT_HEIGHT 720 20 - #define MXC_JPEG_DEFAULT_PFMT V4L2_PIX_FMT_RGB24 20 + #define MXC_JPEG_DEFAULT_PFMT V4L2_PIX_FMT_BGR24 21 21 #define MXC_JPEG_MIN_WIDTH 64 22 22 #define MXC_JPEG_MIN_HEIGHT 64 23 23 #define MXC_JPEG_MAX_WIDTH 0x2000 ··· 49 49 * @h_align: horizontal alignment order (align to 2^h_align) 50 50 * @v_align: vertical alignment order (align to 2^v_align) 51 51 * @flags: flags describing format applicability 52 + * @precision: jpeg sample precision 52 53 */ 53 54 struct mxc_jpeg_fmt { 54 55 const char *name; ··· 61 60 int h_align; 62 61 int v_align; 63 62 u32 flags; 63 + u8 precision; 64 64 }; 65 65 66 66 struct mxc_jpeg_desc { ··· 95 93 unsigned int stopping; 96 94 unsigned int stopped; 97 95 unsigned int slot; 96 + unsigned int source_change; 97 + bool header_parsed; 98 98 }; 99 99 100 100 struct mxc_jpeg_slot_data {

+337 -360

drivers/media/platform/nxp/imx-mipi-csis.c

··· 243 243 #define MIPI_CSI2_DATA_TYPE_RAW14 0x2d 244 244 #define MIPI_CSI2_DATA_TYPE_USER(x) (0x30 + (x)) 245 245 246 - enum { 247 - ST_POWERED = 1, 248 - ST_STREAMING = 2, 249 - ST_SUSPENDED = 4, 250 - }; 251 - 252 246 struct mipi_csis_event { 253 247 bool debug; 254 248 u32 mask; ··· 304 310 unsigned int num_clocks; 305 311 }; 306 312 307 - struct csi_state { 313 + struct mipi_csis_device { 308 314 struct device *dev; 309 315 void __iomem *regs; 310 316 struct clk_bulk_data *clks; ··· 322 328 u32 hs_settle; 323 329 u32 clk_settle; 324 330 325 - struct mutex lock; /* Protect csis_fmt, format_mbus and state */ 331 + struct mutex lock; /* Protect csis_fmt and format_mbus */ 326 332 const struct csis_pix_format *csis_fmt; 327 333 struct v4l2_mbus_framefmt format_mbus[CSIS_PADS_NUM]; 328 - u32 state; 329 334 330 335 spinlock_t slock; /* Protect events */ 331 336 struct mipi_csis_event events[MIPI_CSIS_NUM_EVENTS]; ··· 463 470 .output = MEDIA_BUS_FMT_SRGGB14_1X14, 464 471 .data_type = MIPI_CSI2_DATA_TYPE_RAW14, 465 472 .width = 14, 473 + }, 474 + /* JPEG */ 475 + { 476 + .code = MEDIA_BUS_FMT_JPEG_1X8, 477 + .output = MEDIA_BUS_FMT_JPEG_1X8, 478 + /* 479 + * Map JPEG_1X8 to the RAW8 datatype. 480 + * 481 + * The CSI-2 specification suggests in Annex A "JPEG8 Data 482 + * Format (informative)" to transmit JPEG data using one of the 483 + * Data Types aimed to represent arbitrary data, such as the 484 + * "User Defined Data Type 1" (0x30). 485 + * 486 + * However, when configured with a User Defined Data Type, the 487 + * CSIS outputs data in quad pixel mode regardless of the mode 488 + * selected in the MIPI_CSIS_ISP_CONFIG_CH register. Neither of 489 + * the IP cores connected to the CSIS in i.MX SoCs (CSI bridge 490 + * or ISI) support quad pixel mode, so this will never work in 491 + * practice. 492 + * 493 + * Some sensors (such as the OV5640) send JPEG data using the 494 + * RAW8 data type. This is usable and works, so map the JPEG 495 + * format to RAW8. If the CSIS ends up being integrated in an 496 + * SoC that can support quad pixel mode, this will have to be 497 + * revisited. 498 + */ 499 + .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 500 + .width = 8, 466 501 } 467 502 }; 468 503 ··· 508 487 * Hardware configuration 509 488 */ 510 489 511 - static inline u32 mipi_csis_read(struct csi_state *state, u32 reg) 490 + static inline u32 mipi_csis_read(struct mipi_csis_device *csis, u32 reg) 512 491 { 513 - return readl(state->regs + reg); 492 + return readl(csis->regs + reg); 514 493 } 515 494 516 - static inline void mipi_csis_write(struct csi_state *state, u32 reg, u32 val) 495 + static inline void mipi_csis_write(struct mipi_csis_device *csis, u32 reg, 496 + u32 val) 517 497 { 518 - writel(val, state->regs + reg); 498 + writel(val, csis->regs + reg); 519 499 } 520 500 521 - static void mipi_csis_enable_interrupts(struct csi_state *state, bool on) 501 + static void mipi_csis_enable_interrupts(struct mipi_csis_device *csis, bool on) 522 502 { 523 - mipi_csis_write(state, MIPI_CSIS_INT_MSK, on ? 0xffffffff : 0); 524 - mipi_csis_write(state, MIPI_CSIS_DBG_INTR_MSK, on ? 0xffffffff : 0); 503 + mipi_csis_write(csis, MIPI_CSIS_INT_MSK, on ? 0xffffffff : 0); 504 + mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_MSK, on ? 0xffffffff : 0); 525 505 } 526 506 527 - static void mipi_csis_sw_reset(struct csi_state *state) 507 + static void mipi_csis_sw_reset(struct mipi_csis_device *csis) 528 508 { 529 - u32 val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL); 509 + u32 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 530 510 531 - mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, 511 + mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, 532 512 val | MIPI_CSIS_CMN_CTRL_RESET); 533 513 usleep_range(10, 20); 534 514 } 535 515 536 - static void mipi_csis_system_enable(struct csi_state *state, int on) 516 + static void mipi_csis_system_enable(struct mipi_csis_device *csis, int on) 537 517 { 538 518 u32 val, mask; 539 519 540 - val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL); 520 + val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 541 521 if (on) 542 522 val |= MIPI_CSIS_CMN_CTRL_ENABLE; 543 523 else 544 524 val &= ~MIPI_CSIS_CMN_CTRL_ENABLE; 545 - mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val); 525 + mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val); 546 526 547 - val = mipi_csis_read(state, MIPI_CSIS_DPHY_CMN_CTRL); 527 + val = mipi_csis_read(csis, MIPI_CSIS_DPHY_CMN_CTRL); 548 528 val &= ~MIPI_CSIS_DPHY_CMN_CTRL_ENABLE; 549 529 if (on) { 550 - mask = (1 << (state->bus.num_data_lanes + 1)) - 1; 530 + mask = (1 << (csis->bus.num_data_lanes + 1)) - 1; 551 531 val |= (mask & MIPI_CSIS_DPHY_CMN_CTRL_ENABLE); 552 532 } 553 - mipi_csis_write(state, MIPI_CSIS_DPHY_CMN_CTRL, val); 533 + mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL, val); 554 534 } 555 535 556 - /* Called with the state.lock mutex held */ 557 - static void __mipi_csis_set_format(struct csi_state *state) 536 + /* Called with the csis.lock mutex held */ 537 + static void __mipi_csis_set_format(struct mipi_csis_device *csis) 558 538 { 559 - struct v4l2_mbus_framefmt *mf = &state->format_mbus[CSIS_PAD_SINK]; 539 + struct v4l2_mbus_framefmt *mf = &csis->format_mbus[CSIS_PAD_SINK]; 560 540 u32 val; 561 541 562 542 /* Color format */ 563 - val = mipi_csis_read(state, MIPI_CSIS_ISP_CONFIG_CH(0)); 543 + val = mipi_csis_read(csis, MIPI_CSIS_ISP_CONFIG_CH(0)); 564 544 val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK 565 545 | MIPI_CSIS_ISPCFG_PIXEL_MASK); 566 546 ··· 578 556 * 579 557 * TODO: Verify which other formats require DUAL (or QUAD) modes. 580 558 */ 581 - if (state->csis_fmt->data_type == MIPI_CSI2_DATA_TYPE_YUV422_8) 559 + if (csis->csis_fmt->data_type == MIPI_CSI2_DATA_TYPE_YUV422_8) 582 560 val |= MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL; 583 561 584 - val |= MIPI_CSIS_ISPCFG_FMT(state->csis_fmt->data_type); 585 - mipi_csis_write(state, MIPI_CSIS_ISP_CONFIG_CH(0), val); 562 + val |= MIPI_CSIS_ISPCFG_FMT(csis->csis_fmt->data_type); 563 + mipi_csis_write(csis, MIPI_CSIS_ISP_CONFIG_CH(0), val); 586 564 587 565 /* Pixel resolution */ 588 566 val = mf->width | (mf->height << 16); 589 - mipi_csis_write(state, MIPI_CSIS_ISP_RESOL_CH(0), val); 567 + mipi_csis_write(csis, MIPI_CSIS_ISP_RESOL_CH(0), val); 590 568 } 591 569 592 - static int mipi_csis_calculate_params(struct csi_state *state) 570 + static int mipi_csis_calculate_params(struct mipi_csis_device *csis) 593 571 { 594 572 s64 link_freq; 595 573 u32 lane_rate; 596 574 597 575 /* Calculate the line rate from the pixel rate. */ 598 - link_freq = v4l2_get_link_freq(state->src_sd->ctrl_handler, 599 - state->csis_fmt->width, 600 - state->bus.num_data_lanes * 2); 576 + link_freq = v4l2_get_link_freq(csis->src_sd->ctrl_handler, 577 + csis->csis_fmt->width, 578 + csis->bus.num_data_lanes * 2); 601 579 if (link_freq < 0) { 602 - dev_err(state->dev, "Unable to obtain link frequency: %d\n", 580 + dev_err(csis->dev, "Unable to obtain link frequency: %d\n", 603 581 (int)link_freq); 604 582 return link_freq; 605 583 } ··· 607 585 lane_rate = link_freq * 2; 608 586 609 587 if (lane_rate < 80000000 || lane_rate > 1500000000) { 610 - dev_dbg(state->dev, "Out-of-bound lane rate %u\n", lane_rate); 588 + dev_dbg(csis->dev, "Out-of-bound lane rate %u\n", lane_rate); 611 589 return -EINVAL; 612 590 } 613 591 ··· 617 595 * (which is documented as corresponding to CSI-2 v0.87 to v1.00) until 618 596 * we figure out how to compute it correctly. 619 597 */ 620 - state->hs_settle = (lane_rate - 5000000) / 45000000; 621 - state->clk_settle = 0; 598 + csis->hs_settle = (lane_rate - 5000000) / 45000000; 599 + csis->clk_settle = 0; 622 600 623 - dev_dbg(state->dev, "lane rate %u, Tclk_settle %u, Ths_settle %u\n", 624 - lane_rate, state->clk_settle, state->hs_settle); 601 + dev_dbg(csis->dev, "lane rate %u, Tclk_settle %u, Ths_settle %u\n", 602 + lane_rate, csis->clk_settle, csis->hs_settle); 625 603 626 - if (state->debug.hs_settle < 0xff) { 627 - dev_dbg(state->dev, "overriding Ths_settle with %u\n", 628 - state->debug.hs_settle); 629 - state->hs_settle = state->debug.hs_settle; 604 + if (csis->debug.hs_settle < 0xff) { 605 + dev_dbg(csis->dev, "overriding Ths_settle with %u\n", 606 + csis->debug.hs_settle); 607 + csis->hs_settle = csis->debug.hs_settle; 630 608 } 631 609 632 - if (state->debug.clk_settle < 4) { 633 - dev_dbg(state->dev, "overriding Tclk_settle with %u\n", 634 - state->debug.clk_settle); 635 - state->clk_settle = state->debug.clk_settle; 610 + if (csis->debug.clk_settle < 4) { 611 + dev_dbg(csis->dev, "overriding Tclk_settle with %u\n", 612 + csis->debug.clk_settle); 613 + csis->clk_settle = csis->debug.clk_settle; 636 614 } 637 615 638 616 return 0; 639 617 } 640 618 641 - static void mipi_csis_set_params(struct csi_state *state) 619 + static void mipi_csis_set_params(struct mipi_csis_device *csis) 642 620 { 643 - int lanes = state->bus.num_data_lanes; 621 + int lanes = csis->bus.num_data_lanes; 644 622 u32 val; 645 623 646 - val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL); 624 + val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 647 625 val &= ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK; 648 626 val |= (lanes - 1) << MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET; 649 - if (state->info->version == MIPI_CSIS_V3_3) 627 + if (csis->info->version == MIPI_CSIS_V3_3) 650 628 val |= MIPI_CSIS_CMN_CTRL_INTER_MODE; 651 - mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val); 629 + mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val); 652 630 653 - __mipi_csis_set_format(state); 631 + __mipi_csis_set_format(csis); 654 632 655 - mipi_csis_write(state, MIPI_CSIS_DPHY_CMN_CTRL, 656 - MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(state->hs_settle) | 657 - MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(state->clk_settle)); 633 + mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL, 634 + MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(csis->hs_settle) | 635 + MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(csis->clk_settle)); 658 636 659 637 val = (0 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET) 660 638 | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET) 661 639 | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET); 662 - mipi_csis_write(state, MIPI_CSIS_ISP_SYNC_CH(0), val); 640 + mipi_csis_write(csis, MIPI_CSIS_ISP_SYNC_CH(0), val); 663 641 664 - val = mipi_csis_read(state, MIPI_CSIS_CLK_CTRL); 642 + val = mipi_csis_read(csis, MIPI_CSIS_CLK_CTRL); 665 643 val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC; 666 644 val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15); 667 645 val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK; 668 - mipi_csis_write(state, MIPI_CSIS_CLK_CTRL, val); 646 + mipi_csis_write(csis, MIPI_CSIS_CLK_CTRL, val); 669 647 670 - mipi_csis_write(state, MIPI_CSIS_DPHY_BCTRL_L, 648 + mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_L, 671 649 MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV | 672 650 MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ | 673 651 MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V | ··· 675 653 MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV | 676 654 MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV | 677 655 MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(20000000)); 678 - mipi_csis_write(state, MIPI_CSIS_DPHY_BCTRL_H, 0); 656 + mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_H, 0); 679 657 680 658 /* Update the shadow register. */ 681 - val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL); 682 - mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, 659 + val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 660 + mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, 683 661 val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW | 684 662 MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL); 685 663 } 686 664 687 - static int mipi_csis_clk_enable(struct csi_state *state) 665 + static int mipi_csis_clk_enable(struct mipi_csis_device *csis) 688 666 { 689 - return clk_bulk_prepare_enable(state->info->num_clocks, state->clks); 667 + return clk_bulk_prepare_enable(csis->info->num_clocks, csis->clks); 690 668 } 691 669 692 - static void mipi_csis_clk_disable(struct csi_state *state) 670 + static void mipi_csis_clk_disable(struct mipi_csis_device *csis) 693 671 { 694 - clk_bulk_disable_unprepare(state->info->num_clocks, state->clks); 672 + clk_bulk_disable_unprepare(csis->info->num_clocks, csis->clks); 695 673 } 696 674 697 - static int mipi_csis_clk_get(struct csi_state *state) 675 + static int mipi_csis_clk_get(struct mipi_csis_device *csis) 698 676 { 699 677 unsigned int i; 700 678 int ret; 701 679 702 - state->clks = devm_kcalloc(state->dev, state->info->num_clocks, 703 - sizeof(*state->clks), GFP_KERNEL); 680 + csis->clks = devm_kcalloc(csis->dev, csis->info->num_clocks, 681 + sizeof(*csis->clks), GFP_KERNEL); 704 682 705 - if (!state->clks) 683 + if (!csis->clks) 706 684 return -ENOMEM; 707 685 708 - for (i = 0; i < state->info->num_clocks; i++) 709 - state->clks[i].id = mipi_csis_clk_id[i]; 686 + for (i = 0; i < csis->info->num_clocks; i++) 687 + csis->clks[i].id = mipi_csis_clk_id[i]; 710 688 711 - ret = devm_clk_bulk_get(state->dev, state->info->num_clocks, 712 - state->clks); 689 + ret = devm_clk_bulk_get(csis->dev, csis->info->num_clocks, 690 + csis->clks); 713 691 if (ret < 0) 714 692 return ret; 715 693 716 694 /* Set clock rate */ 717 - ret = clk_set_rate(state->clks[MIPI_CSIS_CLK_WRAP].clk, 718 - state->clk_frequency); 695 + ret = clk_set_rate(csis->clks[MIPI_CSIS_CLK_WRAP].clk, 696 + csis->clk_frequency); 719 697 if (ret < 0) 720 - dev_err(state->dev, "set rate=%d failed: %d\n", 721 - state->clk_frequency, ret); 698 + dev_err(csis->dev, "set rate=%d failed: %d\n", 699 + csis->clk_frequency, ret); 722 700 723 701 return ret; 724 702 } 725 703 726 - static void mipi_csis_start_stream(struct csi_state *state) 704 + static void mipi_csis_start_stream(struct mipi_csis_device *csis) 727 705 { 728 - mipi_csis_sw_reset(state); 729 - mipi_csis_set_params(state); 730 - mipi_csis_system_enable(state, true); 731 - mipi_csis_enable_interrupts(state, true); 706 + mipi_csis_sw_reset(csis); 707 + mipi_csis_set_params(csis); 708 + mipi_csis_system_enable(csis, true); 709 + mipi_csis_enable_interrupts(csis, true); 732 710 } 733 711 734 - static void mipi_csis_stop_stream(struct csi_state *state) 712 + static void mipi_csis_stop_stream(struct mipi_csis_device *csis) 735 713 { 736 - mipi_csis_enable_interrupts(state, false); 737 - mipi_csis_system_enable(state, false); 714 + mipi_csis_enable_interrupts(csis, false); 715 + mipi_csis_system_enable(csis, false); 738 716 } 739 717 740 718 static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id) 741 719 { 742 - struct csi_state *state = dev_id; 720 + struct mipi_csis_device *csis = dev_id; 743 721 unsigned long flags; 744 722 unsigned int i; 745 723 u32 status; 746 724 u32 dbg_status; 747 725 748 - status = mipi_csis_read(state, MIPI_CSIS_INT_SRC); 749 - dbg_status = mipi_csis_read(state, MIPI_CSIS_DBG_INTR_SRC); 726 + status = mipi_csis_read(csis, MIPI_CSIS_INT_SRC); 727 + dbg_status = mipi_csis_read(csis, MIPI_CSIS_DBG_INTR_SRC); 750 728 751 - spin_lock_irqsave(&state->slock, flags); 729 + spin_lock_irqsave(&csis->slock, flags); 752 730 753 731 /* Update the event/error counters */ 754 - if ((status & MIPI_CSIS_INT_SRC_ERRORS) || state->debug.enable) { 732 + if ((status & MIPI_CSIS_INT_SRC_ERRORS) || csis->debug.enable) { 755 733 for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) { 756 - struct mipi_csis_event *event = &state->events[i]; 734 + struct mipi_csis_event *event = &csis->events[i]; 757 735 758 736 if ((!event->debug && (status & event->mask)) || 759 737 (event->debug && (dbg_status & event->mask))) 760 738 event->counter++; 761 739 } 762 740 } 763 - spin_unlock_irqrestore(&state->slock, flags); 741 + spin_unlock_irqrestore(&csis->slock, flags); 764 742 765 - mipi_csis_write(state, MIPI_CSIS_INT_SRC, status); 766 - mipi_csis_write(state, MIPI_CSIS_DBG_INTR_SRC, dbg_status); 743 + mipi_csis_write(csis, MIPI_CSIS_INT_SRC, status); 744 + mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_SRC, dbg_status); 767 745 768 746 return IRQ_HANDLED; 769 747 } ··· 772 750 * PHY regulator and reset 773 751 */ 774 752 775 - static int mipi_csis_phy_enable(struct csi_state *state) 753 + static int mipi_csis_phy_enable(struct mipi_csis_device *csis) 776 754 { 777 - if (state->info->version != MIPI_CSIS_V3_3) 755 + if (csis->info->version != MIPI_CSIS_V3_3) 778 756 return 0; 779 757 780 - return regulator_enable(state->mipi_phy_regulator); 758 + return regulator_enable(csis->mipi_phy_regulator); 781 759 } 782 760 783 - static int mipi_csis_phy_disable(struct csi_state *state) 761 + static int mipi_csis_phy_disable(struct mipi_csis_device *csis) 784 762 { 785 - if (state->info->version != MIPI_CSIS_V3_3) 763 + if (csis->info->version != MIPI_CSIS_V3_3) 786 764 return 0; 787 765 788 - return regulator_disable(state->mipi_phy_regulator); 766 + return regulator_disable(csis->mipi_phy_regulator); 789 767 } 790 768 791 - static void mipi_csis_phy_reset(struct csi_state *state) 769 + static void mipi_csis_phy_reset(struct mipi_csis_device *csis) 792 770 { 793 - if (state->info->version != MIPI_CSIS_V3_3) 771 + if (csis->info->version != MIPI_CSIS_V3_3) 794 772 return; 795 773 796 - reset_control_assert(state->mrst); 774 + reset_control_assert(csis->mrst); 797 775 msleep(20); 798 - reset_control_deassert(state->mrst); 776 + reset_control_deassert(csis->mrst); 799 777 } 800 778 801 - static int mipi_csis_phy_init(struct csi_state *state) 779 + static int mipi_csis_phy_init(struct mipi_csis_device *csis) 802 780 { 803 - if (state->info->version != MIPI_CSIS_V3_3) 781 + if (csis->info->version != MIPI_CSIS_V3_3) 804 782 return 0; 805 783 806 784 /* Get MIPI PHY reset and regulator. */ 807 - state->mrst = devm_reset_control_get_exclusive(state->dev, NULL); 808 - if (IS_ERR(state->mrst)) 809 - return PTR_ERR(state->mrst); 785 + csis->mrst = devm_reset_control_get_exclusive(csis->dev, NULL); 786 + if (IS_ERR(csis->mrst)) 787 + return PTR_ERR(csis->mrst); 810 788 811 - state->mipi_phy_regulator = devm_regulator_get(state->dev, "phy"); 812 - if (IS_ERR(state->mipi_phy_regulator)) 813 - return PTR_ERR(state->mipi_phy_regulator); 789 + csis->mipi_phy_regulator = devm_regulator_get(csis->dev, "phy"); 790 + if (IS_ERR(csis->mipi_phy_regulator)) 791 + return PTR_ERR(csis->mipi_phy_regulator); 814 792 815 - return regulator_set_voltage(state->mipi_phy_regulator, 1000000, 793 + return regulator_set_voltage(csis->mipi_phy_regulator, 1000000, 816 794 1000000); 817 795 } 818 796 ··· 820 798 * Debug 821 799 */ 822 800 823 - static void mipi_csis_clear_counters(struct csi_state *state) 801 + static void mipi_csis_clear_counters(struct mipi_csis_device *csis) 824 802 { 825 803 unsigned long flags; 826 804 unsigned int i; 827 805 828 - spin_lock_irqsave(&state->slock, flags); 806 + spin_lock_irqsave(&csis->slock, flags); 829 807 for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) 830 - state->events[i].counter = 0; 831 - spin_unlock_irqrestore(&state->slock, flags); 808 + csis->events[i].counter = 0; 809 + spin_unlock_irqrestore(&csis->slock, flags); 832 810 } 833 811 834 - static void mipi_csis_log_counters(struct csi_state *state, bool non_errors) 812 + static void mipi_csis_log_counters(struct mipi_csis_device *csis, bool non_errors) 835 813 { 836 814 unsigned int num_events = non_errors ? MIPI_CSIS_NUM_EVENTS 837 815 : MIPI_CSIS_NUM_EVENTS - 8; 838 816 unsigned long flags; 839 817 unsigned int i; 840 818 841 - spin_lock_irqsave(&state->slock, flags); 819 + spin_lock_irqsave(&csis->slock, flags); 842 820 843 821 for (i = 0; i < num_events; ++i) { 844 - if (state->events[i].counter > 0 || state->debug.enable) 845 - dev_info(state->dev, "%s events: %d\n", 846 - state->events[i].name, 847 - state->events[i].counter); 822 + if (csis->events[i].counter > 0 || csis->debug.enable) 823 + dev_info(csis->dev, "%s events: %d\n", 824 + csis->events[i].name, 825 + csis->events[i].counter); 848 826 } 849 - spin_unlock_irqrestore(&state->slock, flags); 827 + spin_unlock_irqrestore(&csis->slock, flags); 850 828 } 851 829 852 - static int mipi_csis_dump_regs(struct csi_state *state) 830 + static int mipi_csis_dump_regs(struct mipi_csis_device *csis) 853 831 { 854 832 static const struct { 855 833 u32 offset; ··· 873 851 unsigned int i; 874 852 u32 cfg; 875 853 876 - dev_info(state->dev, "--- REGISTERS ---\n"); 854 + if (!pm_runtime_get_if_in_use(csis->dev)) 855 + return 0; 856 + 857 + dev_info(csis->dev, "--- REGISTERS ---\n"); 877 858 878 859 for (i = 0; i < ARRAY_SIZE(registers); i++) { 879 - cfg = mipi_csis_read(state, registers[i].offset); 880 - dev_info(state->dev, "%14s: 0x%08x\n", registers[i].name, cfg); 860 + cfg = mipi_csis_read(csis, registers[i].offset); 861 + dev_info(csis->dev, "%14s: 0x%08x\n", registers[i].name, cfg); 881 862 } 863 + 864 + pm_runtime_put(csis->dev); 882 865 883 866 return 0; 884 867 } 885 868 886 869 static int mipi_csis_dump_regs_show(struct seq_file *m, void *private) 887 870 { 888 - struct csi_state *state = m->private; 871 + struct mipi_csis_device *csis = m->private; 889 872 890 - return mipi_csis_dump_regs(state); 873 + return mipi_csis_dump_regs(csis); 891 874 } 892 875 DEFINE_SHOW_ATTRIBUTE(mipi_csis_dump_regs); 893 876 894 - static void mipi_csis_debugfs_init(struct csi_state *state) 877 + static void mipi_csis_debugfs_init(struct mipi_csis_device *csis) 895 878 { 896 - state->debug.hs_settle = UINT_MAX; 897 - state->debug.clk_settle = UINT_MAX; 879 + csis->debug.hs_settle = UINT_MAX; 880 + csis->debug.clk_settle = UINT_MAX; 898 881 899 - state->debugfs_root = debugfs_create_dir(dev_name(state->dev), NULL); 882 + csis->debugfs_root = debugfs_create_dir(dev_name(csis->dev), NULL); 900 883 901 - debugfs_create_bool("debug_enable", 0600, state->debugfs_root, 902 - &state->debug.enable); 903 - debugfs_create_file("dump_regs", 0600, state->debugfs_root, state, 884 + debugfs_create_bool("debug_enable", 0600, csis->debugfs_root, 885 + &csis->debug.enable); 886 + debugfs_create_file("dump_regs", 0600, csis->debugfs_root, csis, 904 887 &mipi_csis_dump_regs_fops); 905 - debugfs_create_u32("tclk_settle", 0600, state->debugfs_root, 906 - &state->debug.clk_settle); 907 - debugfs_create_u32("ths_settle", 0600, state->debugfs_root, 908 - &state->debug.hs_settle); 888 + debugfs_create_u32("tclk_settle", 0600, csis->debugfs_root, 889 + &csis->debug.clk_settle); 890 + debugfs_create_u32("ths_settle", 0600, csis->debugfs_root, 891 + &csis->debug.hs_settle); 909 892 } 910 893 911 - static void mipi_csis_debugfs_exit(struct csi_state *state) 894 + static void mipi_csis_debugfs_exit(struct mipi_csis_device *csis) 912 895 { 913 - debugfs_remove_recursive(state->debugfs_root); 896 + debugfs_remove_recursive(csis->debugfs_root); 914 897 } 915 898 916 899 /* ----------------------------------------------------------------------------- 917 900 * V4L2 subdev operations 918 901 */ 919 902 920 - static struct csi_state *mipi_sd_to_csis_state(struct v4l2_subdev *sdev) 903 + static struct mipi_csis_device *sd_to_mipi_csis_device(struct v4l2_subdev *sdev) 921 904 { 922 - return container_of(sdev, struct csi_state, sd); 905 + return container_of(sdev, struct mipi_csis_device, sd); 923 906 } 924 907 925 908 static int mipi_csis_s_stream(struct v4l2_subdev *sd, int enable) 926 909 { 927 - struct csi_state *state = mipi_sd_to_csis_state(sd); 910 + struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 928 911 int ret; 929 912 930 - if (enable) { 931 - ret = mipi_csis_calculate_params(state); 932 - if (ret < 0) 933 - return ret; 913 + if (!enable) { 914 + mutex_lock(&csis->lock); 934 915 935 - mipi_csis_clear_counters(state); 916 + v4l2_subdev_call(csis->src_sd, video, s_stream, 0); 936 917 937 - ret = pm_runtime_resume_and_get(state->dev); 938 - if (ret < 0) 939 - return ret; 918 + mipi_csis_stop_stream(csis); 919 + if (csis->debug.enable) 920 + mipi_csis_log_counters(csis, true); 940 921 941 - ret = v4l2_subdev_call(state->src_sd, core, s_power, 1); 942 - if (ret < 0 && ret != -ENOIOCTLCMD) 943 - goto done; 922 + mutex_unlock(&csis->lock); 923 + 924 + pm_runtime_put(csis->dev); 925 + 926 + return 0; 944 927 } 945 928 946 - mutex_lock(&state->lock); 929 + ret = mipi_csis_calculate_params(csis); 930 + if (ret < 0) 931 + return ret; 947 932 948 - if (enable) { 949 - if (state->state & ST_SUSPENDED) { 950 - ret = -EBUSY; 951 - goto unlock; 952 - } 933 + mipi_csis_clear_counters(csis); 953 934 954 - mipi_csis_start_stream(state); 955 - ret = v4l2_subdev_call(state->src_sd, video, s_stream, 1); 956 - if (ret < 0) 957 - goto unlock; 935 + ret = pm_runtime_resume_and_get(csis->dev); 936 + if (ret < 0) 937 + return ret; 958 938 959 - mipi_csis_log_counters(state, true); 939 + mutex_lock(&csis->lock); 960 940 961 - state->state |= ST_STREAMING; 962 - } else { 963 - v4l2_subdev_call(state->src_sd, video, s_stream, 0); 964 - ret = v4l2_subdev_call(state->src_sd, core, s_power, 0); 965 - if (ret == -ENOIOCTLCMD) 966 - ret = 0; 967 - mipi_csis_stop_stream(state); 968 - state->state &= ~ST_STREAMING; 969 - if (state->debug.enable) 970 - mipi_csis_log_counters(state, true); 971 - } 941 + mipi_csis_start_stream(csis); 942 + ret = v4l2_subdev_call(csis->src_sd, video, s_stream, 1); 943 + if (ret < 0) 944 + goto error; 972 945 973 - unlock: 974 - mutex_unlock(&state->lock); 946 + mipi_csis_log_counters(csis, true); 975 947 976 - done: 977 - if (!enable || ret < 0) 978 - pm_runtime_put(state->dev); 948 + mutex_unlock(&csis->lock); 949 + 950 + return 0; 951 + 952 + error: 953 + mipi_csis_stop_stream(csis); 954 + mutex_unlock(&csis->lock); 955 + pm_runtime_put(csis->dev); 979 956 980 957 return ret; 981 958 } 982 959 983 960 static struct v4l2_mbus_framefmt * 984 - mipi_csis_get_format(struct csi_state *state, 961 + mipi_csis_get_format(struct mipi_csis_device *csis, 985 962 struct v4l2_subdev_state *sd_state, 986 963 enum v4l2_subdev_format_whence which, 987 964 unsigned int pad) 988 965 { 989 966 if (which == V4L2_SUBDEV_FORMAT_TRY) 990 - return v4l2_subdev_get_try_format(&state->sd, sd_state, pad); 967 + return v4l2_subdev_get_try_format(&csis->sd, sd_state, pad); 991 968 992 - return &state->format_mbus[pad]; 969 + return &csis->format_mbus[pad]; 993 970 } 994 971 995 972 static int mipi_csis_init_cfg(struct v4l2_subdev *sd, 996 973 struct v4l2_subdev_state *sd_state) 997 974 { 998 - struct csi_state *state = mipi_sd_to_csis_state(sd); 975 + struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 999 976 struct v4l2_mbus_framefmt *fmt_sink; 1000 977 struct v4l2_mbus_framefmt *fmt_source; 1001 978 enum v4l2_subdev_format_whence which; 1002 979 1003 980 which = sd_state ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE; 1004 - fmt_sink = mipi_csis_get_format(state, sd_state, which, CSIS_PAD_SINK); 981 + fmt_sink = mipi_csis_get_format(csis, sd_state, which, CSIS_PAD_SINK); 1005 982 1006 983 fmt_sink->code = MEDIA_BUS_FMT_UYVY8_1X16; 1007 984 fmt_sink->width = MIPI_CSIS_DEF_PIX_WIDTH; ··· 1014 993 V4L2_MAP_QUANTIZATION_DEFAULT(false, fmt_sink->colorspace, 1015 994 fmt_sink->ycbcr_enc); 1016 995 1017 - /* 1018 - * When called from mipi_csis_subdev_init() to initialize the active 1019 - * configuration, cfg is NULL, which indicates there's no source pad 1020 - * configuration to set. 1021 - */ 1022 - if (!sd_state) 1023 - return 0; 1024 - 1025 - fmt_source = mipi_csis_get_format(state, sd_state, which, 996 + fmt_source = mipi_csis_get_format(csis, sd_state, which, 1026 997 CSIS_PAD_SOURCE); 1027 998 *fmt_source = *fmt_sink; 1028 999 ··· 1025 1012 struct v4l2_subdev_state *sd_state, 1026 1013 struct v4l2_subdev_format *sdformat) 1027 1014 { 1028 - struct csi_state *state = mipi_sd_to_csis_state(sd); 1015 + struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1029 1016 struct v4l2_mbus_framefmt *fmt; 1030 1017 1031 - fmt = mipi_csis_get_format(state, sd_state, sdformat->which, 1018 + fmt = mipi_csis_get_format(csis, sd_state, sdformat->which, 1032 1019 sdformat->pad); 1033 1020 1034 - mutex_lock(&state->lock); 1021 + mutex_lock(&csis->lock); 1035 1022 sdformat->format = *fmt; 1036 - mutex_unlock(&state->lock); 1023 + mutex_unlock(&csis->lock); 1037 1024 1038 1025 return 0; 1039 1026 } ··· 1042 1029 struct v4l2_subdev_state *sd_state, 1043 1030 struct v4l2_subdev_mbus_code_enum *code) 1044 1031 { 1045 - struct csi_state *state = mipi_sd_to_csis_state(sd); 1032 + struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1046 1033 1047 1034 /* 1048 1035 * The CSIS can't transcode in any way, the source format is identical ··· 1054 1041 if (code->index > 0) 1055 1042 return -EINVAL; 1056 1043 1057 - fmt = mipi_csis_get_format(state, sd_state, code->which, 1044 + fmt = mipi_csis_get_format(csis, sd_state, code->which, 1058 1045 code->pad); 1059 1046 code->code = fmt->code; 1060 1047 return 0; ··· 1075 1062 struct v4l2_subdev_state *sd_state, 1076 1063 struct v4l2_subdev_format *sdformat) 1077 1064 { 1078 - struct csi_state *state = mipi_sd_to_csis_state(sd); 1065 + struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1079 1066 struct csis_pix_format const *csis_fmt; 1080 1067 struct v4l2_mbus_framefmt *fmt; 1081 1068 unsigned int align; ··· 1123 1110 &sdformat->format.height, 1, 1124 1111 CSIS_MAX_PIX_HEIGHT, 0, 0); 1125 1112 1126 - fmt = mipi_csis_get_format(state, sd_state, sdformat->which, 1113 + fmt = mipi_csis_get_format(csis, sd_state, sdformat->which, 1127 1114 sdformat->pad); 1128 1115 1129 - mutex_lock(&state->lock); 1116 + mutex_lock(&csis->lock); 1130 1117 1131 1118 fmt->code = csis_fmt->code; 1132 1119 fmt->width = sdformat->format.width; ··· 1139 1126 sdformat->format = *fmt; 1140 1127 1141 1128 /* Propagate the format from sink to source. */ 1142 - fmt = mipi_csis_get_format(state, sd_state, sdformat->which, 1129 + fmt = mipi_csis_get_format(csis, sd_state, sdformat->which, 1143 1130 CSIS_PAD_SOURCE); 1144 1131 *fmt = sdformat->format; 1145 1132 ··· 1148 1135 1149 1136 /* Store the CSIS format descriptor for active formats. */ 1150 1137 if (sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE) 1151 - state->csis_fmt = csis_fmt; 1138 + csis->csis_fmt = csis_fmt; 1152 1139 1153 - mutex_unlock(&state->lock); 1140 + mutex_unlock(&csis->lock); 1154 1141 1155 1142 return 0; 1156 1143 } 1157 1144 1158 1145 static int mipi_csis_log_status(struct v4l2_subdev *sd) 1159 1146 { 1160 - struct csi_state *state = mipi_sd_to_csis_state(sd); 1147 + struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1161 1148 1162 - mutex_lock(&state->lock); 1163 - mipi_csis_log_counters(state, true); 1164 - if (state->debug.enable && (state->state & ST_POWERED)) 1165 - mipi_csis_dump_regs(state); 1166 - mutex_unlock(&state->lock); 1149 + mipi_csis_log_counters(csis, true); 1150 + if (csis->debug.enable) 1151 + mipi_csis_dump_regs(csis); 1167 1152 1168 1153 return 0; 1169 1154 } ··· 1196 1185 const struct media_pad *remote_pad, u32 flags) 1197 1186 { 1198 1187 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity); 1199 - struct csi_state *state = mipi_sd_to_csis_state(sd); 1188 + struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1200 1189 struct v4l2_subdev *remote_sd; 1201 1190 1202 - dev_dbg(state->dev, "link setup %s -> %s", remote_pad->entity->name, 1191 + dev_dbg(csis->dev, "link setup %s -> %s", remote_pad->entity->name, 1203 1192 local_pad->entity->name); 1204 1193 1205 1194 /* We only care about the link to the source. */ ··· 1209 1198 remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity); 1210 1199 1211 1200 if (flags & MEDIA_LNK_FL_ENABLED) { 1212 - if (state->src_sd) 1201 + if (csis->src_sd) 1213 1202 return -EBUSY; 1214 1203 1215 - state->src_sd = remote_sd; 1204 + csis->src_sd = remote_sd; 1216 1205 } else { 1217 - state->src_sd = NULL; 1206 + csis->src_sd = NULL; 1218 1207 } 1219 1208 1220 1209 return 0; ··· 1230 1219 * Async subdev notifier 1231 1220 */ 1232 1221 1233 - static struct csi_state * 1222 + static struct mipi_csis_device * 1234 1223 mipi_notifier_to_csis_state(struct v4l2_async_notifier *n) 1235 1224 { 1236 - return container_of(n, struct csi_state, notifier); 1225 + return container_of(n, struct mipi_csis_device, notifier); 1237 1226 } 1238 1227 1239 1228 static int mipi_csis_notify_bound(struct v4l2_async_notifier *notifier, 1240 1229 struct v4l2_subdev *sd, 1241 1230 struct v4l2_async_subdev *asd) 1242 1231 { 1243 - struct csi_state *state = mipi_notifier_to_csis_state(notifier); 1244 - struct media_pad *sink = &state->sd.entity.pads[CSIS_PAD_SINK]; 1232 + struct mipi_csis_device *csis = mipi_notifier_to_csis_state(notifier); 1233 + struct media_pad *sink = &csis->sd.entity.pads[CSIS_PAD_SINK]; 1245 1234 1246 1235 return v4l2_create_fwnode_links_to_pad(sd, sink, 0); 1247 1236 } ··· 1250 1239 .bound = mipi_csis_notify_bound, 1251 1240 }; 1252 1241 1253 - static int mipi_csis_async_register(struct csi_state *state) 1242 + static int mipi_csis_async_register(struct mipi_csis_device *csis) 1254 1243 { 1255 1244 struct v4l2_fwnode_endpoint vep = { 1256 1245 .bus_type = V4L2_MBUS_CSI2_DPHY, ··· 1260 1249 unsigned int i; 1261 1250 int ret; 1262 1251 1263 - v4l2_async_nf_init(&state->notifier); 1252 + v4l2_async_nf_init(&csis->notifier); 1264 1253 1265 - ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(state->dev), 0, 0, 1254 + ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csis->dev), 0, 0, 1266 1255 FWNODE_GRAPH_ENDPOINT_NEXT); 1267 1256 if (!ep) 1268 1257 return -ENOTCONN; ··· 1273 1262 1274 1263 for (i = 0; i < vep.bus.mipi_csi2.num_data_lanes; ++i) { 1275 1264 if (vep.bus.mipi_csi2.data_lanes[i] != i + 1) { 1276 - dev_err(state->dev, 1265 + dev_err(csis->dev, 1277 1266 "data lanes reordering is not supported"); 1278 1267 ret = -EINVAL; 1279 1268 goto err_parse; 1280 1269 } 1281 1270 } 1282 1271 1283 - state->bus = vep.bus.mipi_csi2; 1272 + csis->bus = vep.bus.mipi_csi2; 1284 1273 1285 - dev_dbg(state->dev, "data lanes: %d\n", state->bus.num_data_lanes); 1286 - dev_dbg(state->dev, "flags: 0x%08x\n", state->bus.flags); 1274 + dev_dbg(csis->dev, "data lanes: %d\n", csis->bus.num_data_lanes); 1275 + dev_dbg(csis->dev, "flags: 0x%08x\n", csis->bus.flags); 1287 1276 1288 - asd = v4l2_async_nf_add_fwnode_remote(&state->notifier, ep, 1277 + asd = v4l2_async_nf_add_fwnode_remote(&csis->notifier, ep, 1289 1278 struct v4l2_async_subdev); 1290 1279 if (IS_ERR(asd)) { 1291 1280 ret = PTR_ERR(asd); ··· 1294 1283 1295 1284 fwnode_handle_put(ep); 1296 1285 1297 - state->notifier.ops = &mipi_csis_notify_ops; 1286 + csis->notifier.ops = &mipi_csis_notify_ops; 1298 1287 1299 - ret = v4l2_async_subdev_nf_register(&state->sd, &state->notifier); 1288 + ret = v4l2_async_subdev_nf_register(&csis->sd, &csis->notifier); 1300 1289 if (ret) 1301 1290 return ret; 1302 1291 1303 - return v4l2_async_register_subdev(&state->sd); 1292 + return v4l2_async_register_subdev(&csis->sd); 1304 1293 1305 1294 err_parse: 1306 1295 fwnode_handle_put(ep); ··· 1312 1301 * Suspend/resume 1313 1302 */ 1314 1303 1315 - static int mipi_csis_pm_suspend(struct device *dev, bool runtime) 1316 - { 1317 - struct v4l2_subdev *sd = dev_get_drvdata(dev); 1318 - struct csi_state *state = mipi_sd_to_csis_state(sd); 1319 - int ret = 0; 1320 - 1321 - mutex_lock(&state->lock); 1322 - if (state->state & ST_POWERED) { 1323 - mipi_csis_stop_stream(state); 1324 - ret = mipi_csis_phy_disable(state); 1325 - if (ret) 1326 - goto unlock; 1327 - mipi_csis_clk_disable(state); 1328 - state->state &= ~ST_POWERED; 1329 - if (!runtime) 1330 - state->state |= ST_SUSPENDED; 1331 - } 1332 - 1333 - unlock: 1334 - mutex_unlock(&state->lock); 1335 - 1336 - return ret ? -EAGAIN : 0; 1337 - } 1338 - 1339 - static int mipi_csis_pm_resume(struct device *dev, bool runtime) 1340 - { 1341 - struct v4l2_subdev *sd = dev_get_drvdata(dev); 1342 - struct csi_state *state = mipi_sd_to_csis_state(sd); 1343 - int ret = 0; 1344 - 1345 - mutex_lock(&state->lock); 1346 - if (!runtime && !(state->state & ST_SUSPENDED)) 1347 - goto unlock; 1348 - 1349 - if (!(state->state & ST_POWERED)) { 1350 - ret = mipi_csis_phy_enable(state); 1351 - if (ret) 1352 - goto unlock; 1353 - 1354 - state->state |= ST_POWERED; 1355 - mipi_csis_clk_enable(state); 1356 - } 1357 - if (state->state & ST_STREAMING) 1358 - mipi_csis_start_stream(state); 1359 - 1360 - state->state &= ~ST_SUSPENDED; 1361 - 1362 - unlock: 1363 - mutex_unlock(&state->lock); 1364 - 1365 - return ret ? -EAGAIN : 0; 1366 - } 1367 - 1368 - static int __maybe_unused mipi_csis_suspend(struct device *dev) 1369 - { 1370 - return mipi_csis_pm_suspend(dev, false); 1371 - } 1372 - 1373 - static int __maybe_unused mipi_csis_resume(struct device *dev) 1374 - { 1375 - return mipi_csis_pm_resume(dev, false); 1376 - } 1377 - 1378 1304 static int __maybe_unused mipi_csis_runtime_suspend(struct device *dev) 1379 1305 { 1380 - return mipi_csis_pm_suspend(dev, true); 1306 + struct v4l2_subdev *sd = dev_get_drvdata(dev); 1307 + struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1308 + int ret = 0; 1309 + 1310 + mutex_lock(&csis->lock); 1311 + 1312 + ret = mipi_csis_phy_disable(csis); 1313 + if (ret) 1314 + goto unlock; 1315 + 1316 + mipi_csis_clk_disable(csis); 1317 + 1318 + unlock: 1319 + mutex_unlock(&csis->lock); 1320 + 1321 + return ret ? -EAGAIN : 0; 1381 1322 } 1382 1323 1383 1324 static int __maybe_unused mipi_csis_runtime_resume(struct device *dev) 1384 1325 { 1385 - return mipi_csis_pm_resume(dev, true); 1326 + struct v4l2_subdev *sd = dev_get_drvdata(dev); 1327 + struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1328 + int ret = 0; 1329 + 1330 + mutex_lock(&csis->lock); 1331 + 1332 + ret = mipi_csis_phy_enable(csis); 1333 + if (ret) 1334 + goto unlock; 1335 + 1336 + mipi_csis_clk_enable(csis); 1337 + 1338 + unlock: 1339 + mutex_unlock(&csis->lock); 1340 + 1341 + return ret ? -EAGAIN : 0; 1386 1342 } 1387 1343 1388 1344 static const struct dev_pm_ops mipi_csis_pm_ops = { 1389 1345 SET_RUNTIME_PM_OPS(mipi_csis_runtime_suspend, mipi_csis_runtime_resume, 1390 1346 NULL) 1391 - SET_SYSTEM_SLEEP_PM_OPS(mipi_csis_suspend, mipi_csis_resume) 1392 1347 }; 1393 1348 1394 1349 /* ----------------------------------------------------------------------------- 1395 1350 * Probe/remove & platform driver 1396 1351 */ 1397 1352 1398 - static int mipi_csis_subdev_init(struct csi_state *state) 1353 + static int mipi_csis_subdev_init(struct mipi_csis_device *csis) 1399 1354 { 1400 - struct v4l2_subdev *sd = &state->sd; 1355 + struct v4l2_subdev *sd = &csis->sd; 1401 1356 1402 1357 v4l2_subdev_init(sd, &mipi_csis_subdev_ops); 1403 1358 sd->owner = THIS_MODULE; 1404 1359 snprintf(sd->name, sizeof(sd->name), "csis-%s", 1405 - dev_name(state->dev)); 1360 + dev_name(csis->dev)); 1406 1361 1407 1362 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1408 1363 sd->ctrl_handler = NULL; ··· 1376 1399 sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 1377 1400 sd->entity.ops = &mipi_csis_entity_ops; 1378 1401 1379 - sd->dev = state->dev; 1402 + sd->dev = csis->dev; 1380 1403 1381 - state->csis_fmt = &mipi_csis_formats[0]; 1404 + csis->csis_fmt = &mipi_csis_formats[0]; 1382 1405 mipi_csis_init_cfg(sd, NULL); 1383 1406 1384 - state->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK 1407 + csis->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK 1385 1408 | MEDIA_PAD_FL_MUST_CONNECT; 1386 - state->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE 1409 + csis->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE 1387 1410 | MEDIA_PAD_FL_MUST_CONNECT; 1388 1411 return media_entity_pads_init(&sd->entity, CSIS_PADS_NUM, 1389 - state->pads); 1412 + csis->pads); 1390 1413 } 1391 1414 1392 - static int mipi_csis_parse_dt(struct csi_state *state) 1415 + static int mipi_csis_parse_dt(struct mipi_csis_device *csis) 1393 1416 { 1394 - struct device_node *node = state->dev->of_node; 1417 + struct device_node *node = csis->dev->of_node; 1395 1418 1396 1419 if (of_property_read_u32(node, "clock-frequency", 1397 - &state->clk_frequency)) 1398 - state->clk_frequency = DEFAULT_SCLK_CSIS_FREQ; 1420 + &csis->clk_frequency)) 1421 + csis->clk_frequency = DEFAULT_SCLK_CSIS_FREQ; 1399 1422 1400 1423 return 0; 1401 1424 } ··· 1403 1426 static int mipi_csis_probe(struct platform_device *pdev) 1404 1427 { 1405 1428 struct device *dev = &pdev->dev; 1406 - struct csi_state *state; 1429 + struct mipi_csis_device *csis; 1407 1430 int irq; 1408 1431 int ret; 1409 1432 1410 - state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); 1411 - if (!state) 1433 + csis = devm_kzalloc(dev, sizeof(*csis), GFP_KERNEL); 1434 + if (!csis) 1412 1435 return -ENOMEM; 1413 1436 1414 - mutex_init(&state->lock); 1415 - spin_lock_init(&state->slock); 1437 + mutex_init(&csis->lock); 1438 + spin_lock_init(&csis->slock); 1416 1439 1417 - state->dev = dev; 1418 - state->info = of_device_get_match_data(dev); 1440 + csis->dev = dev; 1441 + csis->info = of_device_get_match_data(dev); 1419 1442 1420 - memcpy(state->events, mipi_csis_events, sizeof(state->events)); 1443 + memcpy(csis->events, mipi_csis_events, sizeof(csis->events)); 1421 1444 1422 1445 /* Parse DT properties. */ 1423 - ret = mipi_csis_parse_dt(state); 1446 + ret = mipi_csis_parse_dt(csis); 1424 1447 if (ret < 0) { 1425 1448 dev_err(dev, "Failed to parse device tree: %d\n", ret); 1426 1449 return ret; 1427 1450 } 1428 1451 1429 1452 /* Acquire resources. */ 1430 - state->regs = devm_platform_ioremap_resource(pdev, 0); 1431 - if (IS_ERR(state->regs)) 1432 - return PTR_ERR(state->regs); 1453 + csis->regs = devm_platform_ioremap_resource(pdev, 0); 1454 + if (IS_ERR(csis->regs)) 1455 + return PTR_ERR(csis->regs); 1433 1456 1434 1457 irq = platform_get_irq(pdev, 0); 1435 1458 if (irq < 0) 1436 1459 return irq; 1437 1460 1438 - ret = mipi_csis_phy_init(state); 1461 + ret = mipi_csis_phy_init(csis); 1439 1462 if (ret < 0) 1440 1463 return ret; 1441 1464 1442 - ret = mipi_csis_clk_get(state); 1465 + ret = mipi_csis_clk_get(csis); 1443 1466 if (ret < 0) 1444 1467 return ret; 1445 1468 1446 1469 /* Reset PHY and enable the clocks. */ 1447 - mipi_csis_phy_reset(state); 1470 + mipi_csis_phy_reset(csis); 1448 1471 1449 - ret = mipi_csis_clk_enable(state); 1472 + ret = mipi_csis_clk_enable(csis); 1450 1473 if (ret < 0) { 1451 - dev_err(state->dev, "failed to enable clocks: %d\n", ret); 1474 + dev_err(csis->dev, "failed to enable clocks: %d\n", ret); 1452 1475 return ret; 1453 1476 } 1454 1477 1455 1478 /* Now that the hardware is initialized, request the interrupt. */ 1456 1479 ret = devm_request_irq(dev, irq, mipi_csis_irq_handler, 0, 1457 - dev_name(dev), state); 1480 + dev_name(dev), csis); 1458 1481 if (ret) { 1459 1482 dev_err(dev, "Interrupt request failed\n"); 1460 1483 goto disable_clock; 1461 1484 } 1462 1485 1463 1486 /* Initialize and register the subdev. */ 1464 - ret = mipi_csis_subdev_init(state); 1487 + ret = mipi_csis_subdev_init(csis); 1465 1488 if (ret < 0) 1466 1489 goto disable_clock; 1467 1490 1468 - platform_set_drvdata(pdev, &state->sd); 1491 + platform_set_drvdata(pdev, &csis->sd); 1469 1492 1470 - ret = mipi_csis_async_register(state); 1493 + ret = mipi_csis_async_register(csis); 1471 1494 if (ret < 0) { 1472 1495 dev_err(dev, "async register failed: %d\n", ret); 1473 1496 goto cleanup; 1474 1497 } 1475 1498 1476 1499 /* Initialize debugfs. */ 1477 - mipi_csis_debugfs_init(state); 1500 + mipi_csis_debugfs_init(csis); 1478 1501 1479 1502 /* Enable runtime PM. */ 1480 1503 pm_runtime_enable(dev); 1481 1504 if (!pm_runtime_enabled(dev)) { 1482 - ret = mipi_csis_pm_resume(dev, true); 1505 + ret = mipi_csis_runtime_resume(dev); 1483 1506 if (ret < 0) 1484 1507 goto unregister_all; 1485 1508 } 1486 1509 1487 1510 dev_info(dev, "lanes: %d, freq: %u\n", 1488 - state->bus.num_data_lanes, state->clk_frequency); 1511 + csis->bus.num_data_lanes, csis->clk_frequency); 1489 1512 1490 1513 return 0; 1491 1514 1492 1515 unregister_all: 1493 - mipi_csis_debugfs_exit(state); 1516 + mipi_csis_debugfs_exit(csis); 1494 1517 cleanup: 1495 - media_entity_cleanup(&state->sd.entity); 1496 - v4l2_async_nf_unregister(&state->notifier); 1497 - v4l2_async_nf_cleanup(&state->notifier); 1498 - v4l2_async_unregister_subdev(&state->sd); 1518 + media_entity_cleanup(&csis->sd.entity); 1519 + v4l2_async_nf_unregister(&csis->notifier); 1520 + v4l2_async_nf_cleanup(&csis->notifier); 1521 + v4l2_async_unregister_subdev(&csis->sd); 1499 1522 disable_clock: 1500 - mipi_csis_clk_disable(state); 1501 - mutex_destroy(&state->lock); 1523 + mipi_csis_clk_disable(csis); 1524 + mutex_destroy(&csis->lock); 1502 1525 1503 1526 return ret; 1504 1527 } ··· 1506 1529 static int mipi_csis_remove(struct platform_device *pdev) 1507 1530 { 1508 1531 struct v4l2_subdev *sd = platform_get_drvdata(pdev); 1509 - struct csi_state *state = mipi_sd_to_csis_state(sd); 1532 + struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1510 1533 1511 - mipi_csis_debugfs_exit(state); 1512 - v4l2_async_nf_unregister(&state->notifier); 1513 - v4l2_async_nf_cleanup(&state->notifier); 1514 - v4l2_async_unregister_subdev(&state->sd); 1534 + mipi_csis_debugfs_exit(csis); 1535 + v4l2_async_nf_unregister(&csis->notifier); 1536 + v4l2_async_nf_cleanup(&csis->notifier); 1537 + v4l2_async_unregister_subdev(&csis->sd); 1515 1538 1516 1539 pm_runtime_disable(&pdev->dev); 1517 - mipi_csis_pm_suspend(&pdev->dev, true); 1518 - mipi_csis_clk_disable(state); 1519 - media_entity_cleanup(&state->sd.entity); 1520 - mutex_destroy(&state->lock); 1540 + mipi_csis_runtime_suspend(&pdev->dev); 1541 + mipi_csis_clk_disable(csis); 1542 + media_entity_cleanup(&csis->sd.entity); 1543 + mutex_destroy(&csis->lock); 1521 1544 pm_runtime_set_suspended(&pdev->dev); 1522 1545 1523 1546 return 0;

-4

drivers/media/platform/qcom/camss/camss-video.c

··· 576 576 static int video_querycap(struct file *file, void *fh, 577 577 struct v4l2_capability *cap) 578 578 { 579 - struct camss_video *video = video_drvdata(file); 580 - 581 579 strscpy(cap->driver, "qcom-camss", sizeof(cap->driver)); 582 580 strscpy(cap->card, "Qualcomm Camera Subsystem", sizeof(cap->card)); 583 - snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", 584 - dev_name(video->camss->dev)); 585 581 586 582 return 0; 587 583 }

+1

drivers/media/platform/qcom/venus/core.h

··· 261 261 262 262 u32 header_mode; 263 263 bool aud_enable; 264 + u32 intra_refresh_type; 264 265 u32 intra_refresh_period; 265 266 266 267 struct {

+54 -31

drivers/media/platform/qcom/venus/helpers.c

··· 90 90 } 91 91 EXPORT_SYMBOL_GPL(venus_helper_check_codec); 92 92 93 + static void free_dpb_buf(struct venus_inst *inst, struct intbuf *buf) 94 + { 95 + ida_free(&inst->dpb_ids, buf->dpb_out_tag); 96 + 97 + list_del_init(&buf->list); 98 + dma_free_attrs(inst->core->dev, buf->size, buf->va, buf->da, 99 + buf->attrs); 100 + kfree(buf); 101 + } 102 + 93 103 int venus_helper_queue_dpb_bufs(struct venus_inst *inst) 94 104 { 95 - struct intbuf *buf; 105 + struct intbuf *buf, *next; 106 + unsigned int dpb_size = 0; 96 107 int ret = 0; 97 108 98 - list_for_each_entry(buf, &inst->dpbbufs, list) { 109 + if (inst->dpb_buftype == HFI_BUFFER_OUTPUT) 110 + dpb_size = inst->output_buf_size; 111 + else if (inst->dpb_buftype == HFI_BUFFER_OUTPUT2) 112 + dpb_size = inst->output2_buf_size; 113 + 114 + list_for_each_entry_safe(buf, next, &inst->dpbbufs, list) { 99 115 struct hfi_frame_data fdata; 100 116 101 117 memset(&fdata, 0, sizeof(fdata)); ··· 121 105 122 106 if (buf->owned_by == FIRMWARE) 123 107 continue; 108 + 109 + /* free buffer from previous sequence which was released later */ 110 + if (dpb_size > buf->size) { 111 + free_dpb_buf(inst, buf); 112 + continue; 113 + } 124 114 125 115 fdata.clnt_data = buf->dpb_out_tag; 126 116 ··· 149 127 list_for_each_entry_safe(buf, n, &inst->dpbbufs, list) { 150 128 if (buf->owned_by == FIRMWARE) 151 129 continue; 152 - 153 - ida_free(&inst->dpb_ids, buf->dpb_out_tag); 154 - 155 - list_del_init(&buf->list); 156 - dma_free_attrs(inst->core->dev, buf->size, buf->va, buf->da, 157 - buf->attrs); 158 - kfree(buf); 130 + free_dpb_buf(inst, buf); 159 131 } 160 132 161 133 if (list_empty(&inst->dpbbufs)) ··· 608 592 return HFI_COLOR_FORMAT_NV12; 609 593 case V4L2_PIX_FMT_NV21: 610 594 return HFI_COLOR_FORMAT_NV21; 595 + case V4L2_PIX_FMT_QC08C: 596 + return HFI_COLOR_FORMAT_NV12_UBWC; 597 + case V4L2_PIX_FMT_QC10C: 598 + return HFI_COLOR_FORMAT_YUV420_TP10_UBWC; 611 599 default: 612 600 break; 613 601 } ··· 1194 1174 if (!IS_V6(inst->core)) 1195 1175 return 0; 1196 1176 1197 - if (inst->opb_fmt == HFI_COLOR_FORMAT_NV12_UBWC) 1177 + if (inst->opb_fmt == HFI_COLOR_FORMAT_NV12_UBWC || 1178 + inst->opb_fmt == HFI_COLOR_FORMAT_YUV420_TP10_UBWC) 1198 1179 return 0; 1199 1180 1200 1181 pconstraint.buffer_type = HFI_BUFFER_OUTPUT2; ··· 1766 1745 if (!caps) 1767 1746 return -EINVAL; 1768 1747 1769 - if (inst->bit_depth == VIDC_BITDEPTH_10 && 1770 - inst->session_type == VIDC_SESSION_TYPE_DEC) { 1771 - found_ubwc = 1772 - find_fmt_from_caps(caps, HFI_BUFFER_OUTPUT, 1773 - HFI_COLOR_FORMAT_YUV420_TP10_UBWC); 1774 - found = find_fmt_from_caps(caps, HFI_BUFFER_OUTPUT2, 1775 - HFI_COLOR_FORMAT_NV12); 1776 - if (found_ubwc && found) { 1777 - /* 1778 - * Hard-code DPB buffers to be 10bit UBWC and decoder 1779 - * output buffers in 8bit NV12 until V4L2 is able to 1780 - * expose compressed/tiled formats to applications. 1781 - */ 1782 - *out_fmt = HFI_COLOR_FORMAT_YUV420_TP10_UBWC; 1783 - *out2_fmt = HFI_COLOR_FORMAT_NV12; 1784 - return 0; 1785 - } 1786 - 1787 - return -EINVAL; 1788 - } 1789 - 1790 1748 if (ubwc) { 1791 1749 ubwc_fmt = fmt | HFI_COLOR_FORMAT_UBWC_BASE; 1792 1750 found_ubwc = find_fmt_from_caps(caps, HFI_BUFFER_OUTPUT, ··· 1796 1796 return -EINVAL; 1797 1797 } 1798 1798 EXPORT_SYMBOL_GPL(venus_helper_get_out_fmts); 1799 + 1800 + bool venus_helper_check_format(struct venus_inst *inst, u32 v4l2_pixfmt) 1801 + { 1802 + struct venus_core *core = inst->core; 1803 + u32 fmt = to_hfi_raw_fmt(v4l2_pixfmt); 1804 + struct hfi_plat_caps *caps; 1805 + u32 buftype; 1806 + 1807 + if (!fmt) 1808 + return false; 1809 + 1810 + caps = venus_caps_by_codec(core, inst->hfi_codec, inst->session_type); 1811 + if (!caps) 1812 + return false; 1813 + 1814 + if (inst->session_type == VIDC_SESSION_TYPE_DEC) 1815 + buftype = HFI_BUFFER_OUTPUT2; 1816 + else 1817 + buftype = HFI_BUFFER_OUTPUT; 1818 + 1819 + return find_fmt_from_caps(caps, buftype, fmt); 1820 + } 1821 + EXPORT_SYMBOL_GPL(venus_helper_check_format); 1799 1822 1800 1823 int venus_helper_set_stride(struct venus_inst *inst, 1801 1824 unsigned int width, unsigned int height)

+1

drivers/media/platform/qcom/venus/helpers.h

··· 55 55 int venus_helper_session_init(struct venus_inst *inst); 56 56 int venus_helper_get_out_fmts(struct venus_inst *inst, u32 fmt, u32 *out_fmt, 57 57 u32 *out2_fmt, bool ubwc); 58 + bool venus_helper_check_format(struct venus_inst *inst, u32 v4l2_pixfmt); 58 59 int venus_helper_alloc_dpb_bufs(struct venus_inst *inst); 59 60 int venus_helper_free_dpb_bufs(struct venus_inst *inst); 60 61 int venus_helper_intbufs_alloc(struct venus_inst *inst);

+3

drivers/media/platform/qcom/venus/hfi.c

··· 104 104 mutex_lock(&core->lock); 105 105 } 106 106 107 + if (!core->ops) 108 + goto unlock; 109 + 107 110 ret = core->ops->core_deinit(core); 108 111 109 112 if (!ret)

+2 -2

drivers/media/platform/qcom/venus/hfi_platform_v4.c

··· 55 55 .fmts[3] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV12}, 56 56 .fmts[4] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV21}, 57 57 .fmts[5] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_P010}, 58 - .fmts[6] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_YUV420_TP10}, 58 + .fmts[6] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_YUV420_TP10_UBWC}, 59 59 .num_fmts = 7, 60 60 }, { 61 61 .codec = HFI_VIDEO_CODEC_VP8, ··· 106 106 .fmts[3] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV12}, 107 107 .fmts[4] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV21}, 108 108 .fmts[5] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_P010}, 109 - .fmts[6] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_YUV420_TP10}, 109 + .fmts[6] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_YUV420_TP10_UBWC}, 110 110 .num_fmts = 7, 111 111 }, { 112 112 .codec = HFI_VIDEO_CODEC_MPEG2,

+2 -2

drivers/media/platform/qcom/venus/hfi_platform_v6.c

··· 55 55 .fmts[3] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV12}, 56 56 .fmts[4] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV21}, 57 57 .fmts[5] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_P010}, 58 - .fmts[6] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_YUV420_TP10}, 58 + .fmts[6] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_YUV420_TP10_UBWC}, 59 59 .num_fmts = 7, 60 60 }, { 61 61 .codec = HFI_VIDEO_CODEC_VP8, ··· 106 106 .fmts[3] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV12}, 107 107 .fmts[4] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV21}, 108 108 .fmts[5] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_P010}, 109 - .fmts[6] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_YUV420_TP10}, 109 + .fmts[6] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_YUV420_TP10_UBWC}, 110 110 .num_fmts = 7, 111 111 }, { 112 112 .codec = HFI_VIDEO_CODEC_MPEG2,

+3 -1

drivers/media/platform/qcom/venus/hfi_venus.c

··· 1583 1583 */ 1584 1584 ret = readx_poll_timeout(venus_cpu_and_video_core_idle, hdev, val, val, 1585 1585 1500, 100 * 1500); 1586 - if (ret) 1586 + if (ret) { 1587 + dev_err(dev, "wait for cpu and video core idle fail (%d)\n", ret); 1587 1588 return ret; 1589 + } 1588 1590 1589 1591 ret = venus_prepare_power_collapse(hdev, false); 1590 1592 if (ret) {

+32 -5

drivers/media/platform/qcom/venus/vdec.c

··· 31 31 */ 32 32 static const struct venus_format vdec_formats[] = { 33 33 { 34 + .pixfmt = V4L2_PIX_FMT_QC08C, 35 + .num_planes = 1, 36 + .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, 37 + }, { 38 + .pixfmt = V4L2_PIX_FMT_QC10C, 39 + .num_planes = 1, 40 + .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, 41 + },{ 34 42 .pixfmt = V4L2_PIX_FMT_NV12, 35 43 .num_planes = 1, 36 44 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, ··· 114 106 !venus_helper_check_codec(inst, fmt[i].pixfmt)) 115 107 return NULL; 116 108 109 + if (V4L2_TYPE_IS_CAPTURE(type) && 110 + !venus_helper_check_format(inst, fmt[i].pixfmt)) 111 + return NULL; 112 + 113 + if (V4L2_TYPE_IS_CAPTURE(type) && fmt[i].pixfmt == V4L2_PIX_FMT_QC10C && 114 + !(inst->bit_depth == VIDC_BITDEPTH_10)) 115 + return NULL; 116 + 117 117 return &fmt[i]; 118 118 } 119 119 ··· 140 124 141 125 if (fmt[i].type != type) 142 126 continue; 143 - valid = type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE || 144 - venus_helper_check_codec(inst, fmt[i].pixfmt); 127 + 128 + if (V4L2_TYPE_IS_OUTPUT(type)) { 129 + valid = venus_helper_check_codec(inst, fmt[i].pixfmt); 130 + } else if (V4L2_TYPE_IS_CAPTURE(type)) { 131 + valid = venus_helper_check_format(inst, fmt[i].pixfmt); 132 + 133 + if (fmt[i].pixfmt == V4L2_PIX_FMT_QC10C && 134 + !(inst->bit_depth == VIDC_BITDEPTH_10)) 135 + valid = false; 136 + } 137 + 145 138 if (k == index && valid) 146 139 break; 147 140 if (valid) ··· 701 676 struct venus_core *core = inst->core; 702 677 struct hfi_enable en = { .enable = 1 }; 703 678 struct hfi_buffer_requirements bufreq; 704 - u32 width = inst->out_width; 705 - u32 height = inst->out_height; 679 + u32 width = inst->width; 680 + u32 height = inst->height; 706 681 u32 out_fmt, out2_fmt; 707 682 bool ubwc = false; 708 683 u32 ptype; ··· 1225 1200 struct venus_inst *inst = vb2_get_drv_priv(q); 1226 1201 int ret = -EINVAL; 1227 1202 1203 + vdec_pm_get_put(inst); 1204 + 1228 1205 mutex_lock(&inst->lock); 1229 1206 1230 1207 if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) ··· 1552 1525 static void vdec_inst_init(struct venus_inst *inst) 1553 1526 { 1554 1527 inst->hfi_codec = HFI_VIDEO_CODEC_H264; 1555 - inst->fmt_out = &vdec_formats[6]; 1528 + inst->fmt_out = &vdec_formats[8]; 1556 1529 inst->fmt_cap = &vdec_formats[0]; 1557 1530 inst->width = frame_width_min(inst); 1558 1531 inst->height = ALIGN(frame_height_min(inst), 32);

+5 -1

drivers/media/platform/qcom/venus/venc.c

··· 893 893 mbs++; 894 894 mbs /= ctr->intra_refresh_period; 895 895 896 - intra_refresh.mode = HFI_INTRA_REFRESH_RANDOM; 897 896 intra_refresh.cir_mbs = mbs; 897 + if (ctr->intra_refresh_type == 898 + V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC) 899 + intra_refresh.mode = HFI_INTRA_REFRESH_CYCLIC; 900 + else 901 + intra_refresh.mode = HFI_INTRA_REFRESH_RANDOM; 898 902 } 899 903 900 904 ptype = HFI_PROPERTY_PARAM_VENC_INTRA_REFRESH;

+8

drivers/media/platform/qcom/venus/venc_ctrls.c

··· 316 316 case V4L2_CID_COLORIMETRY_HDR10_MASTERING_DISPLAY: 317 317 ctr->mastering = *ctrl->p_new.p_hdr10_mastering; 318 318 break; 319 + case V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE: 320 + ctr->intra_refresh_type = ctrl->val; 321 + break; 319 322 case V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD: 320 323 ctr->intra_refresh_period = ctrl->val; 321 324 break; ··· 584 581 v4l2_ctrl_new_std_compound(&inst->ctrl_handler, &venc_ctrl_ops, 585 582 V4L2_CID_COLORIMETRY_HDR10_MASTERING_DISPLAY, 586 583 v4l2_ctrl_ptr_create(NULL)); 584 + 585 + v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &venc_ctrl_ops, 586 + V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE, 587 + V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC, 588 + 0, V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM); 587 589 588 590 v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, 589 591 V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD, 0,

-3

drivers/media/platform/renesas/rcar-vin/rcar-core.c

··· 94 94 95 95 strscpy(mdev->driver_name, KBUILD_MODNAME, sizeof(mdev->driver_name)); 96 96 strscpy(mdev->model, match->compatible, sizeof(mdev->model)); 97 - snprintf(mdev->bus_info, sizeof(mdev->bus_info), "platform:%s", 98 - dev_name(mdev->dev)); 99 97 100 98 media_device_init(mdev); 101 99 ··· 889 891 890 892 static int rvin_csi2_create_link(struct rvin_group *group, unsigned int id, 891 893 const struct rvin_group_route *route) 892 - 893 894 { 894 895 struct media_entity *source = &group->remotes[route->csi].subdev->entity; 895 896 struct media_entity *sink = &group->vin[id]->vdev.entity;

+25

drivers/media/platform/renesas/rcar-vin/rcar-dma.c

··· 77 77 78 78 /* Register bit fields for R-Car VIN */ 79 79 /* Video n Main Control Register bits */ 80 + #define VNMC_INF_MASK (7 << 16) 80 81 #define VNMC_DPINE (1 << 27) /* Gen3 specific */ 81 82 #define VNMC_SCLE (1 << 26) /* Gen3 specific */ 82 83 #define VNMC_FOC (1 << 21) ··· 89 88 #define VNMC_INF_RAW8 (4 << 16) 90 89 #define VNMC_INF_YUV16 (5 << 16) 91 90 #define VNMC_INF_RGB888 (6 << 16) 91 + #define VNMC_INF_RGB666 (7 << 16) 92 92 #define VNMC_VUP (1 << 10) 93 93 #define VNMC_IM_ODD (0 << 3) 94 94 #define VNMC_IM_ODD_EVEN (1 << 3) ··· 707 705 break; 708 706 default: 709 707 break; 708 + } 709 + 710 + /* Make sure input interface and input format is valid. */ 711 + if (vin->info->model == RCAR_GEN3) { 712 + switch (vnmc & VNMC_INF_MASK) { 713 + case VNMC_INF_YUV8_BT656: 714 + case VNMC_INF_YUV10_BT656: 715 + case VNMC_INF_YUV16: 716 + case VNMC_INF_RGB666: 717 + if (vin->is_csi) { 718 + vin_err(vin, "Invalid setting in MIPI CSI2\n"); 719 + return -EINVAL; 720 + } 721 + break; 722 + case VNMC_INF_RAW8: 723 + if (!vin->is_csi) { 724 + vin_err(vin, "Invalid setting in Digital Pins\n"); 725 + return -EINVAL; 726 + } 727 + break; 728 + default: 729 + break; 730 + } 710 731 } 711 732 712 733 /* Enable VSYNC Field Toggle mode after one VSYNC input */

+7 -6

drivers/media/platform/renesas/rcar-vin/rcar-v4l2.c

··· 255 255 { 256 256 struct v4l2_subdev *sd = vin_to_source(vin); 257 257 struct v4l2_subdev_state *sd_state; 258 + static struct lock_class_key key; 258 259 struct v4l2_subdev_format format = { 259 260 .which = which, 260 261 .pad = vin->parallel.source_pad, ··· 264 263 u32 width, height; 265 264 int ret; 266 265 267 - sd_state = v4l2_subdev_alloc_state(sd); 266 + /* 267 + * FIXME: Drop this call, drivers are not supposed to use 268 + * __v4l2_subdev_state_alloc(). 269 + */ 270 + sd_state = __v4l2_subdev_state_alloc(sd, "rvin:state->lock", &key); 268 271 if (IS_ERR(sd_state)) 269 272 return PTR_ERR(sd_state); 270 273 ··· 304 299 305 300 rvin_format_align(vin, pix); 306 301 done: 307 - v4l2_subdev_free_state(sd_state); 302 + __v4l2_subdev_state_free(sd_state); 308 303 309 304 return ret; 310 305 } ··· 312 307 static int rvin_querycap(struct file *file, void *priv, 313 308 struct v4l2_capability *cap) 314 309 { 315 - struct rvin_dev *vin = video_drvdata(file); 316 - 317 310 strscpy(cap->driver, KBUILD_MODNAME, sizeof(cap->driver)); 318 311 strscpy(cap->card, "R_Car_VIN", sizeof(cap->card)); 319 - snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", 320 - dev_name(vin->dev)); 321 312 return 0; 322 313 } 323 314

-2

drivers/media/platform/renesas/rcar_jpu.c

··· 670 670 strscpy(cap->card, DRV_NAME " decoder", sizeof(cap->card)); 671 671 672 672 strscpy(cap->driver, DRV_NAME, sizeof(cap->driver)); 673 - snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", 674 - dev_name(ctx->jpu->dev)); 675 673 memset(cap->reserved, 0, sizeof(cap->reserved)); 676 674 677 675 return 0;

+4 -4

drivers/media/platform/renesas/renesas-ceu.c

··· 1606 1606 u32 irq_mask; 1607 1607 }; 1608 1608 1609 - static const struct ceu_data ceu_data_rz = { 1610 - .irq_mask = CEU_CETCR_ALL_IRQS_RZ, 1611 - }; 1612 - 1613 1609 static const struct ceu_data ceu_data_sh4 = { 1614 1610 .irq_mask = CEU_CETCR_ALL_IRQS_SH4, 1615 1611 }; 1616 1612 1617 1613 #if IS_ENABLED(CONFIG_OF) 1614 + static const struct ceu_data ceu_data_rz = { 1615 + .irq_mask = CEU_CETCR_ALL_IRQS_RZ, 1616 + }; 1617 + 1618 1618 static const struct of_device_id ceu_of_match[] = { 1619 1619 { .compatible = "renesas,r7s72100-ceu", .data = &ceu_data_rz }, 1620 1620 { .compatible = "renesas,r8a7740-ceu", .data = &ceu_data_rz },

-2

drivers/media/platform/renesas/vsp1/vsp1_drv.c

··· 243 243 mdev->dev = vsp1->dev; 244 244 mdev->hw_revision = vsp1->version; 245 245 strscpy(mdev->model, vsp1->info->model, sizeof(mdev->model)); 246 - snprintf(mdev->bus_info, sizeof(mdev->bus_info), "platform:%s", 247 - dev_name(mdev->dev)); 248 246 media_device_init(mdev); 249 247 250 248 vsp1->media_ops.link_setup = vsp1_entity_link_setup;

+8 -2

drivers/media/platform/renesas/vsp1/vsp1_entity.c

··· 613 613 const char *name, unsigned int num_pads, 614 614 const struct v4l2_subdev_ops *ops, u32 function) 615 615 { 616 + static struct lock_class_key key; 616 617 struct v4l2_subdev *subdev; 617 618 unsigned int i; 618 619 int ret; ··· 676 675 * Allocate the pad configuration to store formats and selection 677 676 * rectangles. 678 677 */ 679 - entity->config = v4l2_subdev_alloc_state(&entity->subdev); 678 + /* 679 + * FIXME: Drop this call, drivers are not supposed to use 680 + * __v4l2_subdev_state_alloc(). 681 + */ 682 + entity->config = __v4l2_subdev_state_alloc(&entity->subdev, 683 + "vsp1:config->lock", &key); 680 684 if (IS_ERR(entity->config)) { 681 685 media_entity_cleanup(&entity->subdev.entity); 682 686 return PTR_ERR(entity->config); ··· 696 690 entity->ops->destroy(entity); 697 691 if (entity->subdev.ctrl_handler) 698 692 v4l2_ctrl_handler_free(entity->subdev.ctrl_handler); 699 - v4l2_subdev_free_state(entity->config); 693 + __v4l2_subdev_state_free(entity->config); 700 694 media_entity_cleanup(&entity->subdev.entity); 701 695 }

-2

drivers/media/platform/renesas/vsp1/vsp1_histo.c

··· 434 434 435 435 strscpy(cap->driver, "vsp1", sizeof(cap->driver)); 436 436 strscpy(cap->card, histo->video.name, sizeof(cap->card)); 437 - snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", 438 - dev_name(histo->entity.vsp1->dev)); 439 437 440 438 return 0; 441 439 }

+3 -3

drivers/media/platform/renesas/vsp1/vsp1_rpf.c

··· 291 291 + crop.left * fmtinfo->bpp[0] / 8; 292 292 293 293 if (format->num_planes > 1) { 294 + unsigned int bpl = format->plane_fmt[1].bytesperline; 294 295 unsigned int offset; 295 296 296 - offset = crop.top * format->plane_fmt[1].bytesperline 297 - + crop.left / fmtinfo->hsub 298 - * fmtinfo->bpp[1] / 8; 297 + offset = crop.top / fmtinfo->vsub * bpl 298 + + crop.left / fmtinfo->hsub * fmtinfo->bpp[1] / 8; 299 299 mem.addr[1] += offset; 300 300 mem.addr[2] += offset; 301 301 }

+2 -14

drivers/media/platform/renesas/vsp1/vsp1_video.c

··· 959 959 960 960 strscpy(cap->driver, "vsp1", sizeof(cap->driver)); 961 961 strscpy(cap->card, video->video.name, sizeof(cap->card)); 962 - snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", 963 - dev_name(video->vsp1->dev)); 964 962 965 963 return 0; 966 964 } ··· 1030 1032 struct vsp1_pipeline *pipe; 1031 1033 int ret; 1032 1034 1033 - if (video->queue.owner && video->queue.owner != file->private_data) 1035 + if (vb2_queue_is_busy(&video->queue, file)) 1034 1036 return -EBUSY; 1035 1037 1036 1038 /* ··· 1127 1129 static int vsp1_video_release(struct file *file) 1128 1130 { 1129 1131 struct vsp1_video *video = video_drvdata(file); 1130 - struct v4l2_fh *vfh = file->private_data; 1131 1132 1132 - mutex_lock(&video->lock); 1133 - if (video->queue.owner == vfh) { 1134 - vb2_queue_release(&video->queue); 1135 - video->queue.owner = NULL; 1136 - } 1137 - mutex_unlock(&video->lock); 1133 + vb2_fop_release(file); 1138 1134 1139 1135 vsp1_device_put(video->vsp1); 1140 - 1141 - v4l2_fh_release(file); 1142 - 1143 - file->private_data = NULL; 1144 1136 1145 1137 return 0; 1146 1138 }

+4 -2

drivers/media/platform/rockchip/rga/rga.c

··· 865 865 866 866 ret = pm_runtime_resume_and_get(rga->dev); 867 867 if (ret < 0) 868 - goto rel_vdev; 868 + goto rel_m2m; 869 869 870 870 rga->version.major = (rga_read(rga, RGA_VERSION_INFO) >> 24) & 0xFF; 871 871 rga->version.minor = (rga_read(rga, RGA_VERSION_INFO) >> 20) & 0x0F; ··· 881 881 DMA_ATTR_WRITE_COMBINE); 882 882 if (!rga->cmdbuf_virt) { 883 883 ret = -ENOMEM; 884 - goto rel_vdev; 884 + goto rel_m2m; 885 885 } 886 886 887 887 rga->src_mmu_pages = ··· 918 918 free_dma: 919 919 dma_free_attrs(rga->dev, RGA_CMDBUF_SIZE, rga->cmdbuf_virt, 920 920 rga->cmdbuf_phy, DMA_ATTR_WRITE_COMBINE); 921 + rel_m2m: 922 + v4l2_m2m_release(rga->m2m_dev); 921 923 rel_vdev: 922 924 video_device_release(vfd); 923 925 unreg_v4l2_dev:

+18 -16

drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c

··· 14 14 #include <linux/pm_runtime.h> 15 15 #include <linux/videodev2.h> 16 16 #include <linux/vmalloc.h> 17 + 18 + #include <media/mipi-csi2.h> 17 19 #include <media/v4l2-event.h> 18 20 19 21 #include "rkisp1-common.h" ··· 64 62 }, { 65 63 .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10, 66 64 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 67 - .mipi_dt = RKISP1_CIF_CSI2_DT_RAW10, 65 + .mipi_dt = MIPI_CSI2_DT_RAW10, 68 66 .bayer_pat = RKISP1_RAW_RGGB, 69 67 .bus_width = 10, 70 68 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 71 69 }, { 72 70 .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, 73 71 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 74 - .mipi_dt = RKISP1_CIF_CSI2_DT_RAW10, 72 + .mipi_dt = MIPI_CSI2_DT_RAW10, 75 73 .bayer_pat = RKISP1_RAW_BGGR, 76 74 .bus_width = 10, 77 75 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 78 76 }, { 79 77 .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10, 80 78 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 81 - .mipi_dt = RKISP1_CIF_CSI2_DT_RAW10, 79 + .mipi_dt = MIPI_CSI2_DT_RAW10, 82 80 .bayer_pat = RKISP1_RAW_GBRG, 83 81 .bus_width = 10, 84 82 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 85 83 }, { 86 84 .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, 87 85 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 88 - .mipi_dt = RKISP1_CIF_CSI2_DT_RAW10, 86 + .mipi_dt = MIPI_CSI2_DT_RAW10, 89 87 .bayer_pat = RKISP1_RAW_GRBG, 90 88 .bus_width = 10, 91 89 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 92 90 }, { 93 91 .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12, 94 92 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 95 - .mipi_dt = RKISP1_CIF_CSI2_DT_RAW12, 93 + .mipi_dt = MIPI_CSI2_DT_RAW12, 96 94 .bayer_pat = RKISP1_RAW_RGGB, 97 95 .bus_width = 12, 98 96 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 99 97 }, { 100 98 .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, 101 99 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 102 - .mipi_dt = RKISP1_CIF_CSI2_DT_RAW12, 100 + .mipi_dt = MIPI_CSI2_DT_RAW12, 103 101 .bayer_pat = RKISP1_RAW_BGGR, 104 102 .bus_width = 12, 105 103 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 106 104 }, { 107 105 .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12, 108 106 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 109 - .mipi_dt = RKISP1_CIF_CSI2_DT_RAW12, 107 + .mipi_dt = MIPI_CSI2_DT_RAW12, 110 108 .bayer_pat = RKISP1_RAW_GBRG, 111 109 .bus_width = 12, 112 110 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 113 111 }, { 114 112 .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12, 115 113 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 116 - .mipi_dt = RKISP1_CIF_CSI2_DT_RAW12, 114 + .mipi_dt = MIPI_CSI2_DT_RAW12, 117 115 .bayer_pat = RKISP1_RAW_GRBG, 118 116 .bus_width = 12, 119 117 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 120 118 }, { 121 119 .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8, 122 120 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 123 - .mipi_dt = RKISP1_CIF_CSI2_DT_RAW8, 121 + .mipi_dt = MIPI_CSI2_DT_RAW8, 124 122 .bayer_pat = RKISP1_RAW_RGGB, 125 123 .bus_width = 8, 126 124 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 127 125 }, { 128 126 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, 129 127 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 130 - .mipi_dt = RKISP1_CIF_CSI2_DT_RAW8, 128 + .mipi_dt = MIPI_CSI2_DT_RAW8, 131 129 .bayer_pat = RKISP1_RAW_BGGR, 132 130 .bus_width = 8, 133 131 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 134 132 }, { 135 133 .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8, 136 134 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 137 - .mipi_dt = RKISP1_CIF_CSI2_DT_RAW8, 135 + .mipi_dt = MIPI_CSI2_DT_RAW8, 138 136 .bayer_pat = RKISP1_RAW_GBRG, 139 137 .bus_width = 8, 140 138 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 141 139 }, { 142 140 .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8, 143 141 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 144 - .mipi_dt = RKISP1_CIF_CSI2_DT_RAW8, 142 + .mipi_dt = MIPI_CSI2_DT_RAW8, 145 143 .bayer_pat = RKISP1_RAW_GRBG, 146 144 .bus_width = 8, 147 145 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 148 146 }, { 149 147 .mbus_code = MEDIA_BUS_FMT_YUYV8_1X16, 150 148 .pixel_enc = V4L2_PIXEL_ENC_YUV, 151 - .mipi_dt = RKISP1_CIF_CSI2_DT_YUV422_8b, 149 + .mipi_dt = MIPI_CSI2_DT_YUV422_8B, 152 150 .yuv_seq = RKISP1_CIF_ISP_ACQ_PROP_YCBYCR, 153 151 .bus_width = 16, 154 152 .direction = RKISP1_ISP_SD_SINK, 155 153 }, { 156 154 .mbus_code = MEDIA_BUS_FMT_YVYU8_1X16, 157 155 .pixel_enc = V4L2_PIXEL_ENC_YUV, 158 - .mipi_dt = RKISP1_CIF_CSI2_DT_YUV422_8b, 156 + .mipi_dt = MIPI_CSI2_DT_YUV422_8B, 159 157 .yuv_seq = RKISP1_CIF_ISP_ACQ_PROP_YCRYCB, 160 158 .bus_width = 16, 161 159 .direction = RKISP1_ISP_SD_SINK, 162 160 }, { 163 161 .mbus_code = MEDIA_BUS_FMT_UYVY8_1X16, 164 162 .pixel_enc = V4L2_PIXEL_ENC_YUV, 165 - .mipi_dt = RKISP1_CIF_CSI2_DT_YUV422_8b, 163 + .mipi_dt = MIPI_CSI2_DT_YUV422_8B, 166 164 .yuv_seq = RKISP1_CIF_ISP_ACQ_PROP_CBYCRY, 167 165 .bus_width = 16, 168 166 .direction = RKISP1_ISP_SD_SINK, 169 167 }, { 170 168 .mbus_code = MEDIA_BUS_FMT_VYUY8_1X16, 171 169 .pixel_enc = V4L2_PIXEL_ENC_YUV, 172 - .mipi_dt = RKISP1_CIF_CSI2_DT_YUV422_8b, 170 + .mipi_dt = MIPI_CSI2_DT_YUV422_8B, 173 171 .yuv_seq = RKISP1_CIF_ISP_ACQ_PROP_CRYCBY, 174 172 .bus_width = 16, 175 173 .direction = RKISP1_ISP_SD_SINK,

-11

drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

··· 333 333 /* MIPI_DATA_SEL */ 334 334 #define RKISP1_CIF_MIPI_DATA_SEL_VC(a) (((a) & 0x3) << 6) 335 335 #define RKISP1_CIF_MIPI_DATA_SEL_DT(a) (((a) & 0x3F) << 0) 336 - /* MIPI DATA_TYPE */ 337 - #define RKISP1_CIF_CSI2_DT_YUV420_8b 0x18 338 - #define RKISP1_CIF_CSI2_DT_YUV420_10b 0x19 339 - #define RKISP1_CIF_CSI2_DT_YUV422_8b 0x1E 340 - #define RKISP1_CIF_CSI2_DT_YUV422_10b 0x1F 341 - #define RKISP1_CIF_CSI2_DT_RGB565 0x22 342 - #define RKISP1_CIF_CSI2_DT_RGB666 0x23 343 - #define RKISP1_CIF_CSI2_DT_RGB888 0x24 344 - #define RKISP1_CIF_CSI2_DT_RAW8 0x2A 345 - #define RKISP1_CIF_CSI2_DT_RAW10 0x2B 346 - #define RKISP1_CIF_CSI2_DT_RAW12 0x2C 347 336 348 337 /* MIPI_IMSC, MIPI_RIS, MIPI_MIS, MIPI_ICR, MIPI_ISR */ 349 338 #define RKISP1_CIF_MIPI_SYNC_FIFO_OVFLW(a) (((a) & 0xF) << 0)

-5

drivers/media/platform/samsung/exynos-gsc/gsc-m2m.c

··· 285 285 static int gsc_m2m_querycap(struct file *file, void *fh, 286 286 struct v4l2_capability *cap) 287 287 { 288 - struct gsc_ctx *ctx = fh_to_ctx(fh); 289 - struct gsc_dev *gsc = ctx->gsc_dev; 290 - 291 288 strscpy(cap->driver, GSC_MODULE_NAME, sizeof(cap->driver)); 292 289 strscpy(cap->card, GSC_MODULE_NAME " gscaler", sizeof(cap->card)); 293 - snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", 294 - dev_name(&gsc->pdev->dev)); 295 290 return 0; 296 291 } 297 292

-2

drivers/media/platform/samsung/exynos4-is/common.c

··· 41 41 { 42 42 strscpy(cap->driver, dev->driver->name, sizeof(cap->driver)); 43 43 strscpy(cap->card, dev->driver->name, sizeof(cap->card)); 44 - snprintf(cap->bus_info, sizeof(cap->bus_info), 45 - "platform:%s", dev_name(dev)); 46 44 } 47 45 EXPORT_SYMBOL(__fimc_vidioc_querycap); 48 46

+4 -2

drivers/media/platform/samsung/exynos4-is/fimc-is.c

··· 140 140 dev_err(&is->pdev->dev, "clock %s enable failed\n", 141 141 fimc_is_clocks[i]); 142 142 for (--i; i >= 0; i--) 143 - clk_disable(is->clocks[i]); 143 + clk_disable_unprepare(is->clocks[i]); 144 144 return ret; 145 145 } 146 146 pr_debug("enabled clock: %s\n", fimc_is_clocks[i]); ··· 830 830 831 831 ret = pm_runtime_resume_and_get(dev); 832 832 if (ret < 0) 833 - goto err_irq; 833 + goto err_pm_disable; 834 834 835 835 vb2_dma_contig_set_max_seg_size(dev, DMA_BIT_MASK(32)); 836 836 ··· 864 864 pm_runtime_put_noidle(dev); 865 865 if (!pm_runtime_enabled(dev)) 866 866 fimc_is_runtime_suspend(dev); 867 + err_pm_disable: 868 + pm_runtime_disable(dev); 867 869 err_irq: 868 870 free_irq(is->irq, is); 869 871 err_clk:

+1 -1

drivers/media/platform/samsung/exynos4-is/fimc-isp-video.h

··· 32 32 return 0; 33 33 } 34 34 35 - void fimc_isp_video_device_unregister(struct fimc_isp *isp, 35 + static inline void fimc_isp_video_device_unregister(struct fimc_isp *isp, 36 36 enum v4l2_buf_type type) 37 37 { 38 38 }

-4

drivers/media/platform/samsung/exynos4-is/fimc-lite.c

··· 646 646 static int fimc_lite_querycap(struct file *file, void *priv, 647 647 struct v4l2_capability *cap) 648 648 { 649 - struct fimc_lite *fimc = video_drvdata(file); 650 - 651 649 strscpy(cap->driver, FIMC_LITE_DRV_NAME, sizeof(cap->driver)); 652 650 strscpy(cap->card, FIMC_LITE_DRV_NAME, sizeof(cap->card)); 653 - snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", 654 - dev_name(&fimc->pdev->dev)); 655 651 return 0; 656 652 } 657 653

-2

drivers/media/platform/samsung/s5p-jpeg/jpeg-core.c

··· 1257 1257 strscpy(cap->card, S5P_JPEG_M2M_NAME " decoder", 1258 1258 sizeof(cap->card)); 1259 1259 } 1260 - snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", 1261 - dev_name(ctx->jpeg->dev)); 1262 1260 return 0; 1263 1261 } 1264 1262

-1

drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-s5p.c

··· 52 52 { 53 53 unsigned long reg, m; 54 54 55 - m = S5P_PROC_MODE_DECOMPR; 56 55 if (mode == S5P_JPEG_ENCODE) 57 56 m = S5P_PROC_MODE_COMPR; 58 57 else

-2

drivers/media/platform/samsung/s5p-mfc/s5p_mfc_dec.c

··· 288 288 289 289 strscpy(cap->driver, S5P_MFC_NAME, sizeof(cap->driver)); 290 290 strscpy(cap->card, dev->vfd_dec->name, sizeof(cap->card)); 291 - snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", 292 - dev_name(&dev->plat_dev->dev)); 293 291 return 0; 294 292 } 295 293

-2

drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c

··· 1309 1309 1310 1310 strscpy(cap->driver, S5P_MFC_NAME, sizeof(cap->driver)); 1311 1311 strscpy(cap->card, dev->vfd_enc->name, sizeof(cap->card)); 1312 - snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", 1313 - dev_name(&dev->plat_dev->dev)); 1314 1312 return 0; 1315 1313 } 1316 1314

+1 -2

drivers/media/platform/st/sti/bdisp/bdisp-v4l2.c

··· 1394 1394 bdisp_debugfs_remove(bdisp); 1395 1395 v4l2_device_unregister(&bdisp->v4l2_dev); 1396 1396 err_clk: 1397 - if (!IS_ERR(bdisp->clock)) 1398 - clk_unprepare(bdisp->clock); 1397 + clk_unprepare(bdisp->clock); 1399 1398 err_wq: 1400 1399 destroy_workqueue(bdisp->work_queue); 1401 1400 return ret;

-1

drivers/media/platform/st/sti/c8sectpfe/c8sectpfe-common.h

··· 13 13 #include <linux/dvb/dmx.h> 14 14 #include <linux/dvb/frontend.h> 15 15 #include <linux/gpio.h> 16 - #include <linux/version.h> 17 16 18 17 #include <media/dmxdev.h> 19 18 #include <media/dvb_demux.h>

+4 -2

drivers/media/platform/st/sti/delta/delta-v4l2.c

··· 1859 1859 if (ret) { 1860 1860 dev_err(delta->dev, "%s failed to initialize firmware ipc channel\n", 1861 1861 DELTA_PREFIX); 1862 - goto err; 1862 + goto err_pm_disable; 1863 1863 } 1864 1864 1865 1865 /* register all available decoders */ ··· 1873 1873 if (ret) { 1874 1874 dev_err(delta->dev, "%s failed to register V4L2 device\n", 1875 1875 DELTA_PREFIX); 1876 - goto err; 1876 + goto err_pm_disable; 1877 1877 } 1878 1878 1879 1879 delta->work_queue = create_workqueue(DELTA_NAME); ··· 1898 1898 destroy_workqueue(delta->work_queue); 1899 1899 err_v4l2: 1900 1900 v4l2_device_unregister(&delta->v4l2_dev); 1901 + err_pm_disable: 1902 + pm_runtime_disable(dev); 1901 1903 err: 1902 1904 return ret; 1903 1905 }

-2

drivers/media/platform/st/stm32/stm32-dcmi.c

··· 1997 1997 1998 1998 /* Initialize media device */ 1999 1999 strscpy(dcmi->mdev.model, DRV_NAME, sizeof(dcmi->mdev.model)); 2000 - snprintf(dcmi->mdev.bus_info, sizeof(dcmi->mdev.bus_info), 2001 - "platform:%s", DRV_NAME); 2002 2000 dcmi->mdev.dev = &pdev->dev; 2003 2001 media_device_init(&dcmi->mdev); 2004 2002

-2

drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c

··· 173 173 strscpy(csi->mdev.model, "Allwinner Video Capture Device", 174 174 sizeof(csi->mdev.model)); 175 175 csi->mdev.hw_revision = 0; 176 - snprintf(csi->mdev.bus_info, sizeof(csi->mdev.bus_info), "platform:%s", 177 - dev_name(csi->dev)); 178 176 media_device_init(&csi->mdev); 179 177 csi->v4l.mdev = &csi->mdev; 180 178

-4

drivers/media/platform/sunxi/sun4i-csi/sun4i_v4l2.c

··· 53 53 static int sun4i_csi_querycap(struct file *file, void *priv, 54 54 struct v4l2_capability *cap) 55 55 { 56 - struct sun4i_csi *csi = video_drvdata(file); 57 - 58 56 strscpy(cap->driver, KBUILD_MODNAME, sizeof(cap->driver)); 59 57 strscpy(cap->card, "sun4i-csi", sizeof(cap->card)); 60 - snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", 61 - dev_name(csi->dev)); 62 58 63 59 return 0; 64 60 }

-2

drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c

··· 733 733 strscpy(csi->media_dev.model, "Allwinner Video Capture Device", 734 734 sizeof(csi->media_dev.model)); 735 735 csi->media_dev.hw_revision = 0; 736 - snprintf(csi->media_dev.bus_info, sizeof(csi->media_dev.bus_info), 737 - "platform:%s", dev_name(csi->dev)); 738 736 739 737 media_device_init(&csi->media_dev); 740 738 v4l2_async_nf_init(&csi->notifier);

+27

drivers/media/platform/ti/cal/cal-camerarx.c

··· 583 583 return ret; 584 584 } 585 585 586 + int cal_camerarx_get_remote_frame_desc(struct cal_camerarx *phy, 587 + struct v4l2_mbus_frame_desc *desc) 588 + { 589 + struct media_pad *pad; 590 + int ret; 591 + 592 + if (!phy->source) 593 + return -EPIPE; 594 + 595 + pad = media_entity_remote_pad(&phy->pads[CAL_CAMERARX_PAD_SINK]); 596 + if (!pad) 597 + return -EPIPE; 598 + 599 + ret = v4l2_subdev_call(phy->source, pad, get_frame_desc, pad->index, 600 + desc); 601 + if (ret) 602 + return ret; 603 + 604 + if (desc->type != V4L2_MBUS_FRAME_DESC_TYPE_CSI2) { 605 + dev_err(phy->cal->dev, 606 + "Frame descriptor does not describe CSI-2 link"); 607 + return -EINVAL; 608 + } 609 + 610 + return 0; 611 + } 612 + 586 613 /* ------------------------------------------------------------------ 587 614 * V4L2 Subdev Operations 588 615 * ------------------------------------------------------------------

-4

drivers/media/platform/ti/cal/cal-video.c

··· 47 47 static int cal_querycap(struct file *file, void *priv, 48 48 struct v4l2_capability *cap) 49 49 { 50 - struct cal_ctx *ctx = video_drvdata(file); 51 - 52 50 strscpy(cap->driver, CAL_MODULE_NAME, sizeof(cap->driver)); 53 51 strscpy(cap->card, CAL_MODULE_NAME, sizeof(cap->card)); 54 52 55 - snprintf(cap->bus_info, sizeof(cap->bus_info), 56 - "platform:%s", dev_name(ctx->cal->dev)); 57 53 return 0; 58 54 } 59 55

+47 -4

drivers/media/platform/ti/cal/cal.c

··· 469 469 return stopped; 470 470 } 471 471 472 + static int 473 + cal_get_remote_frame_desc_entry(struct cal_camerarx *phy, 474 + struct v4l2_mbus_frame_desc_entry *entry) 475 + { 476 + struct v4l2_mbus_frame_desc fd; 477 + int ret; 478 + 479 + ret = cal_camerarx_get_remote_frame_desc(phy, &fd); 480 + if (ret) { 481 + if (ret != -ENOIOCTLCMD) 482 + dev_err(phy->cal->dev, 483 + "Failed to get remote frame desc: %d\n", ret); 484 + return ret; 485 + } 486 + 487 + if (fd.num_entries == 0) { 488 + dev_err(phy->cal->dev, 489 + "No streams found in the remote frame descriptor\n"); 490 + 491 + return -ENODEV; 492 + } 493 + 494 + if (fd.num_entries > 1) 495 + dev_dbg(phy->cal->dev, 496 + "Multiple streams not supported in remote frame descriptor, using the first one\n"); 497 + 498 + *entry = fd.entry[0]; 499 + 500 + return 0; 501 + } 502 + 472 503 int cal_ctx_prepare(struct cal_ctx *ctx) 473 504 { 505 + struct v4l2_mbus_frame_desc_entry entry; 474 506 int ret; 507 + 508 + ret = cal_get_remote_frame_desc_entry(ctx->phy, &entry); 509 + 510 + if (ret == -ENOIOCTLCMD) { 511 + ctx->vc = 0; 512 + ctx->datatype = CAL_CSI2_CTX_DT_ANY; 513 + } else if (!ret) { 514 + ctx_dbg(2, ctx, "Framedesc: len %u, vc %u, dt %#x\n", 515 + entry.length, entry.bus.csi2.vc, entry.bus.csi2.dt); 516 + 517 + ctx->vc = entry.bus.csi2.vc; 518 + ctx->datatype = entry.bus.csi2.dt; 519 + } else { 520 + return ret; 521 + } 475 522 476 523 ctx->use_pix_proc = !ctx->fmtinfo->meta; 477 524 ··· 931 884 mdev->dev = cal->dev; 932 885 mdev->hw_revision = cal->revision; 933 886 strscpy(mdev->model, "CAL", sizeof(mdev->model)); 934 - snprintf(mdev->bus_info, sizeof(mdev->bus_info), "platform:%s", 935 - dev_name(mdev->dev)); 936 887 media_device_init(mdev); 937 888 938 889 /* ··· 981 936 ctx->dma_ctx = inst; 982 937 ctx->csi2_ctx = inst; 983 938 ctx->cport = inst; 984 - ctx->vc = 0; 985 - ctx->datatype = CAL_CSI2_CTX_DT_ANY; 986 939 987 940 ret = cal_ctx_v4l2_init(ctx); 988 941 if (ret)

+2

drivers/media/platform/ti/cal/cal.h

··· 323 323 324 324 void cal_quickdump_regs(struct cal_dev *cal); 325 325 326 + int cal_camerarx_get_remote_frame_desc(struct cal_camerarx *phy, 327 + struct v4l2_mbus_frame_desc *desc); 326 328 void cal_camerarx_disable(struct cal_camerarx *phy); 327 329 void cal_camerarx_i913_errata(struct cal_camerarx *phy); 328 330 struct cal_camerarx *cal_camerarx_create(struct cal_dev *cal,

+1 -2

drivers/media/platform/ti/davinci/dm355_ccdc.c

··· 918 918 919 919 iounmap(ccdc_cfg.base_addr); 920 920 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 921 - if (res) 922 - release_mem_region(res->start, resource_size(res)); 921 + release_mem_region(res->start, resource_size(res)); 923 922 vpfe_unregister_ccdc_device(&ccdc_hw_dev); 924 923 return 0; 925 924 }

+1 -2

drivers/media/platform/ti/davinci/dm644x_ccdc.c

··· 839 839 840 840 iounmap(ccdc_cfg.base_addr); 841 841 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 842 - if (res) 843 - release_mem_region(res->start, resource_size(res)); 842 + release_mem_region(res->start, resource_size(res)); 844 843 vpfe_unregister_ccdc_device(&ccdc_hw_dev); 845 844 return 0; 846 845 }

+1 -2

drivers/media/platform/ti/davinci/isif.c

··· 1107 1107 isif_cfg.linear_tbl1_addr = NULL; 1108 1108 while (i < 3) { 1109 1109 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 1110 - if (res) 1111 - release_mem_region(res->start, resource_size(res)); 1110 + release_mem_region(res->start, resource_size(res)); 1112 1111 i++; 1113 1112 } 1114 1113 vpfe_unregister_ccdc_device(&isif_hw_dev);

-2

drivers/media/platform/ti/davinci/vpbe_display.c

··· 630 630 631 631 snprintf(cap->driver, sizeof(cap->driver), "%s", 632 632 dev_name(vpbe_dev->pdev)); 633 - snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", 634 - dev_name(vpbe_dev->pdev)); 635 633 strscpy(cap->card, vpbe_dev->cfg->module_name, sizeof(cap->card)); 636 634 637 635 return 0;

-2

drivers/media/platform/ti/davinci/vpif_capture.c

··· 1067 1067 struct vpif_capture_config *config = vpif_dev->platform_data; 1068 1068 1069 1069 strscpy(cap->driver, VPIF_DRIVER_NAME, sizeof(cap->driver)); 1070 - snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", 1071 - dev_name(vpif_dev)); 1072 1070 strscpy(cap->card, config->card_name, sizeof(cap->card)); 1073 1071 1074 1072 return 0;

+1 -4

drivers/media/platform/ti/davinci/vpif_display.c

··· 585 585 struct vpif_display_config *config = vpif_dev->platform_data; 586 586 587 587 strscpy(cap->driver, VPIF_DRIVER_NAME, sizeof(cap->driver)); 588 - snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", 589 - dev_name(vpif_dev)); 590 588 strscpy(cap->card, config->card_name, sizeof(cap->card)); 591 589 592 590 return 0; ··· 1284 1286 goto probe_subdev_out; 1285 1287 } 1286 1288 1287 - if (vpif_obj.sd[i]) 1288 - vpif_obj.sd[i]->grp_id = 1 << i; 1289 + vpif_obj.sd[i]->grp_id = 1 << i; 1289 1290 } 1290 1291 err = vpif_probe_complete(); 1291 1292 if (err)

+2 -1

drivers/media/platform/ti/omap3isp/ispcsiphy.c

··· 31 31 32 32 switch (iface) { 33 33 default: 34 - /* Should not happen in practice, but let's keep the compiler happy. */ 34 + /* Should not happen in practice, but let's keep the compiler happy. */ 35 + return; 35 36 case ISP_INTERFACE_CCP2B_PHY1: 36 37 reg &= ~OMAP3630_CONTROL_CAMERA_PHY_CTRL_CSI1_RX_SEL_PHY2; 37 38 shift = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY1_SHIFT;

+1 -3

drivers/media/platform/video-mux.c

··· 442 442 vmux->mux = devm_mux_control_get(dev, NULL); 443 443 if (IS_ERR(vmux->mux)) { 444 444 ret = PTR_ERR(vmux->mux); 445 - if (ret != -EPROBE_DEFER) 446 - dev_err(dev, "Failed to get mux: %d\n", ret); 447 - return ret; 445 + return dev_err_probe(dev, ret, "Failed to get mux\n"); 448 446 } 449 447 450 448 mutex_init(&vmux->lock);

+2 -2

drivers/media/radio/Kconfig

··· 4 4 # 5 5 6 6 menuconfig RADIO_ADAPTERS 7 - bool "Radio Adapters" 7 + tristate "Radio Adapters" 8 8 depends on VIDEO_DEV 9 9 depends on MEDIA_RADIO_SUPPORT 10 - default y 10 + default VIDEO_DEV 11 11 help 12 12 Say Y here to enable selecting AM/FM radio adapters. 13 13

-2

drivers/media/radio/radio-maxiradio.c

··· 144 144 dev->tea.v4l2_dev = v4l2_dev; 145 145 dev->tea.radio_nr = radio_nr; 146 146 strscpy(dev->tea.card, "Maxi Radio FM2000", sizeof(dev->tea.card)); 147 - snprintf(dev->tea.bus_info, sizeof(dev->tea.bus_info), 148 - "PCI:%s", pci_name(pdev)); 149 147 150 148 retval = -ENODEV; 151 149

+6 -1

drivers/media/rc/gpio-ir-tx.c

··· 62 62 return; 63 63 64 64 /* udelay more than 1ms may not work */ 65 - delta = min(delta, 1000); 65 + if (delta >= 1000) { 66 + mdelay(delta / 1000); 67 + continue; 68 + } 69 + 66 70 udelay(delta); 71 + break; 67 72 } 68 73 } 69 74

+52 -57

drivers/media/rc/imon.c

··· 153 153 const struct imon_usb_dev_descr *dev_descr; 154 154 /* device description with key */ 155 155 /* table for front panels */ 156 + /* 157 + * Fields for deferring free_imon_context(). 158 + * 159 + * Since reference to "struct imon_context" is stored into 160 + * "struct file"->private_data, we need to remember 161 + * how many file descriptors might access this "struct imon_context". 162 + */ 163 + refcount_t users; 164 + /* 165 + * Use a flag for telling display_open()/vfd_write()/lcd_write() that 166 + * imon_disconnect() was already called. 167 + */ 168 + bool disconnected; 169 + /* 170 + * We need to wait for RCU grace period in order to allow 171 + * display_open() to safely check ->disconnected and increment ->users. 172 + */ 173 + struct rcu_head rcu; 156 174 }; 157 175 158 176 #define TOUCH_TIMEOUT (HZ/30) ··· 178 160 /* vfd character device file operations */ 179 161 static const struct file_operations vfd_fops = { 180 162 .owner = THIS_MODULE, 181 - .open = &display_open, 182 - .write = &vfd_write, 183 - .release = &display_close, 163 + .open = display_open, 164 + .write = vfd_write, 165 + .release = display_close, 184 166 .llseek = noop_llseek, 185 167 }; 186 168 187 169 /* lcd character device file operations */ 188 170 static const struct file_operations lcd_fops = { 189 171 .owner = THIS_MODULE, 190 - .open = &display_open, 191 - .write = &lcd_write, 192 - .release = &display_close, 172 + .open = display_open, 173 + .write = lcd_write, 174 + .release = display_close, 193 175 .llseek = noop_llseek, 194 176 }; 195 177 ··· 457 439 .id_table = imon_usb_id_table, 458 440 }; 459 441 460 - /* to prevent races between open() and disconnect(), probing, etc */ 461 - static DEFINE_MUTEX(driver_lock); 462 - 463 442 /* Module bookkeeping bits */ 464 443 MODULE_AUTHOR(MOD_AUTHOR); 465 444 MODULE_DESCRIPTION(MOD_DESC); ··· 496 481 struct device *dev = ictx->dev; 497 482 498 483 usb_free_urb(ictx->tx_urb); 484 + WARN_ON(ictx->dev_present_intf0); 499 485 usb_free_urb(ictx->rx_urb_intf0); 486 + WARN_ON(ictx->dev_present_intf1); 500 487 usb_free_urb(ictx->rx_urb_intf1); 501 - kfree(ictx); 488 + kfree_rcu(ictx, rcu); 502 489 503 490 dev_dbg(dev, "%s: iMON context freed\n", __func__); 504 491 } ··· 516 499 int subminor; 517 500 int retval = 0; 518 501 519 - /* prevent races with disconnect */ 520 - mutex_lock(&driver_lock); 521 - 522 502 subminor = iminor(inode); 523 503 interface = usb_find_interface(&imon_driver, subminor); 524 504 if (!interface) { ··· 523 509 retval = -ENODEV; 524 510 goto exit; 525 511 } 526 - ictx = usb_get_intfdata(interface); 527 512 528 - if (!ictx) { 513 + rcu_read_lock(); 514 + ictx = usb_get_intfdata(interface); 515 + if (!ictx || ictx->disconnected || !refcount_inc_not_zero(&ictx->users)) { 516 + rcu_read_unlock(); 529 517 pr_err("no context found for minor %d\n", subminor); 530 518 retval = -ENODEV; 531 519 goto exit; 532 520 } 521 + rcu_read_unlock(); 533 522 534 523 mutex_lock(&ictx->lock); 535 524 ··· 550 533 551 534 mutex_unlock(&ictx->lock); 552 535 536 + if (retval && refcount_dec_and_test(&ictx->users)) 537 + free_imon_context(ictx); 538 + 553 539 exit: 554 - mutex_unlock(&driver_lock); 555 540 return retval; 556 541 } 557 542 ··· 563 544 */ 564 545 static int display_close(struct inode *inode, struct file *file) 565 546 { 566 - struct imon_context *ictx = NULL; 547 + struct imon_context *ictx = file->private_data; 567 548 int retval = 0; 568 - 569 - ictx = file->private_data; 570 - 571 - if (!ictx) { 572 - pr_err("no context for device\n"); 573 - return -ENODEV; 574 - } 575 549 576 550 mutex_lock(&ictx->lock); 577 551 ··· 580 568 } 581 569 582 570 mutex_unlock(&ictx->lock); 571 + if (refcount_dec_and_test(&ictx->users)) 572 + free_imon_context(ictx); 583 573 return retval; 584 574 } 585 575 ··· 948 934 int offset; 949 935 int seq; 950 936 int retval = 0; 951 - struct imon_context *ictx; 937 + struct imon_context *ictx = file->private_data; 952 938 static const unsigned char vfd_packet6[] = { 953 939 0x01, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF }; 954 940 955 - ictx = file->private_data; 956 - if (!ictx) { 957 - pr_err_ratelimited("no context for device\n"); 941 + if (ictx->disconnected) 958 942 return -ENODEV; 959 - } 960 943 961 944 mutex_lock(&ictx->lock); 962 945 ··· 1029 1018 size_t n_bytes, loff_t *pos) 1030 1019 { 1031 1020 int retval = 0; 1032 - struct imon_context *ictx; 1021 + struct imon_context *ictx = file->private_data; 1033 1022 1034 - ictx = file->private_data; 1035 - if (!ictx) { 1036 - pr_err_ratelimited("no context for device\n"); 1023 + if (ictx->disconnected) 1037 1024 return -ENODEV; 1038 - } 1039 1025 1040 1026 mutex_lock(&ictx->lock); 1041 1027 ··· 2412 2404 int ifnum, sysfs_err; 2413 2405 int ret = 0; 2414 2406 struct imon_context *ictx = NULL; 2415 - struct imon_context *first_if_ctx = NULL; 2416 2407 u16 vendor, product; 2417 2408 2418 2409 usbdev = usb_get_dev(interface_to_usbdev(interface)); ··· 2423 2416 dev_dbg(dev, "%s: found iMON device (%04x:%04x, intf%d)\n", 2424 2417 __func__, vendor, product, ifnum); 2425 2418 2426 - /* prevent races probing devices w/multiple interfaces */ 2427 - mutex_lock(&driver_lock); 2428 - 2429 2419 first_if = usb_ifnum_to_if(usbdev, 0); 2430 2420 if (!first_if) { 2431 2421 ret = -ENODEV; 2432 2422 goto fail; 2433 2423 } 2434 - 2435 - first_if_ctx = usb_get_intfdata(first_if); 2436 2424 2437 2425 if (ifnum == 0) { 2438 2426 ictx = imon_init_intf0(interface, id); ··· 2436 2434 ret = -ENODEV; 2437 2435 goto fail; 2438 2436 } 2437 + refcount_set(&ictx->users, 1); 2439 2438 2440 2439 } else { 2441 2440 /* this is the secondary interface on the device */ 2441 + struct imon_context *first_if_ctx = usb_get_intfdata(first_if); 2442 2442 2443 2443 /* fail early if first intf failed to register */ 2444 2444 if (!first_if_ctx) { ··· 2454 2450 ret = -ENODEV; 2455 2451 goto fail; 2456 2452 } 2453 + refcount_inc(&ictx->users); 2457 2454 2458 2455 } 2459 2456 2460 2457 usb_set_intfdata(interface, ictx); 2461 2458 2462 2459 if (ifnum == 0) { 2463 - mutex_lock(&ictx->lock); 2464 - 2465 2460 if (product == 0xffdc && ictx->rf_device) { 2466 2461 sysfs_err = sysfs_create_group(&interface->dev.kobj, 2467 2462 &imon_rf_attr_group); ··· 2471 2468 2472 2469 if (ictx->display_supported) 2473 2470 imon_init_display(ictx, interface); 2474 - 2475 - mutex_unlock(&ictx->lock); 2476 2471 } 2477 2472 2478 2473 dev_info(dev, "iMON device (%04x:%04x, intf%d) on usb<%d:%d> initialized\n", 2479 2474 vendor, product, ifnum, 2480 2475 usbdev->bus->busnum, usbdev->devnum); 2481 2476 2482 - mutex_unlock(&driver_lock); 2483 2477 usb_put_dev(usbdev); 2484 2478 2485 2479 return 0; 2486 2480 2487 2481 fail: 2488 - mutex_unlock(&driver_lock); 2489 2482 usb_put_dev(usbdev); 2490 2483 dev_err(dev, "unable to register, err %d\n", ret); 2491 2484 ··· 2497 2498 struct device *dev; 2498 2499 int ifnum; 2499 2500 2500 - /* prevent races with multi-interface device probing and display_open */ 2501 - mutex_lock(&driver_lock); 2502 - 2503 2501 ictx = usb_get_intfdata(interface); 2502 + ictx->disconnected = true; 2504 2503 dev = ictx->dev; 2505 2504 ifnum = interface->cur_altsetting->desc.bInterfaceNumber; 2506 2505 ··· 2520 2523 if (ifnum == 0) { 2521 2524 ictx->dev_present_intf0 = false; 2522 2525 usb_kill_urb(ictx->rx_urb_intf0); 2523 - usb_put_dev(ictx->usbdev_intf0); 2524 2526 input_unregister_device(ictx->idev); 2525 2527 rc_unregister_device(ictx->rdev); 2526 2528 if (ictx->display_supported) { ··· 2528 2532 else if (ictx->display_type == IMON_DISPLAY_TYPE_VFD) 2529 2533 usb_deregister_dev(interface, &imon_vfd_class); 2530 2534 } 2535 + usb_put_dev(ictx->usbdev_intf0); 2531 2536 } else { 2532 2537 ictx->dev_present_intf1 = false; 2533 2538 usb_kill_urb(ictx->rx_urb_intf1); 2534 - usb_put_dev(ictx->usbdev_intf1); 2535 2539 if (ictx->display_type == IMON_DISPLAY_TYPE_VGA) { 2536 - input_unregister_device(ictx->touch); 2537 2540 del_timer_sync(&ictx->ttimer); 2541 + input_unregister_device(ictx->touch); 2538 2542 } 2543 + usb_put_dev(ictx->usbdev_intf1); 2539 2544 } 2540 2545 2541 - if (!ictx->dev_present_intf0 && !ictx->dev_present_intf1) 2546 + if (refcount_dec_and_test(&ictx->users)) 2542 2547 free_imon_context(ictx); 2543 - 2544 - mutex_unlock(&driver_lock); 2545 2548 2546 2549 dev_dbg(dev, "%s: iMON device (intf%d) disconnected\n", 2547 2550 __func__, ifnum); ··· 2573 2578 usb_rx_callback_intf0, ictx, 2574 2579 ictx->rx_endpoint_intf0->bInterval); 2575 2580 2576 - rc = usb_submit_urb(ictx->rx_urb_intf0, GFP_ATOMIC); 2581 + rc = usb_submit_urb(ictx->rx_urb_intf0, GFP_NOIO); 2577 2582 2578 2583 } else { 2579 2584 usb_fill_int_urb(ictx->rx_urb_intf1, ictx->usbdev_intf1, ··· 2583 2588 usb_rx_callback_intf1, ictx, 2584 2589 ictx->rx_endpoint_intf1->bInterval); 2585 2590 2586 - rc = usb_submit_urb(ictx->rx_urb_intf1, GFP_ATOMIC); 2591 + rc = usb_submit_urb(ictx->rx_urb_intf1, GFP_NOIO); 2587 2592 } 2588 2593 2589 2594 return rc;

+1 -3

drivers/media/rc/meson-ir-tx.c

··· 323 323 return PTR_ERR(ir->reg_base); 324 324 325 325 irq = platform_get_irq(pdev, 0); 326 - if (irq < 0) { 327 - dev_err(dev, "no irq resource found\n"); 326 + if (irq < 0) 328 327 return -ENODEV; 329 - } 330 328 331 329 ir->dev = dev; 332 330 ir->carrier = MIRTX_DEFAULT_CARRIER;

+12 -6

drivers/media/usb/dvb-usb/a800.c

··· 72 72 } 73 73 74 74 /* do not change the order of the ID table */ 75 - static struct usb_device_id a800_table [] = { 76 - /* 00 */ { USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_DVBT_USB2_COLD) }, 77 - /* 01 */ { USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_DVBT_USB2_WARM) }, 78 - { } /* Terminating entry */ 75 + enum { 76 + AVERMEDIA_DVBT_USB2_COLD, 77 + AVERMEDIA_DVBT_USB2_WARM, 79 78 }; 79 + 80 + static struct usb_device_id a800_table[] = { 81 + DVB_USB_DEV(AVERMEDIA, AVERMEDIA_DVBT_USB2_COLD), 82 + DVB_USB_DEV(AVERMEDIA, AVERMEDIA_DVBT_USB2_WARM), 83 + { } 84 + }; 85 + 80 86 MODULE_DEVICE_TABLE (usb, a800_table); 81 87 82 88 static struct dvb_usb_device_properties a800_properties = { ··· 138 132 .num_device_descs = 1, 139 133 .devices = { 140 134 { "AVerMedia AverTV DVB-T USB 2.0 (A800)", 141 - { &a800_table[0], NULL }, 142 - { &a800_table[1], NULL }, 135 + { &a800_table[AVERMEDIA_DVBT_USB2_COLD], NULL }, 136 + { &a800_table[AVERMEDIA_DVBT_USB2_WARM], NULL }, 143 137 }, 144 138 } 145 139 };

+8 -11

drivers/media/usb/dvb-usb/af9005.c

··· 994 994 THIS_MODULE, NULL, adapter_nr); 995 995 } 996 996 997 - enum af9005_usb_table_entry { 997 + enum { 998 998 AFATECH_AF9005, 999 - TERRATEC_AF9005, 1000 - ANSONIC_AF9005, 999 + TERRATEC_CINERGY_T_USB_XE, 1000 + ANSONIC_DVBT_USB, 1001 1001 }; 1002 1002 1003 1003 static struct usb_device_id af9005_usb_table[] = { 1004 - [AFATECH_AF9005] = {USB_DEVICE(USB_VID_AFATECH, 1005 - USB_PID_AFATECH_AF9005)}, 1006 - [TERRATEC_AF9005] = {USB_DEVICE(USB_VID_TERRATEC, 1007 - USB_PID_TERRATEC_CINERGY_T_USB_XE)}, 1008 - [ANSONIC_AF9005] = {USB_DEVICE(USB_VID_ANSONIC, 1009 - USB_PID_ANSONIC_DVBT_USB)}, 1004 + DVB_USB_DEV(AFATECH, AFATECH_AF9005), 1005 + DVB_USB_DEV(TERRATEC, TERRATEC_CINERGY_T_USB_XE), 1006 + DVB_USB_DEV(ANSONIC, ANSONIC_DVBT_USB), 1010 1007 { } 1011 1008 }; 1012 1009 ··· 1068 1071 .warm_ids = {NULL}, 1069 1072 }, 1070 1073 {.name = "TerraTec Cinergy T USB XE", 1071 - .cold_ids = {&af9005_usb_table[TERRATEC_AF9005], NULL}, 1074 + .cold_ids = {&af9005_usb_table[TERRATEC_CINERGY_T_USB_XE], NULL}, 1072 1075 .warm_ids = {NULL}, 1073 1076 }, 1074 1077 {.name = "Ansonic DVB-T USB1.1 stick", 1075 - .cold_ids = {&af9005_usb_table[ANSONIC_AF9005], NULL}, 1078 + .cold_ids = {&af9005_usb_table[ANSONIC_DVBT_USB], NULL}, 1076 1079 .warm_ids = {NULL}, 1077 1080 }, 1078 1081 {NULL},

+28 -17

drivers/media/usb/dvb-usb/az6027.c

··· 1080 1080 } 1081 1081 1082 1082 1083 + enum { 1084 + AZUREWAVE_AZ6027, 1085 + TERRATEC_DVBS2CI_V1, 1086 + TERRATEC_DVBS2CI_V2, 1087 + TECHNISAT_USB2_HDCI_V1, 1088 + TECHNISAT_USB2_HDCI_V2, 1089 + ELGATO_EYETV_SAT, 1090 + ELGATO_EYETV_SAT_V2, 1091 + ELGATO_EYETV_SAT_V3, 1092 + }; 1093 + 1083 1094 static struct usb_device_id az6027_usb_table[] = { 1084 - { USB_DEVICE(USB_VID_AZUREWAVE, USB_PID_AZUREWAVE_AZ6027) }, 1085 - { USB_DEVICE(USB_VID_TERRATEC, USB_PID_TERRATEC_DVBS2CI_V1) }, 1086 - { USB_DEVICE(USB_VID_TERRATEC, USB_PID_TERRATEC_DVBS2CI_V2) }, 1087 - { USB_DEVICE(USB_VID_TECHNISAT, USB_PID_TECHNISAT_USB2_HDCI_V1) }, 1088 - { USB_DEVICE(USB_VID_TECHNISAT, USB_PID_TECHNISAT_USB2_HDCI_V2) }, 1089 - { USB_DEVICE(USB_VID_ELGATO, USB_PID_ELGATO_EYETV_SAT) }, 1090 - { USB_DEVICE(USB_VID_ELGATO, USB_PID_ELGATO_EYETV_SAT_V2) }, 1091 - { USB_DEVICE(USB_VID_ELGATO, USB_PID_ELGATO_EYETV_SAT_V3) }, 1092 - { }, 1095 + DVB_USB_DEV(AZUREWAVE, AZUREWAVE_AZ6027), 1096 + DVB_USB_DEV(TERRATEC, TERRATEC_DVBS2CI_V1), 1097 + DVB_USB_DEV(TERRATEC, TERRATEC_DVBS2CI_V2), 1098 + DVB_USB_DEV(TECHNISAT, TECHNISAT_USB2_HDCI_V1), 1099 + DVB_USB_DEV(TECHNISAT, TECHNISAT_USB2_HDCI_V2), 1100 + DVB_USB_DEV(ELGATO, ELGATO_EYETV_SAT), 1101 + DVB_USB_DEV(ELGATO, ELGATO_EYETV_SAT_V2), 1102 + DVB_USB_DEV(ELGATO, ELGATO_EYETV_SAT_V3), 1103 + { } 1093 1104 }; 1094 1105 1095 1106 MODULE_DEVICE_TABLE(usb, az6027_usb_table); ··· 1152 1141 .devices = { 1153 1142 { 1154 1143 .name = "AZUREWAVE DVB-S/S2 USB2.0 (AZ6027)", 1155 - .cold_ids = { &az6027_usb_table[0], NULL }, 1144 + .cold_ids = { &az6027_usb_table[AZUREWAVE_AZ6027], NULL }, 1156 1145 .warm_ids = { NULL }, 1157 1146 }, { 1158 1147 .name = "TERRATEC S7", 1159 - .cold_ids = { &az6027_usb_table[1], NULL }, 1148 + .cold_ids = { &az6027_usb_table[TERRATEC_DVBS2CI_V1], NULL }, 1160 1149 .warm_ids = { NULL }, 1161 1150 }, { 1162 1151 .name = "TERRATEC S7 MKII", 1163 - .cold_ids = { &az6027_usb_table[2], NULL }, 1152 + .cold_ids = { &az6027_usb_table[TERRATEC_DVBS2CI_V2], NULL }, 1164 1153 .warm_ids = { NULL }, 1165 1154 }, { 1166 1155 .name = "Technisat SkyStar USB 2 HD CI", 1167 - .cold_ids = { &az6027_usb_table[3], NULL }, 1156 + .cold_ids = { &az6027_usb_table[TECHNISAT_USB2_HDCI_V1], NULL }, 1168 1157 .warm_ids = { NULL }, 1169 1158 }, { 1170 1159 .name = "Technisat SkyStar USB 2 HD CI", 1171 - .cold_ids = { &az6027_usb_table[4], NULL }, 1160 + .cold_ids = { &az6027_usb_table[TECHNISAT_USB2_HDCI_V2], NULL }, 1172 1161 .warm_ids = { NULL }, 1173 1162 }, { 1174 1163 .name = "Elgato EyeTV Sat", 1175 - .cold_ids = { &az6027_usb_table[5], NULL }, 1164 + .cold_ids = { &az6027_usb_table[ELGATO_EYETV_SAT], NULL }, 1176 1165 .warm_ids = { NULL }, 1177 1166 }, { 1178 1167 .name = "Elgato EyeTV Sat", 1179 - .cold_ids = { &az6027_usb_table[6], NULL }, 1168 + .cold_ids = { &az6027_usb_table[ELGATO_EYETV_SAT_V2], NULL }, 1180 1169 .warm_ids = { NULL }, 1181 1170 }, { 1182 1171 .name = "Elgato EyeTV Sat", 1183 - .cold_ids = { &az6027_usb_table[7], NULL }, 1172 + .cold_ids = { &az6027_usb_table[ELGATO_EYETV_SAT_V3], NULL }, 1184 1173 .warm_ids = { NULL }, 1185 1174 }, 1186 1175 { NULL },

+7 -3

drivers/media/usb/dvb-usb/cinergyT2-core.c

··· 193 193 THIS_MODULE, NULL, adapter_nr); 194 194 } 195 195 196 + enum { 197 + TERRATEC_CINERGY_T2, 198 + }; 199 + 196 200 static struct usb_device_id cinergyt2_usb_table[] = { 197 - { USB_DEVICE(USB_VID_TERRATEC, 0x0038) }, 198 - { 0 } 201 + DVB_USB_DEV(TERRATEC, TERRATEC_CINERGY_T2), 202 + { } 199 203 }; 200 204 201 205 MODULE_DEVICE_TABLE(usb, cinergyt2_usb_table); ··· 244 240 .devices = { 245 241 { .name = "TerraTec/qanu USB2.0 Highspeed DVB-T Receiver", 246 242 .cold_ids = {NULL}, 247 - .warm_ids = { &cinergyt2_usb_table[0], NULL }, 243 + .warm_ids = { &cinergyt2_usb_table[TERRATEC_CINERGY_T2], NULL }, 248 244 }, 249 245 { NULL }, 250 246 }

+23 -65

drivers/media/usb/dvb-usb/cxusb.c

··· 1692 1692 dvb_usb_device_exit(intf); 1693 1693 } 1694 1694 1695 - static struct usb_device_id cxusb_table[NR__cxusb_table_index + 1] = { 1696 - [MEDION_MD95700] = { 1697 - USB_DEVICE(USB_VID_MEDION, USB_PID_MEDION_MD95700) 1698 - }, 1699 - [DVICO_BLUEBIRD_LG064F_COLD] = { 1700 - USB_DEVICE(USB_VID_DVICO, USB_PID_DVICO_BLUEBIRD_LG064F_COLD) 1701 - }, 1702 - [DVICO_BLUEBIRD_LG064F_WARM] = { 1703 - USB_DEVICE(USB_VID_DVICO, USB_PID_DVICO_BLUEBIRD_LG064F_WARM) 1704 - }, 1705 - [DVICO_BLUEBIRD_DUAL_1_COLD] = { 1706 - USB_DEVICE(USB_VID_DVICO, USB_PID_DVICO_BLUEBIRD_DUAL_1_COLD) 1707 - }, 1708 - [DVICO_BLUEBIRD_DUAL_1_WARM] = { 1709 - USB_DEVICE(USB_VID_DVICO, USB_PID_DVICO_BLUEBIRD_DUAL_1_WARM) 1710 - }, 1711 - [DVICO_BLUEBIRD_LGZ201_COLD] = { 1712 - USB_DEVICE(USB_VID_DVICO, USB_PID_DVICO_BLUEBIRD_LGZ201_COLD) 1713 - }, 1714 - [DVICO_BLUEBIRD_LGZ201_WARM] = { 1715 - USB_DEVICE(USB_VID_DVICO, USB_PID_DVICO_BLUEBIRD_LGZ201_WARM) 1716 - }, 1717 - [DVICO_BLUEBIRD_TH7579_COLD] = { 1718 - USB_DEVICE(USB_VID_DVICO, USB_PID_DVICO_BLUEBIRD_TH7579_COLD) 1719 - }, 1720 - [DVICO_BLUEBIRD_TH7579_WARM] = { 1721 - USB_DEVICE(USB_VID_DVICO, USB_PID_DVICO_BLUEBIRD_TH7579_WARM) 1722 - }, 1723 - [DIGITALNOW_BLUEBIRD_DUAL_1_COLD] = { 1724 - USB_DEVICE(USB_VID_DVICO, 1725 - USB_PID_DIGITALNOW_BLUEBIRD_DUAL_1_COLD) 1726 - }, 1727 - [DIGITALNOW_BLUEBIRD_DUAL_1_WARM] = { 1728 - USB_DEVICE(USB_VID_DVICO, 1729 - USB_PID_DIGITALNOW_BLUEBIRD_DUAL_1_WARM) 1730 - }, 1731 - [DVICO_BLUEBIRD_DUAL_2_COLD] = { 1732 - USB_DEVICE(USB_VID_DVICO, USB_PID_DVICO_BLUEBIRD_DUAL_2_COLD) 1733 - }, 1734 - [DVICO_BLUEBIRD_DUAL_2_WARM] = { 1735 - USB_DEVICE(USB_VID_DVICO, USB_PID_DVICO_BLUEBIRD_DUAL_2_WARM) 1736 - }, 1737 - [DVICO_BLUEBIRD_DUAL_4] = { 1738 - USB_DEVICE(USB_VID_DVICO, USB_PID_DVICO_BLUEBIRD_DUAL_4) 1739 - }, 1740 - [DVICO_BLUEBIRD_DVB_T_NANO_2] = { 1741 - USB_DEVICE(USB_VID_DVICO, USB_PID_DVICO_BLUEBIRD_DVB_T_NANO_2) 1742 - }, 1743 - [DVICO_BLUEBIRD_DVB_T_NANO_2_NFW_WARM] = { 1744 - USB_DEVICE(USB_VID_DVICO, 1745 - USB_PID_DVICO_BLUEBIRD_DVB_T_NANO_2_NFW_WARM) 1746 - }, 1747 - [AVERMEDIA_VOLAR_A868R] = { 1748 - USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_VOLAR_A868R) 1749 - }, 1750 - [DVICO_BLUEBIRD_DUAL_4_REV_2] = { 1751 - USB_DEVICE(USB_VID_DVICO, USB_PID_DVICO_BLUEBIRD_DUAL_4_REV_2) 1752 - }, 1753 - [CONEXANT_D680_DMB] = { 1754 - USB_DEVICE(USB_VID_CONEXANT, USB_PID_CONEXANT_D680_DMB) 1755 - }, 1756 - [MYGICA_D689] = { 1757 - USB_DEVICE(USB_VID_CONEXANT, USB_PID_MYGICA_D689) 1758 - }, 1759 - {} /* Terminating entry */ 1695 + static struct usb_device_id cxusb_table[] = { 1696 + DVB_USB_DEV(MEDION, MEDION_MD95700), 1697 + DVB_USB_DEV(DVICO, DVICO_BLUEBIRD_LG064F_COLD), 1698 + DVB_USB_DEV(DVICO, DVICO_BLUEBIRD_LG064F_WARM), 1699 + DVB_USB_DEV(DVICO, DVICO_BLUEBIRD_DUAL_1_COLD), 1700 + DVB_USB_DEV(DVICO, DVICO_BLUEBIRD_DUAL_1_WARM), 1701 + DVB_USB_DEV(DVICO, DVICO_BLUEBIRD_LGZ201_COLD), 1702 + DVB_USB_DEV(DVICO, DVICO_BLUEBIRD_LGZ201_WARM), 1703 + DVB_USB_DEV(DVICO, DVICO_BLUEBIRD_TH7579_COLD), 1704 + DVB_USB_DEV(DVICO, DVICO_BLUEBIRD_TH7579_WARM), 1705 + DVB_USB_DEV(DVICO, DIGITALNOW_BLUEBIRD_DUAL_1_COLD), 1706 + DVB_USB_DEV(DVICO, DIGITALNOW_BLUEBIRD_DUAL_1_WARM), 1707 + DVB_USB_DEV(DVICO, DVICO_BLUEBIRD_DUAL_2_COLD), 1708 + DVB_USB_DEV(DVICO, DVICO_BLUEBIRD_DUAL_2_WARM), 1709 + DVB_USB_DEV(DVICO, DVICO_BLUEBIRD_DUAL_4), 1710 + DVB_USB_DEV(DVICO, DVICO_BLUEBIRD_DVB_T_NANO_2), 1711 + DVB_USB_DEV(DVICO, DVICO_BLUEBIRD_DVB_T_NANO_2_NFW_WARM), 1712 + DVB_USB_DEV(AVERMEDIA, AVERMEDIA_VOLAR_A868R), 1713 + DVB_USB_DEV(DVICO, DVICO_BLUEBIRD_DUAL_4_REV_2), 1714 + DVB_USB_DEV(CONEXANT, CONEXANT_D680_DMB), 1715 + DVB_USB_DEV(CONEXANT, MYGICA_D689), 1716 + { } 1760 1717 }; 1718 + 1761 1719 MODULE_DEVICE_TABLE(usb, cxusb_table); 1762 1720 1763 1721 static struct dvb_usb_device_properties cxusb_medion_properties = {

+259 -171

drivers/media/usb/dvb-usb/dib0700_devices.c

··· 3816 3816 3817 3817 3818 3818 /* DVB-USB and USB stuff follows */ 3819 - struct usb_device_id dib0700_usb_id_table[] = { 3820 - /* 0 */ { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_STK7700P) }, 3821 - { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_STK7700P_PC) }, 3822 - { USB_DEVICE(USB_VID_HAUPPAUGE, USB_PID_HAUPPAUGE_NOVA_T_500) }, 3823 - { USB_DEVICE(USB_VID_HAUPPAUGE, USB_PID_HAUPPAUGE_NOVA_T_500_2) }, 3824 - { USB_DEVICE(USB_VID_HAUPPAUGE, USB_PID_HAUPPAUGE_NOVA_T_STICK) }, 3825 - /* 5 */ { USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_VOLAR) }, 3826 - { USB_DEVICE(USB_VID_COMPRO, USB_PID_COMPRO_VIDEOMATE_U500) }, 3827 - { USB_DEVICE(USB_VID_UNIWILL, USB_PID_UNIWILL_STK7700P) }, 3828 - { USB_DEVICE(USB_VID_LEADTEK, USB_PID_WINFAST_DTV_DONGLE_STK7700P) }, 3829 - { USB_DEVICE(USB_VID_HAUPPAUGE, USB_PID_HAUPPAUGE_NOVA_T_STICK_2) }, 3830 - /* 10 */{ USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_VOLAR_2) }, 3831 - { USB_DEVICE(USB_VID_PINNACLE, USB_PID_PINNACLE_PCTV2000E) }, 3832 - { USB_DEVICE(USB_VID_TERRATEC, 3833 - USB_PID_TERRATEC_CINERGY_DT_XS_DIVERSITY) }, 3834 - { USB_DEVICE(USB_VID_HAUPPAUGE, USB_PID_HAUPPAUGE_NOVA_TD_STICK) }, 3835 - { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_STK7700D) }, 3836 - /* 15 */{ USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_STK7070P) }, 3837 - { USB_DEVICE(USB_VID_PINNACLE, USB_PID_PINNACLE_PCTV_DVB_T_FLASH) }, 3838 - { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_STK7070PD) }, 3839 - { USB_DEVICE(USB_VID_PINNACLE, 3840 - USB_PID_PINNACLE_PCTV_DUAL_DIVERSITY_DVB_T) }, 3841 - { USB_DEVICE(USB_VID_COMPRO, USB_PID_COMPRO_VIDEOMATE_U500_PC) }, 3842 - /* 20 */{ USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_EXPRESS) }, 3843 - { USB_DEVICE(USB_VID_GIGABYTE, USB_PID_GIGABYTE_U7000) }, 3844 - { USB_DEVICE(USB_VID_ULTIMA_ELECTRONIC, USB_PID_ARTEC_T14BR) }, 3845 - { USB_DEVICE(USB_VID_ASUS, USB_PID_ASUS_U3000) }, 3846 - { USB_DEVICE(USB_VID_ASUS, USB_PID_ASUS_U3100) }, 3847 - /* 25 */{ USB_DEVICE(USB_VID_HAUPPAUGE, USB_PID_HAUPPAUGE_NOVA_T_STICK_3) }, 3848 - { USB_DEVICE(USB_VID_HAUPPAUGE, USB_PID_HAUPPAUGE_MYTV_T) }, 3849 - { USB_DEVICE(USB_VID_TERRATEC, USB_PID_TERRATEC_CINERGY_HT_USB_XE) }, 3850 - { USB_DEVICE(USB_VID_PINNACLE, USB_PID_PINNACLE_EXPRESSCARD_320CX) }, 3851 - { USB_DEVICE(USB_VID_PINNACLE, USB_PID_PINNACLE_PCTV72E) }, 3852 - /* 30 */{ USB_DEVICE(USB_VID_PINNACLE, USB_PID_PINNACLE_PCTV73E) }, 3853 - { USB_DEVICE(USB_VID_YUAN, USB_PID_YUAN_EC372S) }, 3854 - { USB_DEVICE(USB_VID_TERRATEC, USB_PID_TERRATEC_CINERGY_HT_EXPRESS) }, 3855 - { USB_DEVICE(USB_VID_TERRATEC, USB_PID_TERRATEC_CINERGY_T_XXS) }, 3856 - { USB_DEVICE(USB_VID_LEADTEK, USB_PID_WINFAST_DTV_DONGLE_STK7700P_2) }, 3857 - /* 35 */{ USB_DEVICE(USB_VID_HAUPPAUGE, USB_PID_HAUPPAUGE_NOVA_TD_STICK_52009) }, 3858 - { USB_DEVICE(USB_VID_HAUPPAUGE, USB_PID_HAUPPAUGE_NOVA_T_500_3) }, 3859 - { USB_DEVICE(USB_VID_GIGABYTE, USB_PID_GIGABYTE_U8000) }, 3860 - { USB_DEVICE(USB_VID_YUAN, USB_PID_YUAN_STK7700PH) }, 3861 - { USB_DEVICE(USB_VID_ASUS, USB_PID_ASUS_U3000H) }, 3862 - /* 40 */{ USB_DEVICE(USB_VID_PINNACLE, USB_PID_PINNACLE_PCTV801E) }, 3863 - { USB_DEVICE(USB_VID_PINNACLE, USB_PID_PINNACLE_PCTV801E_SE) }, 3864 - { USB_DEVICE(USB_VID_TERRATEC, USB_PID_TERRATEC_CINERGY_T_EXPRESS) }, 3865 - { USB_DEVICE(USB_VID_TERRATEC, 3866 - USB_PID_TERRATEC_CINERGY_DT_XS_DIVERSITY_2) }, 3867 - { USB_DEVICE(USB_VID_SONY, USB_PID_SONY_PLAYTV) }, 3868 - /* 45 */{ USB_DEVICE(USB_VID_YUAN, USB_PID_YUAN_PD378S) }, 3869 - { USB_DEVICE(USB_VID_HAUPPAUGE, USB_PID_HAUPPAUGE_TIGER_ATSC) }, 3870 - { USB_DEVICE(USB_VID_HAUPPAUGE, USB_PID_HAUPPAUGE_TIGER_ATSC_B210) }, 3871 - { USB_DEVICE(USB_VID_YUAN, USB_PID_YUAN_MC770) }, 3872 - { USB_DEVICE(USB_VID_ELGATO, USB_PID_ELGATO_EYETV_DTT) }, 3873 - /* 50 */{ USB_DEVICE(USB_VID_ELGATO, USB_PID_ELGATO_EYETV_DTT_Dlx) }, 3874 - { USB_DEVICE(USB_VID_LEADTEK, USB_PID_WINFAST_DTV_DONGLE_H) }, 3875 - { USB_DEVICE(USB_VID_TERRATEC, USB_PID_TERRATEC_T3) }, 3876 - { USB_DEVICE(USB_VID_TERRATEC, USB_PID_TERRATEC_T5) }, 3877 - { USB_DEVICE(USB_VID_YUAN, USB_PID_YUAN_STK7700D) }, 3878 - /* 55 */{ USB_DEVICE(USB_VID_YUAN, USB_PID_YUAN_STK7700D_2) }, 3879 - { USB_DEVICE(USB_VID_PINNACLE, USB_PID_PINNACLE_PCTV73A) }, 3880 - { USB_DEVICE(USB_VID_PCTV, USB_PID_PINNACLE_PCTV73ESE) }, 3881 - { USB_DEVICE(USB_VID_PCTV, USB_PID_PINNACLE_PCTV282E) }, 3882 - { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_STK7770P) }, 3883 - /* 60 */{ USB_DEVICE(USB_VID_TERRATEC, USB_PID_TERRATEC_CINERGY_T_XXS_2) }, 3884 - { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_STK807XPVR) }, 3885 - { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_STK807XP) }, 3886 - { USB_DEVICE_VER(USB_VID_PIXELVIEW, USB_PID_PIXELVIEW_SBTVD, 0x000, 0x3f00) }, 3887 - { USB_DEVICE(USB_VID_EVOLUTEPC, USB_PID_TVWAY_PLUS) }, 3888 - /* 65 */{ USB_DEVICE(USB_VID_PINNACLE, USB_PID_PINNACLE_PCTV73ESE) }, 3889 - { USB_DEVICE(USB_VID_PINNACLE, USB_PID_PINNACLE_PCTV282E) }, 3890 - { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_STK8096GP) }, 3891 - { USB_DEVICE(USB_VID_ELGATO, USB_PID_ELGATO_EYETV_DIVERSITY) }, 3892 - { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_NIM9090M) }, 3893 - /* 70 */{ USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_NIM8096MD) }, 3894 - { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_NIM9090MD) }, 3895 - { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_NIM7090) }, 3896 - { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_TFE7090PVR) }, 3897 - { USB_DEVICE(USB_VID_TECHNISAT, USB_PID_TECHNISAT_AIRSTAR_TELESTICK_2) }, 3898 - /* 75 */{ USB_DEVICE(USB_VID_MEDION, USB_PID_CREATIX_CTX1921) }, 3899 - { USB_DEVICE(USB_VID_PINNACLE, USB_PID_PINNACLE_PCTV340E) }, 3900 - { USB_DEVICE(USB_VID_PINNACLE, USB_PID_PINNACLE_PCTV340E_SE) }, 3901 - { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_TFE7790P) }, 3902 - { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_TFE8096P) }, 3903 - /* 80 */{ USB_DEVICE(USB_VID_ELGATO, USB_PID_ELGATO_EYETV_DTT_2) }, 3904 - { USB_DEVICE(USB_VID_PCTV, USB_PID_PCTV_2002E) }, 3905 - { USB_DEVICE(USB_VID_PCTV, USB_PID_PCTV_2002E_SE) }, 3906 - { USB_DEVICE(USB_VID_PCTV, USB_PID_DIBCOM_STK8096PVR) }, 3907 - { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_STK8096PVR) }, 3908 - /* 85 */{ USB_DEVICE(USB_VID_HAMA, USB_PID_HAMA_DVBT_HYBRID) }, 3909 - { USB_DEVICE(USB_VID_MICROSOFT, USB_PID_XBOX_ONE_TUNER) }, 3910 - { 0 } /* Terminating entry */ 3819 + enum { 3820 + DIBCOM_STK7700P, 3821 + DIBCOM_STK7700P_PC, 3822 + HAUPPAUGE_NOVA_T_500, 3823 + HAUPPAUGE_NOVA_T_500_2, 3824 + HAUPPAUGE_NOVA_T_STICK, 3825 + AVERMEDIA_VOLAR, 3826 + COMPRO_VIDEOMATE_U500, 3827 + UNIWILL_STK7700P, 3828 + LEADTEK_WINFAST_DTV_DONGLE_STK7700P, 3829 + HAUPPAUGE_NOVA_T_STICK_2, 3830 + AVERMEDIA_VOLAR_2, 3831 + PINNACLE_PCTV2000E, 3832 + TERRATEC_CINERGY_DT_XS_DIVERSITY, 3833 + HAUPPAUGE_NOVA_TD_STICK, 3834 + DIBCOM_STK7700D, 3835 + DIBCOM_STK7070P, 3836 + PINNACLE_PCTV_DVB_T_FLASH, 3837 + DIBCOM_STK7070PD, 3838 + PINNACLE_PCTV_DUAL_DIVERSITY_DVB_T, 3839 + COMPRO_VIDEOMATE_U500_PC, 3840 + AVERMEDIA_EXPRESS, 3841 + GIGABYTE_U7000, 3842 + ULTIMA_ARTEC_T14BR, 3843 + ASUS_U3000, 3844 + ASUS_U3100, 3845 + HAUPPAUGE_NOVA_T_STICK_3, 3846 + HAUPPAUGE_MYTV_T, 3847 + TERRATEC_CINERGY_HT_USB_XE, 3848 + PINNACLE_EXPRESSCARD_320CX, 3849 + PINNACLE_PCTV72E, 3850 + PINNACLE_PCTV73E, 3851 + YUAN_EC372S, 3852 + TERRATEC_CINERGY_HT_EXPRESS, 3853 + TERRATEC_CINERGY_T_XXS, 3854 + LEADTEK_WINFAST_DTV_DONGLE_STK7700P_2, 3855 + HAUPPAUGE_NOVA_TD_STICK_52009, 3856 + HAUPPAUGE_NOVA_T_500_3, 3857 + GIGABYTE_U8000, 3858 + YUAN_STK7700PH, 3859 + ASUS_U3000H, 3860 + PINNACLE_PCTV801E, 3861 + PINNACLE_PCTV801E_SE, 3862 + TERRATEC_CINERGY_T_EXPRESS, 3863 + TERRATEC_CINERGY_DT_XS_DIVERSITY_2, 3864 + SONY_PLAYTV, 3865 + YUAN_PD378S, 3866 + HAUPPAUGE_TIGER_ATSC, 3867 + HAUPPAUGE_TIGER_ATSC_B210, 3868 + YUAN_MC770, 3869 + ELGATO_EYETV_DTT, 3870 + ELGATO_EYETV_DTT_Dlx, 3871 + LEADTEK_WINFAST_DTV_DONGLE_H, 3872 + TERRATEC_T3, 3873 + TERRATEC_T5, 3874 + YUAN_STK7700D, 3875 + YUAN_STK7700D_2, 3876 + PINNACLE_PCTV73A, 3877 + PCTV_PINNACLE_PCTV73ESE, 3878 + PCTV_PINNACLE_PCTV282E, 3879 + DIBCOM_STK7770P, 3880 + TERRATEC_CINERGY_T_XXS_2, 3881 + DIBCOM_STK807XPVR, 3882 + DIBCOM_STK807XP, 3883 + PIXELVIEW_SBTVD, 3884 + EVOLUTEPC_TVWAY_PLUS, 3885 + PINNACLE_PCTV73ESE, 3886 + PINNACLE_PCTV282E, 3887 + DIBCOM_STK8096GP, 3888 + ELGATO_EYETV_DIVERSITY, 3889 + DIBCOM_NIM9090M, 3890 + DIBCOM_NIM8096MD, 3891 + DIBCOM_NIM9090MD, 3892 + DIBCOM_NIM7090, 3893 + DIBCOM_TFE7090PVR, 3894 + TECHNISAT_AIRSTAR_TELESTICK_2, 3895 + MEDION_CREATIX_CTX1921, 3896 + PINNACLE_PCTV340E, 3897 + PINNACLE_PCTV340E_SE, 3898 + DIBCOM_TFE7790P, 3899 + DIBCOM_TFE8096P, 3900 + ELGATO_EYETV_DTT_2, 3901 + PCTV_2002E, 3902 + PCTV_2002E_SE, 3903 + PCTV_DIBCOM_STK8096PVR, 3904 + DIBCOM_STK8096PVR, 3905 + HAMA_DVBT_HYBRID, 3906 + MICROSOFT_XBOX_ONE_TUNER, 3911 3907 }; 3908 + 3909 + struct usb_device_id dib0700_usb_id_table[] = { 3910 + DVB_USB_DEV(DIBCOM, DIBCOM_STK7700P), 3911 + DVB_USB_DEV(DIBCOM, DIBCOM_STK7700P_PC), 3912 + DVB_USB_DEV(HAUPPAUGE, HAUPPAUGE_NOVA_T_500), 3913 + DVB_USB_DEV(HAUPPAUGE, HAUPPAUGE_NOVA_T_500_2), 3914 + DVB_USB_DEV(HAUPPAUGE, HAUPPAUGE_NOVA_T_STICK), 3915 + DVB_USB_DEV(AVERMEDIA, AVERMEDIA_VOLAR), 3916 + DVB_USB_DEV(COMPRO, COMPRO_VIDEOMATE_U500), 3917 + DVB_USB_DEV(UNIWILL, UNIWILL_STK7700P), 3918 + DVB_USB_DEV(LEADTEK, LEADTEK_WINFAST_DTV_DONGLE_STK7700P), 3919 + DVB_USB_DEV(HAUPPAUGE, HAUPPAUGE_NOVA_T_STICK_2), 3920 + DVB_USB_DEV(AVERMEDIA, AVERMEDIA_VOLAR_2), 3921 + DVB_USB_DEV(PINNACLE, PINNACLE_PCTV2000E), 3922 + DVB_USB_DEV(TERRATEC, TERRATEC_CINERGY_DT_XS_DIVERSITY), 3923 + DVB_USB_DEV(HAUPPAUGE, HAUPPAUGE_NOVA_TD_STICK), 3924 + DVB_USB_DEV(DIBCOM, DIBCOM_STK7700D), 3925 + DVB_USB_DEV(DIBCOM, DIBCOM_STK7070P), 3926 + DVB_USB_DEV(PINNACLE, PINNACLE_PCTV_DVB_T_FLASH), 3927 + DVB_USB_DEV(DIBCOM, DIBCOM_STK7070PD), 3928 + DVB_USB_DEV(PINNACLE, PINNACLE_PCTV_DUAL_DIVERSITY_DVB_T), 3929 + DVB_USB_DEV(COMPRO, COMPRO_VIDEOMATE_U500_PC), 3930 + DVB_USB_DEV(AVERMEDIA, AVERMEDIA_EXPRESS), 3931 + DVB_USB_DEV(GIGABYTE, GIGABYTE_U7000), 3932 + DVB_USB_DEV(ULTIMA_ELECTRONIC, ULTIMA_ARTEC_T14BR), 3933 + DVB_USB_DEV(ASUS, ASUS_U3000), 3934 + DVB_USB_DEV(ASUS, ASUS_U3100), 3935 + DVB_USB_DEV(HAUPPAUGE, HAUPPAUGE_NOVA_T_STICK_3), 3936 + DVB_USB_DEV(HAUPPAUGE, HAUPPAUGE_MYTV_T), 3937 + DVB_USB_DEV(TERRATEC, TERRATEC_CINERGY_HT_USB_XE), 3938 + DVB_USB_DEV(PINNACLE, PINNACLE_EXPRESSCARD_320CX), 3939 + DVB_USB_DEV(PINNACLE, PINNACLE_PCTV72E), 3940 + DVB_USB_DEV(PINNACLE, PINNACLE_PCTV73E), 3941 + DVB_USB_DEV(YUAN, YUAN_EC372S), 3942 + DVB_USB_DEV(TERRATEC, TERRATEC_CINERGY_HT_EXPRESS), 3943 + DVB_USB_DEV(TERRATEC, TERRATEC_CINERGY_T_XXS), 3944 + DVB_USB_DEV(LEADTEK, LEADTEK_WINFAST_DTV_DONGLE_STK7700P_2), 3945 + DVB_USB_DEV(HAUPPAUGE, HAUPPAUGE_NOVA_TD_STICK_52009), 3946 + DVB_USB_DEV(HAUPPAUGE, HAUPPAUGE_NOVA_T_500_3), 3947 + DVB_USB_DEV(GIGABYTE, GIGABYTE_U8000), 3948 + DVB_USB_DEV(YUAN, YUAN_STK7700PH), 3949 + DVB_USB_DEV(ASUS, ASUS_U3000H), 3950 + DVB_USB_DEV(PINNACLE, PINNACLE_PCTV801E), 3951 + DVB_USB_DEV(PINNACLE, PINNACLE_PCTV801E_SE), 3952 + DVB_USB_DEV(TERRATEC, TERRATEC_CINERGY_T_EXPRESS), 3953 + DVB_USB_DEV(TERRATEC, TERRATEC_CINERGY_DT_XS_DIVERSITY_2), 3954 + DVB_USB_DEV(SONY, SONY_PLAYTV), 3955 + DVB_USB_DEV(YUAN, YUAN_PD378S), 3956 + DVB_USB_DEV(HAUPPAUGE, HAUPPAUGE_TIGER_ATSC), 3957 + DVB_USB_DEV(HAUPPAUGE, HAUPPAUGE_TIGER_ATSC_B210), 3958 + DVB_USB_DEV(YUAN, YUAN_MC770), 3959 + DVB_USB_DEV(ELGATO, ELGATO_EYETV_DTT), 3960 + DVB_USB_DEV(ELGATO, ELGATO_EYETV_DTT_Dlx), 3961 + DVB_USB_DEV(LEADTEK, LEADTEK_WINFAST_DTV_DONGLE_H), 3962 + DVB_USB_DEV(TERRATEC, TERRATEC_T3), 3963 + DVB_USB_DEV(TERRATEC, TERRATEC_T5), 3964 + DVB_USB_DEV(YUAN, YUAN_STK7700D), 3965 + DVB_USB_DEV(YUAN, YUAN_STK7700D_2), 3966 + DVB_USB_DEV(PINNACLE, PINNACLE_PCTV73A), 3967 + DVB_USB_DEV(PCTV, PCTV_PINNACLE_PCTV73ESE), 3968 + DVB_USB_DEV(PCTV, PCTV_PINNACLE_PCTV282E), 3969 + DVB_USB_DEV(DIBCOM, DIBCOM_STK7770P), 3970 + DVB_USB_DEV(TERRATEC, TERRATEC_CINERGY_T_XXS_2), 3971 + DVB_USB_DEV(DIBCOM, DIBCOM_STK807XPVR), 3972 + DVB_USB_DEV(DIBCOM, DIBCOM_STK807XP), 3973 + DVB_USB_DEV_VER(PIXELVIEW, PIXELVIEW_SBTVD, 0x000, 0x3f00), 3974 + DVB_USB_DEV(EVOLUTEPC, EVOLUTEPC_TVWAY_PLUS), 3975 + DVB_USB_DEV(PINNACLE, PINNACLE_PCTV73ESE), 3976 + DVB_USB_DEV(PINNACLE, PINNACLE_PCTV282E), 3977 + DVB_USB_DEV(DIBCOM, DIBCOM_STK8096GP), 3978 + DVB_USB_DEV(ELGATO, ELGATO_EYETV_DIVERSITY), 3979 + DVB_USB_DEV(DIBCOM, DIBCOM_NIM9090M), 3980 + DVB_USB_DEV(DIBCOM, DIBCOM_NIM8096MD), 3981 + DVB_USB_DEV(DIBCOM, DIBCOM_NIM9090MD), 3982 + DVB_USB_DEV(DIBCOM, DIBCOM_NIM7090), 3983 + DVB_USB_DEV(DIBCOM, DIBCOM_TFE7090PVR), 3984 + DVB_USB_DEV(TECHNISAT, TECHNISAT_AIRSTAR_TELESTICK_2), 3985 + DVB_USB_DEV(MEDION, MEDION_CREATIX_CTX1921), 3986 + DVB_USB_DEV(PINNACLE, PINNACLE_PCTV340E), 3987 + DVB_USB_DEV(PINNACLE, PINNACLE_PCTV340E_SE), 3988 + DVB_USB_DEV(DIBCOM, DIBCOM_TFE7790P), 3989 + DVB_USB_DEV(DIBCOM, DIBCOM_TFE8096P), 3990 + DVB_USB_DEV(ELGATO, ELGATO_EYETV_DTT_2), 3991 + DVB_USB_DEV(PCTV, PCTV_2002E), 3992 + DVB_USB_DEV(PCTV, PCTV_2002E_SE), 3993 + DVB_USB_DEV(PCTV, PCTV_DIBCOM_STK8096PVR), 3994 + DVB_USB_DEV(DIBCOM, DIBCOM_STK8096PVR), 3995 + DVB_USB_DEV(HAMA, HAMA_DVBT_HYBRID), 3996 + DVB_USB_DEV(MICROSOFT, MICROSOFT_XBOX_ONE_TUNER), 3997 + { } 3998 + }; 3999 + 3912 4000 MODULE_DEVICE_TABLE(usb, dib0700_usb_id_table); 3913 4001 3914 4002 #define DIB0700_DEFAULT_DEVICE_PROPERTIES \ ··· 4050 3962 .num_device_descs = 8, 4051 3963 .devices = { 4052 3964 { "DiBcom STK7700P reference design", 4053 - { &dib0700_usb_id_table[0], &dib0700_usb_id_table[1] }, 3965 + { &dib0700_usb_id_table[DIBCOM_STK7700P], &dib0700_usb_id_table[DIBCOM_STK7700P_PC] }, 4054 3966 { NULL }, 4055 3967 }, 4056 3968 { "Hauppauge Nova-T Stick", 4057 - { &dib0700_usb_id_table[4], &dib0700_usb_id_table[9], NULL }, 3969 + { &dib0700_usb_id_table[HAUPPAUGE_NOVA_T_STICK], &dib0700_usb_id_table[HAUPPAUGE_NOVA_T_STICK_2], NULL }, 4058 3970 { NULL }, 4059 3971 }, 4060 3972 { "AVerMedia AVerTV DVB-T Volar", 4061 - { &dib0700_usb_id_table[5], &dib0700_usb_id_table[10] }, 3973 + { &dib0700_usb_id_table[AVERMEDIA_VOLAR], &dib0700_usb_id_table[AVERMEDIA_VOLAR_2] }, 4062 3974 { NULL }, 4063 3975 }, 4064 3976 { "Compro Videomate U500", 4065 - { &dib0700_usb_id_table[6], &dib0700_usb_id_table[19] }, 3977 + { &dib0700_usb_id_table[COMPRO_VIDEOMATE_U500], &dib0700_usb_id_table[COMPRO_VIDEOMATE_U500_PC] }, 4066 3978 { NULL }, 4067 3979 }, 4068 3980 { "Uniwill STK7700P based (Hama and others)", 4069 - { &dib0700_usb_id_table[7], NULL }, 3981 + { &dib0700_usb_id_table[UNIWILL_STK7700P], NULL }, 4070 3982 { NULL }, 4071 3983 }, 4072 3984 { "Leadtek Winfast DTV Dongle (STK7700P based)", 4073 - { &dib0700_usb_id_table[8], &dib0700_usb_id_table[34] }, 3985 + { &dib0700_usb_id_table[LEADTEK_WINFAST_DTV_DONGLE_STK7700P], &dib0700_usb_id_table[LEADTEK_WINFAST_DTV_DONGLE_STK7700P_2] }, 4074 3986 { NULL }, 4075 3987 }, 4076 3988 { "AVerMedia AVerTV DVB-T Express", 4077 - { &dib0700_usb_id_table[20] }, 3989 + { &dib0700_usb_id_table[AVERMEDIA_EXPRESS] }, 4078 3990 { NULL }, 4079 3991 }, 4080 3992 { "Gigabyte U7000", 4081 - { &dib0700_usb_id_table[21], NULL }, 3993 + { &dib0700_usb_id_table[GIGABYTE_U7000], NULL }, 4082 3994 { NULL }, 4083 3995 } 4084 3996 }, ··· 4118 4030 .num_device_descs = 1, 4119 4031 .devices = { 4120 4032 { "Hauppauge Nova-T 500 Dual DVB-T", 4121 - { &dib0700_usb_id_table[2], &dib0700_usb_id_table[3], NULL }, 4033 + { &dib0700_usb_id_table[HAUPPAUGE_NOVA_T_500], &dib0700_usb_id_table[HAUPPAUGE_NOVA_T_500_2], NULL }, 4122 4034 { NULL }, 4123 4035 }, 4124 4036 }, ··· 4166 4078 .num_device_descs = 5, 4167 4079 .devices = { 4168 4080 { "Pinnacle PCTV 2000e", 4169 - { &dib0700_usb_id_table[11], NULL }, 4081 + { &dib0700_usb_id_table[PINNACLE_PCTV2000E], NULL }, 4170 4082 { NULL }, 4171 4083 }, 4172 4084 { "Terratec Cinergy DT XS Diversity", 4173 - { &dib0700_usb_id_table[12], NULL }, 4085 + { &dib0700_usb_id_table[TERRATEC_CINERGY_DT_XS_DIVERSITY], NULL }, 4174 4086 { NULL }, 4175 4087 }, 4176 4088 { "Hauppauge Nova-TD Stick/Elgato Eye-TV Diversity", 4177 - { &dib0700_usb_id_table[13], NULL }, 4089 + { &dib0700_usb_id_table[HAUPPAUGE_NOVA_TD_STICK], NULL }, 4178 4090 { NULL }, 4179 4091 }, 4180 4092 { "DiBcom STK7700D reference design", 4181 - { &dib0700_usb_id_table[14], NULL }, 4093 + { &dib0700_usb_id_table[DIBCOM_STK7700D], NULL }, 4182 4094 { NULL }, 4183 4095 }, 4184 4096 { "YUAN High-Tech DiBcom STK7700D", 4185 - { &dib0700_usb_id_table[55], NULL }, 4097 + { &dib0700_usb_id_table[YUAN_STK7700D_2], NULL }, 4186 4098 { NULL }, 4187 4099 }, 4188 4100 ··· 4219 4131 .num_device_descs = 3, 4220 4132 .devices = { 4221 4133 { "ASUS My Cinema U3000 Mini DVBT Tuner", 4222 - { &dib0700_usb_id_table[23], NULL }, 4134 + { &dib0700_usb_id_table[ASUS_U3000], NULL }, 4223 4135 { NULL }, 4224 4136 }, 4225 4137 { "Yuan EC372S", 4226 - { &dib0700_usb_id_table[31], NULL }, 4138 + { &dib0700_usb_id_table[YUAN_EC372S], NULL }, 4227 4139 { NULL }, 4228 4140 }, 4229 4141 { "Terratec Cinergy T Express", 4230 - { &dib0700_usb_id_table[42], NULL }, 4142 + { &dib0700_usb_id_table[TERRATEC_CINERGY_T_EXPRESS], NULL }, 4231 4143 { NULL }, 4232 4144 } 4233 4145 }, ··· 4264 4176 .num_device_descs = 12, 4265 4177 .devices = { 4266 4178 { "DiBcom STK7070P reference design", 4267 - { &dib0700_usb_id_table[15], NULL }, 4179 + { &dib0700_usb_id_table[DIBCOM_STK7070P], NULL }, 4268 4180 { NULL }, 4269 4181 }, 4270 4182 { "Pinnacle PCTV DVB-T Flash Stick", 4271 - { &dib0700_usb_id_table[16], NULL }, 4183 + { &dib0700_usb_id_table[PINNACLE_PCTV_DVB_T_FLASH], NULL }, 4272 4184 { NULL }, 4273 4185 }, 4274 4186 { "Artec T14BR DVB-T", 4275 - { &dib0700_usb_id_table[22], NULL }, 4187 + { &dib0700_usb_id_table[ULTIMA_ARTEC_T14BR], NULL }, 4276 4188 { NULL }, 4277 4189 }, 4278 4190 { "ASUS My Cinema U3100 Mini DVBT Tuner", 4279 - { &dib0700_usb_id_table[24], NULL }, 4191 + { &dib0700_usb_id_table[ASUS_U3100], NULL }, 4280 4192 { NULL }, 4281 4193 }, 4282 4194 { "Hauppauge Nova-T Stick", 4283 - { &dib0700_usb_id_table[25], NULL }, 4195 + { &dib0700_usb_id_table[HAUPPAUGE_NOVA_T_STICK_3], NULL }, 4284 4196 { NULL }, 4285 4197 }, 4286 4198 { "Hauppauge Nova-T MyTV.t", 4287 - { &dib0700_usb_id_table[26], NULL }, 4199 + { &dib0700_usb_id_table[HAUPPAUGE_MYTV_T], NULL }, 4288 4200 { NULL }, 4289 4201 }, 4290 4202 { "Pinnacle PCTV 72e", 4291 - { &dib0700_usb_id_table[29], NULL }, 4203 + { &dib0700_usb_id_table[PINNACLE_PCTV72E], NULL }, 4292 4204 { NULL }, 4293 4205 }, 4294 4206 { "Pinnacle PCTV 73e", 4295 - { &dib0700_usb_id_table[30], NULL }, 4207 + { &dib0700_usb_id_table[PINNACLE_PCTV73E], NULL }, 4296 4208 { NULL }, 4297 4209 }, 4298 4210 { "Elgato EyeTV DTT", 4299 - { &dib0700_usb_id_table[49], NULL }, 4211 + { &dib0700_usb_id_table[ELGATO_EYETV_DTT], NULL }, 4300 4212 { NULL }, 4301 4213 }, 4302 4214 { "Yuan PD378S", 4303 - { &dib0700_usb_id_table[45], NULL }, 4215 + { &dib0700_usb_id_table[YUAN_PD378S], NULL }, 4304 4216 { NULL }, 4305 4217 }, 4306 4218 { "Elgato EyeTV Dtt Dlx PD378S", 4307 - { &dib0700_usb_id_table[50], NULL }, 4219 + { &dib0700_usb_id_table[ELGATO_EYETV_DTT_Dlx], NULL }, 4308 4220 { NULL }, 4309 4221 }, 4310 4222 { "Elgato EyeTV DTT rev. 2", 4311 - { &dib0700_usb_id_table[80], NULL }, 4223 + { &dib0700_usb_id_table[ELGATO_EYETV_DTT_2], NULL }, 4312 4224 { NULL }, 4313 4225 }, 4314 4226 }, ··· 4345 4257 .num_device_descs = 3, 4346 4258 .devices = { 4347 4259 { "Pinnacle PCTV 73A", 4348 - { &dib0700_usb_id_table[56], NULL }, 4260 + { &dib0700_usb_id_table[PINNACLE_PCTV73A], NULL }, 4349 4261 { NULL }, 4350 4262 }, 4351 4263 { "Pinnacle PCTV 73e SE", 4352 - { &dib0700_usb_id_table[57], &dib0700_usb_id_table[65], NULL }, 4264 + { &dib0700_usb_id_table[PCTV_PINNACLE_PCTV73ESE], &dib0700_usb_id_table[PINNACLE_PCTV73ESE], NULL }, 4353 4265 { NULL }, 4354 4266 }, 4355 4267 { "Pinnacle PCTV 282e", 4356 - { &dib0700_usb_id_table[58], &dib0700_usb_id_table[66], NULL }, 4268 + { &dib0700_usb_id_table[PCTV_PINNACLE_PCTV282E], &dib0700_usb_id_table[PINNACLE_PCTV282E], NULL }, 4357 4269 { NULL }, 4358 4270 }, 4359 4271 }, ··· 4402 4314 .num_device_descs = 3, 4403 4315 .devices = { 4404 4316 { "Hauppauge Nova-TD Stick (52009)", 4405 - { &dib0700_usb_id_table[35], NULL }, 4317 + { &dib0700_usb_id_table[HAUPPAUGE_NOVA_TD_STICK_52009], NULL }, 4406 4318 { NULL }, 4407 4319 }, 4408 4320 { "PCTV 2002e", 4409 - { &dib0700_usb_id_table[81], NULL }, 4321 + { &dib0700_usb_id_table[PCTV_2002E], NULL }, 4410 4322 { NULL }, 4411 4323 }, 4412 4324 { "PCTV 2002e SE", 4413 - { &dib0700_usb_id_table[82], NULL }, 4325 + { &dib0700_usb_id_table[PCTV_2002E_SE], NULL }, 4414 4326 { NULL }, 4415 4327 }, 4416 4328 }, ··· 4459 4371 .num_device_descs = 5, 4460 4372 .devices = { 4461 4373 { "DiBcom STK7070PD reference design", 4462 - { &dib0700_usb_id_table[17], NULL }, 4374 + { &dib0700_usb_id_table[DIBCOM_STK7070PD], NULL }, 4463 4375 { NULL }, 4464 4376 }, 4465 4377 { "Pinnacle PCTV Dual DVB-T Diversity Stick", 4466 - { &dib0700_usb_id_table[18], NULL }, 4378 + { &dib0700_usb_id_table[PINNACLE_PCTV_DUAL_DIVERSITY_DVB_T], NULL }, 4467 4379 { NULL }, 4468 4380 }, 4469 4381 { "Hauppauge Nova-TD-500 (84xxx)", 4470 - { &dib0700_usb_id_table[36], NULL }, 4382 + { &dib0700_usb_id_table[HAUPPAUGE_NOVA_T_500_3], NULL }, 4471 4383 { NULL }, 4472 4384 }, 4473 4385 { "Terratec Cinergy DT USB XS Diversity/ T5", 4474 - { &dib0700_usb_id_table[43], 4475 - &dib0700_usb_id_table[53], NULL}, 4386 + { &dib0700_usb_id_table[TERRATEC_CINERGY_DT_XS_DIVERSITY_2], 4387 + &dib0700_usb_id_table[TERRATEC_T5], NULL}, 4476 4388 { NULL }, 4477 4389 }, 4478 4390 { "Sony PlayTV", 4479 - { &dib0700_usb_id_table[44], NULL }, 4391 + { &dib0700_usb_id_table[SONY_PLAYTV], NULL }, 4480 4392 { NULL }, 4481 4393 }, 4482 4394 }, ··· 4525 4437 .num_device_descs = 1, 4526 4438 .devices = { 4527 4439 { "Elgato EyeTV Diversity", 4528 - { &dib0700_usb_id_table[68], NULL }, 4440 + { &dib0700_usb_id_table[ELGATO_EYETV_DIVERSITY], NULL }, 4529 4441 { NULL }, 4530 4442 }, 4531 4443 }, ··· 4562 4474 .num_device_descs = 10, 4563 4475 .devices = { 4564 4476 { "Terratec Cinergy HT USB XE", 4565 - { &dib0700_usb_id_table[27], NULL }, 4477 + { &dib0700_usb_id_table[TERRATEC_CINERGY_HT_USB_XE], NULL }, 4566 4478 { NULL }, 4567 4479 }, 4568 4480 { "Pinnacle Expresscard 320cx", 4569 - { &dib0700_usb_id_table[28], NULL }, 4481 + { &dib0700_usb_id_table[PINNACLE_EXPRESSCARD_320CX], NULL }, 4570 4482 { NULL }, 4571 4483 }, 4572 4484 { "Terratec Cinergy HT Express", 4573 - { &dib0700_usb_id_table[32], NULL }, 4485 + { &dib0700_usb_id_table[TERRATEC_CINERGY_HT_EXPRESS], NULL }, 4574 4486 { NULL }, 4575 4487 }, 4576 4488 { "Gigabyte U8000-RH", 4577 - { &dib0700_usb_id_table[37], NULL }, 4489 + { &dib0700_usb_id_table[GIGABYTE_U8000], NULL }, 4578 4490 { NULL }, 4579 4491 }, 4580 4492 { "YUAN High-Tech STK7700PH", 4581 - { &dib0700_usb_id_table[38], NULL }, 4493 + { &dib0700_usb_id_table[YUAN_STK7700PH], NULL }, 4582 4494 { NULL }, 4583 4495 }, 4584 4496 { "Asus My Cinema-U3000Hybrid", 4585 - { &dib0700_usb_id_table[39], NULL }, 4497 + { &dib0700_usb_id_table[ASUS_U3000H], NULL }, 4586 4498 { NULL }, 4587 4499 }, 4588 4500 { "YUAN High-Tech MC770", 4589 - { &dib0700_usb_id_table[48], NULL }, 4501 + { &dib0700_usb_id_table[YUAN_MC770], NULL }, 4590 4502 { NULL }, 4591 4503 }, 4592 4504 { "Leadtek WinFast DTV Dongle H", 4593 - { &dib0700_usb_id_table[51], NULL }, 4505 + { &dib0700_usb_id_table[LEADTEK_WINFAST_DTV_DONGLE_H], NULL }, 4594 4506 { NULL }, 4595 4507 }, 4596 4508 { "YUAN High-Tech STK7700D", 4597 - { &dib0700_usb_id_table[54], NULL }, 4509 + { &dib0700_usb_id_table[YUAN_STK7700D], NULL }, 4598 4510 { NULL }, 4599 4511 }, 4600 4512 { "Hama DVB=T Hybrid USB Stick", 4601 - { &dib0700_usb_id_table[85], NULL }, 4513 + { &dib0700_usb_id_table[HAMA_DVBT_HYBRID], NULL }, 4602 4514 { NULL }, 4603 4515 }, 4604 4516 }, ··· 4630 4542 .num_device_descs = 2, 4631 4543 .devices = { 4632 4544 { "Pinnacle PCTV HD Pro USB Stick", 4633 - { &dib0700_usb_id_table[40], NULL }, 4545 + { &dib0700_usb_id_table[PINNACLE_PCTV801E], NULL }, 4634 4546 { NULL }, 4635 4547 }, 4636 4548 { "Pinnacle PCTV HD USB Stick", 4637 - { &dib0700_usb_id_table[41], NULL }, 4549 + { &dib0700_usb_id_table[PINNACLE_PCTV801E_SE], NULL }, 4638 4550 { NULL }, 4639 4551 }, 4640 4552 }, ··· 4666 4578 .num_device_descs = 2, 4667 4579 .devices = { 4668 4580 { "Hauppauge ATSC MiniCard (B200)", 4669 - { &dib0700_usb_id_table[46], NULL }, 4581 + { &dib0700_usb_id_table[HAUPPAUGE_TIGER_ATSC], NULL }, 4670 4582 { NULL }, 4671 4583 }, 4672 4584 { "Hauppauge ATSC MiniCard (B210)", 4673 - { &dib0700_usb_id_table[47], NULL }, 4585 + { &dib0700_usb_id_table[HAUPPAUGE_TIGER_ATSC_B210], NULL }, 4674 4586 { NULL }, 4675 4587 }, 4676 4588 }, ··· 4696 4608 .num_device_descs = 4, 4697 4609 .devices = { 4698 4610 { "DiBcom STK7770P reference design", 4699 - { &dib0700_usb_id_table[59], NULL }, 4611 + { &dib0700_usb_id_table[DIBCOM_STK7770P], NULL }, 4700 4612 { NULL }, 4701 4613 }, 4702 4614 { "Terratec Cinergy T USB XXS (HD)/ T3", 4703 - { &dib0700_usb_id_table[33], 4704 - &dib0700_usb_id_table[52], 4705 - &dib0700_usb_id_table[60], NULL}, 4615 + { &dib0700_usb_id_table[TERRATEC_CINERGY_T_XXS], 4616 + &dib0700_usb_id_table[TERRATEC_T3], 4617 + &dib0700_usb_id_table[TERRATEC_CINERGY_T_XXS_2], NULL}, 4706 4618 { NULL }, 4707 4619 }, 4708 4620 { "TechniSat AirStar TeleStick 2", 4709 - { &dib0700_usb_id_table[74], NULL }, 4621 + { &dib0700_usb_id_table[TECHNISAT_AIRSTAR_TELESTICK_2], NULL }, 4710 4622 { NULL }, 4711 4623 }, 4712 4624 { "Medion CTX1921 DVB-T USB", 4713 - { &dib0700_usb_id_table[75], NULL }, 4625 + { &dib0700_usb_id_table[MEDION_CREATIX_CTX1921], NULL }, 4714 4626 { NULL }, 4715 4627 }, 4716 4628 }, ··· 4746 4658 .num_device_descs = 3, 4747 4659 .devices = { 4748 4660 { "DiBcom STK807xP reference design", 4749 - { &dib0700_usb_id_table[62], NULL }, 4661 + { &dib0700_usb_id_table[DIBCOM_STK807XP], NULL }, 4750 4662 { NULL }, 4751 4663 }, 4752 4664 { "Prolink Pixelview SBTVD", 4753 - { &dib0700_usb_id_table[63], NULL }, 4665 + { &dib0700_usb_id_table[PIXELVIEW_SBTVD], NULL }, 4754 4666 { NULL }, 4755 4667 }, 4756 4668 { "EvolutePC TVWay+", 4757 - { &dib0700_usb_id_table[64], NULL }, 4669 + { &dib0700_usb_id_table[EVOLUTEPC_TVWAY_PLUS], NULL }, 4758 4670 { NULL }, 4759 4671 }, 4760 4672 }, ··· 4803 4715 .num_device_descs = 1, 4804 4716 .devices = { 4805 4717 { "DiBcom STK807xPVR reference design", 4806 - { &dib0700_usb_id_table[61], NULL }, 4718 + { &dib0700_usb_id_table[DIBCOM_STK807XPVR], NULL }, 4807 4719 { NULL }, 4808 4720 }, 4809 4721 }, ··· 4840 4752 .num_device_descs = 1, 4841 4753 .devices = { 4842 4754 { "DiBcom STK8096GP reference design", 4843 - { &dib0700_usb_id_table[67], NULL }, 4755 + { &dib0700_usb_id_table[DIBCOM_STK8096GP], NULL }, 4844 4756 { NULL }, 4845 4757 }, 4846 4758 }, ··· 4877 4789 .num_device_descs = 1, 4878 4790 .devices = { 4879 4791 { "DiBcom STK9090M reference design", 4880 - { &dib0700_usb_id_table[69], NULL }, 4792 + { &dib0700_usb_id_table[DIBCOM_NIM9090M], NULL }, 4881 4793 { NULL }, 4882 4794 }, 4883 4795 }, ··· 4914 4826 .num_device_descs = 1, 4915 4827 .devices = { 4916 4828 { "DiBcom NIM8096MD reference design", 4917 - { &dib0700_usb_id_table[70], NULL }, 4829 + { &dib0700_usb_id_table[DIBCOM_NIM8096MD], NULL }, 4918 4830 { NULL }, 4919 4831 }, 4920 4832 }, ··· 4951 4863 .num_device_descs = 1, 4952 4864 .devices = { 4953 4865 { "DiBcom NIM9090MD reference design", 4954 - { &dib0700_usb_id_table[71], NULL }, 4866 + { &dib0700_usb_id_table[DIBCOM_NIM9090MD], NULL }, 4955 4867 { NULL }, 4956 4868 }, 4957 4869 }, ··· 4988 4900 .num_device_descs = 1, 4989 4901 .devices = { 4990 4902 { "DiBcom NIM7090 reference design", 4991 - { &dib0700_usb_id_table[72], NULL }, 4903 + { &dib0700_usb_id_table[DIBCOM_NIM7090], NULL }, 4992 4904 { NULL }, 4993 4905 }, 4994 4906 }, ··· 5039 4951 .num_device_descs = 1, 5040 4952 .devices = { 5041 4953 { "DiBcom TFE7090PVR reference design", 5042 - { &dib0700_usb_id_table[73], NULL }, 4954 + { &dib0700_usb_id_table[DIBCOM_TFE7090PVR], NULL }, 5043 4955 { NULL }, 5044 4956 }, 5045 4957 }, ··· 5071 4983 .num_device_descs = 2, 5072 4984 .devices = { 5073 4985 { "Pinnacle PCTV 340e HD Pro USB Stick", 5074 - { &dib0700_usb_id_table[76], NULL }, 4986 + { &dib0700_usb_id_table[PINNACLE_PCTV340E], NULL }, 5075 4987 { NULL }, 5076 4988 }, 5077 4989 { "Pinnacle PCTV Hybrid Stick Solo", 5078 - { &dib0700_usb_id_table[77], NULL }, 4990 + { &dib0700_usb_id_table[PINNACLE_PCTV340E_SE], NULL }, 5079 4991 { NULL }, 5080 4992 }, 5081 4993 }, ··· 5111 5023 .num_device_descs = 1, 5112 5024 .devices = { 5113 5025 { "DiBcom TFE7790P reference design", 5114 - { &dib0700_usb_id_table[78], NULL }, 5026 + { &dib0700_usb_id_table[DIBCOM_TFE7790P], NULL }, 5115 5027 { NULL }, 5116 5028 }, 5117 5029 }, ··· 5149 5061 .num_device_descs = 1, 5150 5062 .devices = { 5151 5063 { "DiBcom TFE8096P reference design", 5152 - { &dib0700_usb_id_table[79], NULL }, 5064 + { &dib0700_usb_id_table[DIBCOM_TFE8096P], NULL }, 5153 5065 { NULL }, 5154 5066 }, 5155 5067 }, ··· 5202 5114 .num_device_descs = 1, 5203 5115 .devices = { 5204 5116 { "DiBcom STK8096-PVR reference design", 5205 - { &dib0700_usb_id_table[83], 5206 - &dib0700_usb_id_table[84], NULL}, 5117 + { &dib0700_usb_id_table[PCTV_DIBCOM_STK8096PVR], 5118 + &dib0700_usb_id_table[DIBCOM_STK8096PVR], NULL}, 5207 5119 { NULL }, 5208 5120 }, 5209 5121 }, ··· 5233 5145 .num_device_descs = 1, 5234 5146 .devices = { 5235 5147 { "Microsoft Xbox One Digital TV Tuner", 5236 - { &dib0700_usb_id_table[86], NULL }, 5148 + { &dib0700_usb_id_table[MICROSOFT_XBOX_ONE_TUNER], NULL }, 5237 5149 { NULL }, 5238 5150 }, 5239 5151 },

+96 -75

drivers/media/usb/dvb-usb/dibusb-mb.c

··· 121 121 } 122 122 123 123 /* do not change the order of the ID table */ 124 - static struct usb_device_id dibusb_dib3000mb_table [] = { 125 - /* 00 */ { USB_DEVICE(USB_VID_WIDEVIEW, USB_PID_AVERMEDIA_DVBT_USB_COLD) }, 126 - /* 01 */ { USB_DEVICE(USB_VID_WIDEVIEW, USB_PID_AVERMEDIA_DVBT_USB_WARM) }, 127 - /* 02 */ { USB_DEVICE(USB_VID_COMPRO, USB_PID_COMPRO_DVBU2000_COLD) }, 128 - /* 03 */ { USB_DEVICE(USB_VID_COMPRO, USB_PID_COMPRO_DVBU2000_WARM) }, 129 - /* 04 */ { USB_DEVICE(USB_VID_COMPRO_UNK, USB_PID_COMPRO_DVBU2000_UNK_COLD) }, 130 - /* 05 */ { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_MOD3000_COLD) }, 131 - /* 06 */ { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_MOD3000_WARM) }, 132 - /* 07 */ { USB_DEVICE(USB_VID_EMPIA, USB_PID_KWORLD_VSTREAM_COLD) }, 133 - /* 08 */ { USB_DEVICE(USB_VID_EMPIA, USB_PID_KWORLD_VSTREAM_WARM) }, 134 - /* 09 */ { USB_DEVICE(USB_VID_GRANDTEC, USB_PID_GRANDTEC_DVBT_USB_COLD) }, 135 - /* 10 */ { USB_DEVICE(USB_VID_GRANDTEC, USB_PID_GRANDTEC_DVBT_USB_WARM) }, 136 - /* 11 */ { USB_DEVICE(USB_VID_GRANDTEC, USB_PID_DIBCOM_MOD3000_COLD) }, 137 - /* 12 */ { USB_DEVICE(USB_VID_GRANDTEC, USB_PID_DIBCOM_MOD3000_WARM) }, 138 - /* 13 */ { USB_DEVICE(USB_VID_HYPER_PALTEK, USB_PID_UNK_HYPER_PALTEK_COLD) }, 139 - /* 14 */ { USB_DEVICE(USB_VID_HYPER_PALTEK, USB_PID_UNK_HYPER_PALTEK_WARM) }, 140 - /* 15 */ { USB_DEVICE(USB_VID_VISIONPLUS, USB_PID_TWINHAN_VP7041_COLD) }, 141 - /* 16 */ { USB_DEVICE(USB_VID_VISIONPLUS, USB_PID_TWINHAN_VP7041_WARM) }, 142 - /* 17 */ { USB_DEVICE(USB_VID_TWINHAN, USB_PID_TWINHAN_VP7041_COLD) }, 143 - /* 18 */ { USB_DEVICE(USB_VID_TWINHAN, USB_PID_TWINHAN_VP7041_WARM) }, 144 - /* 19 */ { USB_DEVICE(USB_VID_ULTIMA_ELECTRONIC, USB_PID_ULTIMA_TVBOX_COLD) }, 145 - /* 20 */ { USB_DEVICE(USB_VID_ULTIMA_ELECTRONIC, USB_PID_ULTIMA_TVBOX_WARM) }, 146 - /* 21 */ { USB_DEVICE(USB_VID_ULTIMA_ELECTRONIC, USB_PID_ULTIMA_TVBOX_AN2235_COLD) }, 147 - /* 22 */ { USB_DEVICE(USB_VID_ULTIMA_ELECTRONIC, USB_PID_ULTIMA_TVBOX_AN2235_WARM) }, 148 - /* 23 */ { USB_DEVICE(USB_VID_ADSTECH, USB_PID_ADSTECH_USB2_COLD) }, 149 - 150 - /* device ID with default DIBUSB2_0-firmware and with the hacked firmware */ 151 - /* 24 */ { USB_DEVICE(USB_VID_ADSTECH, USB_PID_ADSTECH_USB2_WARM) }, 152 - /* 25 */ { USB_DEVICE(USB_VID_KYE, USB_PID_KYE_DVB_T_COLD) }, 153 - /* 26 */ { USB_DEVICE(USB_VID_KYE, USB_PID_KYE_DVB_T_WARM) }, 154 - 155 - /* 27 */ { USB_DEVICE(USB_VID_KWORLD, USB_PID_KWORLD_VSTREAM_COLD) }, 156 - 157 - /* 28 */ { USB_DEVICE(USB_VID_ULTIMA_ELECTRONIC, USB_PID_ULTIMA_TVBOX_USB2_COLD) }, 158 - /* 29 */ { USB_DEVICE(USB_VID_ULTIMA_ELECTRONIC, USB_PID_ULTIMA_TVBOX_USB2_WARM) }, 159 - 160 - /* 161 - * XXX: As Artec just 'forgot' to program the EEPROM on some Artec T1 devices 162 - * we don't catch these faulty IDs (namely 'Cypress FX1 USB controller') that 163 - * have been left on the device. If you don't have such a device but an Artec 164 - * device that's supposed to work with this driver but is not detected by it, 165 - * free to enable CONFIG_DVB_USB_DIBUSB_MB_FAULTY via your kernel config. 166 - */ 167 - 168 - #ifdef CONFIG_DVB_USB_DIBUSB_MB_FAULTY 169 - /* 30 */ { USB_DEVICE(USB_VID_ANCHOR, USB_PID_ULTIMA_TVBOX_ANCHOR_COLD) }, 170 - #endif 171 - 172 - { } /* Terminating entry */ 124 + enum { 125 + WIDEVIEW_DVBT_USB_COLD, 126 + WIDEVIEW_DVBT_USB_WARM, 127 + COMPRO_DVBU2000_COLD, 128 + COMPRO_DVBU2000_WARM, 129 + COMPRO_DVBU2000_UNK_COLD, 130 + DIBCOM_MOD3000_COLD, 131 + DIBCOM_MOD3000_WARM, 132 + EMPIA_VSTREAM_COLD, 133 + EMPIA_VSTREAM_WARM, 134 + GRANDTEC_DVBT_USB_COLD, 135 + GRANDTEC_DVBT_USB_WARM, 136 + GRANDTEC_MOD3000_COLD, 137 + GRANDTEC_MOD3000_WARM, 138 + UNK_HYPER_PALTEK_COLD, 139 + UNK_HYPER_PALTEK_WARM, 140 + VISIONPLUS_VP7041_COLD, 141 + VISIONPLUS_VP7041_WARM, 142 + TWINHAN_VP7041_COLD, 143 + TWINHAN_VP7041_WARM, 144 + ULTIMA_TVBOX_COLD, 145 + ULTIMA_TVBOX_WARM, 146 + ULTIMA_TVBOX_AN2235_COLD, 147 + ULTIMA_TVBOX_AN2235_WARM, 148 + ADSTECH_USB2_COLD, 149 + ADSTECH_USB2_WARM, 150 + KYE_DVB_T_COLD, 151 + KYE_DVB_T_WARM, 152 + KWORLD_VSTREAM_COLD, 153 + ULTIMA_TVBOX_USB2_COLD, 154 + ULTIMA_TVBOX_USB2_WARM, 155 + ULTIMA_TVBOX_ANCHOR_COLD, 173 156 }; 157 + 158 + static struct usb_device_id dibusb_dib3000mb_table[] = { 159 + DVB_USB_DEV(WIDEVIEW, WIDEVIEW_DVBT_USB_COLD), 160 + DVB_USB_DEV(WIDEVIEW, WIDEVIEW_DVBT_USB_WARM), 161 + DVB_USB_DEV(COMPRO, COMPRO_DVBU2000_COLD), 162 + DVB_USB_DEV(COMPRO, COMPRO_DVBU2000_WARM), 163 + DVB_USB_DEV(COMPRO_UNK, COMPRO_DVBU2000_UNK_COLD), 164 + DVB_USB_DEV(DIBCOM, DIBCOM_MOD3000_COLD), 165 + DVB_USB_DEV(DIBCOM, DIBCOM_MOD3000_WARM), 166 + DVB_USB_DEV(EMPIA, EMPIA_VSTREAM_COLD), 167 + DVB_USB_DEV(EMPIA, EMPIA_VSTREAM_WARM), 168 + DVB_USB_DEV(GRANDTEC, GRANDTEC_DVBT_USB_COLD), 169 + DVB_USB_DEV(GRANDTEC, GRANDTEC_DVBT_USB_WARM), 170 + DVB_USB_DEV(GRANDTEC, GRANDTEC_MOD3000_COLD), 171 + DVB_USB_DEV(GRANDTEC, GRANDTEC_MOD3000_WARM), 172 + DVB_USB_DEV(HYPER_PALTEK, UNK_HYPER_PALTEK_COLD), 173 + DVB_USB_DEV(HYPER_PALTEK, UNK_HYPER_PALTEK_WARM), 174 + DVB_USB_DEV(VISIONPLUS, VISIONPLUS_VP7041_COLD), 175 + DVB_USB_DEV(VISIONPLUS, VISIONPLUS_VP7041_WARM), 176 + DVB_USB_DEV(TWINHAN, TWINHAN_VP7041_COLD), 177 + DVB_USB_DEV(TWINHAN, TWINHAN_VP7041_WARM), 178 + DVB_USB_DEV(ULTIMA_ELECTRONIC, ULTIMA_TVBOX_COLD), 179 + DVB_USB_DEV(ULTIMA_ELECTRONIC, ULTIMA_TVBOX_WARM), 180 + DVB_USB_DEV(ULTIMA_ELECTRONIC, ULTIMA_TVBOX_AN2235_COLD), 181 + DVB_USB_DEV(ULTIMA_ELECTRONIC, ULTIMA_TVBOX_AN2235_WARM), 182 + DVB_USB_DEV(ADSTECH, ADSTECH_USB2_COLD), 183 + DVB_USB_DEV(ADSTECH, ADSTECH_USB2_WARM), 184 + DVB_USB_DEV(KYE, KYE_DVB_T_COLD), 185 + DVB_USB_DEV(KYE, KYE_DVB_T_WARM), 186 + DVB_USB_DEV(KWORLD, KWORLD_VSTREAM_COLD), 187 + DVB_USB_DEV(ULTIMA_ELECTRONIC, ULTIMA_TVBOX_USB2_COLD), 188 + DVB_USB_DEV(ULTIMA_ELECTRONIC, ULTIMA_TVBOX_USB2_WARM), 189 + #ifdef CONFIG_DVB_USB_DIBUSB_MB_FAULTY 190 + DVB_USB_DEV(ANCHOR, ULTIMA_TVBOX_ANCHOR_COLD), 191 + #endif 192 + { } 193 + }; 194 + 174 195 MODULE_DEVICE_TABLE (usb, dibusb_dib3000mb_table); 175 196 176 197 static struct dvb_usb_device_properties dibusb1_1_properties = { ··· 247 226 .num_device_descs = 9, 248 227 .devices = { 249 228 { "AVerMedia AverTV DVBT USB1.1", 250 - { &dibusb_dib3000mb_table[0], NULL }, 251 - { &dibusb_dib3000mb_table[1], NULL }, 229 + { &dibusb_dib3000mb_table[WIDEVIEW_DVBT_USB_COLD], NULL }, 230 + { &dibusb_dib3000mb_table[WIDEVIEW_DVBT_USB_WARM], NULL }, 252 231 }, 253 232 { "Compro Videomate DVB-U2000 - DVB-T USB1.1 (please confirm to linux-dvb)", 254 - { &dibusb_dib3000mb_table[2], &dibusb_dib3000mb_table[4], NULL}, 255 - { &dibusb_dib3000mb_table[3], NULL }, 233 + { &dibusb_dib3000mb_table[COMPRO_DVBU2000_COLD], &dibusb_dib3000mb_table[COMPRO_DVBU2000_UNK_COLD], NULL}, 234 + { &dibusb_dib3000mb_table[COMPRO_DVBU2000_WARM], NULL }, 256 235 }, 257 236 { "DiBcom USB1.1 DVB-T reference design (MOD3000)", 258 - { &dibusb_dib3000mb_table[5], NULL }, 259 - { &dibusb_dib3000mb_table[6], NULL }, 237 + { &dibusb_dib3000mb_table[DIBCOM_MOD3000_COLD], NULL }, 238 + { &dibusb_dib3000mb_table[DIBCOM_MOD3000_WARM], NULL }, 260 239 }, 261 240 { "KWorld V-Stream XPERT DTV - DVB-T USB1.1", 262 - { &dibusb_dib3000mb_table[7], NULL }, 263 - { &dibusb_dib3000mb_table[8], NULL }, 241 + { &dibusb_dib3000mb_table[EMPIA_VSTREAM_COLD], NULL }, 242 + { &dibusb_dib3000mb_table[EMPIA_VSTREAM_WARM], NULL }, 264 243 }, 265 244 { "Grandtec USB1.1 DVB-T", 266 - { &dibusb_dib3000mb_table[9], &dibusb_dib3000mb_table[11], NULL }, 267 - { &dibusb_dib3000mb_table[10], &dibusb_dib3000mb_table[12], NULL }, 245 + { &dibusb_dib3000mb_table[GRANDTEC_DVBT_USB_COLD], &dibusb_dib3000mb_table[GRANDTEC_MOD3000_COLD], NULL }, 246 + { &dibusb_dib3000mb_table[GRANDTEC_DVBT_USB_WARM], &dibusb_dib3000mb_table[GRANDTEC_MOD3000_WARM], NULL }, 268 247 }, 269 248 { "Unknown USB1.1 DVB-T device ???? please report the name to the author", 270 - { &dibusb_dib3000mb_table[13], NULL }, 271 - { &dibusb_dib3000mb_table[14], NULL }, 249 + { &dibusb_dib3000mb_table[UNK_HYPER_PALTEK_COLD], NULL }, 250 + { &dibusb_dib3000mb_table[UNK_HYPER_PALTEK_WARM], NULL }, 272 251 }, 273 252 { "TwinhanDTV USB-Ter USB1.1 / Magic Box I / HAMA USB1.1 DVB-T device", 274 - { &dibusb_dib3000mb_table[15], &dibusb_dib3000mb_table[17], NULL}, 275 - { &dibusb_dib3000mb_table[16], &dibusb_dib3000mb_table[18], NULL}, 253 + { &dibusb_dib3000mb_table[VISIONPLUS_VP7041_COLD], &dibusb_dib3000mb_table[TWINHAN_VP7041_COLD], NULL}, 254 + { &dibusb_dib3000mb_table[VISIONPLUS_VP7041_WARM], &dibusb_dib3000mb_table[TWINHAN_VP7041_WARM], NULL}, 276 255 }, 277 256 { "Artec T1 USB1.1 TVBOX with AN2135", 278 - { &dibusb_dib3000mb_table[19], NULL }, 279 - { &dibusb_dib3000mb_table[20], NULL }, 257 + { &dibusb_dib3000mb_table[ULTIMA_TVBOX_COLD], NULL }, 258 + { &dibusb_dib3000mb_table[ULTIMA_TVBOX_WARM], NULL }, 280 259 }, 281 260 { "VideoWalker DVB-T USB", 282 - { &dibusb_dib3000mb_table[25], NULL }, 283 - { &dibusb_dib3000mb_table[26], NULL }, 261 + { &dibusb_dib3000mb_table[KYE_DVB_T_COLD], NULL }, 262 + { &dibusb_dib3000mb_table[KYE_DVB_T_WARM], NULL }, 284 263 }, 285 264 } 286 265 }; ··· 340 319 #endif 341 320 .devices = { 342 321 { "Artec T1 USB1.1 TVBOX with AN2235", 343 - { &dibusb_dib3000mb_table[21], NULL }, 344 - { &dibusb_dib3000mb_table[22], NULL }, 322 + { &dibusb_dib3000mb_table[ULTIMA_TVBOX_AN2235_COLD], NULL }, 323 + { &dibusb_dib3000mb_table[ULTIMA_TVBOX_AN2235_WARM], NULL }, 345 324 }, 346 325 #ifdef CONFIG_DVB_USB_DIBUSB_MB_FAULTY 347 326 { "Artec T1 USB1.1 TVBOX with AN2235 (faulty USB IDs)", 348 - { &dibusb_dib3000mb_table[30], NULL }, 327 + { &dibusb_dib3000mb_table[ULTIMA_TVBOX_ANCHOR_COLD], NULL }, 349 328 { NULL }, 350 329 }, 351 330 { NULL }, ··· 405 384 .num_device_descs = 2, 406 385 .devices = { 407 386 { "KWorld/ADSTech Instant DVB-T USB2.0", 408 - { &dibusb_dib3000mb_table[23], NULL }, 409 - { &dibusb_dib3000mb_table[24], NULL }, 387 + { &dibusb_dib3000mb_table[ADSTECH_USB2_COLD], NULL }, 388 + { &dibusb_dib3000mb_table[ADSTECH_USB2_WARM], NULL }, 410 389 }, 411 390 { "KWorld Xpert DVB-T USB2.0", 412 - { &dibusb_dib3000mb_table[27], NULL }, 391 + { &dibusb_dib3000mb_table[KWORLD_VSTREAM_COLD], NULL }, 413 392 { NULL } 414 393 }, 415 394 { NULL }, ··· 467 446 .num_device_descs = 1, 468 447 .devices = { 469 448 { "Artec T1 USB2.0", 470 - { &dibusb_dib3000mb_table[28], NULL }, 471 - { &dibusb_dib3000mb_table[29], NULL }, 449 + { &dibusb_dib3000mb_table[ULTIMA_TVBOX_USB2_COLD], NULL }, 450 + { &dibusb_dib3000mb_table[ULTIMA_TVBOX_USB2_WARM], NULL }, 472 451 }, 473 452 { NULL }, 474 453 }

+54 -34

drivers/media/usb/dvb-usb/dibusb-mc.c

··· 24 24 } 25 25 26 26 /* do not change the order of the ID table */ 27 - static struct usb_device_id dibusb_dib3000mc_table [] = { 28 - /* 00 */ { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_MOD3001_COLD) }, 29 - /* 01 */ { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_MOD3001_WARM) }, 30 - /* 02 */ { USB_DEVICE(USB_VID_ULTIMA_ELECTRONIC, USB_PID_ULTIMA_TVBOX_USB2_COLD) }, 31 - /* 03 */ { USB_DEVICE(USB_VID_ULTIMA_ELECTRONIC, USB_PID_ULTIMA_TVBOX_USB2_WARM) }, // ( ? ) 32 - /* 04 */ { USB_DEVICE(USB_VID_LITEON, USB_PID_LITEON_DVB_T_COLD) }, 33 - /* 05 */ { USB_DEVICE(USB_VID_LITEON, USB_PID_LITEON_DVB_T_WARM) }, 34 - /* 06 */ { USB_DEVICE(USB_VID_EMPIA, USB_PID_DIGIVOX_MINI_SL_COLD) }, 35 - /* 07 */ { USB_DEVICE(USB_VID_EMPIA, USB_PID_DIGIVOX_MINI_SL_WARM) }, 36 - /* 08 */ { USB_DEVICE(USB_VID_GRANDTEC, USB_PID_GRANDTEC_DVBT_USB2_COLD) }, 37 - /* 09 */ { USB_DEVICE(USB_VID_GRANDTEC, USB_PID_GRANDTEC_DVBT_USB2_WARM) }, 38 - /* 10 */ { USB_DEVICE(USB_VID_ULTIMA_ELECTRONIC, USB_PID_ARTEC_T14_COLD) }, 39 - /* 11 */ { USB_DEVICE(USB_VID_ULTIMA_ELECTRONIC, USB_PID_ARTEC_T14_WARM) }, 40 - /* 12 */ { USB_DEVICE(USB_VID_LEADTEK, USB_PID_WINFAST_DTV_DONGLE_COLD) }, 41 - /* 13 */ { USB_DEVICE(USB_VID_LEADTEK, USB_PID_WINFAST_DTV_DONGLE_WARM) }, 42 - /* 14 */ { USB_DEVICE(USB_VID_HUMAX_COEX, USB_PID_DVB_T_USB_STICK_HIGH_SPEED_COLD) }, 43 - /* 15 */ { USB_DEVICE(USB_VID_HUMAX_COEX, USB_PID_DVB_T_USB_STICK_HIGH_SPEED_WARM) }, 44 - { } /* Terminating entry */ 27 + enum { 28 + DIBCOM_MOD3001_COLD, 29 + DIBCOM_MOD3001_WARM, 30 + ULTIMA_TVBOX_USB2_COLD, 31 + ULTIMA_TVBOX_USB2_WARM, 32 + LITEON_DVB_T_COLD, 33 + LITEON_DVB_T_WARM, 34 + EMPIA_DIGIVOX_MINI_SL_COLD, 35 + EMPIA_DIGIVOX_MINI_SL_WARM, 36 + GRANDTEC_DVBT_USB2_COLD, 37 + GRANDTEC_DVBT_USB2_WARM, 38 + ULTIMA_ARTEC_T14_COLD, 39 + ULTIMA_ARTEC_T14_WARM, 40 + LEADTEK_WINFAST_DTV_DONGLE_COLD, 41 + LEADTEK_WINFAST_DTV_DONGLE_WARM, 42 + HUMAX_DVB_T_STICK_HIGH_SPEED_COLD, 43 + HUMAX_DVB_T_STICK_HIGH_SPEED_WARM, 45 44 }; 45 + 46 + static struct usb_device_id dibusb_dib3000mc_table[] = { 47 + DVB_USB_DEV(DIBCOM, DIBCOM_MOD3001_COLD), 48 + DVB_USB_DEV(DIBCOM, DIBCOM_MOD3001_WARM), 49 + DVB_USB_DEV(ULTIMA_ELECTRONIC, ULTIMA_TVBOX_USB2_COLD), 50 + DVB_USB_DEV(ULTIMA_ELECTRONIC, ULTIMA_TVBOX_USB2_WARM), 51 + DVB_USB_DEV(LITEON, LITEON_DVB_T_COLD), 52 + DVB_USB_DEV(LITEON, LITEON_DVB_T_WARM), 53 + DVB_USB_DEV(EMPIA, EMPIA_DIGIVOX_MINI_SL_COLD), 54 + DVB_USB_DEV(EMPIA, EMPIA_DIGIVOX_MINI_SL_WARM), 55 + DVB_USB_DEV(GRANDTEC, GRANDTEC_DVBT_USB2_COLD), 56 + DVB_USB_DEV(GRANDTEC, GRANDTEC_DVBT_USB2_WARM), 57 + DVB_USB_DEV(ULTIMA_ELECTRONIC, ULTIMA_ARTEC_T14_COLD), 58 + DVB_USB_DEV(ULTIMA_ELECTRONIC, ULTIMA_ARTEC_T14_WARM), 59 + DVB_USB_DEV(LEADTEK, LEADTEK_WINFAST_DTV_DONGLE_COLD), 60 + DVB_USB_DEV(LEADTEK, LEADTEK_WINFAST_DTV_DONGLE_WARM), 61 + DVB_USB_DEV(HUMAX_COEX, HUMAX_DVB_T_STICK_HIGH_SPEED_COLD), 62 + DVB_USB_DEV(HUMAX_COEX, HUMAX_DVB_T_STICK_HIGH_SPEED_WARM), 63 + { } 64 + }; 65 + 46 66 MODULE_DEVICE_TABLE (usb, dibusb_dib3000mc_table); 47 67 48 68 static struct dvb_usb_device_properties dibusb_mc_properties = { ··· 115 95 .num_device_descs = 8, 116 96 .devices = { 117 97 { "DiBcom USB2.0 DVB-T reference design (MOD3000P)", 118 - { &dibusb_dib3000mc_table[0], NULL }, 119 - { &dibusb_dib3000mc_table[1], NULL }, 98 + { &dibusb_dib3000mc_table[DIBCOM_MOD3001_COLD], NULL }, 99 + { &dibusb_dib3000mc_table[DIBCOM_MOD3001_WARM], NULL }, 120 100 }, 121 101 { "Artec T1 USB2.0 TVBOX (please check the warm ID)", 122 - { &dibusb_dib3000mc_table[2], NULL }, 123 - { &dibusb_dib3000mc_table[3], NULL }, 102 + { &dibusb_dib3000mc_table[ULTIMA_TVBOX_USB2_COLD], NULL }, 103 + { &dibusb_dib3000mc_table[ULTIMA_TVBOX_USB2_WARM], NULL }, 124 104 }, 125 105 { "LITE-ON USB2.0 DVB-T Tuner", 126 106 /* Also rebranded as Intuix S800, Toshiba */ 127 - { &dibusb_dib3000mc_table[4], NULL }, 128 - { &dibusb_dib3000mc_table[5], NULL }, 107 + { &dibusb_dib3000mc_table[LITEON_DVB_T_COLD], NULL }, 108 + { &dibusb_dib3000mc_table[LITEON_DVB_T_WARM], NULL }, 129 109 }, 130 110 { "MSI Digivox Mini SL", 131 - { &dibusb_dib3000mc_table[6], NULL }, 132 - { &dibusb_dib3000mc_table[7], NULL }, 111 + { &dibusb_dib3000mc_table[EMPIA_DIGIVOX_MINI_SL_COLD], NULL }, 112 + { &dibusb_dib3000mc_table[EMPIA_DIGIVOX_MINI_SL_WARM], NULL }, 133 113 }, 134 114 { "GRAND - USB2.0 DVB-T adapter", 135 - { &dibusb_dib3000mc_table[8], NULL }, 136 - { &dibusb_dib3000mc_table[9], NULL }, 115 + { &dibusb_dib3000mc_table[GRANDTEC_DVBT_USB2_COLD], NULL }, 116 + { &dibusb_dib3000mc_table[GRANDTEC_DVBT_USB2_WARM], NULL }, 137 117 }, 138 118 { "Artec T14 - USB2.0 DVB-T", 139 - { &dibusb_dib3000mc_table[10], NULL }, 140 - { &dibusb_dib3000mc_table[11], NULL }, 119 + { &dibusb_dib3000mc_table[ULTIMA_ARTEC_T14_COLD], NULL }, 120 + { &dibusb_dib3000mc_table[ULTIMA_ARTEC_T14_WARM], NULL }, 141 121 }, 142 122 { "Leadtek - USB2.0 Winfast DTV dongle", 143 - { &dibusb_dib3000mc_table[12], NULL }, 144 - { &dibusb_dib3000mc_table[13], NULL }, 123 + { &dibusb_dib3000mc_table[LEADTEK_WINFAST_DTV_DONGLE_COLD], NULL }, 124 + { &dibusb_dib3000mc_table[LEADTEK_WINFAST_DTV_DONGLE_WARM], NULL }, 145 125 }, 146 126 { "Humax/Coex DVB-T USB Stick 2.0 High Speed", 147 - { &dibusb_dib3000mc_table[14], NULL }, 148 - { &dibusb_dib3000mc_table[15], NULL }, 127 + { &dibusb_dib3000mc_table[HUMAX_DVB_T_STICK_HIGH_SPEED_COLD], NULL }, 128 + { &dibusb_dib3000mc_table[HUMAX_DVB_T_STICK_HIGH_SPEED_WARM], NULL }, 149 129 }, 150 130 { NULL }, 151 131 }

+9 -4

drivers/media/usb/dvb-usb/digitv.c

··· 291 291 return ret; 292 292 } 293 293 294 - static struct usb_device_id digitv_table [] = { 295 - { USB_DEVICE(USB_VID_ANCHOR, USB_PID_NEBULA_DIGITV) }, 296 - { } /* Terminating entry */ 294 + enum { 295 + ANCHOR_NEBULA_DIGITV, 297 296 }; 297 + 298 + static struct usb_device_id digitv_table[] = { 299 + DVB_USB_DEV(ANCHOR, ANCHOR_NEBULA_DIGITV), 300 + { } 301 + }; 302 + 298 303 MODULE_DEVICE_TABLE (usb, digitv_table); 299 304 300 305 static struct dvb_usb_device_properties digitv_properties = { ··· 348 343 .num_device_descs = 1, 349 344 .devices = { 350 345 { "Nebula Electronics uDigiTV DVB-T USB2.0)", 351 - { &digitv_table[0], NULL }, 346 + { &digitv_table[ANCHOR_NEBULA_DIGITV], NULL }, 352 347 { NULL }, 353 348 }, 354 349 { NULL },

+35 -21

drivers/media/usb/dvb-usb/dtt200u.c

··· 158 158 return -ENODEV; 159 159 } 160 160 161 - static struct usb_device_id dtt200u_usb_table [] = { 162 - { USB_DEVICE(USB_VID_WIDEVIEW, USB_PID_DTT200U_COLD) }, 163 - { USB_DEVICE(USB_VID_WIDEVIEW, USB_PID_DTT200U_WARM) }, 164 - { USB_DEVICE(USB_VID_WIDEVIEW, USB_PID_WT220U_COLD) }, 165 - { USB_DEVICE(USB_VID_WIDEVIEW, USB_PID_WT220U_WARM) }, 166 - { USB_DEVICE(USB_VID_WIDEVIEW, USB_PID_WT220U_ZL0353_COLD) }, 167 - { USB_DEVICE(USB_VID_WIDEVIEW, USB_PID_WT220U_ZL0353_WARM) }, 168 - { USB_DEVICE(USB_VID_WIDEVIEW, USB_PID_WT220U_FC_COLD) }, 169 - { USB_DEVICE(USB_VID_WIDEVIEW, USB_PID_WT220U_FC_WARM) }, 170 - { USB_DEVICE(USB_VID_WIDEVIEW, USB_PID_WT220U_ZAP250_COLD) }, 171 - { USB_DEVICE(USB_VID_MIGLIA, USB_PID_WT220U_ZAP250_COLD) }, 172 - { 0 }, 161 + enum { 162 + WIDEVIEW_DTT200U_COLD, 163 + WIDEVIEW_DTT200U_WARM, 164 + WIDEVIEW_WT220U_COLD, 165 + WIDEVIEW_WT220U_WARM, 166 + WIDEVIEW_WT220U_ZL0353_COLD, 167 + WIDEVIEW_WT220U_ZL0353_WARM, 168 + WIDEVIEW_WT220U_FC_COLD, 169 + WIDEVIEW_WT220U_FC_WARM, 170 + WIDEVIEW_WT220U_ZAP250_COLD, 171 + MIGLIA_WT220U_ZAP250_COLD, 173 172 }; 173 + 174 + static struct usb_device_id dtt200u_usb_table[] = { 175 + DVB_USB_DEV(WIDEVIEW, WIDEVIEW_DTT200U_COLD), 176 + DVB_USB_DEV(WIDEVIEW, WIDEVIEW_DTT200U_WARM), 177 + DVB_USB_DEV(WIDEVIEW, WIDEVIEW_WT220U_COLD), 178 + DVB_USB_DEV(WIDEVIEW, WIDEVIEW_WT220U_WARM), 179 + DVB_USB_DEV(WIDEVIEW, WIDEVIEW_WT220U_ZL0353_COLD), 180 + DVB_USB_DEV(WIDEVIEW, WIDEVIEW_WT220U_ZL0353_WARM), 181 + DVB_USB_DEV(WIDEVIEW, WIDEVIEW_WT220U_FC_COLD), 182 + DVB_USB_DEV(WIDEVIEW, WIDEVIEW_WT220U_FC_WARM), 183 + DVB_USB_DEV(WIDEVIEW, WIDEVIEW_WT220U_ZAP250_COLD), 184 + DVB_USB_DEV(MIGLIA, MIGLIA_WT220U_ZAP250_COLD), 185 + { } 186 + }; 187 + 174 188 MODULE_DEVICE_TABLE(usb, dtt200u_usb_table); 175 189 176 190 static struct dvb_usb_device_properties dtt200u_properties = { ··· 232 218 .num_device_descs = 1, 233 219 .devices = { 234 220 { .name = "WideView/Yuan/Yakumo/Hama/Typhoon DVB-T USB2.0 (WT-200U)", 235 - .cold_ids = { &dtt200u_usb_table[0], NULL }, 236 - .warm_ids = { &dtt200u_usb_table[1], NULL }, 221 + .cold_ids = { &dtt200u_usb_table[WIDEVIEW_DTT200U_COLD], NULL }, 222 + .warm_ids = { &dtt200u_usb_table[WIDEVIEW_DTT200U_WARM], NULL }, 237 223 }, 238 224 { NULL }, 239 225 } ··· 284 270 .num_device_descs = 1, 285 271 .devices = { 286 272 { .name = "WideView WT-220U PenType Receiver (Typhoon/Freecom)", 287 - .cold_ids = { &dtt200u_usb_table[2], &dtt200u_usb_table[8], NULL }, 288 - .warm_ids = { &dtt200u_usb_table[3], NULL }, 273 + .cold_ids = { &dtt200u_usb_table[WIDEVIEW_WT220U_COLD], &dtt200u_usb_table[WIDEVIEW_WT220U_ZAP250_COLD], NULL }, 274 + .warm_ids = { &dtt200u_usb_table[WIDEVIEW_WT220U_WARM], NULL }, 289 275 }, 290 276 { NULL }, 291 277 } ··· 336 322 .num_device_descs = 1, 337 323 .devices = { 338 324 { .name = "WideView WT-220U PenType Receiver (Typhoon/Freecom)", 339 - .cold_ids = { &dtt200u_usb_table[6], NULL }, 340 - .warm_ids = { &dtt200u_usb_table[7], NULL }, 325 + .cold_ids = { &dtt200u_usb_table[WIDEVIEW_WT220U_FC_COLD], NULL }, 326 + .warm_ids = { &dtt200u_usb_table[WIDEVIEW_WT220U_FC_WARM], NULL }, 341 327 }, 342 328 { NULL }, 343 329 } ··· 388 374 .num_device_descs = 1, 389 375 .devices = { 390 376 { .name = "WideView WT-220U PenType Receiver (based on ZL353)", 391 - .cold_ids = { &dtt200u_usb_table[4], NULL }, 392 - .warm_ids = { &dtt200u_usb_table[5], NULL }, 377 + .cold_ids = { &dtt200u_usb_table[WIDEVIEW_WT220U_ZL0353_COLD], NULL }, 378 + .warm_ids = { &dtt200u_usb_table[WIDEVIEW_WT220U_ZL0353_WARM], NULL }, 393 379 }, 394 380 { NULL }, 395 381 } ··· 407 393 .num_device_descs = 1, 408 394 .devices = { 409 395 { .name = "WideView WT-220U PenType Receiver (Miglia)", 410 - .cold_ids = { &dtt200u_usb_table[9], NULL }, 396 + .cold_ids = { &dtt200u_usb_table[MIGLIA_WT220U_ZAP250_COLD], NULL }, 411 397 /* This device turns into WT220U_ZL0353_WARM when fw 412 398 has been uploaded */ 413 399 .warm_ids = { NULL },

+9 -4

drivers/media/usb/dvb-usb/dtv5100.c

··· 162 162 return 0; 163 163 } 164 164 165 - static struct usb_device_id dtv5100_table[] = { 166 - { USB_DEVICE(0x06be, 0xa232) }, 167 - { } /* Terminating entry */ 165 + enum { 166 + AME_DTV5100, 168 167 }; 168 + 169 + static struct usb_device_id dtv5100_table[] = { 170 + DVB_USB_DEV(AME, AME_DTV5100), 171 + { } 172 + }; 173 + 169 174 MODULE_DEVICE_TABLE(usb, dtv5100_table); 170 175 171 176 static struct dvb_usb_device_properties dtv5100_properties = { ··· 206 201 { 207 202 .name = "AME DTV-5100 USB2.0 DVB-T", 208 203 .cold_ids = { NULL }, 209 - .warm_ids = { &dtv5100_table[0], NULL }, 204 + .warm_ids = { &dtv5100_table[AME_DTV5100], NULL }, 210 205 }, 211 206 } 212 207 };

+39 -45

drivers/media/usb/dvb-usb/dw2102.c

··· 1771 1771 PROF_7500, 1772 1772 GENIATECH_SU3000, 1773 1773 HAUPPAUGE_MAX_S2, 1774 - TERRATEC_CINERGY_S2, 1774 + TERRATEC_CINERGY_S2_R1, 1775 1775 TEVII_S480_1, 1776 1776 TEVII_S480_2, 1777 - X3M_SPC1400HD, 1777 + GENIATECH_X3M_SPC1400HD, 1778 1778 TEVII_S421, 1779 1779 TEVII_S632, 1780 1780 TERRATEC_CINERGY_S2_R2, ··· 1784 1784 TERRATEC_CINERGY_S2_2, 1785 1785 GOTVIEW_SAT_HD, 1786 1786 GENIATECH_T220, 1787 - TECHNOTREND_S2_4600, 1787 + TECHNOTREND_CONNECT_S2_4600, 1788 1788 TEVII_S482_1, 1789 1789 TEVII_S482_2, 1790 1790 TERRATEC_CINERGY_S2_BOX, ··· 1792 1792 }; 1793 1793 1794 1794 static struct usb_device_id dw2102_table[] = { 1795 - [CYPRESS_DW2102] = {USB_DEVICE(USB_VID_CYPRESS, USB_PID_DW2102)}, 1796 - [CYPRESS_DW2101] = {USB_DEVICE(USB_VID_CYPRESS, 0x2101)}, 1797 - [CYPRESS_DW2104] = {USB_DEVICE(USB_VID_CYPRESS, USB_PID_DW2104)}, 1798 - [TEVII_S650] = {USB_DEVICE(0x9022, USB_PID_TEVII_S650)}, 1799 - [TERRATEC_CINERGY_S] = {USB_DEVICE(USB_VID_TERRATEC, USB_PID_TERRATEC_CINERGY_S)}, 1800 - [CYPRESS_DW3101] = {USB_DEVICE(USB_VID_CYPRESS, USB_PID_DW3101)}, 1801 - [TEVII_S630] = {USB_DEVICE(0x9022, USB_PID_TEVII_S630)}, 1802 - [PROF_1100] = {USB_DEVICE(0x3011, USB_PID_PROF_1100)}, 1803 - [TEVII_S660] = {USB_DEVICE(0x9022, USB_PID_TEVII_S660)}, 1804 - [PROF_7500] = {USB_DEVICE(0x3034, 0x7500)}, 1805 - [GENIATECH_SU3000] = {USB_DEVICE(0x1f4d, 0x3000)}, 1806 - [HAUPPAUGE_MAX_S2] = {USB_DEVICE(0x2040, 0xd900)}, 1807 - [TERRATEC_CINERGY_S2] = {USB_DEVICE(USB_VID_TERRATEC, USB_PID_TERRATEC_CINERGY_S2_R1)}, 1808 - [TEVII_S480_1] = {USB_DEVICE(0x9022, USB_PID_TEVII_S480_1)}, 1809 - [TEVII_S480_2] = {USB_DEVICE(0x9022, USB_PID_TEVII_S480_2)}, 1810 - [X3M_SPC1400HD] = {USB_DEVICE(0x1f4d, 0x3100)}, 1811 - [TEVII_S421] = {USB_DEVICE(0x9022, USB_PID_TEVII_S421)}, 1812 - [TEVII_S632] = {USB_DEVICE(0x9022, USB_PID_TEVII_S632)}, 1813 - [TERRATEC_CINERGY_S2_R2] = {USB_DEVICE(USB_VID_TERRATEC, 1814 - USB_PID_TERRATEC_CINERGY_S2_R2)}, 1815 - [TERRATEC_CINERGY_S2_R3] = {USB_DEVICE(USB_VID_TERRATEC, 1816 - USB_PID_TERRATEC_CINERGY_S2_R3)}, 1817 - [TERRATEC_CINERGY_S2_R4] = {USB_DEVICE(USB_VID_TERRATEC, 1818 - USB_PID_TERRATEC_CINERGY_S2_R4)}, 1819 - [TERRATEC_CINERGY_S2_1] = {USB_DEVICE(USB_VID_TERRATEC_2, 1820 - USB_PID_TERRATEC_CINERGY_S2_1)}, 1821 - [TERRATEC_CINERGY_S2_2] = {USB_DEVICE(USB_VID_TERRATEC_2, 1822 - USB_PID_TERRATEC_CINERGY_S2_2)}, 1823 - [GOTVIEW_SAT_HD] = {USB_DEVICE(0x1FE1, USB_PID_GOTVIEW_SAT_HD)}, 1824 - [GENIATECH_T220] = {USB_DEVICE(0x1f4d, 0xD220)}, 1825 - [TECHNOTREND_S2_4600] = {USB_DEVICE(USB_VID_TECHNOTREND, 1826 - USB_PID_TECHNOTREND_CONNECT_S2_4600)}, 1827 - [TEVII_S482_1] = {USB_DEVICE(0x9022, 0xd483)}, 1828 - [TEVII_S482_2] = {USB_DEVICE(0x9022, 0xd484)}, 1829 - [TERRATEC_CINERGY_S2_BOX] = {USB_DEVICE(USB_VID_TERRATEC, 0x0105)}, 1830 - [TEVII_S662] = {USB_DEVICE(0x9022, USB_PID_TEVII_S662)}, 1795 + DVB_USB_DEV(CYPRESS, CYPRESS_DW2102), 1796 + DVB_USB_DEV(CYPRESS, CYPRESS_DW2101), 1797 + DVB_USB_DEV(CYPRESS, CYPRESS_DW2104), 1798 + DVB_USB_DEV(TEVII, TEVII_S650), 1799 + DVB_USB_DEV(TERRATEC, TERRATEC_CINERGY_S), 1800 + DVB_USB_DEV(CYPRESS, CYPRESS_DW3101), 1801 + DVB_USB_DEV(TEVII, TEVII_S630), 1802 + DVB_USB_DEV(PROF_1, PROF_1100), 1803 + DVB_USB_DEV(TEVII, TEVII_S660), 1804 + DVB_USB_DEV(PROF_2, PROF_7500), 1805 + DVB_USB_DEV(GTEK, GENIATECH_SU3000), 1806 + DVB_USB_DEV(HAUPPAUGE, HAUPPAUGE_MAX_S2), 1807 + DVB_USB_DEV(TERRATEC, TERRATEC_CINERGY_S2_R1), 1808 + DVB_USB_DEV(TEVII, TEVII_S480_1), 1809 + DVB_USB_DEV(TEVII, TEVII_S480_2), 1810 + DVB_USB_DEV(GTEK, GENIATECH_X3M_SPC1400HD), 1811 + DVB_USB_DEV(TEVII, TEVII_S421), 1812 + DVB_USB_DEV(TEVII, TEVII_S632), 1813 + DVB_USB_DEV(TERRATEC, TERRATEC_CINERGY_S2_R2), 1814 + DVB_USB_DEV(TERRATEC, TERRATEC_CINERGY_S2_R3), 1815 + DVB_USB_DEV(TERRATEC, TERRATEC_CINERGY_S2_R4), 1816 + DVB_USB_DEV(TERRATEC_2, TERRATEC_CINERGY_S2_1), 1817 + DVB_USB_DEV(TERRATEC_2, TERRATEC_CINERGY_S2_2), 1818 + DVB_USB_DEV(GOTVIEW, GOTVIEW_SAT_HD), 1819 + DVB_USB_DEV(GTEK, GENIATECH_T220), 1820 + DVB_USB_DEV(TECHNOTREND, TECHNOTREND_CONNECT_S2_4600), 1821 + DVB_USB_DEV(TEVII, TEVII_S482_1), 1822 + DVB_USB_DEV(TEVII, TEVII_S482_2), 1823 + DVB_USB_DEV(TERRATEC, TERRATEC_CINERGY_S2_BOX), 1824 + DVB_USB_DEV(TEVII, TEVII_S662), 1831 1825 { } 1832 1826 }; 1833 1827 ··· 1883 1889 case USB_PID_TEVII_S650: 1884 1890 dw2104_properties.rc.core.rc_codes = RC_MAP_TEVII_NEC; 1885 1891 fallthrough; 1886 - case USB_PID_DW2104: 1892 + case USB_PID_CYPRESS_DW2104: 1887 1893 reset = 1; 1888 1894 dw210x_op_rw(dev, 0xc4, 0x0000, 0, &reset, 1, 1889 1895 DW210X_WRITE_MSG); 1890 1896 fallthrough; 1891 - case USB_PID_DW3101: 1897 + case USB_PID_CYPRESS_DW3101: 1892 1898 reset = 0; 1893 1899 dw210x_op_rw(dev, 0xbf, 0x0040, 0, &reset, 0, 1894 1900 DW210X_WRITE_MSG); 1895 1901 break; 1896 1902 case USB_PID_TERRATEC_CINERGY_S: 1897 - case USB_PID_DW2102: 1903 + case USB_PID_CYPRESS_DW2102: 1898 1904 dw210x_op_rw(dev, 0xbf, 0x0040, 0, &reset, 0, 1899 1905 DW210X_WRITE_MSG); 1900 1906 dw210x_op_rw(dev, 0xb9, 0x0000, 0, &reset16[0], 2, ··· 2344 2350 { NULL }, 2345 2351 }, 2346 2352 { "Terratec Cinergy S2 USB HD", 2347 - { &dw2102_table[TERRATEC_CINERGY_S2], NULL }, 2353 + { &dw2102_table[TERRATEC_CINERGY_S2_R1], NULL }, 2348 2354 { NULL }, 2349 2355 }, 2350 2356 { "X3M TV SPC1400HD PCI", 2351 - { &dw2102_table[X3M_SPC1400HD], NULL }, 2357 + { &dw2102_table[GENIATECH_X3M_SPC1400HD], NULL }, 2352 2358 { NULL }, 2353 2359 }, 2354 2360 { "Terratec Cinergy S2 USB HD Rev.2", ··· 2519 2525 .num_device_descs = 5, 2520 2526 .devices = { 2521 2527 { "TechnoTrend TT-connect S2-4600", 2522 - { &dw2102_table[TECHNOTREND_S2_4600], NULL }, 2528 + { &dw2102_table[TECHNOTREND_CONNECT_S2_4600], NULL }, 2523 2529 { NULL }, 2524 2530 }, 2525 2531 { "TeVii S482 (tuner 1)",

+23 -13

drivers/media/usb/dvb-usb/gp8psk.c

··· 310 310 return ret; 311 311 } 312 312 313 - static struct usb_device_id gp8psk_usb_table [] = { 314 - { USB_DEVICE(USB_VID_GENPIX, USB_PID_GENPIX_8PSK_REV_1_COLD) }, 315 - { USB_DEVICE(USB_VID_GENPIX, USB_PID_GENPIX_8PSK_REV_1_WARM) }, 316 - { USB_DEVICE(USB_VID_GENPIX, USB_PID_GENPIX_8PSK_REV_2) }, 317 - { USB_DEVICE(USB_VID_GENPIX, USB_PID_GENPIX_SKYWALKER_1) }, 318 - { USB_DEVICE(USB_VID_GENPIX, USB_PID_GENPIX_SKYWALKER_2) }, 319 - /* { USB_DEVICE(USB_VID_GENPIX, USB_PID_GENPIX_SKYWALKER_CW3K) }, */ 320 - { 0 }, 313 + enum { 314 + GENPIX_8PSK_REV_1_COLD, 315 + GENPIX_8PSK_REV_1_WARM, 316 + GENPIX_8PSK_REV_2, 317 + GENPIX_SKYWALKER_1, 318 + GENPIX_SKYWALKER_2, 319 + GENPIX_SKYWALKER_CW3K, 321 320 }; 321 + 322 + static struct usb_device_id gp8psk_usb_table[] = { 323 + DVB_USB_DEV(GENPIX, GENPIX_8PSK_REV_1_COLD), 324 + DVB_USB_DEV(GENPIX, GENPIX_8PSK_REV_1_WARM), 325 + DVB_USB_DEV(GENPIX, GENPIX_8PSK_REV_2), 326 + DVB_USB_DEV(GENPIX, GENPIX_SKYWALKER_1), 327 + DVB_USB_DEV(GENPIX, GENPIX_SKYWALKER_2), 328 + DVB_USB_DEV(GENPIX, GENPIX_SKYWALKER_CW3K), 329 + { } 330 + }; 331 + 322 332 MODULE_DEVICE_TABLE(usb, gp8psk_usb_table); 323 333 324 334 static struct dvb_usb_device_properties gp8psk_properties = { ··· 365 355 .num_device_descs = 4, 366 356 .devices = { 367 357 { .name = "Genpix 8PSK-to-USB2 Rev.1 DVB-S receiver", 368 - .cold_ids = { &gp8psk_usb_table[0], NULL }, 369 - .warm_ids = { &gp8psk_usb_table[1], NULL }, 358 + .cold_ids = { &gp8psk_usb_table[GENPIX_8PSK_REV_1_COLD], NULL }, 359 + .warm_ids = { &gp8psk_usb_table[GENPIX_8PSK_REV_1_WARM], NULL }, 370 360 }, 371 361 { .name = "Genpix 8PSK-to-USB2 Rev.2 DVB-S receiver", 372 362 .cold_ids = { NULL }, 373 - .warm_ids = { &gp8psk_usb_table[2], NULL }, 363 + .warm_ids = { &gp8psk_usb_table[GENPIX_8PSK_REV_2], NULL }, 374 364 }, 375 365 { .name = "Genpix SkyWalker-1 DVB-S receiver", 376 366 .cold_ids = { NULL }, 377 - .warm_ids = { &gp8psk_usb_table[3], NULL }, 367 + .warm_ids = { &gp8psk_usb_table[GENPIX_SKYWALKER_1], NULL }, 378 368 }, 379 369 { .name = "Genpix SkyWalker-2 DVB-S receiver", 380 370 .cold_ids = { NULL }, 381 - .warm_ids = { &gp8psk_usb_table[4], NULL }, 371 + .warm_ids = { &gp8psk_usb_table[GENPIX_SKYWALKER_2], NULL }, 382 372 }, 383 373 { NULL }, 384 374 }

+30 -21

drivers/media/usb/dvb-usb/m920x.c

··· 897 897 return ret; 898 898 } 899 899 900 - static struct usb_device_id m920x_table [] = { 901 - { USB_DEVICE(USB_VID_MSI, USB_PID_MSI_MEGASKY580) }, 902 - { USB_DEVICE(USB_VID_ANUBIS_ELECTRONIC, 903 - USB_PID_MSI_DIGI_VOX_MINI_II) }, 904 - { USB_DEVICE(USB_VID_ANUBIS_ELECTRONIC, 905 - USB_PID_LIFEVIEW_TV_WALKER_TWIN_COLD) }, 906 - { USB_DEVICE(USB_VID_ANUBIS_ELECTRONIC, 907 - USB_PID_LIFEVIEW_TV_WALKER_TWIN_WARM) }, 908 - { USB_DEVICE(USB_VID_DPOSH, USB_PID_DPOSH_M9206_COLD) }, 909 - { USB_DEVICE(USB_VID_DPOSH, USB_PID_DPOSH_M9206_WARM) }, 910 - { USB_DEVICE(USB_VID_VISIONPLUS, USB_PID_PINNACLE_PCTV310E) }, 911 - { USB_DEVICE(USB_VID_AZUREWAVE, USB_PID_TWINHAN_VP7049) }, 912 - { } /* Terminating entry */ 900 + enum { 901 + MSI_MEGASKY580, 902 + ANUBIS_MSI_DIGI_VOX_MINI_II, 903 + ANUBIS_LIFEVIEW_TV_WALKER_TWIN_COLD, 904 + ANUBIS_LIFEVIEW_TV_WALKER_TWIN_WARM, 905 + DPOSH_M9206_COLD, 906 + DPOSH_M9206_WARM, 907 + VISIONPLUS_PINNACLE_PCTV310E, 908 + AZUREWAVE_TWINHAN_VP7049, 913 909 }; 910 + 911 + static struct usb_device_id m920x_table[] = { 912 + DVB_USB_DEV(MSI, MSI_MEGASKY580), 913 + DVB_USB_DEV(ANUBIS_ELECTRONIC, ANUBIS_MSI_DIGI_VOX_MINI_II), 914 + DVB_USB_DEV(ANUBIS_ELECTRONIC, ANUBIS_LIFEVIEW_TV_WALKER_TWIN_COLD), 915 + DVB_USB_DEV(ANUBIS_ELECTRONIC, ANUBIS_LIFEVIEW_TV_WALKER_TWIN_WARM), 916 + DVB_USB_DEV(DPOSH, DPOSH_M9206_COLD), 917 + DVB_USB_DEV(DPOSH, DPOSH_M9206_WARM), 918 + DVB_USB_DEV(VISIONPLUS, VISIONPLUS_PINNACLE_PCTV310E), 919 + DVB_USB_DEV(AZUREWAVE, AZUREWAVE_TWINHAN_VP7049), 920 + { } 921 + }; 922 + 914 923 MODULE_DEVICE_TABLE (usb, m920x_table); 915 924 916 925 static struct dvb_usb_device_properties megasky_properties = { ··· 971 962 .num_device_descs = 1, 972 963 .devices = { 973 964 { "MSI Mega Sky 580 DVB-T USB2.0", 974 - { &m920x_table[0], NULL }, 965 + { &m920x_table[MSI_MEGASKY580], NULL }, 975 966 { NULL }, 976 967 } 977 968 } ··· 1019 1010 .num_device_descs = 1, 1020 1011 .devices = { 1021 1012 { "MSI DIGI VOX mini II DVB-T USB2.0", 1022 - { &m920x_table[1], NULL }, 1013 + { &m920x_table[ANUBIS_MSI_DIGI_VOX_MINI_II], NULL }, 1023 1014 { NULL }, 1024 1015 }, 1025 1016 } ··· 1106 1097 .num_device_descs = 1, 1107 1098 .devices = { 1108 1099 { .name = "LifeView TV Walker Twin DVB-T USB2.0", 1109 - .cold_ids = { &m920x_table[2], NULL }, 1110 - .warm_ids = { &m920x_table[3], NULL }, 1100 + .cold_ids = { &m920x_table[ANUBIS_LIFEVIEW_TV_WALKER_TWIN_COLD], NULL }, 1101 + .warm_ids = { &m920x_table[ANUBIS_LIFEVIEW_TV_WALKER_TWIN_WARM], NULL }, 1111 1102 }, 1112 1103 } 1113 1104 }; ··· 1148 1139 .num_device_descs = 1, 1149 1140 .devices = { 1150 1141 { .name = "Dposh DVB-T USB2.0", 1151 - .cold_ids = { &m920x_table[4], NULL }, 1152 - .warm_ids = { &m920x_table[5], NULL }, 1142 + .cold_ids = { &m920x_table[DPOSH_M9206_COLD], NULL }, 1143 + .warm_ids = { &m920x_table[DPOSH_M9206_WARM], NULL }, 1153 1144 }, 1154 1145 } 1155 1146 }; ··· 1204 1195 .num_device_descs = 1, 1205 1196 .devices = { 1206 1197 { "Pinnacle PCTV 310e", 1207 - { &m920x_table[6], NULL }, 1198 + { &m920x_table[VISIONPLUS_PINNACLE_PCTV310E], NULL }, 1208 1199 { NULL }, 1209 1200 } 1210 1201 } ··· 1259 1250 .num_device_descs = 1, 1260 1251 .devices = { 1261 1252 { "DTV-DVB UDTT7049", 1262 - { &m920x_table[7], NULL }, 1253 + { &m920x_table[AZUREWAVE_TWINHAN_VP7049], NULL }, 1263 1254 { NULL }, 1264 1255 } 1265 1256 }

+12 -6

drivers/media/usb/dvb-usb/nova-t-usb2.c

··· 160 160 } 161 161 162 162 /* do not change the order of the ID table */ 163 - static struct usb_device_id nova_t_table [] = { 164 - /* 00 */ { USB_DEVICE(USB_VID_HAUPPAUGE, USB_PID_WINTV_NOVA_T_USB2_COLD) }, 165 - /* 01 */ { USB_DEVICE(USB_VID_HAUPPAUGE, USB_PID_WINTV_NOVA_T_USB2_WARM) }, 166 - { } /* Terminating entry */ 163 + enum { 164 + HAUPPAUGE_WINTV_NOVA_T_USB2_COLD, 165 + HAUPPAUGE_WINTV_NOVA_T_USB2_WARM, 167 166 }; 167 + 168 + static struct usb_device_id nova_t_table[] = { 169 + DVB_USB_DEV(HAUPPAUGE, HAUPPAUGE_WINTV_NOVA_T_USB2_COLD), 170 + DVB_USB_DEV(HAUPPAUGE, HAUPPAUGE_WINTV_NOVA_T_USB2_WARM), 171 + { } 172 + }; 173 + 168 174 MODULE_DEVICE_TABLE(usb, nova_t_table); 169 175 170 176 static struct dvb_usb_device_properties nova_t_properties = { ··· 227 221 .num_device_descs = 1, 228 222 .devices = { 229 223 { "Hauppauge WinTV-NOVA-T usb2", 230 - { &nova_t_table[0], NULL }, 231 - { &nova_t_table[1], NULL }, 224 + { &nova_t_table[HAUPPAUGE_WINTV_NOVA_T_USB2_COLD], NULL }, 225 + { &nova_t_table[HAUPPAUGE_WINTV_NOVA_T_USB2_WARM], NULL }, 232 226 }, 233 227 { NULL }, 234 228 }

+10 -5

drivers/media/usb/dvb-usb/opera1.c

··· 425 425 return 0; 426 426 } 427 427 428 + enum { 429 + CYPRESS_OPERA1_COLD, 430 + OPERA1_WARM, 431 + }; 432 + 428 433 static struct usb_device_id opera1_table[] = { 429 - {USB_DEVICE(USB_VID_CYPRESS, USB_PID_OPERA1_COLD)}, 430 - {USB_DEVICE(USB_VID_OPERA1, USB_PID_OPERA1_WARM)}, 431 - {} 434 + DVB_USB_DEV(CYPRESS, CYPRESS_OPERA1_COLD), 435 + DVB_USB_DEV(OPERA1, OPERA1_WARM), 436 + { } 432 437 }; 433 438 434 439 MODULE_DEVICE_TABLE(usb, opera1_table); ··· 545 540 .num_device_descs = 1, 546 541 .devices = { 547 542 {"Opera1 DVB-S USB2.0", 548 - {&opera1_table[0], NULL}, 549 - {&opera1_table[1], NULL}, 543 + {&opera1_table[CYPRESS_OPERA1_COLD], NULL}, 544 + {&opera1_table[OPERA1_WARM], NULL}, 550 545 }, 551 546 } 552 547 };

+15 -9

drivers/media/usb/dvb-usb/pctv452e.c

··· 951 951 return 0; 952 952 } 953 953 954 - static struct usb_device_id pctv452e_usb_table[] = { 955 - {USB_DEVICE(USB_VID_PINNACLE, USB_PID_PCTV_452E)}, 956 - {USB_DEVICE(USB_VID_TECHNOTREND, USB_PID_TECHNOTREND_CONNECT_S2_3600)}, 957 - {USB_DEVICE(USB_VID_TECHNOTREND, 958 - USB_PID_TECHNOTREND_CONNECT_S2_3650_CI)}, 959 - {} 954 + enum { 955 + PINNACLE_PCTV_452E, 956 + TECHNOTREND_CONNECT_S2_3600, 957 + TECHNOTREND_CONNECT_S2_3650_CI, 960 958 }; 959 + 960 + static struct usb_device_id pctv452e_usb_table[] = { 961 + DVB_USB_DEV(PINNACLE, PINNACLE_PCTV_452E), 962 + DVB_USB_DEV(TECHNOTREND, TECHNOTREND_CONNECT_S2_3600), 963 + DVB_USB_DEV(TECHNOTREND, TECHNOTREND_CONNECT_S2_3650_CI), 964 + { } 965 + }; 966 + 961 967 MODULE_DEVICE_TABLE(usb, pctv452e_usb_table); 962 968 963 969 static struct dvb_usb_device_properties pctv452e_properties = { ··· 1012 1006 .devices = { 1013 1007 { .name = "PCTV HDTV USB", 1014 1008 .cold_ids = { NULL, NULL }, /* this is a warm only device */ 1015 - .warm_ids = { &pctv452e_usb_table[0], NULL } 1009 + .warm_ids = { &pctv452e_usb_table[PINNACLE_PCTV_452E], NULL } 1016 1010 }, 1017 1011 { NULL }, 1018 1012 } ··· 1066 1060 .devices = { 1067 1061 { .name = "Technotrend TT Connect S2-3600", 1068 1062 .cold_ids = { NULL, NULL }, /* this is a warm only device */ 1069 - .warm_ids = { &pctv452e_usb_table[1], NULL } 1063 + .warm_ids = { &pctv452e_usb_table[TECHNOTREND_CONNECT_S2_3600], NULL } 1070 1064 }, 1071 1065 { .name = "Technotrend TT Connect S2-3650-CI", 1072 1066 .cold_ids = { NULL, NULL }, 1073 - .warm_ids = { &pctv452e_usb_table[2], NULL } 1067 + .warm_ids = { &pctv452e_usb_table[TECHNOTREND_CONNECT_S2_3650_CI], NULL } 1074 1068 }, 1075 1069 { NULL }, 1076 1070 }

+9 -4

drivers/media/usb/dvb-usb/technisat-usb2.c

··· 689 689 } 690 690 691 691 /* DVB-USB and USB stuff follows */ 692 - static struct usb_device_id technisat_usb2_id_table[] = { 693 - { USB_DEVICE(USB_VID_TECHNISAT, USB_PID_TECHNISAT_USB2_DVB_S2) }, 694 - { 0 } /* Terminating entry */ 692 + enum { 693 + TECHNISAT_USB2_DVB_S2, 695 694 }; 695 + 696 + static struct usb_device_id technisat_usb2_id_table[] = { 697 + DVB_USB_DEV(TECHNISAT, TECHNISAT_USB2_DVB_S2), 698 + { } 699 + }; 700 + 696 701 MODULE_DEVICE_TABLE(usb, technisat_usb2_id_table); 697 702 698 703 /* device description */ ··· 743 738 .num_device_descs = 1, 744 739 .devices = { 745 740 { "Technisat SkyStar USB HD (DVB-S/S2)", 746 - { &technisat_usb2_id_table[0], NULL }, 741 + { &technisat_usb2_id_table[TECHNISAT_USB2_DVB_S2], NULL }, 747 742 { NULL }, 748 743 }, 749 744 },

+21 -15

drivers/media/usb/dvb-usb/ttusb2.c

··· 630 630 return -ENODEV; 631 631 } 632 632 633 - static struct usb_device_id ttusb2_table [] = { 634 - { USB_DEVICE(USB_VID_PINNACLE, USB_PID_PCTV_400E) }, 635 - { USB_DEVICE(USB_VID_PINNACLE, USB_PID_PCTV_450E) }, 636 - { USB_DEVICE(USB_VID_TECHNOTREND, 637 - USB_PID_TECHNOTREND_CONNECT_S2400) }, 638 - { USB_DEVICE(USB_VID_TECHNOTREND, 639 - USB_PID_TECHNOTREND_CONNECT_CT3650) }, 640 - { USB_DEVICE(USB_VID_TECHNOTREND, 641 - USB_PID_TECHNOTREND_CONNECT_S2400_8KEEPROM) }, 642 - {} /* Terminating entry */ 633 + enum { 634 + PINNACLE_PCTV_400E, 635 + PINNACLE_PCTV_450E, 636 + TECHNOTREND_CONNECT_S2400, 637 + TECHNOTREND_CONNECT_CT3650, 638 + TECHNOTREND_CONNECT_S2400_8KEEPROM, 643 639 }; 640 + 641 + static struct usb_device_id ttusb2_table[] = { 642 + DVB_USB_DEV(PINNACLE, PINNACLE_PCTV_400E), 643 + DVB_USB_DEV(PINNACLE, PINNACLE_PCTV_450E), 644 + DVB_USB_DEV(TECHNOTREND, TECHNOTREND_CONNECT_S2400), 645 + DVB_USB_DEV(TECHNOTREND, TECHNOTREND_CONNECT_CT3650), 646 + DVB_USB_DEV(TECHNOTREND, TECHNOTREND_CONNECT_S2400_8KEEPROM), 647 + { } 648 + }; 649 + 644 650 MODULE_DEVICE_TABLE (usb, ttusb2_table); 645 651 646 652 static struct dvb_usb_device_properties ttusb2_properties = { ··· 694 688 .num_device_descs = 2, 695 689 .devices = { 696 690 { "Pinnacle 400e DVB-S USB2.0", 697 - { &ttusb2_table[0], NULL }, 691 + { &ttusb2_table[PINNACLE_PCTV_400E], NULL }, 698 692 { NULL }, 699 693 }, 700 694 { "Pinnacle 450e DVB-S USB2.0", 701 - { &ttusb2_table[1], NULL }, 695 + { &ttusb2_table[PINNACLE_PCTV_450E], NULL }, 702 696 { NULL }, 703 697 }, 704 698 } ··· 749 743 .num_device_descs = 2, 750 744 .devices = { 751 745 { "Technotrend TT-connect S-2400", 752 - { &ttusb2_table[2], NULL }, 746 + { &ttusb2_table[TECHNOTREND_CONNECT_S2400], NULL }, 753 747 { NULL }, 754 748 }, 755 749 { "Technotrend TT-connect S-2400 (8kB EEPROM)", 756 - { &ttusb2_table[4], NULL }, 750 + { &ttusb2_table[TECHNOTREND_CONNECT_S2400_8KEEPROM], NULL }, 757 751 { NULL }, 758 752 }, 759 753 } ··· 829 823 .num_device_descs = 1, 830 824 .devices = { 831 825 { "Technotrend TT-connect CT-3650", 832 - .warm_ids = { &ttusb2_table[3], NULL }, 826 + .warm_ids = { &ttusb2_table[TECHNOTREND_CONNECT_CT3650], NULL }, 833 827 }, 834 828 } 835 829 };

+12 -6

drivers/media/usb/dvb-usb/umt-010.c

··· 81 81 } 82 82 83 83 /* do not change the order of the ID table */ 84 - static struct usb_device_id umt_table [] = { 85 - /* 00 */ { USB_DEVICE(USB_VID_HANFTEK, USB_PID_HANFTEK_UMT_010_COLD) }, 86 - /* 01 */ { USB_DEVICE(USB_VID_HANFTEK, USB_PID_HANFTEK_UMT_010_WARM) }, 87 - { } /* Terminating entry */ 84 + enum { 85 + HANFTEK_UMT_010_COLD, 86 + HANFTEK_UMT_010_WARM, 88 87 }; 88 + 89 + static struct usb_device_id umt_table[] = { 90 + DVB_USB_DEV(HANFTEK, HANFTEK_UMT_010_COLD), 91 + DVB_USB_DEV(HANFTEK, HANFTEK_UMT_010_WARM), 92 + { } 93 + }; 94 + 89 95 MODULE_DEVICE_TABLE (usb, umt_table); 90 96 91 97 static struct dvb_usb_device_properties umt_properties = { ··· 133 127 .num_device_descs = 1, 134 128 .devices = { 135 129 { "Hanftek UMT-010 DVB-T USB2.0", 136 - { &umt_table[0], NULL }, 137 - { &umt_table[1], NULL }, 130 + { &umt_table[HANFTEK_UMT_010_COLD], NULL }, 131 + { &umt_table[HANFTEK_UMT_010_WARM], NULL }, 138 132 }, 139 133 } 140 134 };

+15 -8

drivers/media/usb/dvb-usb/vp702x.c

··· 369 369 dvb_usb_device_exit(intf); 370 370 } 371 371 372 - static struct usb_device_id vp702x_usb_table [] = { 373 - { USB_DEVICE(USB_VID_VISIONPLUS, USB_PID_TWINHAN_VP7021_COLD) }, 374 - // { USB_DEVICE(USB_VID_VISIONPLUS, USB_PID_TWINHAN_VP7020_COLD) }, 375 - // { USB_DEVICE(USB_VID_VISIONPLUS, USB_PID_TWINHAN_VP7020_WARM) }, 376 - { 0 }, 372 + enum { 373 + VISIONPLUS_VP7021_COLD, 374 + VISIONPLUS_VP7020_COLD, 375 + VISIONPLUS_VP7020_WARM, 377 376 }; 377 + 378 + static struct usb_device_id vp702x_usb_table[] = { 379 + DVB_USB_DEV(VISIONPLUS, VISIONPLUS_VP7021_COLD), 380 + // DVB_USB_DEV(VISIONPLUS, VISIONPLUS_VP7020_COLD), 381 + // DVB_USB_DEV(VISIONPLUS, VISIONPLUS_VP7020_WARM), 382 + { } 383 + }; 384 + 378 385 MODULE_DEVICE_TABLE(usb, vp702x_usb_table); 379 386 380 387 static struct dvb_usb_device_properties vp702x_properties = { ··· 428 421 .num_device_descs = 1, 429 422 .devices = { 430 423 { .name = "TwinhanDTV StarBox DVB-S USB2.0 (VP7021)", 431 - .cold_ids = { &vp702x_usb_table[0], NULL }, 424 + .cold_ids = { &vp702x_usb_table[VISIONPLUS_VP7021_COLD], NULL }, 432 425 .warm_ids = { NULL }, 433 426 }, 434 427 /* { .name = "TwinhanDTV StarBox DVB-S USB2.0 (VP7020)", 435 - .cold_ids = { &vp702x_usb_table[2], NULL }, 436 - .warm_ids = { &vp702x_usb_table[3], NULL }, 428 + .cold_ids = { &vp702x_usb_table[VISIONPLUS_VP7020_COLD], NULL }, 429 + .warm_ids = { &vp702x_usb_table[VISIONPLUS_VP7020_WARM], NULL }, 437 430 }, 438 431 */ { NULL }, 439 432 }

+18 -10

drivers/media/usb/dvb-usb/vp7045.c

··· 172 172 THIS_MODULE, NULL, adapter_nr); 173 173 } 174 174 175 - static struct usb_device_id vp7045_usb_table [] = { 176 - { USB_DEVICE(USB_VID_VISIONPLUS, USB_PID_TWINHAN_VP7045_COLD) }, 177 - { USB_DEVICE(USB_VID_VISIONPLUS, USB_PID_TWINHAN_VP7045_WARM) }, 178 - { USB_DEVICE(USB_VID_VISIONPLUS, USB_PID_DNTV_TINYUSB2_COLD) }, 179 - { USB_DEVICE(USB_VID_VISIONPLUS, USB_PID_DNTV_TINYUSB2_WARM) }, 180 - { 0 }, 175 + enum { 176 + VISIONPLUS_VP7045_COLD, 177 + VISIONPLUS_VP7045_WARM, 178 + VISIONPLUS_TINYUSB2_COLD, 179 + VISIONPLUS_TINYUSB2_WARM, 181 180 }; 181 + 182 + static struct usb_device_id vp7045_usb_table[] = { 183 + DVB_USB_DEV(VISIONPLUS, VISIONPLUS_VP7045_COLD), 184 + DVB_USB_DEV(VISIONPLUS, VISIONPLUS_VP7045_WARM), 185 + DVB_USB_DEV(VISIONPLUS, VISIONPLUS_TINYUSB2_COLD), 186 + DVB_USB_DEV(VISIONPLUS, VISIONPLUS_TINYUSB2_WARM), 187 + { } 188 + }; 189 + 182 190 MODULE_DEVICE_TABLE(usb, vp7045_usb_table); 183 191 184 192 static struct dvb_usb_device_properties vp7045_properties = { ··· 229 221 .num_device_descs = 2, 230 222 .devices = { 231 223 { .name = "Twinhan USB2.0 DVB-T receiver (TwinhanDTV Alpha/MagicBox II)", 232 - .cold_ids = { &vp7045_usb_table[0], NULL }, 233 - .warm_ids = { &vp7045_usb_table[1], NULL }, 224 + .cold_ids = { &vp7045_usb_table[VISIONPLUS_VP7045_COLD], NULL }, 225 + .warm_ids = { &vp7045_usb_table[VISIONPLUS_VP7045_WARM], NULL }, 234 226 }, 235 227 { .name = "DigitalNow TinyUSB 2 DVB-t Receiver", 236 - .cold_ids = { &vp7045_usb_table[2], NULL }, 237 - .warm_ids = { &vp7045_usb_table[3], NULL }, 228 + .cold_ids = { &vp7045_usb_table[VISIONPLUS_TINYUSB2_COLD], NULL }, 229 + .warm_ids = { &vp7045_usb_table[VISIONPLUS_TINYUSB2_WARM], NULL }, 238 230 }, 239 231 { NULL }, 240 232 }

+1 -1

drivers/media/usb/gspca/spca561.c

··· 510 510 /* We choose to use the high bits setting the fixed framerate divisor 511 511 asap, as setting high basic exposure setting without the fixed 512 512 divider in combination with high gains makes the cam stop */ 513 - int table[] = { 0, 450, 550, 625, EXPOSURE_MAX }; 513 + static const int table[] = { 0, 450, 550, 625, EXPOSURE_MAX }; 514 514 515 515 for (i = 0; i < ARRAY_SIZE(table) - 1; i++) { 516 516 if (val <= table[i + 1]) {

+5 -2

drivers/media/usb/pvrusb2/pvrusb2-hdw.c

··· 2569 2569 } while (0); 2570 2570 mutex_unlock(&pvr2_unit_mtx); 2571 2571 2572 + INIT_WORK(&hdw->workpoll, pvr2_hdw_worker_poll); 2573 + 2574 + if (hdw->unit_number == -1) 2575 + goto fail; 2576 + 2572 2577 cnt1 = 0; 2573 2578 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2"); 2574 2579 cnt1 += cnt2; ··· 2584 2579 } 2585 2580 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1; 2586 2581 hdw->name[cnt1] = 0; 2587 - 2588 - INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll); 2589 2582 2590 2583 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s", 2591 2584 hdw->unit_number,hdw->name);

+2 -9

drivers/media/usb/stkwebcam/stk-webcam.c

··· 150 150 int stk_camera_read_reg(struct stk_camera *dev, u16 index, u8 *value) 151 151 { 152 152 struct usb_device *udev = dev->udev; 153 - unsigned char *buf; 154 153 int ret; 155 - 156 - buf = kmalloc(sizeof(u8), GFP_KERNEL); 157 - if (!buf) 158 - return -ENOMEM; 159 154 160 155 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 161 156 0x00, 162 157 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 163 158 0x00, 164 159 index, 165 - buf, 160 + &dev->read_reg_scratch, 166 161 sizeof(u8), 167 162 500); 168 163 if (ret >= 0) 169 - *value = *buf; 170 - 171 - kfree(buf); 164 + *value = dev->read_reg_scratch; 172 165 173 166 if (ret < 0) 174 167 return ret;

+2

drivers/media/usb/stkwebcam/stk-webcam.h

··· 105 105 struct list_head sio_avail; 106 106 struct list_head sio_full; 107 107 unsigned sequence; 108 + 109 + u8 read_reg_scratch; 108 110 }; 109 111 110 112 #define vdev_to_camera(d) container_of(d, struct stk_camera, vdev)

+10

drivers/media/usb/uvc/uvc_ctrl.c

··· 2188 2188 if (map == NULL) 2189 2189 return -ENOMEM; 2190 2190 2191 + /* For UVCIOC_CTRL_MAP custom control */ 2192 + if (mapping->name) { 2193 + map->name = kstrdup(mapping->name, GFP_KERNEL); 2194 + if (!map->name) { 2195 + kfree(map); 2196 + return -ENOMEM; 2197 + } 2198 + } 2199 + 2191 2200 INIT_LIST_HEAD(&map->ev_subs); 2192 2201 2193 2202 size = sizeof(*mapping->menu_info) * mapping->menu_count; 2194 2203 map->menu_info = kmemdup(mapping->menu_info, size, GFP_KERNEL); 2195 2204 if (map->menu_info == NULL) { 2205 + kfree(map->name); 2196 2206 kfree(map); 2197 2207 return -ENOMEM; 2198 2208 }

+7 -4

drivers/media/usb/uvc/uvc_driver.c

··· 155 155 .fcc = V4L2_PIX_FMT_H264, 156 156 }, 157 157 { 158 + .name = "H.265", 159 + .guid = UVC_GUID_FORMAT_H265, 160 + .fcc = V4L2_PIX_FMT_HEVC, 161 + }, 162 + { 158 163 .name = "Greyscale 8 L/R (Y8I)", 159 164 .guid = UVC_GUID_FORMAT_Y8I, 160 165 .fcc = V4L2_PIX_FMT_Y8I, ··· 1014 1009 streaming->header.bEndpointAddress); 1015 1010 if (ep == NULL) 1016 1011 continue; 1017 - 1018 - psize = le16_to_cpu(ep->desc.wMaxPacketSize); 1019 - psize = (psize & 0x07ff) * (1 + ((psize >> 11) & 3)); 1012 + psize = uvc_endpoint_max_bpi(dev->udev, ep); 1020 1013 if (psize > streaming->maxpsize) 1021 1014 streaming->maxpsize = psize; 1022 1015 } ··· 2446 2443 "Forcing device quirks to 0x%x by module parameter for testing purpose.\n", 2447 2444 dev->quirks); 2448 2445 dev_info(&dev->udev->dev, 2449 - "Please report required quirks to the linux-uvc-devel mailing list.\n"); 2446 + "Please report required quirks to the linux-media mailing list.\n"); 2450 2447 } 2451 2448 2452 2449 if (dev->info->uvc_version) {

+15 -13

drivers/media/usb/uvc/uvc_v4l2.c

··· 42 42 map->id = xmap->id; 43 43 /* Non standard control id. */ 44 44 if (v4l2_ctrl_get_name(map->id) == NULL) { 45 - map->name = kmemdup(xmap->name, sizeof(xmap->name), 46 - GFP_KERNEL); 47 - if (!map->name) { 48 - ret = -ENOMEM; 45 + if (xmap->name[0] == '\0') { 46 + ret = -EINVAL; 49 47 goto free_map; 50 48 } 49 + xmap->name[sizeof(xmap->name) - 1] = '\0'; 50 + map->name = xmap->name; 51 51 } 52 52 memcpy(map->entity, xmap->entity, sizeof(map->entity)); 53 53 map->selector = xmap->selector; ··· 871 871 struct uvc_video_chain *chain = handle->chain; 872 872 const struct uvc_entity *selector = chain->selector; 873 873 struct uvc_entity *iterm = NULL; 874 + struct uvc_entity *it; 874 875 u32 index = input->index; 875 - int pin = 0; 876 876 877 877 if (selector == NULL || 878 878 (chain->dev->quirks & UVC_QUIRK_IGNORE_SELECTOR_UNIT)) { 879 879 if (index != 0) 880 880 return -EINVAL; 881 - list_for_each_entry(iterm, &chain->entities, chain) { 882 - if (UVC_ENTITY_IS_ITERM(iterm)) 881 + list_for_each_entry(it, &chain->entities, chain) { 882 + if (UVC_ENTITY_IS_ITERM(it)) { 883 + iterm = it; 883 884 break; 885 + } 884 886 } 885 - pin = iterm->id; 886 887 } else if (index < selector->bNrInPins) { 887 - pin = selector->baSourceID[index]; 888 - list_for_each_entry(iterm, &chain->entities, chain) { 889 - if (!UVC_ENTITY_IS_ITERM(iterm)) 888 + list_for_each_entry(it, &chain->entities, chain) { 889 + if (!UVC_ENTITY_IS_ITERM(it)) 890 890 continue; 891 - if (iterm->id == pin) 891 + if (it->id == selector->baSourceID[index]) { 892 + iterm = it; 892 893 break; 894 + } 893 895 } 894 896 } 895 897 896 - if (iterm == NULL || iterm->id != pin) 898 + if (iterm == NULL) 897 899 return -EINVAL; 898 900 899 901 memset(input, 0, sizeof(*input));

+3 -13

drivers/media/usb/uvc/uvc_video.c

··· 383 383 struct uvc_streaming_control *probe) 384 384 { 385 385 struct uvc_streaming_control probe_min, probe_max; 386 - u16 bandwidth; 387 386 unsigned int i; 388 387 int ret; 389 388 ··· 420 421 if (stream->intf->num_altsetting == 1) 421 422 break; 422 423 423 - bandwidth = probe->dwMaxPayloadTransferSize; 424 - if (bandwidth <= stream->maxpsize) 424 + if (probe->dwMaxPayloadTransferSize <= stream->maxpsize) 425 425 break; 426 426 427 427 if (stream->dev->quirks & UVC_QUIRK_PROBE_MINMAX) { ··· 1754 1756 /* 1755 1757 * Compute the maximum number of bytes per interval for an endpoint. 1756 1758 */ 1757 - static unsigned int uvc_endpoint_max_bpi(struct usb_device *dev, 1758 - struct usb_host_endpoint *ep) 1759 + u16 uvc_endpoint_max_bpi(struct usb_device *dev, struct usb_host_endpoint *ep) 1759 1760 { 1760 1761 u16 psize; 1761 - u16 mult; 1762 1762 1763 1763 switch (dev->speed) { 1764 1764 case USB_SPEED_SUPER: 1765 1765 case USB_SPEED_SUPER_PLUS: 1766 1766 return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval); 1767 - case USB_SPEED_HIGH: 1768 - psize = usb_endpoint_maxp(&ep->desc); 1769 - mult = usb_endpoint_maxp_mult(&ep->desc); 1770 - return psize * mult; 1771 - case USB_SPEED_WIRELESS: 1772 - psize = usb_endpoint_maxp(&ep->desc); 1773 - return psize; 1774 1767 default: 1775 1768 psize = usb_endpoint_maxp(&ep->desc); 1769 + psize *= usb_endpoint_maxp_mult(&ep->desc); 1776 1770 return psize; 1777 1771 } 1778 1772 }

+4

drivers/media/usb/uvc/uvcvideo.h

··· 139 139 #define UVC_GUID_FORMAT_H264 \ 140 140 { 'H', '2', '6', '4', 0x00, 0x00, 0x10, 0x00, \ 141 141 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71} 142 + #define UVC_GUID_FORMAT_H265 \ 143 + { 'H', '2', '6', '5', 0x00, 0x00, 0x10, 0x00, \ 144 + 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71} 142 145 #define UVC_GUID_FORMAT_Y8I \ 143 146 { 'Y', '8', 'I', ' ', 0x00, 0x00, 0x10, 0x00, \ 144 147 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71} ··· 914 911 u32 uvc_fraction_to_interval(u32 numerator, u32 denominator); 915 912 struct usb_host_endpoint *uvc_find_endpoint(struct usb_host_interface *alts, 916 913 u8 epaddr); 914 + u16 uvc_endpoint_max_bpi(struct usb_device *dev, struct usb_host_endpoint *ep); 917 915 918 916 /* Quirks support */ 919 917 void uvc_video_decode_isight(struct uvc_urb *uvc_urb,

+2 -2

drivers/media/v4l2-core/tuner-core.c

··· 1118 1118 if (t->mode != V4L2_TUNER_RADIO) 1119 1119 return; 1120 1120 if (fe_tuner_ops->get_status) { 1121 - u32 tuner_status; 1121 + u32 tuner_status = 0; 1122 1122 1123 1123 fe_tuner_ops->get_status(&t->fe, &tuner_status); 1124 1124 if (tuner_status & TUNER_STATUS_LOCKED) ··· 1258 1258 if (vt->type == t->mode) { 1259 1259 vt->rxsubchans = V4L2_TUNER_SUB_MONO | V4L2_TUNER_SUB_STEREO; 1260 1260 if (fe_tuner_ops->get_status) { 1261 - u32 tuner_status; 1261 + u32 tuner_status = 0; 1262 1262 1263 1263 fe_tuner_ops->get_status(&t->fe, &tuner_status); 1264 1264 vt->rxsubchans =

+32 -1

drivers/media/v4l2-core/v4l2-async.c

··· 275 275 static int 276 276 v4l2_async_nf_try_all_subdevs(struct v4l2_async_notifier *notifier); 277 277 278 + static int v4l2_async_create_ancillary_links(struct v4l2_async_notifier *n, 279 + struct v4l2_subdev *sd) 280 + { 281 + struct media_link *link = NULL; 282 + 283 + #if IS_ENABLED(CONFIG_MEDIA_CONTROLLER) 284 + 285 + if (sd->entity.function != MEDIA_ENT_F_LENS && 286 + sd->entity.function != MEDIA_ENT_F_FLASH) 287 + return 0; 288 + 289 + link = media_create_ancillary_link(&n->sd->entity, &sd->entity); 290 + 291 + #endif 292 + 293 + return IS_ERR(link) ? PTR_ERR(link) : 0; 294 + } 295 + 278 296 static int v4l2_async_match_notify(struct v4l2_async_notifier *notifier, 279 297 struct v4l2_device *v4l2_dev, 280 298 struct v4l2_subdev *sd, ··· 307 289 308 290 ret = v4l2_async_nf_call_bound(notifier, sd, asd); 309 291 if (ret < 0) { 292 + v4l2_device_unregister_subdev(sd); 293 + return ret; 294 + } 295 + 296 + /* 297 + * Depending of the function of the entities involved, we may want to 298 + * create links between them (for example between a sensor and its lens 299 + * or between a sensor's source pad and the connected device's sink 300 + * pad). 301 + */ 302 + ret = v4l2_async_create_ancillary_links(notifier, sd); 303 + if (ret) { 304 + v4l2_async_nf_call_unbind(notifier, sd, asd); 310 305 v4l2_device_unregister_subdev(sd); 311 306 return ret; 312 307 } ··· 693 662 struct v4l2_async_subdev *asd; 694 663 struct fwnode_handle *remote; 695 664 696 - remote = fwnode_graph_get_remote_port_parent(endpoint); 665 + remote = fwnode_graph_get_remote_endpoint(endpoint); 697 666 if (!remote) 698 667 return ERR_PTR(-ENOTCONN); 699 668

+2 -3

drivers/media/v4l2-core/v4l2-ctrls-core.c

··· 1140 1140 INIT_LIST_HEAD(&hdl->ctrls); 1141 1141 INIT_LIST_HEAD(&hdl->ctrl_refs); 1142 1142 hdl->nr_of_buckets = 1 + nr_of_controls_hint / 8; 1143 - hdl->buckets = kvmalloc_array(hdl->nr_of_buckets, 1144 - sizeof(hdl->buckets[0]), 1145 - GFP_KERNEL | __GFP_ZERO); 1143 + hdl->buckets = kvcalloc(hdl->nr_of_buckets, sizeof(hdl->buckets[0]), 1144 + GFP_KERNEL); 1146 1145 hdl->error = hdl->buckets ? 0 : -ENOMEM; 1147 1146 v4l2_ctrl_handler_init_request(hdl); 1148 1147 return hdl->error;

+9

drivers/media/v4l2-core/v4l2-ctrls-defs.c

··· 572 572 "VBV/CPB Limit", 573 573 NULL, 574 574 }; 575 + static const char * const intra_refresh_period_type[] = { 576 + "Random", 577 + "Cyclic", 578 + NULL, 579 + }; 575 580 576 581 switch (id) { 577 582 case V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ: ··· 710 705 return hevc_start_code; 711 706 case V4L2_CID_CAMERA_ORIENTATION: 712 707 return camera_orientation; 708 + case V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE: 709 + return intra_refresh_period_type; 713 710 default: 714 711 return NULL; 715 712 } ··· 841 834 case V4L2_CID_MPEG_VIDEO_DECODER_SLICE_INTERFACE: return "Decoder Slice Interface"; 842 835 case V4L2_CID_MPEG_VIDEO_DECODER_MPEG4_DEBLOCK_FILTER: return "MPEG4 Loop Filter Enable"; 843 836 case V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB: return "Number of Intra Refresh MBs"; 837 + case V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE: return "Intra Refresh Period Type"; 844 838 case V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD: return "Intra Refresh Period"; 845 839 case V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE: return "Frame Level Rate Control Enable"; 846 840 case V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE: return "H264 MB Level Rate Control"; ··· 1368 1360 case V4L2_CID_STATELESS_H264_DECODE_MODE: 1369 1361 case V4L2_CID_STATELESS_H264_START_CODE: 1370 1362 case V4L2_CID_CAMERA_ORIENTATION: 1363 + case V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE: 1371 1364 *type = V4L2_CTRL_TYPE_MENU; 1372 1365 break; 1373 1366 case V4L2_CID_LINK_FREQ:

+4

drivers/media/v4l2-core/v4l2-fwnode.c

··· 61 61 V4L2_FWNODE_BUS_TYPE_BT656, 62 62 V4L2_MBUS_BT656, 63 63 "Bt.656", 64 + }, { 65 + V4L2_FWNODE_BUS_TYPE_DPI, 66 + V4L2_MBUS_DPI, 67 + "DPI", 64 68 } 65 69 }; 66 70

+228 -47

drivers/media/v4l2-core/v4l2-h264.c

··· 12 12 13 13 #include <media/v4l2-h264.h> 14 14 15 + /* 16 + * Size of the tempory buffer allocated when printing reference lists. The 17 + * output will be truncated if the size is too small. 18 + */ 19 + static const int tmp_str_size = 1024; 20 + 15 21 /** 16 22 * v4l2_h264_init_reflist_builder() - Initialize a P/B0/B1 reference list 17 23 * builder ··· 40 34 cur_frame_num = dec_params->frame_num; 41 35 42 36 memset(b, 0, sizeof(*b)); 43 - if (!(dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC)) 37 + if (!(dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC)) { 44 38 b->cur_pic_order_count = min(dec_params->bottom_field_order_cnt, 45 39 dec_params->top_field_order_cnt); 46 - else if (dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD) 40 + b->cur_pic_fields = V4L2_H264_FRAME_REF; 41 + } else if (dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD) { 47 42 b->cur_pic_order_count = dec_params->bottom_field_order_cnt; 48 - else 43 + b->cur_pic_fields = V4L2_H264_BOTTOM_FIELD_REF; 44 + } else { 49 45 b->cur_pic_order_count = dec_params->top_field_order_cnt; 46 + b->cur_pic_fields = V4L2_H264_TOP_FIELD_REF; 47 + } 50 48 51 49 for (i = 0; i < V4L2_H264_NUM_DPB_ENTRIES; i++) { 52 - u32 pic_order_count; 53 - 54 50 if (!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) 55 51 continue; 56 52 57 - b->refs[i].pic_num = dpb[i].pic_num; 58 53 if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) 59 54 b->refs[i].longterm = true; 60 55 61 56 /* 62 57 * Handle frame_num wraparound as described in section 63 58 * '8.2.4.1 Decoding process for picture numbers' of the spec. 64 - * TODO: This logic will have to be adjusted when we start 65 - * supporting interlaced content. 59 + * For long term references, frame_num is set to 60 + * long_term_frame_idx which requires no wrapping. 66 61 */ 67 - if (dpb[i].frame_num > cur_frame_num) 62 + if (!b->refs[i].longterm && dpb[i].frame_num > cur_frame_num) 68 63 b->refs[i].frame_num = (int)dpb[i].frame_num - 69 64 max_frame_num; 70 65 else 71 66 b->refs[i].frame_num = dpb[i].frame_num; 72 67 73 - if (dpb[i].fields == V4L2_H264_FRAME_REF) 74 - pic_order_count = min(dpb[i].top_field_order_cnt, 75 - dpb[i].bottom_field_order_cnt); 76 - else if (dpb[i].fields & V4L2_H264_BOTTOM_FIELD_REF) 77 - pic_order_count = dpb[i].bottom_field_order_cnt; 78 - else 79 - pic_order_count = dpb[i].top_field_order_cnt; 68 + b->refs[i].top_field_order_cnt = dpb[i].top_field_order_cnt; 69 + b->refs[i].bottom_field_order_cnt = dpb[i].bottom_field_order_cnt; 80 70 81 - b->refs[i].pic_order_count = pic_order_count; 82 - b->unordered_reflist[b->num_valid] = i; 83 - b->num_valid++; 71 + if (b->cur_pic_fields == V4L2_H264_FRAME_REF) { 72 + u8 fields = V4L2_H264_FRAME_REF; 73 + 74 + b->unordered_reflist[b->num_valid].index = i; 75 + b->unordered_reflist[b->num_valid].fields = fields; 76 + b->num_valid++; 77 + continue; 78 + } 79 + 80 + if (dpb[i].fields & V4L2_H264_TOP_FIELD_REF) { 81 + u8 fields = V4L2_H264_TOP_FIELD_REF; 82 + 83 + b->unordered_reflist[b->num_valid].index = i; 84 + b->unordered_reflist[b->num_valid].fields = fields; 85 + b->num_valid++; 86 + } 87 + 88 + if (dpb[i].fields & V4L2_H264_BOTTOM_FIELD_REF) { 89 + u8 fields = V4L2_H264_BOTTOM_FIELD_REF; 90 + 91 + b->unordered_reflist[b->num_valid].index = i; 92 + b->unordered_reflist[b->num_valid].fields = fields; 93 + b->num_valid++; 94 + } 84 95 } 85 96 86 97 for (i = b->num_valid; i < ARRAY_SIZE(b->unordered_reflist); i++) 87 - b->unordered_reflist[i] = i; 98 + b->unordered_reflist[i].index = i; 88 99 } 89 100 EXPORT_SYMBOL_GPL(v4l2_h264_init_reflist_builder); 101 + 102 + static s32 v4l2_h264_get_poc(const struct v4l2_h264_reflist_builder *b, 103 + const struct v4l2_h264_reference *ref) 104 + { 105 + switch (ref->fields) { 106 + case V4L2_H264_FRAME_REF: 107 + return min(b->refs[ref->index].top_field_order_cnt, 108 + b->refs[ref->index].bottom_field_order_cnt); 109 + case V4L2_H264_TOP_FIELD_REF: 110 + return b->refs[ref->index].top_field_order_cnt; 111 + case V4L2_H264_BOTTOM_FIELD_REF: 112 + return b->refs[ref->index].bottom_field_order_cnt; 113 + } 114 + 115 + /* not reached */ 116 + return 0; 117 + } 90 118 91 119 static int v4l2_h264_p_ref_list_cmp(const void *ptra, const void *ptrb, 92 120 const void *data) ··· 128 88 const struct v4l2_h264_reflist_builder *builder = data; 129 89 u8 idxa, idxb; 130 90 131 - idxa = *((u8 *)ptra); 132 - idxb = *((u8 *)ptrb); 91 + idxa = ((struct v4l2_h264_reference *)ptra)->index; 92 + idxb = ((struct v4l2_h264_reference *)ptrb)->index; 133 93 134 94 if (WARN_ON(idxa >= V4L2_H264_NUM_DPB_ENTRIES || 135 95 idxb >= V4L2_H264_NUM_DPB_ENTRIES)) ··· 144 104 } 145 105 146 106 /* 147 - * Short term pics in descending pic num order, long term ones in 148 - * ascending order. 107 + * For frames, short term pics are in descending pic num order and long 108 + * term ones in ascending order. For fields, the same direction is used 109 + * but with frame_num (wrapped). For frames, the value of pic_num and 110 + * frame_num are the same (see formula (8-28) and (8-29)). For this 111 + * reason we can use frame_num only and share this function between 112 + * frames and fields reflist. 149 113 */ 150 114 if (!builder->refs[idxa].longterm) 151 115 return builder->refs[idxb].frame_num < 152 116 builder->refs[idxa].frame_num ? 153 117 -1 : 1; 154 118 155 - return builder->refs[idxa].pic_num < builder->refs[idxb].pic_num ? 119 + return builder->refs[idxa].frame_num < builder->refs[idxb].frame_num ? 156 120 -1 : 1; 157 121 } 158 122 ··· 167 123 s32 poca, pocb; 168 124 u8 idxa, idxb; 169 125 170 - idxa = *((u8 *)ptra); 171 - idxb = *((u8 *)ptrb); 126 + idxa = ((struct v4l2_h264_reference *)ptra)->index; 127 + idxb = ((struct v4l2_h264_reference *)ptrb)->index; 172 128 173 129 if (WARN_ON(idxa >= V4L2_H264_NUM_DPB_ENTRIES || 174 130 idxb >= V4L2_H264_NUM_DPB_ENTRIES)) ··· 182 138 return 1; 183 139 } 184 140 185 - /* Long term pics in ascending pic num order. */ 141 + /* Long term pics in ascending frame num order. */ 186 142 if (builder->refs[idxa].longterm) 187 - return builder->refs[idxa].pic_num < 188 - builder->refs[idxb].pic_num ? 143 + return builder->refs[idxa].frame_num < 144 + builder->refs[idxb].frame_num ? 189 145 -1 : 1; 190 146 191 - poca = builder->refs[idxa].pic_order_count; 192 - pocb = builder->refs[idxb].pic_order_count; 147 + poca = v4l2_h264_get_poc(builder, ptra); 148 + pocb = v4l2_h264_get_poc(builder, ptrb); 193 149 194 150 /* 195 151 * Short term pics with POC < cur POC first in POC descending order ··· 212 168 s32 poca, pocb; 213 169 u8 idxa, idxb; 214 170 215 - idxa = *((u8 *)ptra); 216 - idxb = *((u8 *)ptrb); 171 + idxa = ((struct v4l2_h264_reference *)ptra)->index; 172 + idxb = ((struct v4l2_h264_reference *)ptrb)->index; 217 173 218 174 if (WARN_ON(idxa >= V4L2_H264_NUM_DPB_ENTRIES || 219 175 idxb >= V4L2_H264_NUM_DPB_ENTRIES)) ··· 227 183 return 1; 228 184 } 229 185 230 - /* Long term pics in ascending pic num order. */ 186 + /* Long term pics in ascending frame num order. */ 231 187 if (builder->refs[idxa].longterm) 232 - return builder->refs[idxa].pic_num < 233 - builder->refs[idxb].pic_num ? 188 + return builder->refs[idxa].frame_num < 189 + builder->refs[idxb].frame_num ? 234 190 -1 : 1; 235 191 236 - poca = builder->refs[idxa].pic_order_count; 237 - pocb = builder->refs[idxb].pic_order_count; 192 + poca = v4l2_h264_get_poc(builder, ptra); 193 + pocb = v4l2_h264_get_poc(builder, ptrb); 238 194 239 195 /* 240 196 * Short term pics with POC > cur POC first in POC ascending order ··· 250 206 return poca < pocb ? -1 : 1; 251 207 } 252 208 209 + /* 210 + * The references need to be reordered so that references are alternating 211 + * between top and bottom field references starting with the current picture 212 + * parity. This has to be done for short term and long term references 213 + * separately. 214 + */ 215 + static void reorder_field_reflist(const struct v4l2_h264_reflist_builder *b, 216 + struct v4l2_h264_reference *reflist) 217 + { 218 + struct v4l2_h264_reference tmplist[V4L2_H264_REF_LIST_LEN]; 219 + u8 lt, i = 0, j = 0, k = 0; 220 + 221 + memcpy(tmplist, reflist, sizeof(tmplist[0]) * b->num_valid); 222 + 223 + for (lt = 0; lt <= 1; lt++) { 224 + do { 225 + for (; i < b->num_valid && b->refs[tmplist[i].index].longterm == lt; i++) { 226 + if (tmplist[i].fields == b->cur_pic_fields) { 227 + reflist[k++] = tmplist[i++]; 228 + break; 229 + } 230 + } 231 + 232 + for (; j < b->num_valid && b->refs[tmplist[j].index].longterm == lt; j++) { 233 + if (tmplist[j].fields != b->cur_pic_fields) { 234 + reflist[k++] = tmplist[j++]; 235 + break; 236 + } 237 + } 238 + } while ((i < b->num_valid && b->refs[tmplist[i].index].longterm == lt) || 239 + (j < b->num_valid && b->refs[tmplist[j].index].longterm == lt)); 240 + } 241 + } 242 + 243 + static char ref_type_to_char(u8 ref_type) 244 + { 245 + switch (ref_type) { 246 + case V4L2_H264_FRAME_REF: 247 + return 'f'; 248 + case V4L2_H264_TOP_FIELD_REF: 249 + return 't'; 250 + case V4L2_H264_BOTTOM_FIELD_REF: 251 + return 'b'; 252 + } 253 + 254 + return '?'; 255 + } 256 + 257 + static const char *format_ref_list_p(const struct v4l2_h264_reflist_builder *builder, 258 + struct v4l2_h264_reference *reflist, 259 + char **out_str) 260 + { 261 + int n = 0, i; 262 + 263 + *out_str = kmalloc(tmp_str_size, GFP_KERNEL); 264 + 265 + n += snprintf(*out_str + n, tmp_str_size - n, "|"); 266 + 267 + for (i = 0; i < builder->num_valid; i++) { 268 + /* this is pic_num for frame and frame_num (wrapped) for field, 269 + * but for frame pic_num is equal to frame_num (wrapped). 270 + */ 271 + int frame_num = builder->refs[reflist[i].index].frame_num; 272 + bool longterm = builder->refs[reflist[i].index].longterm; 273 + 274 + n += scnprintf(*out_str + n, tmp_str_size - n, "%i%c%c|", 275 + frame_num, longterm ? 'l' : 's', 276 + ref_type_to_char(reflist[i].fields)); 277 + } 278 + 279 + return *out_str; 280 + } 281 + 282 + static void print_ref_list_p(const struct v4l2_h264_reflist_builder *builder, 283 + struct v4l2_h264_reference *reflist) 284 + { 285 + char *buf = NULL; 286 + 287 + pr_debug("ref_pic_list_p (cur_poc %u%c) %s\n", 288 + builder->cur_pic_order_count, 289 + ref_type_to_char(builder->cur_pic_fields), 290 + format_ref_list_p(builder, reflist, &buf)); 291 + 292 + kfree(buf); 293 + } 294 + 295 + static const char *format_ref_list_b(const struct v4l2_h264_reflist_builder *builder, 296 + struct v4l2_h264_reference *reflist, 297 + char **out_str) 298 + { 299 + int n = 0, i; 300 + 301 + *out_str = kmalloc(tmp_str_size, GFP_KERNEL); 302 + 303 + n += snprintf(*out_str + n, tmp_str_size - n, "|"); 304 + 305 + for (i = 0; i < builder->num_valid; i++) { 306 + int frame_num = builder->refs[reflist[i].index].frame_num; 307 + u32 poc = v4l2_h264_get_poc(builder, reflist + i); 308 + bool longterm = builder->refs[reflist[i].index].longterm; 309 + 310 + n += scnprintf(*out_str + n, tmp_str_size - n, "%i%c%c|", 311 + longterm ? frame_num : poc, 312 + longterm ? 'l' : 's', 313 + ref_type_to_char(reflist[i].fields)); 314 + } 315 + 316 + return *out_str; 317 + } 318 + 319 + static void print_ref_list_b(const struct v4l2_h264_reflist_builder *builder, 320 + struct v4l2_h264_reference *reflist, u8 list_num) 321 + { 322 + char *buf = NULL; 323 + 324 + pr_debug("ref_pic_list_b%u (cur_poc %u%c) %s", 325 + list_num, builder->cur_pic_order_count, 326 + ref_type_to_char(builder->cur_pic_fields), 327 + format_ref_list_b(builder, reflist, &buf)); 328 + 329 + kfree(buf); 330 + } 331 + 253 332 /** 254 333 * v4l2_h264_build_p_ref_list() - Build the P reference list 255 334 * 256 335 * @builder: reference list builder context 257 - * @reflist: 16-bytes array used to store the P reference list. Each entry 258 - * is an index in the DPB 336 + * @reflist: 32 sized array used to store the P reference list. Each entry 337 + * is a v4l2_h264_reference structure 259 338 * 260 339 * This functions builds the P reference lists. This procedure is describe in 261 340 * section '8.2.4 Decoding process for reference picture lists construction' ··· 387 220 */ 388 221 void 389 222 v4l2_h264_build_p_ref_list(const struct v4l2_h264_reflist_builder *builder, 390 - u8 *reflist) 223 + struct v4l2_h264_reference *reflist) 391 224 { 392 225 memcpy(reflist, builder->unordered_reflist, 393 226 sizeof(builder->unordered_reflist[0]) * builder->num_valid); 394 227 sort_r(reflist, builder->num_valid, sizeof(*reflist), 395 228 v4l2_h264_p_ref_list_cmp, NULL, builder); 229 + 230 + if (builder->cur_pic_fields != V4L2_H264_FRAME_REF) 231 + reorder_field_reflist(builder, reflist); 232 + 233 + print_ref_list_p(builder, reflist); 396 234 } 397 235 EXPORT_SYMBOL_GPL(v4l2_h264_build_p_ref_list); 398 236 ··· 405 233 * v4l2_h264_build_b_ref_lists() - Build the B0/B1 reference lists 406 234 * 407 235 * @builder: reference list builder context 408 - * @b0_reflist: 16-bytes array used to store the B0 reference list. Each entry 409 - * is an index in the DPB 410 - * @b1_reflist: 16-bytes array used to store the B1 reference list. Each entry 411 - * is an index in the DPB 236 + * @b0_reflist: 32 sized array used to store the B0 reference list. Each entry 237 + * is a v4l2_h264_reference structure 238 + * @b1_reflist: 32 sized array used to store the B1 reference list. Each entry 239 + * is a v4l2_h264_reference structure 412 240 * 413 241 * This functions builds the B0/B1 reference lists. This procedure is described 414 242 * in section '8.2.4 Decoding process for reference picture lists construction' ··· 417 245 */ 418 246 void 419 247 v4l2_h264_build_b_ref_lists(const struct v4l2_h264_reflist_builder *builder, 420 - u8 *b0_reflist, u8 *b1_reflist) 248 + struct v4l2_h264_reference *b0_reflist, 249 + struct v4l2_h264_reference *b1_reflist) 421 250 { 422 251 memcpy(b0_reflist, builder->unordered_reflist, 423 252 sizeof(builder->unordered_reflist[0]) * builder->num_valid); ··· 430 257 sort_r(b1_reflist, builder->num_valid, sizeof(*b1_reflist), 431 258 v4l2_h264_b1_ref_list_cmp, NULL, builder); 432 259 260 + if (builder->cur_pic_fields != V4L2_H264_FRAME_REF) { 261 + reorder_field_reflist(builder, b0_reflist); 262 + reorder_field_reflist(builder, b1_reflist); 263 + } 264 + 433 265 if (builder->num_valid > 1 && 434 266 !memcmp(b1_reflist, b0_reflist, builder->num_valid)) 435 267 swap(b1_reflist[0], b1_reflist[1]); 268 + 269 + print_ref_list_b(builder, b0_reflist, 0); 270 + print_ref_list_b(builder, b1_reflist, 1); 436 271 } 437 272 EXPORT_SYMBOL_GPL(v4l2_h264_build_b_ref_lists); 438 273

+7

drivers/media/v4l2-core/v4l2-ioctl.c

··· 18 18 19 19 #include <linux/videodev2.h> 20 20 21 + #include <media/media-device.h> /* for media_set_bus_info() */ 21 22 #include <media/v4l2-common.h> 22 23 #include <media/v4l2-ioctl.h> 23 24 #include <media/v4l2-ctrls.h> ··· 1053 1052 cap->device_caps = vfd->device_caps; 1054 1053 cap->capabilities = vfd->device_caps | V4L2_CAP_DEVICE_CAPS; 1055 1054 1055 + media_set_bus_info(cap->bus_info, sizeof(cap->bus_info), 1056 + vfd->dev_parent); 1057 + 1056 1058 ret = ops->vidioc_querycap(file, fh, cap); 1057 1059 1058 1060 /* ··· 1269 1265 case V4L2_PIX_FMT_Y16_BE: descr = "16-bit Greyscale BE"; break; 1270 1266 case V4L2_PIX_FMT_Y10BPACK: descr = "10-bit Greyscale (Packed)"; break; 1271 1267 case V4L2_PIX_FMT_Y10P: descr = "10-bit Greyscale (MIPI Packed)"; break; 1268 + case V4L2_PIX_FMT_IPU3_Y10: descr = "10-bit greyscale (IPU3 Packed)"; break; 1272 1269 case V4L2_PIX_FMT_Y8I: descr = "Interleaved 8-bit Greyscale"; break; 1273 1270 case V4L2_PIX_FMT_Y12I: descr = "Interleaved 12-bit Greyscale"; break; 1274 1271 case V4L2_PIX_FMT_Z16: descr = "16-bit Depth"; break; ··· 1446 1441 case V4L2_PIX_FMT_SE401: descr = "GSPCA SE401"; break; 1447 1442 case V4L2_PIX_FMT_S5C_UYVY_JPG: descr = "S5C73MX interleaved UYVY/JPEG"; break; 1448 1443 case V4L2_PIX_FMT_MT21C: descr = "Mediatek Compressed Format"; break; 1444 + case V4L2_PIX_FMT_QC08C: descr = "QCOM Compressed 8-bit Format"; break; 1445 + case V4L2_PIX_FMT_QC10C: descr = "QCOM Compressed 10-bit Format"; break; 1449 1446 default: 1450 1447 if (fmt->description[0]) 1451 1448 return;

+5 -4

drivers/media/v4l2-core/v4l2-mem2mem.c

··· 68 68 * struct v4l2_m2m_dev - per-device context 69 69 * @source: &struct media_entity pointer with the source entity 70 70 * Used only when the M2M device is registered via 71 - * v4l2_m2m_unregister_media_controller(). 71 + * v4l2_m2m_register_media_controller(). 72 72 * @source_pad: &struct media_pad with the source pad. 73 73 * Used only when the M2M device is registered via 74 - * v4l2_m2m_unregister_media_controller(). 74 + * v4l2_m2m_register_media_controller(). 75 75 * @sink: &struct media_entity pointer with the sink entity 76 76 * Used only when the M2M device is registered via 77 - * v4l2_m2m_unregister_media_controller(). 77 + * v4l2_m2m_register_media_controller(). 78 78 * @sink_pad: &struct media_pad with the sink pad. 79 79 * Used only when the M2M device is registered via 80 - * v4l2_m2m_unregister_media_controller(). 80 + * v4l2_m2m_register_media_controller(). 81 81 * @proc: &struct media_entity pointer with the M2M device itself. 82 82 * @proc_pads: &struct media_pad with the @proc pads. 83 83 * Used only when the M2M device is registered via ··· 336 336 if (src && dst && dst->is_held && 337 337 dst->vb2_buf.copied_timestamp && 338 338 dst->vb2_buf.timestamp != src->vb2_buf.timestamp) { 339 + dprintk("Timestamp mismatch, returning held capture buffer\n"); 339 340 dst->is_held = false; 340 341 v4l2_m2m_dst_buf_remove(m2m_ctx); 341 342 v4l2_m2m_buf_done(dst, VB2_BUF_STATE_DONE);

+187 -32

drivers/media/v4l2-core/v4l2-subdev.c

··· 27 27 static int subdev_fh_init(struct v4l2_subdev_fh *fh, struct v4l2_subdev *sd) 28 28 { 29 29 struct v4l2_subdev_state *state; 30 + static struct lock_class_key key; 30 31 31 - state = v4l2_subdev_alloc_state(sd); 32 + state = __v4l2_subdev_state_alloc(sd, "fh->state->lock", &key); 32 33 if (IS_ERR(state)) 33 34 return PTR_ERR(state); 34 35 ··· 40 39 41 40 static void subdev_fh_free(struct v4l2_subdev_fh *fh) 42 41 { 43 - v4l2_subdev_free_state(fh->state); 42 + __v4l2_subdev_state_free(fh->state); 44 43 fh->state = NULL; 45 44 } 46 45 ··· 64 63 v4l2_fh_init(&subdev_fh->vfh, vdev); 65 64 v4l2_fh_add(&subdev_fh->vfh); 66 65 file->private_data = &subdev_fh->vfh; 67 - #if defined(CONFIG_MEDIA_CONTROLLER) 66 + 68 67 if (sd->v4l2_dev->mdev && sd->entity.graph_obj.mdev->dev) { 69 68 struct module *owner; 70 69 ··· 75 74 } 76 75 subdev_fh->owner = owner; 77 76 } 78 - #endif 79 77 80 78 if (sd->internal_ops && sd->internal_ops->open) { 81 79 ret = sd->internal_ops->open(sd, subdev_fh); ··· 318 318 sd->ops->pad->get_mbus_config(sd, pad, config); 319 319 } 320 320 321 + #ifdef CONFIG_MEDIA_CONTROLLER 322 + /* 323 + * Create state-management wrapper for pad ops dealing with subdev state. The 324 + * wrapper handles the case where the caller does not provide the called 325 + * subdev's state. This should be removed when all the callers are fixed. 326 + */ 327 + #define DEFINE_STATE_WRAPPER(f, arg_type) \ 328 + static int call_##f##_state(struct v4l2_subdev *sd, \ 329 + struct v4l2_subdev_state *_state, \ 330 + arg_type *arg) \ 331 + { \ 332 + struct v4l2_subdev_state *state = _state; \ 333 + int ret; \ 334 + if (!_state) \ 335 + state = v4l2_subdev_lock_and_get_active_state(sd); \ 336 + ret = call_##f(sd, state, arg); \ 337 + if (!_state && state) \ 338 + v4l2_subdev_unlock_state(state); \ 339 + return ret; \ 340 + } 341 + 342 + #else /* CONFIG_MEDIA_CONTROLLER */ 343 + 344 + #define DEFINE_STATE_WRAPPER(f, arg_type) \ 345 + static int call_##f##_state(struct v4l2_subdev *sd, \ 346 + struct v4l2_subdev_state *state, \ 347 + arg_type *arg) \ 348 + { \ 349 + return call_##f(sd, state, arg); \ 350 + } 351 + 352 + #endif /* CONFIG_MEDIA_CONTROLLER */ 353 + 354 + DEFINE_STATE_WRAPPER(get_fmt, struct v4l2_subdev_format); 355 + DEFINE_STATE_WRAPPER(set_fmt, struct v4l2_subdev_format); 356 + DEFINE_STATE_WRAPPER(enum_mbus_code, struct v4l2_subdev_mbus_code_enum); 357 + DEFINE_STATE_WRAPPER(enum_frame_size, struct v4l2_subdev_frame_size_enum); 358 + DEFINE_STATE_WRAPPER(enum_frame_interval, struct v4l2_subdev_frame_interval_enum); 359 + DEFINE_STATE_WRAPPER(get_selection, struct v4l2_subdev_selection); 360 + DEFINE_STATE_WRAPPER(set_selection, struct v4l2_subdev_selection); 361 + 321 362 static const struct v4l2_subdev_pad_ops v4l2_subdev_call_pad_wrappers = { 322 - .get_fmt = call_get_fmt, 323 - .set_fmt = call_set_fmt, 324 - .enum_mbus_code = call_enum_mbus_code, 325 - .enum_frame_size = call_enum_frame_size, 326 - .enum_frame_interval = call_enum_frame_interval, 327 - .get_selection = call_get_selection, 328 - .set_selection = call_set_selection, 363 + .get_fmt = call_get_fmt_state, 364 + .set_fmt = call_set_fmt_state, 365 + .enum_mbus_code = call_enum_mbus_code_state, 366 + .enum_frame_size = call_enum_frame_size_state, 367 + .enum_frame_interval = call_enum_frame_interval_state, 368 + .get_selection = call_get_selection_state, 369 + .set_selection = call_set_selection_state, 329 370 .get_edid = call_get_edid, 330 371 .set_edid = call_set_edid, 331 372 .dv_timings_cap = call_dv_timings_cap, ··· 386 345 EXPORT_SYMBOL(v4l2_subdev_call_wrappers); 387 346 388 347 #if defined(CONFIG_VIDEO_V4L2_SUBDEV_API) 389 - static long subdev_do_ioctl(struct file *file, unsigned int cmd, void *arg) 348 + 349 + static struct v4l2_subdev_state * 350 + subdev_ioctl_get_state(struct v4l2_subdev *sd, struct v4l2_subdev_fh *subdev_fh, 351 + unsigned int cmd, void *arg) 352 + { 353 + u32 which; 354 + 355 + switch (cmd) { 356 + default: 357 + return NULL; 358 + case VIDIOC_SUBDEV_G_FMT: 359 + case VIDIOC_SUBDEV_S_FMT: 360 + which = ((struct v4l2_subdev_format *)arg)->which; 361 + break; 362 + case VIDIOC_SUBDEV_G_CROP: 363 + case VIDIOC_SUBDEV_S_CROP: 364 + which = ((struct v4l2_subdev_crop *)arg)->which; 365 + break; 366 + case VIDIOC_SUBDEV_ENUM_MBUS_CODE: 367 + which = ((struct v4l2_subdev_mbus_code_enum *)arg)->which; 368 + break; 369 + case VIDIOC_SUBDEV_ENUM_FRAME_SIZE: 370 + which = ((struct v4l2_subdev_frame_size_enum *)arg)->which; 371 + break; 372 + case VIDIOC_SUBDEV_ENUM_FRAME_INTERVAL: 373 + which = ((struct v4l2_subdev_frame_interval_enum *)arg)->which; 374 + break; 375 + case VIDIOC_SUBDEV_G_SELECTION: 376 + case VIDIOC_SUBDEV_S_SELECTION: 377 + which = ((struct v4l2_subdev_selection *)arg)->which; 378 + break; 379 + } 380 + 381 + return which == V4L2_SUBDEV_FORMAT_TRY ? 382 + subdev_fh->state : 383 + v4l2_subdev_get_unlocked_active_state(sd); 384 + } 385 + 386 + static long subdev_do_ioctl(struct file *file, unsigned int cmd, void *arg, 387 + struct v4l2_subdev_state *state) 390 388 { 391 389 struct video_device *vdev = video_devdata(file); 392 390 struct v4l2_subdev *sd = vdev_to_v4l2_subdev(vdev); 393 391 struct v4l2_fh *vfh = file->private_data; 394 - struct v4l2_subdev_fh *subdev_fh = to_v4l2_subdev_fh(vfh); 395 392 bool ro_subdev = test_bit(V4L2_FL_SUBDEV_RO_DEVNODE, &vdev->flags); 396 393 int rval; 397 394 ··· 555 476 556 477 memset(format->reserved, 0, sizeof(format->reserved)); 557 478 memset(format->format.reserved, 0, sizeof(format->format.reserved)); 558 - return v4l2_subdev_call(sd, pad, get_fmt, subdev_fh->state, format); 479 + return v4l2_subdev_call(sd, pad, get_fmt, state, format); 559 480 } 560 481 561 482 case VIDIOC_SUBDEV_S_FMT: { ··· 566 487 567 488 memset(format->reserved, 0, sizeof(format->reserved)); 568 489 memset(format->format.reserved, 0, sizeof(format->format.reserved)); 569 - return v4l2_subdev_call(sd, pad, set_fmt, subdev_fh->state, format); 490 + return v4l2_subdev_call(sd, pad, set_fmt, state, format); 570 491 } 571 492 572 493 case VIDIOC_SUBDEV_G_CROP: { ··· 580 501 sel.target = V4L2_SEL_TGT_CROP; 581 502 582 503 rval = v4l2_subdev_call( 583 - sd, pad, get_selection, subdev_fh->state, &sel); 504 + sd, pad, get_selection, state, &sel); 584 505 585 506 crop->rect = sel.r; 586 507 ··· 602 523 sel.r = crop->rect; 603 524 604 525 rval = v4l2_subdev_call( 605 - sd, pad, set_selection, subdev_fh->state, &sel); 526 + sd, pad, set_selection, state, &sel); 606 527 607 528 crop->rect = sel.r; 608 529 ··· 613 534 struct v4l2_subdev_mbus_code_enum *code = arg; 614 535 615 536 memset(code->reserved, 0, sizeof(code->reserved)); 616 - return v4l2_subdev_call(sd, pad, enum_mbus_code, subdev_fh->state, 537 + return v4l2_subdev_call(sd, pad, enum_mbus_code, state, 617 538 code); 618 539 } 619 540 ··· 621 542 struct v4l2_subdev_frame_size_enum *fse = arg; 622 543 623 544 memset(fse->reserved, 0, sizeof(fse->reserved)); 624 - return v4l2_subdev_call(sd, pad, enum_frame_size, subdev_fh->state, 545 + return v4l2_subdev_call(sd, pad, enum_frame_size, state, 625 546 fse); 626 547 } 627 548 ··· 646 567 struct v4l2_subdev_frame_interval_enum *fie = arg; 647 568 648 569 memset(fie->reserved, 0, sizeof(fie->reserved)); 649 - return v4l2_subdev_call(sd, pad, enum_frame_interval, subdev_fh->state, 570 + return v4l2_subdev_call(sd, pad, enum_frame_interval, state, 650 571 fie); 651 572 } 652 573 ··· 655 576 656 577 memset(sel->reserved, 0, sizeof(sel->reserved)); 657 578 return v4l2_subdev_call( 658 - sd, pad, get_selection, subdev_fh->state, sel); 579 + sd, pad, get_selection, state, sel); 659 580 } 660 581 661 582 case VIDIOC_SUBDEV_S_SELECTION: { ··· 666 587 667 588 memset(sel->reserved, 0, sizeof(sel->reserved)); 668 589 return v4l2_subdev_call( 669 - sd, pad, set_selection, subdev_fh->state, sel); 590 + sd, pad, set_selection, state, sel); 670 591 } 671 592 672 593 case VIDIOC_G_EDID: { ··· 745 666 746 667 if (lock && mutex_lock_interruptible(lock)) 747 668 return -ERESTARTSYS; 748 - if (video_is_registered(vdev)) 749 - ret = subdev_do_ioctl(file, cmd, arg); 669 + 670 + if (video_is_registered(vdev)) { 671 + struct v4l2_subdev *sd = vdev_to_v4l2_subdev(vdev); 672 + struct v4l2_fh *vfh = file->private_data; 673 + struct v4l2_subdev_fh *subdev_fh = to_v4l2_subdev_fh(vfh); 674 + struct v4l2_subdev_state *state; 675 + 676 + state = subdev_ioctl_get_state(sd, subdev_fh, cmd, arg); 677 + 678 + if (state) 679 + v4l2_subdev_lock_state(state); 680 + 681 + ret = subdev_do_ioctl(file, cmd, arg, state); 682 + 683 + if (state) 684 + v4l2_subdev_unlock_state(state); 685 + } 686 + 750 687 if (lock) 751 688 mutex_unlock(lock); 752 689 return ret; ··· 919 824 920 825 fmt->which = V4L2_SUBDEV_FORMAT_ACTIVE; 921 826 fmt->pad = pad->index; 922 - return v4l2_subdev_call(sd, pad, get_fmt, NULL, fmt); 827 + return v4l2_subdev_call_state_active(sd, pad, get_fmt, fmt); 923 828 } 924 829 925 830 WARN(pad->entity->function != MEDIA_ENT_F_IO_V4L, ··· 957 862 } 958 863 EXPORT_SYMBOL_GPL(v4l2_subdev_link_validate); 959 864 960 - struct v4l2_subdev_state *v4l2_subdev_alloc_state(struct v4l2_subdev *sd) 865 + struct v4l2_subdev_state * 866 + __v4l2_subdev_state_alloc(struct v4l2_subdev *sd, const char *lock_name, 867 + struct lock_class_key *lock_key) 961 868 { 962 869 struct v4l2_subdev_state *state; 963 870 int ret; ··· 968 871 if (!state) 969 872 return ERR_PTR(-ENOMEM); 970 873 874 + __mutex_init(&state->_lock, lock_name, lock_key); 875 + if (sd->state_lock) 876 + state->lock = sd->state_lock; 877 + else 878 + state->lock = &state->_lock; 879 + 971 880 if (sd->entity.num_pads) { 972 - state->pads = kvmalloc_array(sd->entity.num_pads, 973 - sizeof(*state->pads), 974 - GFP_KERNEL | __GFP_ZERO); 881 + state->pads = kvcalloc(sd->entity.num_pads, 882 + sizeof(*state->pads), GFP_KERNEL); 975 883 if (!state->pads) { 976 884 ret = -ENOMEM; 977 885 goto err; 978 886 } 979 887 } 980 888 889 + /* 890 + * There can be no race at this point, but we lock the state anyway to 891 + * satisfy lockdep checks. 892 + */ 893 + v4l2_subdev_lock_state(state); 981 894 ret = v4l2_subdev_call(sd, pad, init_cfg, state); 895 + v4l2_subdev_unlock_state(state); 896 + 982 897 if (ret < 0 && ret != -ENOIOCTLCMD) 983 898 goto err; 984 899 ··· 1004 895 1005 896 return ERR_PTR(ret); 1006 897 } 1007 - EXPORT_SYMBOL_GPL(v4l2_subdev_alloc_state); 898 + EXPORT_SYMBOL_GPL(__v4l2_subdev_state_alloc); 1008 899 1009 - void v4l2_subdev_free_state(struct v4l2_subdev_state *state) 900 + void __v4l2_subdev_state_free(struct v4l2_subdev_state *state) 1010 901 { 1011 902 if (!state) 1012 903 return; 1013 904 905 + mutex_destroy(&state->_lock); 906 + 1014 907 kvfree(state->pads); 1015 908 kfree(state); 1016 909 } 1017 - EXPORT_SYMBOL_GPL(v4l2_subdev_free_state); 910 + EXPORT_SYMBOL_GPL(__v4l2_subdev_state_free); 911 + 912 + int __v4l2_subdev_init_finalize(struct v4l2_subdev *sd, const char *name, 913 + struct lock_class_key *key) 914 + { 915 + struct v4l2_subdev_state *state; 916 + 917 + state = __v4l2_subdev_state_alloc(sd, name, key); 918 + if (IS_ERR(state)) 919 + return PTR_ERR(state); 920 + 921 + sd->active_state = state; 922 + 923 + return 0; 924 + } 925 + EXPORT_SYMBOL_GPL(__v4l2_subdev_init_finalize); 926 + 927 + void v4l2_subdev_cleanup(struct v4l2_subdev *sd) 928 + { 929 + __v4l2_subdev_state_free(sd->active_state); 930 + sd->active_state = NULL; 931 + } 932 + EXPORT_SYMBOL_GPL(v4l2_subdev_cleanup); 933 + 934 + #if defined(CONFIG_VIDEO_V4L2_SUBDEV_API) 935 + 936 + int v4l2_subdev_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_state *state, 937 + struct v4l2_subdev_format *format) 938 + { 939 + struct v4l2_mbus_framefmt *fmt; 940 + 941 + if (format->pad >= sd->entity.num_pads) 942 + return -EINVAL; 943 + 944 + fmt = v4l2_subdev_get_pad_format(sd, state, format->pad); 945 + if (!fmt) 946 + return -EINVAL; 947 + 948 + format->format = *fmt; 949 + 950 + return 0; 951 + } 952 + EXPORT_SYMBOL_GPL(v4l2_subdev_get_fmt); 953 + 954 + #endif /* CONFIG_VIDEO_V4L2_SUBDEV_API */ 1018 955 1019 956 #endif /* CONFIG_MEDIA_CONTROLLER */ 1020 957

+2 -2

drivers/staging/media/atomisp/pci/runtime/rmgr/src/rmgr_vbuf.c

··· 254 254 void ia_css_rmgr_acq_vbuf(struct ia_css_rmgr_vbuf_pool *pool, 255 255 struct ia_css_rmgr_vbuf_handle **handle) 256 256 { 257 - struct ia_css_rmgr_vbuf_handle h; 257 + struct ia_css_rmgr_vbuf_handle h = { 0 }; 258 258 259 259 if ((!pool) || (!handle) || (!*handle)) { 260 260 IA_CSS_LOG("Invalid inputs"); ··· 272 272 h.size = (*handle)->size; 273 273 /* release ref to current buffer */ 274 274 ia_css_rmgr_refcount_release_vbuf(handle); 275 - *handle = &h; 275 + **handle = h; 276 276 } 277 277 /* get new buffer for needed size */ 278 278 if ((*handle)->vptr == 0x0) {

+23 -23

drivers/staging/media/av7110/av7110_av.c

··· 595 595 case PROG_STREAM_MAP: 596 596 case PRIVATE_STREAM2: 597 597 case PROG_STREAM_DIR: 598 - case ECM_STREAM : 599 - case EMM_STREAM : 600 - case PADDING_STREAM : 601 - case DSM_CC_STREAM : 598 + case ECM_STREAM: 599 + case EMM_STREAM: 600 + case PADDING_STREAM: 601 + case DSM_CC_STREAM: 602 602 case ISO13522_STREAM: 603 603 case PRIVATE_STREAM1: 604 604 case AUDIO_STREAM_S ... AUDIO_STREAM_E: ··· 659 659 case PROG_STREAM_MAP: 660 660 case PRIVATE_STREAM2: 661 661 case PROG_STREAM_DIR: 662 - case ECM_STREAM : 663 - case EMM_STREAM : 664 - case PADDING_STREAM : 665 - case DSM_CC_STREAM : 662 + case ECM_STREAM: 663 + case EMM_STREAM: 664 + case PADDING_STREAM: 665 + case DSM_CC_STREAM: 666 666 case ISO13522_STREAM: 667 667 case PRIVATE_STREAM1: 668 668 case AUDIO_STREAM_S ... AUDIO_STREAM_E: ··· 770 770 if (length > 3 && 771 771 buf[0] == 0x00 && buf[1] == 0x00 && buf[2] == 0x01) 772 772 switch (buf[3]) { 773 - case PROG_STREAM_MAP: 774 - case PRIVATE_STREAM2: 775 - case PROG_STREAM_DIR: 776 - case ECM_STREAM : 777 - case EMM_STREAM : 778 - case PADDING_STREAM : 779 - case DSM_CC_STREAM : 780 - case ISO13522_STREAM: 781 - case PRIVATE_STREAM1: 782 - case AUDIO_STREAM_S ... AUDIO_STREAM_E: 783 - case VIDEO_STREAM_S ... VIDEO_STREAM_E: 784 - pes_start = 1; 785 - break; 773 + case PROG_STREAM_MAP: 774 + case PRIVATE_STREAM2: 775 + case PROG_STREAM_DIR: 776 + case ECM_STREAM: 777 + case EMM_STREAM: 778 + case PADDING_STREAM: 779 + case DSM_CC_STREAM: 780 + case ISO13522_STREAM: 781 + case PRIVATE_STREAM1: 782 + case AUDIO_STREAM_S ... AUDIO_STREAM_E: 783 + case VIDEO_STREAM_S ... VIDEO_STREAM_E: 784 + pes_start = 1; 785 + break; 786 786 787 - default: 788 - break; 787 + default: 788 + break; 789 789 } 790 790 791 791 while (c < length) {

+2 -6

drivers/staging/media/hantro/TODO

··· 1 - * Support for VP8, VP9 and H264 is planned for this driver. 2 - 3 - Given the V4L controls for those CODECs will be part of 4 - the uABI, it will be required to have the driver in staging. 5 - 6 - For this reason, we are keeping this driver in staging for now. 1 + The V4L controls for the HEVC CODEC are not yet part of the stable uABI, 2 + we are keeping this driver in staging until the HEVC uABI has been merged.

+2

drivers/staging/media/hantro/hantro.h

··· 475 475 void hantro_postproc_enable(struct hantro_ctx *ctx); 476 476 void hantro_postproc_free(struct hantro_ctx *ctx); 477 477 int hantro_postproc_alloc(struct hantro_ctx *ctx); 478 + int hanto_postproc_enum_framesizes(struct hantro_ctx *ctx, 479 + struct v4l2_frmsizeenum *fsize); 478 480 479 481 #endif /* HANTRO_H_ */

+16 -2

drivers/staging/media/hantro/hantro_drv.c

··· 56 56 return hantro_get_dec_buf_addr(ctx, buf); 57 57 } 58 58 59 + static const struct v4l2_event hantro_eos_event = { 60 + .type = V4L2_EVENT_EOS 61 + }; 62 + 59 63 static void hantro_job_finish_no_pm(struct hantro_dev *vpu, 60 64 struct hantro_ctx *ctx, 61 65 enum vb2_buffer_state result) ··· 76 72 77 73 src->sequence = ctx->sequence_out++; 78 74 dst->sequence = ctx->sequence_cap++; 75 + 76 + if (v4l2_m2m_is_last_draining_src_buf(ctx->fh.m2m_ctx, src)) { 77 + dst->flags |= V4L2_BUF_FLAG_LAST; 78 + v4l2_event_queue_fh(&ctx->fh, &hantro_eos_event); 79 + v4l2_m2m_mark_stopped(ctx->fh.m2m_ctx); 80 + } 79 81 80 82 v4l2_m2m_buf_done_and_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx, 81 83 result); ··· 638 628 { .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, }, 639 629 { .compatible = "rockchip,rk3328-vpu", .data = &rk3328_vpu_variant, }, 640 630 { .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, }, 631 + { .compatible = "rockchip,rk3568-vpu", .data = &rk3568_vpu_variant, }, 641 632 #endif 642 633 #ifdef CONFIG_VIDEO_HANTRO_IMX8M 643 634 { .compatible = "nxp,imx8mm-vpu-g1", .data = &imx8mm_vpu_g1_variant, }, ··· 820 809 snprintf(vfd->name, sizeof(vfd->name), "%s-%s", match->compatible, 821 810 funcid == MEDIA_ENT_F_PROC_VIDEO_ENCODER ? "enc" : "dec"); 822 811 823 - if (funcid == MEDIA_ENT_F_PROC_VIDEO_ENCODER) 812 + if (funcid == MEDIA_ENT_F_PROC_VIDEO_ENCODER) { 824 813 vpu->encoder = func; 825 - else 814 + } else { 826 815 vpu->decoder = func; 816 + v4l2_disable_ioctl(vfd, VIDIOC_TRY_ENCODER_CMD); 817 + v4l2_disable_ioctl(vfd, VIDIOC_ENCODER_CMD); 818 + } 827 819 828 820 video_set_drvdata(vfd, vpu); 829 821

+19 -19

drivers/staging/media/hantro/hantro_g1_h264_dec.c

··· 126 126 127 127 static void set_ref(struct hantro_ctx *ctx) 128 128 { 129 - const u8 *b0_reflist, *b1_reflist, *p_reflist; 129 + const struct v4l2_h264_reference *b0_reflist, *b1_reflist, *p_reflist; 130 130 struct hantro_dev *vpu = ctx->dev; 131 131 int reg_num; 132 132 u32 reg; ··· 157 157 */ 158 158 reg_num = 0; 159 159 for (i = 0; i < 15; i += 3) { 160 - reg = G1_REG_BD_REF_PIC_BINIT_RLIST_F0(b0_reflist[i]) | 161 - G1_REG_BD_REF_PIC_BINIT_RLIST_F1(b0_reflist[i + 1]) | 162 - G1_REG_BD_REF_PIC_BINIT_RLIST_F2(b0_reflist[i + 2]) | 163 - G1_REG_BD_REF_PIC_BINIT_RLIST_B0(b1_reflist[i]) | 164 - G1_REG_BD_REF_PIC_BINIT_RLIST_B1(b1_reflist[i + 1]) | 165 - G1_REG_BD_REF_PIC_BINIT_RLIST_B2(b1_reflist[i + 2]); 160 + reg = G1_REG_BD_REF_PIC_BINIT_RLIST_F0(b0_reflist[i].index) | 161 + G1_REG_BD_REF_PIC_BINIT_RLIST_F1(b0_reflist[i + 1].index) | 162 + G1_REG_BD_REF_PIC_BINIT_RLIST_F2(b0_reflist[i + 2].index) | 163 + G1_REG_BD_REF_PIC_BINIT_RLIST_B0(b1_reflist[i].index) | 164 + G1_REG_BD_REF_PIC_BINIT_RLIST_B1(b1_reflist[i + 1].index) | 165 + G1_REG_BD_REF_PIC_BINIT_RLIST_B2(b1_reflist[i + 2].index); 166 166 vdpu_write_relaxed(vpu, reg, G1_REG_BD_REF_PIC(reg_num++)); 167 167 } 168 168 ··· 171 171 * of forward and backward reference picture lists and first 4 entries 172 172 * of P forward picture list. 173 173 */ 174 - reg = G1_REG_BD_P_REF_PIC_BINIT_RLIST_F15(b0_reflist[15]) | 175 - G1_REG_BD_P_REF_PIC_BINIT_RLIST_B15(b1_reflist[15]) | 176 - G1_REG_BD_P_REF_PIC_PINIT_RLIST_F0(p_reflist[0]) | 177 - G1_REG_BD_P_REF_PIC_PINIT_RLIST_F1(p_reflist[1]) | 178 - G1_REG_BD_P_REF_PIC_PINIT_RLIST_F2(p_reflist[2]) | 179 - G1_REG_BD_P_REF_PIC_PINIT_RLIST_F3(p_reflist[3]); 174 + reg = G1_REG_BD_P_REF_PIC_BINIT_RLIST_F15(b0_reflist[15].index) | 175 + G1_REG_BD_P_REF_PIC_BINIT_RLIST_B15(b1_reflist[15].index) | 176 + G1_REG_BD_P_REF_PIC_PINIT_RLIST_F0(p_reflist[0].index) | 177 + G1_REG_BD_P_REF_PIC_PINIT_RLIST_F1(p_reflist[1].index) | 178 + G1_REG_BD_P_REF_PIC_PINIT_RLIST_F2(p_reflist[2].index) | 179 + G1_REG_BD_P_REF_PIC_PINIT_RLIST_F3(p_reflist[3].index); 180 180 vdpu_write_relaxed(vpu, reg, G1_REG_BD_P_REF_PIC); 181 181 182 182 /* ··· 185 185 */ 186 186 reg_num = 0; 187 187 for (i = 4; i < HANTRO_H264_DPB_SIZE; i += 6) { 188 - reg = G1_REG_FWD_PIC_PINIT_RLIST_F0(p_reflist[i]) | 189 - G1_REG_FWD_PIC_PINIT_RLIST_F1(p_reflist[i + 1]) | 190 - G1_REG_FWD_PIC_PINIT_RLIST_F2(p_reflist[i + 2]) | 191 - G1_REG_FWD_PIC_PINIT_RLIST_F3(p_reflist[i + 3]) | 192 - G1_REG_FWD_PIC_PINIT_RLIST_F4(p_reflist[i + 4]) | 193 - G1_REG_FWD_PIC_PINIT_RLIST_F5(p_reflist[i + 5]); 188 + reg = G1_REG_FWD_PIC_PINIT_RLIST_F0(p_reflist[i].index) | 189 + G1_REG_FWD_PIC_PINIT_RLIST_F1(p_reflist[i + 1].index) | 190 + G1_REG_FWD_PIC_PINIT_RLIST_F2(p_reflist[i + 2].index) | 191 + G1_REG_FWD_PIC_PINIT_RLIST_F3(p_reflist[i + 3].index) | 192 + G1_REG_FWD_PIC_PINIT_RLIST_F4(p_reflist[i + 4].index) | 193 + G1_REG_FWD_PIC_PINIT_RLIST_F5(p_reflist[i + 5].index); 194 194 vdpu_write_relaxed(vpu, reg, G1_REG_FWD_PIC(reg_num++)); 195 195 } 196 196

+21 -15

drivers/staging/media/hantro/hantro_g2_hevc_dec.c

··· 8 8 #include "hantro_hw.h" 9 9 #include "hantro_g2_regs.h" 10 10 11 + #define G2_ALIGN 16 12 + 13 + static size_t hantro_hevc_chroma_offset(struct hantro_ctx *ctx) 14 + { 15 + return ctx->dst_fmt.width * ctx->dst_fmt.height; 16 + } 17 + 18 + static size_t hantro_hevc_motion_vectors_offset(struct hantro_ctx *ctx) 19 + { 20 + size_t cr_offset = hantro_hevc_chroma_offset(ctx); 21 + 22 + return ALIGN((cr_offset * 3) / 2, G2_ALIGN); 23 + } 24 + 11 25 static void prepare_tile_info_buffer(struct hantro_ctx *ctx) 12 26 { 13 27 struct hantro_dev *vpu = ctx->dev; ··· 74 60 no_chroma = 1; 75 61 for (j = 0, tmp_w = 0; j < num_tile_cols - 1; j++) { 76 62 tmp_w += pps->column_width_minus1[j] + 1; 77 - *p++ = pps->column_width_minus1[j + 1]; 63 + *p++ = pps->column_width_minus1[j] + 1; 78 64 *p++ = h; 79 65 if (i == 0 && h == 1 && ctb_size == 16) 80 66 no_chroma = 1; ··· 194 180 hantro_reg_write(vpu, &g2_max_cu_qpd_depth, 0); 195 181 } 196 182 197 - if (pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT) { 198 - hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset); 199 - hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset); 200 - } else { 201 - hantro_reg_write(vpu, &g2_cb_qp_offset, 0); 202 - hantro_reg_write(vpu, &g2_cr_qp_offset, 0); 203 - } 183 + hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset); 184 + hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset); 204 185 205 186 hantro_reg_write(vpu, &g2_filt_offset_beta, pps->pps_beta_offset_div2); 206 187 hantro_reg_write(vpu, &g2_filt_offset_tc, pps->pps_tc_offset_div2); ··· 344 335 static int set_ref(struct hantro_ctx *ctx) 345 336 { 346 337 const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls; 347 - const struct v4l2_ctrl_hevc_sps *sps = ctrls->sps; 348 338 const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps; 349 339 const struct v4l2_ctrl_hevc_decode_params *decode_params = ctrls->decode_params; 350 340 const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; ··· 351 343 struct hantro_dev *vpu = ctx->dev; 352 344 struct vb2_v4l2_buffer *vb2_dst; 353 345 struct hantro_decoded_buffer *dst; 354 - size_t cr_offset = hantro_hevc_chroma_offset(sps); 355 - size_t mv_offset = hantro_hevc_motion_vectors_offset(sps); 346 + size_t cr_offset = hantro_hevc_chroma_offset(ctx); 347 + size_t mv_offset = hantro_hevc_motion_vectors_offset(ctx); 356 348 u32 max_ref_frames; 357 349 u16 dpb_longterm_e; 358 350 static const struct hantro_reg cur_poc[] = { ··· 414 406 415 407 set_ref_pic_list(ctx); 416 408 417 - /* We will only keep the references picture that are still used */ 418 - ctx->hevc_dec.ref_bufs_used = 0; 409 + /* We will only keep the reference pictures that are still used */ 410 + hantro_hevc_ref_init(ctx); 419 411 420 412 /* Set up addresses of DPB buffers */ 421 413 dpb_longterm_e = 0; ··· 455 447 hantro_write_addr(vpu, G2_OUT_LUMA_ADDR, luma_addr); 456 448 hantro_write_addr(vpu, G2_OUT_CHROMA_ADDR, chroma_addr); 457 449 hantro_write_addr(vpu, G2_OUT_MV_ADDR, mv_addr); 458 - 459 - hantro_hevc_ref_remove_unused(ctx); 460 450 461 451 for (; i < V4L2_HEVC_DPB_ENTRIES_NUM_MAX; i++) { 462 452 hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), 0);

+6

drivers/staging/media/hantro/hantro_g2_regs.h

··· 290 290 #define g2_buswidth G2_DEC_REG(58, 8, 0x7) 291 291 #define g2_max_burst G2_DEC_REG(58, 0, 0xff) 292 292 293 + #define g2_down_scale_e G2_DEC_REG(184, 7, 0x1) 294 + #define g2_down_scale_y G2_DEC_REG(184, 2, 0x3) 295 + #define g2_down_scale_x G2_DEC_REG(184, 0, 0x3) 296 + 293 297 #define G2_REG_CONFIG G2_SWREG(58) 294 298 #define G2_REG_CONFIG_DEC_CLK_GATE_E BIT(16) 295 299 #define G2_REG_CONFIG_DEC_CLK_GATE_IDLE_E BIT(17) ··· 316 312 #define G2_TILE_FILTER_ADDR (G2_SWREG(179)) 317 313 #define G2_TILE_SAO_ADDR (G2_SWREG(181)) 318 314 #define G2_TILE_BSD_ADDR (G2_SWREG(183)) 315 + #define G2_DS_DST (G2_SWREG(186)) 316 + #define G2_DS_DST_CHR (G2_SWREG(188)) 319 317 320 318 #define g2_strm_buffer_len G2_DEC_REG(258, 0, 0xffffffff) 321 319 #define g2_strm_start_offset G2_DEC_REG(259, 0, 0xffffffff)

+112 -22

drivers/staging/media/hantro/hantro_h264.c

··· 22 22 #define POC_BUFFER_SIZE 34 23 23 #define SCALING_LIST_SIZE (6 * 16 + 2 * 64) 24 24 25 + /* 26 + * For valid and long term reference marking, index are reversed, so bit 31 27 + * indicates the status of the picture 0. 28 + */ 29 + #define REF_BIT(i) BIT(32 - 1 - (i)) 30 + 25 31 /* Data structure describing auxiliary buffer format. */ 26 32 struct hantro_h264_dec_priv_tbl { 27 33 u32 cabac_table[CABAC_INIT_BUFFER_SIZE]; ··· 233 227 { 234 228 const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; 235 229 const struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode; 230 + const struct v4l2_ctrl_h264_sps *sps = ctrls->sps; 236 231 struct hantro_h264_dec_priv_tbl *tbl = ctx->h264_dec.priv.cpu; 237 232 const struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb; 238 233 u32 dpb_longterm = 0; ··· 244 237 tbl->poc[i * 2] = dpb[i].top_field_order_cnt; 245 238 tbl->poc[i * 2 + 1] = dpb[i].bottom_field_order_cnt; 246 239 240 + if (!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_VALID)) 241 + continue; 242 + 247 243 /* 248 244 * Set up bit maps of valid and long term DPBs. 249 - * NOTE: The bits are reversed, i.e. MSb is DPB 0. 245 + * NOTE: The bits are reversed, i.e. MSb is DPB 0. For frame 246 + * decoding, bit 31 to 15 are used, while for field decoding, 247 + * all bits are used, with bit 31 being a top field, 30 a bottom 248 + * field and so on. 250 249 */ 251 - if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) 252 - dpb_valid |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); 253 - if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) 254 - dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); 255 - } 256 - ctx->h264_dec.dpb_valid = dpb_valid << 16; 257 - ctx->h264_dec.dpb_longterm = dpb_longterm << 16; 250 + if (dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC) { 251 + if (dpb[i].fields & V4L2_H264_TOP_FIELD_REF) 252 + dpb_valid |= REF_BIT(i * 2); 258 253 259 - tbl->poc[32] = dec_param->top_field_order_cnt; 260 - tbl->poc[33] = dec_param->bottom_field_order_cnt; 254 + if (dpb[i].fields & V4L2_H264_BOTTOM_FIELD_REF) 255 + dpb_valid |= REF_BIT(i * 2 + 1); 256 + 257 + if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) { 258 + dpb_longterm |= REF_BIT(i * 2); 259 + dpb_longterm |= REF_BIT(i * 2 + 1); 260 + } 261 + } else { 262 + dpb_valid |= REF_BIT(i); 263 + 264 + if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) 265 + dpb_longterm |= REF_BIT(i); 266 + } 267 + } 268 + ctx->h264_dec.dpb_valid = dpb_valid; 269 + ctx->h264_dec.dpb_longterm = dpb_longterm; 270 + 271 + if ((dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC) || 272 + !(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD)) { 273 + tbl->poc[32] = ctx->h264_dec.cur_poc; 274 + tbl->poc[33] = 0; 275 + } else { 276 + tbl->poc[32] = dec_param->top_field_order_cnt; 277 + tbl->poc[33] = dec_param->bottom_field_order_cnt; 278 + } 261 279 262 280 assemble_scaling_list(ctx); 263 281 } ··· 290 258 static bool dpb_entry_match(const struct v4l2_h264_dpb_entry *a, 291 259 const struct v4l2_h264_dpb_entry *b) 292 260 { 293 - return a->top_field_order_cnt == b->top_field_order_cnt && 294 - a->bottom_field_order_cnt == b->bottom_field_order_cnt; 261 + return a->reference_ts == b->reference_ts; 295 262 } 296 263 297 264 static void update_dpb(struct hantro_ctx *ctx) ··· 304 273 305 274 /* Disable all entries by default. */ 306 275 for (i = 0; i < ARRAY_SIZE(ctx->h264_dec.dpb); i++) 307 - ctx->h264_dec.dpb[i].flags &= ~V4L2_H264_DPB_ENTRY_FLAG_ACTIVE; 276 + ctx->h264_dec.dpb[i].flags = 0; 308 277 309 278 /* Try to match new DPB entries with existing ones by their POCs. */ 310 279 for (i = 0; i < ARRAY_SIZE(dec_param->dpb); i++) { 311 280 const struct v4l2_h264_dpb_entry *ndpb = &dec_param->dpb[i]; 312 281 313 - if (!(ndpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) 282 + if (!(ndpb->flags & V4L2_H264_DPB_ENTRY_FLAG_VALID)) 314 283 continue; 315 284 316 285 /* ··· 321 290 struct v4l2_h264_dpb_entry *cdpb; 322 291 323 292 cdpb = &ctx->h264_dec.dpb[j]; 324 - if (cdpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE || 325 - !dpb_entry_match(cdpb, ndpb)) 293 + if (!dpb_entry_match(cdpb, ndpb)) 326 294 continue; 327 295 328 296 *cdpb = *ndpb; ··· 358 328 { 359 329 struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb; 360 330 dma_addr_t dma_addr = 0; 331 + s32 cur_poc = ctx->h264_dec.cur_poc; 332 + u32 flags; 361 333 362 334 if (dpb[dpb_idx].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) 363 335 dma_addr = hantro_get_ref(ctx, dpb[dpb_idx].reference_ts); ··· 377 345 dma_addr = hantro_get_dec_buf_addr(ctx, buf); 378 346 } 379 347 380 - return dma_addr; 348 + flags = dpb[dpb_idx].flags & V4L2_H264_DPB_ENTRY_FLAG_FIELD ? 0x2 : 0; 349 + flags |= abs(dpb[dpb_idx].top_field_order_cnt - cur_poc) < 350 + abs(dpb[dpb_idx].bottom_field_order_cnt - cur_poc) ? 351 + 0x1 : 0; 352 + 353 + return dma_addr | flags; 381 354 } 382 355 383 356 u16 hantro_h264_get_ref_nbr(struct hantro_ctx *ctx, unsigned int dpb_idx) ··· 391 354 392 355 if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) 393 356 return 0; 394 - if (dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) 395 - return dpb->pic_num; 396 357 return dpb->frame_num; 358 + } 359 + 360 + /* 361 + * Removes all references with the same parity as the current picture from the 362 + * reference list. The remaining list will have references with the opposite 363 + * parity. This is effectively a deduplication of references since each buffer 364 + * stores two fields. For this reason, each buffer is found twice in the 365 + * reference list. 366 + * 367 + * This technique has been chosen through trial and error. This simple approach 368 + * resulted in the highest conformance score. Note that this method may suffer 369 + * worse quality in the case an opposite reference frame has been lost. If this 370 + * becomes a problem in the future, it should be possible to add a preprocessing 371 + * to identify un-paired fields and avoid removing them. 372 + */ 373 + static void deduplicate_reflist(struct v4l2_h264_reflist_builder *b, 374 + struct v4l2_h264_reference *reflist) 375 + { 376 + int write_idx = 0; 377 + int i; 378 + 379 + if (b->cur_pic_fields == V4L2_H264_FRAME_REF) { 380 + write_idx = b->num_valid; 381 + goto done; 382 + } 383 + 384 + for (i = 0; i < b->num_valid; i++) { 385 + if (!(b->cur_pic_fields == reflist[i].fields)) { 386 + reflist[write_idx++] = reflist[i]; 387 + continue; 388 + } 389 + } 390 + 391 + done: 392 + /* Should not happen unless we have a bug in the reflist builder. */ 393 + if (WARN_ON(write_idx > 16)) 394 + write_idx = 16; 395 + 396 + /* Clear the remaining, some streams fails otherwise */ 397 + for (; write_idx < 16; write_idx++) 398 + reflist[write_idx].index = 15; 397 399 } 398 400 399 401 int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx) ··· 466 390 /* Update the DPB with new refs. */ 467 391 update_dpb(ctx); 468 392 469 - /* Prepare data in memory. */ 470 - prepare_table(ctx); 471 - 472 393 /* Build the P/B{0,1} ref lists. */ 473 394 v4l2_h264_init_reflist_builder(&reflist_builder, ctrls->decode, 474 395 ctrls->sps, ctx->h264_dec.dpb); 396 + h264_ctx->cur_poc = reflist_builder.cur_pic_order_count; 397 + 398 + /* Prepare data in memory. */ 399 + prepare_table(ctx); 400 + 475 401 v4l2_h264_build_p_ref_list(&reflist_builder, h264_ctx->reflists.p); 476 402 v4l2_h264_build_b_ref_lists(&reflist_builder, h264_ctx->reflists.b0, 477 403 h264_ctx->reflists.b1); 404 + 405 + /* 406 + * Reduce ref lists to at most 16 entries, Hantro hardware will deduce 407 + * the actual picture lists in field through the dpb_valid, 408 + * dpb_longterm bitmap along with the current frame parity. 409 + */ 410 + if (reflist_builder.cur_pic_fields != V4L2_H264_FRAME_REF) { 411 + deduplicate_reflist(&reflist_builder, h264_ctx->reflists.p); 412 + deduplicate_reflist(&reflist_builder, h264_ctx->reflists.b0); 413 + deduplicate_reflist(&reflist_builder, h264_ctx->reflists.b1); 414 + } 415 + 478 416 return 0; 479 417 } 480 418

+4 -42

drivers/staging/media/hantro/hantro_hevc.c

··· 25 25 #define MAX_TILE_COLS 20 26 26 #define MAX_TILE_ROWS 22 27 27 28 - #define UNUSED_REF -1 29 - 30 - #define G2_ALIGN 16 31 - 32 - size_t hantro_hevc_chroma_offset(const struct v4l2_ctrl_hevc_sps *sps) 33 - { 34 - int bytes_per_pixel = sps->bit_depth_luma_minus8 == 0 ? 1 : 2; 35 - 36 - return sps->pic_width_in_luma_samples * 37 - sps->pic_height_in_luma_samples * bytes_per_pixel; 38 - } 39 - 40 - size_t hantro_hevc_motion_vectors_offset(const struct v4l2_ctrl_hevc_sps *sps) 41 - { 42 - size_t cr_offset = hantro_hevc_chroma_offset(sps); 43 - 44 - return ALIGN((cr_offset * 3) / 2, G2_ALIGN); 45 - } 46 - 47 - static void hantro_hevc_ref_init(struct hantro_ctx *ctx) 28 + void hantro_hevc_ref_init(struct hantro_ctx *ctx) 48 29 { 49 30 struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec; 50 - int i; 51 31 52 - for (i = 0; i < NUM_REF_PICTURES; i++) 53 - hevc_dec->ref_bufs_poc[i] = UNUSED_REF; 32 + hevc_dec->ref_bufs_used = 0; 54 33 } 55 34 56 35 dma_addr_t hantro_hevc_get_ref_buf(struct hantro_ctx *ctx, ··· 38 59 struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec; 39 60 int i; 40 61 41 - /* Find the reference buffer in already know ones */ 62 + /* Find the reference buffer in already known ones */ 42 63 for (i = 0; i < NUM_REF_PICTURES; i++) { 43 64 if (hevc_dec->ref_bufs_poc[i] == poc) { 44 65 hevc_dec->ref_bufs_used |= 1 << i; ··· 56 77 57 78 /* Add a new reference buffer */ 58 79 for (i = 0; i < NUM_REF_PICTURES; i++) { 59 - if (hevc_dec->ref_bufs_poc[i] == UNUSED_REF) { 80 + if (!(hevc_dec->ref_bufs_used & 1 << i)) { 60 81 hevc_dec->ref_bufs_used |= 1 << i; 61 82 hevc_dec->ref_bufs_poc[i] = poc; 62 83 hevc_dec->ref_bufs[i].dma = addr; ··· 65 86 } 66 87 67 88 return -EINVAL; 68 - } 69 - 70 - void hantro_hevc_ref_remove_unused(struct hantro_ctx *ctx) 71 - { 72 - struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec; 73 - int i; 74 - 75 - /* Just tag buffer as unused, do not free them */ 76 - for (i = 0; i < NUM_REF_PICTURES; i++) { 77 - if (hevc_dec->ref_bufs_poc[i] == UNUSED_REF) 78 - continue; 79 - 80 - if (hevc_dec->ref_bufs_used & (1 << i)) 81 - continue; 82 - 83 - hevc_dec->ref_bufs_poc[i] = UNUSED_REF; 84 - } 85 89 } 86 90 87 91 static int tile_buffer_reallocate(struct hantro_ctx *ctx)

+13 -8

drivers/staging/media/hantro/hantro_hw.h

··· 69 69 * @b1: B1 reflist 70 70 */ 71 71 struct hantro_h264_dec_reflists { 72 - u8 p[HANTRO_H264_DPB_SIZE]; 73 - u8 b0[HANTRO_H264_DPB_SIZE]; 74 - u8 b1[HANTRO_H264_DPB_SIZE]; 72 + struct v4l2_h264_reference p[V4L2_H264_REF_LIST_LEN]; 73 + struct v4l2_h264_reference b0[V4L2_H264_REF_LIST_LEN]; 74 + struct v4l2_h264_reference b1[V4L2_H264_REF_LIST_LEN]; 75 75 }; 76 76 77 77 /** ··· 83 83 * @ctrls: V4L2 controls attached to a run 84 84 * @dpb_longterm: DPB long-term 85 85 * @dpb_valid: DPB valid 86 + * @cur_poc: Current picture order count 86 87 */ 87 88 struct hantro_h264_dec_hw_ctx { 88 89 struct hantro_aux_buf priv; ··· 92 91 struct hantro_h264_dec_ctrls ctrls; 93 92 u32 dpb_longterm; 94 93 u32 dpb_valid; 94 + s32 cur_poc; 95 95 }; 96 96 97 97 /** ··· 247 245 /** 248 246 * struct hantro_postproc_ops - post-processor operations 249 247 * 250 - * @enable: Enable the post-processor block. Optional. 251 - * @disable: Disable the post-processor block. Optional. 248 + * @enable: Enable the post-processor block. Optional. 249 + * @disable: Disable the post-processor block. Optional. 250 + * @enum_framesizes: Enumerate possible scaled output formats. 251 + * Returns zero if OK, a negative value in error cases. 252 + * Optional. 252 253 */ 253 254 struct hantro_postproc_ops { 254 255 void (*enable)(struct hantro_ctx *ctx); 255 256 void (*disable)(struct hantro_ctx *ctx); 257 + int (*enum_framesizes)(struct hantro_ctx *ctx, struct v4l2_frmsizeenum *fsize); 256 258 }; 257 259 258 260 /** ··· 306 300 extern const struct hantro_variant rk3288_vpu_variant; 307 301 extern const struct hantro_variant rk3328_vpu_variant; 308 302 extern const struct hantro_variant rk3399_vpu_variant; 303 + extern const struct hantro_variant rk3568_vpu_variant; 309 304 extern const struct hantro_variant sama5d4_vdec_variant; 310 305 extern const struct hantro_variant sunxi_vpu_variant; 311 306 ··· 344 337 void hantro_hevc_dec_exit(struct hantro_ctx *ctx); 345 338 int hantro_g2_hevc_dec_run(struct hantro_ctx *ctx); 346 339 int hantro_hevc_dec_prepare_run(struct hantro_ctx *ctx); 340 + void hantro_hevc_ref_init(struct hantro_ctx *ctx); 347 341 dma_addr_t hantro_hevc_get_ref_buf(struct hantro_ctx *ctx, int poc); 348 342 int hantro_hevc_add_ref_buf(struct hantro_ctx *ctx, int poc, dma_addr_t addr); 349 - void hantro_hevc_ref_remove_unused(struct hantro_ctx *ctx); 350 - size_t hantro_hevc_chroma_offset(const struct v4l2_ctrl_hevc_sps *sps); 351 - size_t hantro_hevc_motion_vectors_offset(const struct v4l2_ctrl_hevc_sps *sps); 352 343 353 344 static inline unsigned short hantro_vp9_num_sbs(unsigned short dimension) 354 345 {

+51 -2

drivers/staging/media/hantro/hantro_postproc.c

··· 100 100 HANTRO_PP_REG_WRITE(vpu, display_width, ctx->dst_fmt.width); 101 101 } 102 102 103 + static int down_scale_factor(struct hantro_ctx *ctx) 104 + { 105 + if (ctx->src_fmt.width == ctx->dst_fmt.width) 106 + return 0; 107 + 108 + return DIV_ROUND_CLOSEST(ctx->src_fmt.width, ctx->dst_fmt.width); 109 + } 110 + 103 111 static void hantro_postproc_g2_enable(struct hantro_ctx *ctx) 104 112 { 105 113 struct hantro_dev *vpu = ctx->dev; 106 114 struct vb2_v4l2_buffer *dst_buf; 107 115 size_t chroma_offset = ctx->dst_fmt.width * ctx->dst_fmt.height; 116 + int down_scale = down_scale_factor(ctx); 108 117 dma_addr_t dst_dma; 109 118 110 119 dst_buf = hantro_get_dst_buf(ctx); 111 120 dst_dma = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); 112 121 113 - hantro_write_addr(vpu, G2_RS_OUT_LUMA_ADDR, dst_dma); 114 - hantro_write_addr(vpu, G2_RS_OUT_CHROMA_ADDR, dst_dma + chroma_offset); 122 + if (down_scale) { 123 + hantro_reg_write(vpu, &g2_down_scale_e, 1); 124 + hantro_reg_write(vpu, &g2_down_scale_y, down_scale >> 2); 125 + hantro_reg_write(vpu, &g2_down_scale_x, down_scale >> 2); 126 + hantro_write_addr(vpu, G2_DS_DST, dst_dma); 127 + hantro_write_addr(vpu, G2_DS_DST_CHR, dst_dma + (chroma_offset >> down_scale)); 128 + } else { 129 + hantro_write_addr(vpu, G2_RS_OUT_LUMA_ADDR, dst_dma); 130 + hantro_write_addr(vpu, G2_RS_OUT_CHROMA_ADDR, dst_dma + chroma_offset); 131 + } 115 132 hantro_reg_write(vpu, &g2_out_rs_e, 1); 133 + } 134 + 135 + static int hantro_postproc_g2_enum_framesizes(struct hantro_ctx *ctx, 136 + struct v4l2_frmsizeenum *fsize) 137 + { 138 + /** 139 + * G2 scaler can scale down by 0, 2, 4 or 8 140 + * use fsize->index has power of 2 diviser 141 + **/ 142 + if (fsize->index > 3) 143 + return -EINVAL; 144 + 145 + if (!ctx->src_fmt.width || !ctx->src_fmt.height) 146 + return -EINVAL; 147 + 148 + fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE; 149 + fsize->discrete.width = ctx->src_fmt.width >> fsize->index; 150 + fsize->discrete.height = ctx->src_fmt.height >> fsize->index; 151 + 152 + return 0; 116 153 } 117 154 118 155 void hantro_postproc_free(struct hantro_ctx *ctx) ··· 234 197 vpu->variant->postproc_ops->enable(ctx); 235 198 } 236 199 200 + int hanto_postproc_enum_framesizes(struct hantro_ctx *ctx, 201 + struct v4l2_frmsizeenum *fsize) 202 + { 203 + struct hantro_dev *vpu = ctx->dev; 204 + 205 + if (vpu->variant->postproc_ops && vpu->variant->postproc_ops->enum_framesizes) 206 + return vpu->variant->postproc_ops->enum_framesizes(ctx, fsize); 207 + 208 + return -EINVAL; 209 + } 210 + 237 211 const struct hantro_postproc_ops hantro_g1_postproc_ops = { 238 212 .enable = hantro_postproc_g1_enable, 239 213 .disable = hantro_postproc_g1_disable, ··· 253 205 const struct hantro_postproc_ops hantro_g2_postproc_ops = { 254 206 .enable = hantro_postproc_g2_enable, 255 207 .disable = hantro_postproc_g2_disable, 208 + .enum_framesizes = hantro_postproc_g2_enum_framesizes, 256 209 };

+97 -10

drivers/staging/media/hantro/hantro_v4l2.c

··· 116 116 struct hantro_ctx *ctx = fh_to_ctx(priv); 117 117 const struct hantro_fmt *fmt; 118 118 119 - if (fsize->index != 0) { 120 - vpu_debug(0, "invalid frame size index (expected 0, got %d)\n", 121 - fsize->index); 122 - return -EINVAL; 123 - } 124 - 125 119 fmt = hantro_find_format(ctx, fsize->pixel_format); 126 120 if (!fmt) { 127 121 vpu_debug(0, "unsupported bitstream format (%08x)\n", ··· 123 129 return -EINVAL; 124 130 } 125 131 126 - /* This only makes sense for coded formats */ 127 - if (fmt->codec_mode == HANTRO_MODE_NONE) 132 + /* For non-coded formats check if postprocessing scaling is possible */ 133 + if (fmt->codec_mode == HANTRO_MODE_NONE && hantro_needs_postproc(ctx, fmt)) { 134 + return hanto_postproc_enum_framesizes(ctx, fsize); 135 + } else if (fsize->index != 0) { 136 + vpu_debug(0, "invalid frame size index (expected 0, got %d)\n", 137 + fsize->index); 128 138 return -EINVAL; 139 + } 129 140 130 141 fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; 131 142 fsize->stepwise = fmt->frmsize; ··· 408 409 } 409 410 } 410 411 412 + static void 413 + hantro_update_requires_hold_capture_buf(struct hantro_ctx *ctx, u32 fourcc) 414 + { 415 + struct vb2_queue *vq; 416 + 417 + vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, 418 + V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); 419 + 420 + switch (fourcc) { 421 + case V4L2_PIX_FMT_JPEG: 422 + case V4L2_PIX_FMT_MPEG2_SLICE: 423 + case V4L2_PIX_FMT_VP8_FRAME: 424 + case V4L2_PIX_FMT_HEVC_SLICE: 425 + case V4L2_PIX_FMT_VP9_FRAME: 426 + vq->subsystem_flags &= ~(VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF); 427 + break; 428 + case V4L2_PIX_FMT_H264_SLICE: 429 + vq->subsystem_flags |= VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF; 430 + break; 431 + default: 432 + break; 433 + } 434 + } 435 + 411 436 static int hantro_set_fmt_out(struct hantro_ctx *ctx, 412 437 struct v4l2_pix_format_mplane *pix_mp) 413 438 { ··· 495 472 ctx->dst_fmt.quantization = pix_mp->quantization; 496 473 497 474 hantro_update_requires_request(ctx, pix_mp->pixelformat); 475 + hantro_update_requires_hold_capture_buf(ctx, pix_mp->pixelformat); 498 476 499 477 vpu_debug(0, "OUTPUT codec mode: %d\n", ctx->vpu_src_fmt->codec_mode); 500 478 vpu_debug(0, "fmt - w: %d, h: %d\n", ··· 652 628 return 0; 653 629 } 654 630 631 + static const struct v4l2_event hantro_eos_event = { 632 + .type = V4L2_EVENT_EOS 633 + }; 634 + 635 + static int vidioc_encoder_cmd(struct file *file, void *priv, 636 + struct v4l2_encoder_cmd *ec) 637 + { 638 + struct hantro_ctx *ctx = fh_to_ctx(priv); 639 + int ret; 640 + 641 + ret = v4l2_m2m_ioctl_try_encoder_cmd(file, priv, ec); 642 + if (ret < 0) 643 + return ret; 644 + 645 + if (!vb2_is_streaming(v4l2_m2m_get_src_vq(ctx->fh.m2m_ctx)) || 646 + !vb2_is_streaming(v4l2_m2m_get_dst_vq(ctx->fh.m2m_ctx))) 647 + return 0; 648 + 649 + ret = v4l2_m2m_ioctl_encoder_cmd(file, priv, ec); 650 + if (ret < 0) 651 + return ret; 652 + 653 + if (ec->cmd == V4L2_ENC_CMD_STOP && 654 + v4l2_m2m_has_stopped(ctx->fh.m2m_ctx)) 655 + v4l2_event_queue_fh(&ctx->fh, &hantro_eos_event); 656 + 657 + if (ec->cmd == V4L2_ENC_CMD_START) 658 + vb2_clear_last_buffer_dequeued(&ctx->fh.m2m_ctx->cap_q_ctx.q); 659 + 660 + return 0; 661 + } 662 + 655 663 const struct v4l2_ioctl_ops hantro_ioctl_ops = { 656 664 .vidioc_querycap = vidioc_querycap, 657 665 .vidioc_enum_framesizes = vidioc_enum_framesizes, ··· 713 657 714 658 .vidioc_g_selection = vidioc_g_selection, 715 659 .vidioc_s_selection = vidioc_s_selection, 660 + 661 + .vidioc_try_encoder_cmd = v4l2_m2m_ioctl_try_encoder_cmd, 662 + .vidioc_encoder_cmd = vidioc_encoder_cmd, 716 663 }; 717 664 718 665 static int ··· 792 733 * (for OUTPUT buffers, if userspace passes 0 bytesused, v4l2-core sets 793 734 * it to buffer length). 794 735 */ 795 - if (V4L2_TYPE_IS_CAPTURE(vq->type)) 796 - vb2_set_plane_payload(vb, 0, pix_fmt->plane_fmt[0].sizeimage); 736 + if (V4L2_TYPE_IS_CAPTURE(vq->type)) { 737 + if (ctx->is_encoder) 738 + vb2_set_plane_payload(vb, 0, 0); 739 + else 740 + vb2_set_plane_payload(vb, 0, pix_fmt->plane_fmt[0].sizeimage); 741 + } 797 742 798 743 return 0; 799 744 } ··· 806 743 { 807 744 struct hantro_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); 808 745 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 746 + 747 + if (V4L2_TYPE_IS_CAPTURE(vb->vb2_queue->type) && 748 + vb2_is_streaming(vb->vb2_queue) && 749 + v4l2_m2m_dst_buf_is_last(ctx->fh.m2m_ctx)) { 750 + unsigned int i; 751 + 752 + for (i = 0; i < vb->num_planes; i++) 753 + vb2_set_plane_payload(vb, i, 0); 754 + 755 + vbuf->field = V4L2_FIELD_NONE; 756 + vbuf->sequence = ctx->sequence_cap++; 757 + 758 + v4l2_m2m_last_buffer_done(ctx->fh.m2m_ctx, vbuf); 759 + v4l2_event_queue_fh(&ctx->fh, &hantro_eos_event); 760 + return; 761 + } 809 762 810 763 v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf); 811 764 } ··· 837 758 { 838 759 struct hantro_ctx *ctx = vb2_get_drv_priv(q); 839 760 int ret = 0; 761 + 762 + v4l2_m2m_update_start_streaming_state(ctx->fh.m2m_ctx, q); 840 763 841 764 if (V4L2_TYPE_IS_OUTPUT(q->type)) 842 765 ctx->sequence_out = 0; ··· 912 831 hantro_return_bufs(q, v4l2_m2m_src_buf_remove); 913 832 else 914 833 hantro_return_bufs(q, v4l2_m2m_dst_buf_remove); 834 + 835 + v4l2_m2m_update_stop_streaming_state(ctx->fh.m2m_ctx, q); 836 + 837 + if (V4L2_TYPE_IS_OUTPUT(q->type) && 838 + v4l2_m2m_has_stopped(ctx->fh.m2m_ctx)) 839 + v4l2_event_queue_fh(&ctx->fh, &hantro_eos_event); 915 840 } 916 841 917 842 static void hantro_buf_request_complete(struct vb2_buffer *vb)

+49 -49

drivers/staging/media/hantro/rockchip_vpu2_hw_h264_dec.c

··· 298 298 299 299 static void set_ref(struct hantro_ctx *ctx) 300 300 { 301 - const u8 *b0_reflist, *b1_reflist, *p_reflist; 301 + const struct v4l2_h264_reference *b0_reflist, *b1_reflist, *p_reflist; 302 302 struct hantro_dev *vpu = ctx->dev; 303 303 u32 reg; 304 304 int i; ··· 307 307 b1_reflist = ctx->h264_dec.reflists.b1; 308 308 p_reflist = ctx->h264_dec.reflists.p; 309 309 310 - reg = VDPU_REG_PINIT_RLIST_F9(p_reflist[9]) | 311 - VDPU_REG_PINIT_RLIST_F8(p_reflist[8]) | 312 - VDPU_REG_PINIT_RLIST_F7(p_reflist[7]) | 313 - VDPU_REG_PINIT_RLIST_F6(p_reflist[6]) | 314 - VDPU_REG_PINIT_RLIST_F5(p_reflist[5]) | 315 - VDPU_REG_PINIT_RLIST_F4(p_reflist[4]); 310 + reg = VDPU_REG_PINIT_RLIST_F9(p_reflist[9].index) | 311 + VDPU_REG_PINIT_RLIST_F8(p_reflist[8].index) | 312 + VDPU_REG_PINIT_RLIST_F7(p_reflist[7].index) | 313 + VDPU_REG_PINIT_RLIST_F6(p_reflist[6].index) | 314 + VDPU_REG_PINIT_RLIST_F5(p_reflist[5].index) | 315 + VDPU_REG_PINIT_RLIST_F4(p_reflist[4].index); 316 316 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(74)); 317 317 318 - reg = VDPU_REG_PINIT_RLIST_F15(p_reflist[15]) | 319 - VDPU_REG_PINIT_RLIST_F14(p_reflist[14]) | 320 - VDPU_REG_PINIT_RLIST_F13(p_reflist[13]) | 321 - VDPU_REG_PINIT_RLIST_F12(p_reflist[12]) | 322 - VDPU_REG_PINIT_RLIST_F11(p_reflist[11]) | 323 - VDPU_REG_PINIT_RLIST_F10(p_reflist[10]); 318 + reg = VDPU_REG_PINIT_RLIST_F15(p_reflist[15].index) | 319 + VDPU_REG_PINIT_RLIST_F14(p_reflist[14].index) | 320 + VDPU_REG_PINIT_RLIST_F13(p_reflist[13].index) | 321 + VDPU_REG_PINIT_RLIST_F12(p_reflist[12].index) | 322 + VDPU_REG_PINIT_RLIST_F11(p_reflist[11].index) | 323 + VDPU_REG_PINIT_RLIST_F10(p_reflist[10].index); 324 324 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(75)); 325 325 326 326 reg = VDPU_REG_REFER1_NBR(hantro_h264_get_ref_nbr(ctx, 1)) | ··· 355 355 VDPU_REG_REFER14_NBR(hantro_h264_get_ref_nbr(ctx, 14)); 356 356 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(83)); 357 357 358 - reg = VDPU_REG_BINIT_RLIST_F5(b0_reflist[5]) | 359 - VDPU_REG_BINIT_RLIST_F4(b0_reflist[4]) | 360 - VDPU_REG_BINIT_RLIST_F3(b0_reflist[3]) | 361 - VDPU_REG_BINIT_RLIST_F2(b0_reflist[2]) | 362 - VDPU_REG_BINIT_RLIST_F1(b0_reflist[1]) | 363 - VDPU_REG_BINIT_RLIST_F0(b0_reflist[0]); 358 + reg = VDPU_REG_BINIT_RLIST_F5(b0_reflist[5].index) | 359 + VDPU_REG_BINIT_RLIST_F4(b0_reflist[4].index) | 360 + VDPU_REG_BINIT_RLIST_F3(b0_reflist[3].index) | 361 + VDPU_REG_BINIT_RLIST_F2(b0_reflist[2].index) | 362 + VDPU_REG_BINIT_RLIST_F1(b0_reflist[1].index) | 363 + VDPU_REG_BINIT_RLIST_F0(b0_reflist[0].index); 364 364 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(100)); 365 365 366 - reg = VDPU_REG_BINIT_RLIST_F11(b0_reflist[11]) | 367 - VDPU_REG_BINIT_RLIST_F10(b0_reflist[10]) | 368 - VDPU_REG_BINIT_RLIST_F9(b0_reflist[9]) | 369 - VDPU_REG_BINIT_RLIST_F8(b0_reflist[8]) | 370 - VDPU_REG_BINIT_RLIST_F7(b0_reflist[7]) | 371 - VDPU_REG_BINIT_RLIST_F6(b0_reflist[6]); 366 + reg = VDPU_REG_BINIT_RLIST_F11(b0_reflist[11].index) | 367 + VDPU_REG_BINIT_RLIST_F10(b0_reflist[10].index) | 368 + VDPU_REG_BINIT_RLIST_F9(b0_reflist[9].index) | 369 + VDPU_REG_BINIT_RLIST_F8(b0_reflist[8].index) | 370 + VDPU_REG_BINIT_RLIST_F7(b0_reflist[7].index) | 371 + VDPU_REG_BINIT_RLIST_F6(b0_reflist[6].index); 372 372 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(101)); 373 373 374 - reg = VDPU_REG_BINIT_RLIST_F15(b0_reflist[15]) | 375 - VDPU_REG_BINIT_RLIST_F14(b0_reflist[14]) | 376 - VDPU_REG_BINIT_RLIST_F13(b0_reflist[13]) | 377 - VDPU_REG_BINIT_RLIST_F12(b0_reflist[12]); 374 + reg = VDPU_REG_BINIT_RLIST_F15(b0_reflist[15].index) | 375 + VDPU_REG_BINIT_RLIST_F14(b0_reflist[14].index) | 376 + VDPU_REG_BINIT_RLIST_F13(b0_reflist[13].index) | 377 + VDPU_REG_BINIT_RLIST_F12(b0_reflist[12].index); 378 378 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(102)); 379 379 380 - reg = VDPU_REG_BINIT_RLIST_B5(b1_reflist[5]) | 381 - VDPU_REG_BINIT_RLIST_B4(b1_reflist[4]) | 382 - VDPU_REG_BINIT_RLIST_B3(b1_reflist[3]) | 383 - VDPU_REG_BINIT_RLIST_B2(b1_reflist[2]) | 384 - VDPU_REG_BINIT_RLIST_B1(b1_reflist[1]) | 385 - VDPU_REG_BINIT_RLIST_B0(b1_reflist[0]); 380 + reg = VDPU_REG_BINIT_RLIST_B5(b1_reflist[5].index) | 381 + VDPU_REG_BINIT_RLIST_B4(b1_reflist[4].index) | 382 + VDPU_REG_BINIT_RLIST_B3(b1_reflist[3].index) | 383 + VDPU_REG_BINIT_RLIST_B2(b1_reflist[2].index) | 384 + VDPU_REG_BINIT_RLIST_B1(b1_reflist[1].index) | 385 + VDPU_REG_BINIT_RLIST_B0(b1_reflist[0].index); 386 386 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(103)); 387 387 388 - reg = VDPU_REG_BINIT_RLIST_B11(b1_reflist[11]) | 389 - VDPU_REG_BINIT_RLIST_B10(b1_reflist[10]) | 390 - VDPU_REG_BINIT_RLIST_B9(b1_reflist[9]) | 391 - VDPU_REG_BINIT_RLIST_B8(b1_reflist[8]) | 392 - VDPU_REG_BINIT_RLIST_B7(b1_reflist[7]) | 393 - VDPU_REG_BINIT_RLIST_B6(b1_reflist[6]); 388 + reg = VDPU_REG_BINIT_RLIST_B11(b1_reflist[11].index) | 389 + VDPU_REG_BINIT_RLIST_B10(b1_reflist[10].index) | 390 + VDPU_REG_BINIT_RLIST_B9(b1_reflist[9].index) | 391 + VDPU_REG_BINIT_RLIST_B8(b1_reflist[8].index) | 392 + VDPU_REG_BINIT_RLIST_B7(b1_reflist[7].index) | 393 + VDPU_REG_BINIT_RLIST_B6(b1_reflist[6].index); 394 394 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(104)); 395 395 396 - reg = VDPU_REG_BINIT_RLIST_B15(b1_reflist[15]) | 397 - VDPU_REG_BINIT_RLIST_B14(b1_reflist[14]) | 398 - VDPU_REG_BINIT_RLIST_B13(b1_reflist[13]) | 399 - VDPU_REG_BINIT_RLIST_B12(b1_reflist[12]); 396 + reg = VDPU_REG_BINIT_RLIST_B15(b1_reflist[15].index) | 397 + VDPU_REG_BINIT_RLIST_B14(b1_reflist[14].index) | 398 + VDPU_REG_BINIT_RLIST_B13(b1_reflist[13].index) | 399 + VDPU_REG_BINIT_RLIST_B12(b1_reflist[12].index); 400 400 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(105)); 401 401 402 - reg = VDPU_REG_PINIT_RLIST_F3(p_reflist[3]) | 403 - VDPU_REG_PINIT_RLIST_F2(p_reflist[2]) | 404 - VDPU_REG_PINIT_RLIST_F1(p_reflist[1]) | 405 - VDPU_REG_PINIT_RLIST_F0(p_reflist[0]); 402 + reg = VDPU_REG_PINIT_RLIST_F3(p_reflist[3].index) | 403 + VDPU_REG_PINIT_RLIST_F2(p_reflist[2].index) | 404 + VDPU_REG_PINIT_RLIST_F1(p_reflist[1].index) | 405 + VDPU_REG_PINIT_RLIST_F0(p_reflist[0].index); 406 406 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(106)); 407 407 408 408 reg = VDPU_REG_REFER_LTERM_E(ctx->h264_dec.dpb_longterm);

+14

drivers/staging/media/hantro/rockchip_vpu_hw.c

··· 545 545 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) 546 546 }; 547 547 548 + const struct hantro_variant rk3568_vpu_variant = { 549 + .dec_offset = 0x400, 550 + .dec_fmts = rk3399_vpu_dec_fmts, 551 + .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts), 552 + .codec = HANTRO_MPEG2_DECODER | 553 + HANTRO_VP8_DECODER | HANTRO_H264_DECODER, 554 + .codec_ops = rk3399_vpu_codec_ops, 555 + .irqs = rockchip_vdpu2_irqs, 556 + .num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs), 557 + .init = rockchip_vpu_hw_init, 558 + .clk_names = rockchip_vpu_clk_names, 559 + .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) 560 + }; 561 + 548 562 const struct hantro_variant px30_vpu_variant = { 549 563 .enc_offset = 0x0, 550 564 .enc_fmts = rockchip_vpu_enc_fmts,

+3 -1

drivers/staging/media/ipu3/ipu3-css-fw.c

··· 117 117 unsigned int i, j, binary_nr; 118 118 int r; 119 119 120 - r = request_firmware(&css->fw, IMGU_FW_NAME, css->dev); 120 + r = request_firmware(&css->fw, IMGU_FW_NAME_20161208, css->dev); 121 + if (r == -ENOENT) 122 + r = request_firmware(&css->fw, IMGU_FW_NAME, css->dev); 121 123 if (r) 122 124 return r; 123 125

+3 -1

drivers/staging/media/ipu3/ipu3-css-fw.h

··· 6 6 7 7 /******************* Firmware file definitions *******************/ 8 8 9 - #define IMGU_FW_NAME "intel/ipu3-fw.bin" 9 + #define IMGU_FW_NAME "intel/ipu3-fw.bin" 10 + #define IMGU_FW_NAME_20161208 \ 11 + "intel/irci_irci_ecr-master_20161208_0213_20170112_1500.bin" 10 12 11 13 typedef u32 imgu_fw_ptr; 12 14

+20

drivers/staging/media/ipu3/ipu3-css-params.c

··· 2556 2556 /* Enable only for rightmost stripe, disable left */ 2557 2557 acc->af.stripes[0].grid_cfg.y_start &= 2558 2558 ~IPU3_UAPI_GRID_Y_START_EN; 2559 + acc->af.stripes[1].grid_cfg.x_start = 2560 + (acc->af.stripes[1].grid_cfg.x_start - 2561 + acc->stripe.down_scaled_stripes[1].offset) & 2562 + IPU3_UAPI_GRID_START_MASK; 2563 + b_w_log2 = acc->af.stripes[1].grid_cfg.block_width_log2; 2564 + acc->af.stripes[1].grid_cfg.x_end = 2565 + imgu_css_grid_end(acc->af.stripes[1].grid_cfg.x_start, 2566 + acc->af.stripes[1].grid_cfg.width, 2567 + b_w_log2); 2559 2568 } else if (acc->af.config.grid_cfg.x_end <= 2560 2569 acc->stripe.bds_out_stripes[0].width - min_overlap) { 2561 2570 /* Enable only for leftmost stripe, disable right */ ··· 2636 2627 acc->stripe.down_scaled_stripes[1].offset + min_overlap) { 2637 2628 /* Enable only for rightmost stripe, disable left */ 2638 2629 acc->awb.stripes[0].rgbs_thr_b &= ~IPU3_UAPI_AWB_RGBS_THR_B_EN; 2630 + 2631 + acc->awb.stripes[1].grid.x_start = 2632 + (acc->awb.stripes[1].grid.x_start - 2633 + acc->stripe.down_scaled_stripes[1].offset) & 2634 + IPU3_UAPI_GRID_START_MASK; 2635 + 2636 + b_w_log2 = acc->awb.stripes[1].grid.block_width_log2; 2637 + acc->awb.stripes[1].grid.x_end = 2638 + imgu_css_grid_end(acc->awb.stripes[1].grid.x_start, 2639 + acc->awb.stripes[1].grid.width, 2640 + b_w_log2); 2639 2641 } else if (acc->awb.config.grid.x_end <= 2640 2642 acc->stripe.bds_out_stripes[0].width - min_overlap) { 2641 2643 /* Enable only for leftmost stripe, disable right */

+1

drivers/staging/media/ipu3/ipu3-v4l2.c

··· 485 485 486 486 pipe = node->pipe; 487 487 imgu_pipe = &imgu->imgu_pipe[pipe]; 488 + atomic_set(&node->sequence, 0); 488 489 r = media_pipeline_start(&node->vdev.entity, &imgu_pipe->pipeline); 489 490 if (r < 0) 490 491 goto fail_return_bufs;

+11 -14

drivers/staging/media/ipu3/ipu3.c

··· 440 440 return r; 441 441 } 442 442 443 + static void imgu_video_nodes_exit(struct imgu_device *imgu) 444 + { 445 + int i; 446 + 447 + for (i = 0; i < IMGU_MAX_PIPE_NUM; i++) 448 + imgu_dummybufs_cleanup(imgu, i); 449 + 450 + imgu_v4l2_unregister(imgu); 451 + } 452 + 443 453 static int imgu_video_nodes_init(struct imgu_device *imgu) 444 454 { 445 455 struct v4l2_pix_format_mplane *fmts[IPU3_CSS_QUEUES] = { NULL }; ··· 499 489 return 0; 500 490 501 491 out_cleanup: 502 - for (j = 0; j < IMGU_MAX_PIPE_NUM; j++) 503 - imgu_dummybufs_cleanup(imgu, j); 504 - 505 - imgu_v4l2_unregister(imgu); 492 + imgu_video_nodes_exit(imgu); 506 493 507 494 return r; 508 - } 509 - 510 - static void imgu_video_nodes_exit(struct imgu_device *imgu) 511 - { 512 - int i; 513 - 514 - for (i = 0; i < IMGU_MAX_PIPE_NUM; i++) 515 - imgu_dummybufs_cleanup(imgu, i); 516 - 517 - imgu_v4l2_unregister(imgu); 518 495 } 519 496 520 497 /**************** PCI interface ****************/

+2 -2

drivers/staging/media/rkvdec/TODO

··· 1 - * Support for VP9 is planned for this driver. 1 + * Support for HEVC is planned for this driver. 2 2 3 - Given the V4L controls for those CODECs will be part of 3 + Given the V4L controls for that CODEC will be part of 4 4 the uABI, it will be required to have the driver in staging. 5 5 6 6 For this reason, we are keeping this driver in staging for now.

+116 -41

drivers/staging/media/rkvdec/rkvdec-h264.c

··· 97 97 u8 err_info[RKV_ERROR_INFO_SIZE]; 98 98 }; 99 99 100 - #define RKVDEC_H264_DPB_SIZE 16 101 - 102 100 struct rkvdec_h264_reflists { 103 - u8 p[RKVDEC_H264_DPB_SIZE]; 104 - u8 b0[RKVDEC_H264_DPB_SIZE]; 105 - u8 b1[RKVDEC_H264_DPB_SIZE]; 106 - u8 num_valid; 101 + struct v4l2_h264_reference p[V4L2_H264_REF_LIST_LEN]; 102 + struct v4l2_h264_reference b0[V4L2_H264_REF_LIST_LEN]; 103 + struct v4l2_h264_reference b1[V4L2_H264_REF_LIST_LEN]; 107 104 }; 108 105 109 106 struct rkvdec_h264_run { ··· 109 112 const struct v4l2_ctrl_h264_sps *sps; 110 113 const struct v4l2_ctrl_h264_pps *pps; 111 114 const struct v4l2_ctrl_h264_scaling_matrix *scaling_matrix; 115 + int ref_buf_idx[V4L2_H264_NUM_DPB_ENTRIES]; 112 116 }; 113 117 114 118 struct rkvdec_h264_ctx { ··· 659 661 WRITE_PPS(0xff, PROFILE_IDC); 660 662 WRITE_PPS(1, CONSTRAINT_SET3_FLAG); 661 663 WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC); 662 - WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA); 663 - WRITE_PPS(sps->bit_depth_chroma_minus8 + 8, BIT_DEPTH_CHROMA); 664 + WRITE_PPS(sps->bit_depth_luma_minus8, BIT_DEPTH_LUMA); 665 + WRITE_PPS(sps->bit_depth_chroma_minus8, BIT_DEPTH_CHROMA); 664 666 WRITE_PPS(0, QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG); 665 667 WRITE_PPS(sps->log2_max_frame_num_minus4, LOG2_MAX_FRAME_NUM_MINUS4); 666 668 WRITE_PPS(sps->max_num_ref_frames, MAX_NUM_REF_FRAMES); ··· 669 671 LOG2_MAX_PIC_ORDER_CNT_LSB_MINUS4); 670 672 WRITE_PPS(!!(sps->flags & V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO), 671 673 DELTA_PIC_ORDER_ALWAYS_ZERO_FLAG); 672 - WRITE_PPS(DIV_ROUND_UP(ctx->coded_fmt.fmt.pix_mp.width, 16), PIC_WIDTH_IN_MBS); 673 - WRITE_PPS(DIV_ROUND_UP(ctx->coded_fmt.fmt.pix_mp.height, 16), PIC_HEIGHT_IN_MBS); 674 + 675 + /* 676 + * Use the SPS values since they are already in macroblocks 677 + * dimensions, height can be field height (halved) if 678 + * V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY is not set and also it allows 679 + * decoding smaller images into larger allocation which can be used 680 + * to implementing SVC spatial layer support. 681 + */ 682 + WRITE_PPS(sps->pic_width_in_mbs_minus1 + 1, PIC_WIDTH_IN_MBS); 683 + WRITE_PPS(sps->pic_height_in_map_units_minus1 + 1, PIC_HEIGHT_IN_MBS); 684 + 674 685 WRITE_PPS(!!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY), 675 686 FRAME_MBS_ONLY_FLAG); 676 687 WRITE_PPS(!!(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD), ··· 732 725 } 733 726 } 734 727 728 + static void lookup_ref_buf_idx(struct rkvdec_ctx *ctx, 729 + struct rkvdec_h264_run *run) 730 + { 731 + const struct v4l2_ctrl_h264_decode_params *dec_params = run->decode_params; 732 + u32 i; 733 + 734 + for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) { 735 + struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; 736 + const struct v4l2_h264_dpb_entry *dpb = run->decode_params->dpb; 737 + struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; 738 + int buf_idx = -1; 739 + 740 + if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) { 741 + buf_idx = vb2_find_timestamp(cap_q, 742 + dpb[i].reference_ts, 0); 743 + if (buf_idx < 0) 744 + pr_debug("No buffer for reference_ts %llu", 745 + dpb[i].reference_ts); 746 + } 747 + 748 + run->ref_buf_idx[i] = buf_idx; 749 + } 750 + } 751 + 735 752 static void assemble_hw_rps(struct rkvdec_ctx *ctx, 753 + struct v4l2_h264_reflist_builder *builder, 736 754 struct rkvdec_h264_run *run) 737 755 { 738 756 const struct v4l2_ctrl_h264_decode_params *dec_params = run->decode_params; 739 757 const struct v4l2_h264_dpb_entry *dpb = dec_params->dpb; 740 758 struct rkvdec_h264_ctx *h264_ctx = ctx->priv; 741 - const struct v4l2_ctrl_h264_sps *sps = run->sps; 742 759 struct rkvdec_h264_priv_tbl *priv_tbl = h264_ctx->priv_tbl.cpu; 743 - u32 max_frame_num = 1 << (sps->log2_max_frame_num_minus4 + 4); 744 760 745 761 u32 *hw_rps = priv_tbl->rps; 746 762 u32 i, j; ··· 781 751 if (!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) 782 752 continue; 783 753 784 - if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM || 785 - dpb[i].frame_num < dec_params->frame_num) { 786 - p[i] = dpb[i].frame_num; 787 - continue; 788 - } 789 - 790 - p[i] = dpb[i].frame_num - max_frame_num; 754 + p[i] = builder->refs[i].frame_num; 791 755 } 792 756 793 757 for (j = 0; j < RKVDEC_NUM_REFLIST; j++) { 794 - for (i = 0; i < h264_ctx->reflists.num_valid; i++) { 795 - u8 dpb_valid = 0; 796 - u8 idx = 0; 758 + for (i = 0; i < builder->num_valid; i++) { 759 + struct v4l2_h264_reference *ref; 760 + bool dpb_valid; 761 + bool bottom; 797 762 798 763 switch (j) { 799 764 case 0: 800 - idx = h264_ctx->reflists.p[i]; 765 + ref = &h264_ctx->reflists.p[i]; 801 766 break; 802 767 case 1: 803 - idx = h264_ctx->reflists.b0[i]; 768 + ref = &h264_ctx->reflists.b0[i]; 804 769 break; 805 770 case 2: 806 - idx = h264_ctx->reflists.b1[i]; 771 + ref = &h264_ctx->reflists.b1[i]; 807 772 break; 808 773 } 809 774 810 - if (idx >= ARRAY_SIZE(dec_params->dpb)) 775 + if (WARN_ON(ref->index >= ARRAY_SIZE(dec_params->dpb))) 811 776 continue; 812 - dpb_valid = !!(dpb[idx].flags & 813 - V4L2_H264_DPB_ENTRY_FLAG_ACTIVE); 777 + 778 + dpb_valid = run->ref_buf_idx[ref->index] >= 0; 779 + bottom = ref->fields == V4L2_H264_BOTTOM_FIELD_REF; 814 780 815 781 set_ps_field(hw_rps, DPB_INFO(i, j), 816 - idx | dpb_valid << 4); 782 + ref->index | dpb_valid << 4); 783 + set_ps_field(hw_rps, BOTTOM_FLAG(i, j), bottom); 817 784 } 818 785 } 819 786 } ··· 886 859 unsigned int dpb_idx) 887 860 { 888 861 struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; 889 - const struct v4l2_h264_dpb_entry *dpb = run->decode_params->dpb; 890 862 struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; 891 - int buf_idx = -1; 892 - 893 - if (dpb[dpb_idx].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) 894 - buf_idx = vb2_find_timestamp(cap_q, 895 - dpb[dpb_idx].reference_ts, 0); 863 + int buf_idx = run->ref_buf_idx[dpb_idx]; 896 864 897 865 /* 898 866 * If a DPB entry is unused or invalid, address of current destination ··· 998 976 rkvdec->regs + RKVDEC_REG_H264_BASE_REFER15); 999 977 } 1000 978 1001 - /* 1002 - * Since support frame mode only 1003 - * top_field_order_cnt is the same as bottom_field_order_cnt 1004 - */ 1005 979 reg = RKVDEC_CUR_POC(dec_params->top_field_order_cnt); 1006 980 writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0); 1007 981 ··· 1039 1021 return 0; 1040 1022 } 1041 1023 1024 + static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx, 1025 + const struct v4l2_ctrl_h264_sps *sps) 1026 + { 1027 + unsigned int width, height; 1028 + 1029 + /* 1030 + * TODO: The hardware supports 10-bit and 4:2:2 profiles, 1031 + * but it's currently broken in the driver. 1032 + * Reject them for now, until it's fixed. 1033 + */ 1034 + if (sps->chroma_format_idc > 1) 1035 + /* Only 4:0:0 and 4:2:0 are supported */ 1036 + return -EINVAL; 1037 + if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) 1038 + /* Luma and chroma bit depth mismatch */ 1039 + return -EINVAL; 1040 + if (sps->bit_depth_luma_minus8 != 0) 1041 + /* Only 8-bit is supported */ 1042 + return -EINVAL; 1043 + 1044 + width = (sps->pic_width_in_mbs_minus1 + 1) * 16; 1045 + height = (sps->pic_height_in_map_units_minus1 + 1) * 16; 1046 + 1047 + /* 1048 + * When frame_mbs_only_flag is not set, this is field height, 1049 + * which is half the final height (see (7-18) in the 1050 + * specification) 1051 + */ 1052 + if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY)) 1053 + height *= 2; 1054 + 1055 + if (width > ctx->coded_fmt.fmt.pix_mp.width || 1056 + height > ctx->coded_fmt.fmt.pix_mp.height) 1057 + return -EINVAL; 1058 + 1059 + return 0; 1060 + } 1061 + 1042 1062 static int rkvdec_h264_start(struct rkvdec_ctx *ctx) 1043 1063 { 1044 1064 struct rkvdec_dev *rkvdec = ctx->dev; 1045 1065 struct rkvdec_h264_priv_tbl *priv_tbl; 1046 1066 struct rkvdec_h264_ctx *h264_ctx; 1067 + struct v4l2_ctrl *ctrl; 1047 1068 int ret; 1069 + 1070 + ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, 1071 + V4L2_CID_STATELESS_H264_SPS); 1072 + if (!ctrl) 1073 + return -EINVAL; 1074 + 1075 + ret = rkvdec_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps); 1076 + if (ret) 1077 + return ret; 1048 1078 1049 1079 h264_ctx = kzalloc(sizeof(*h264_ctx), GFP_KERNEL); 1050 1080 if (!h264_ctx) ··· 1161 1095 /* Build the P/B{0,1} ref lists. */ 1162 1096 v4l2_h264_init_reflist_builder(&reflist_builder, run.decode_params, 1163 1097 run.sps, run.decode_params->dpb); 1164 - h264_ctx->reflists.num_valid = reflist_builder.num_valid; 1165 1098 v4l2_h264_build_p_ref_list(&reflist_builder, h264_ctx->reflists.p); 1166 1099 v4l2_h264_build_b_ref_lists(&reflist_builder, h264_ctx->reflists.b0, 1167 1100 h264_ctx->reflists.b1); 1168 1101 1169 1102 assemble_hw_scaling_list(ctx, &run); 1170 1103 assemble_hw_pps(ctx, &run); 1171 - assemble_hw_rps(ctx, &run); 1104 + lookup_ref_buf_idx(ctx, &run); 1105 + assemble_hw_rps(ctx, &reflist_builder, &run); 1172 1106 config_registers(ctx, &run); 1173 1107 1174 1108 rkvdec_run_postamble(ctx, &run.base); ··· 1188 1122 return 0; 1189 1123 } 1190 1124 1125 + static int rkvdec_h264_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) 1126 + { 1127 + if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) 1128 + return rkvdec_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps); 1129 + 1130 + return 0; 1131 + } 1132 + 1191 1133 const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops = { 1192 1134 .adjust_fmt = rkvdec_h264_adjust_fmt, 1193 1135 .start = rkvdec_h264_start, 1194 1136 .stop = rkvdec_h264_stop, 1195 1137 .run = rkvdec_h264_run, 1138 + .try_ctrl = rkvdec_h264_try_ctrl, 1196 1139 };

+12 -23

drivers/staging/media/rkvdec/rkvdec.c

··· 29 29 30 30 static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) 31 31 { 32 - if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) { 33 - const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps; 34 - /* 35 - * TODO: The hardware supports 10-bit and 4:2:2 profiles, 36 - * but it's currently broken in the driver. 37 - * Reject them for now, until it's fixed. 38 - */ 39 - if (sps->chroma_format_idc > 1) 40 - /* Only 4:0:0 and 4:2:0 are supported */ 41 - return -EINVAL; 42 - if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) 43 - /* Luma and chroma bit depth mismatch */ 44 - return -EINVAL; 45 - if (sps->bit_depth_luma_minus8 != 0) 46 - /* Only 8-bit is supported */ 47 - return -EINVAL; 48 - } 32 + struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); 33 + const struct rkvdec_coded_fmt_desc *desc = ctx->coded_fmt_desc; 34 + 35 + if (desc->ops->try_ctrl) 36 + return desc->ops->try_ctrl(ctx, ctrl); 37 + 49 38 return 0; 50 39 } 51 40 ··· 127 138 .ops = &rkvdec_h264_fmt_ops, 128 139 .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_vp9_decoded_fmts), 129 140 .decoded_fmts = rkvdec_h264_vp9_decoded_fmts, 141 + .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, 130 142 }, 131 143 { 132 144 .fourcc = V4L2_PIX_FMT_VP9_FRAME, ··· 258 268 pix_mp->pixelformat = coded_desc->decoded_fmts[0]; 259 269 260 270 /* Always apply the frmsize constraint of the coded end. */ 271 + pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width); 272 + pix_mp->height = max(pix_mp->height, ctx->coded_fmt.fmt.pix_mp.height); 261 273 v4l2_apply_frmsize_constraints(&pix_mp->width, 262 274 &pix_mp->height, 263 275 &coded_desc->frmsize); ··· 385 393 cap_fmt->fmt.pix_mp.xfer_func = f->fmt.pix_mp.xfer_func; 386 394 cap_fmt->fmt.pix_mp.ycbcr_enc = f->fmt.pix_mp.ycbcr_enc; 387 395 cap_fmt->fmt.pix_mp.quantization = f->fmt.pix_mp.quantization; 396 + 397 + /* Enable format specific queue features */ 398 + vq->subsystem_flags |= desc->subsystem_flags; 388 399 389 400 return 0; 390 401 } ··· 1021 1026 rkvdec->clocks); 1022 1027 if (ret) 1023 1028 return ret; 1024 - 1025 - /* 1026 - * Bump ACLK to max. possible freq. (500 MHz) to improve performance 1027 - * When 4k video playback. 1028 - */ 1029 - clk_set_rate(rkvdec->clocks[0].clk, 500 * 1000 * 1000); 1030 1029 1031 1030 rkvdec->regs = devm_platform_ioremap_resource(pdev, 0); 1032 1031 if (IS_ERR(rkvdec->regs))

+2

drivers/staging/media/rkvdec/rkvdec.h

··· 72 72 void (*done)(struct rkvdec_ctx *ctx, struct vb2_v4l2_buffer *src_buf, 73 73 struct vb2_v4l2_buffer *dst_buf, 74 74 enum vb2_buffer_state result); 75 + int (*try_ctrl)(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl); 75 76 }; 76 77 77 78 struct rkvdec_coded_fmt_desc { ··· 82 81 const struct rkvdec_coded_fmt_ops *ops; 83 82 unsigned int num_decoded_fmts; 84 83 const u32 *decoded_fmts; 84 + u32 subsystem_flags; 85 85 }; 86 86 87 87 struct rkvdec_dev {

+8 -2

drivers/staging/media/tegra-video/vi.c

··· 491 491 struct v4l2_pix_format *pix) 492 492 { 493 493 const struct tegra_video_format *fmtinfo; 494 + static struct lock_class_key key; 494 495 struct v4l2_subdev *subdev; 495 496 struct v4l2_subdev_format fmt; 496 497 struct v4l2_subdev_state *sd_state; ··· 508 507 if (!subdev) 509 508 return -ENODEV; 510 509 511 - sd_state = v4l2_subdev_alloc_state(subdev); 510 + /* 511 + * FIXME: Drop this call, drivers are not supposed to use 512 + * __v4l2_subdev_state_alloc(). 513 + */ 514 + sd_state = __v4l2_subdev_state_alloc(subdev, "tegra:state->lock", 515 + &key); 512 516 if (IS_ERR(sd_state)) 513 517 return PTR_ERR(sd_state); 514 518 /* ··· 564 558 v4l2_fill_pix_format(pix, &fmt.format); 565 559 tegra_channel_fmt_align(chan, pix, fmtinfo->bpp); 566 560 567 - v4l2_subdev_free_state(sd_state); 561 + __v4l2_subdev_state_free(sd_state); 568 562 569 563 return 0; 570 564 }

+2

include/linux/remoteproc/mtk_scp.h

··· 41 41 SCP_IPI_ISP_FRAME, 42 42 SCP_IPI_FD_CMD, 43 43 SCP_IPI_CROS_HOST_CMD, 44 + SCP_IPI_VDEC_LAT, 45 + SCP_IPI_VDEC_CORE, 44 46 SCP_IPI_NS_SERVICE = 0xFF, 45 47 SCP_IPI_MAX = 0x100, 46 48 };

+14

include/media/cec.h

··· 118 118 int (*adap_monitor_all_enable)(struct cec_adapter *adap, bool enable); 119 119 int (*adap_monitor_pin_enable)(struct cec_adapter *adap, bool enable); 120 120 int (*adap_log_addr)(struct cec_adapter *adap, u8 logical_addr); 121 + void (*adap_configured)(struct cec_adapter *adap, bool configured); 121 122 int (*adap_transmit)(struct cec_adapter *adap, u8 attempts, 122 123 u32 signal_free_time, struct cec_msg *msg); 123 124 void (*adap_status)(struct cec_adapter *adap, struct seq_file *file); ··· 164 163 * @wait_queue: queue of transmits waiting for a reply 165 164 * @transmitting: CEC messages currently being transmitted 166 165 * @transmit_in_progress: true if a transmit is in progress 166 + * @transmit_in_progress_aborted: true if a transmit is in progress is to be 167 + * aborted. This happens if the logical address is 168 + * invalidated while the transmit is ongoing. In that 169 + * case the transmit will finish, but will not retransmit 170 + * and be marked as ABORTED. 171 + * @xfer_timeout_ms: the transfer timeout in ms. 172 + * If 0, then timeout after 2.1 ms. 167 173 * @kthread_config: kthread used to configure a CEC adapter 168 174 * @config_completion: used to signal completion of the config kthread 169 175 * @kthread: main CEC processing thread ··· 183 175 * @needs_hpd: if true, then the HDMI HotPlug Detect pin must be high 184 176 * in order to transmit or receive CEC messages. This is usually a HW 185 177 * limitation. 178 + * @is_enabled: the CEC adapter is enabled 186 179 * @is_configuring: the CEC adapter is configuring (i.e. claiming LAs) 180 + * @must_reconfigure: while configuring, the PA changed, so reclaim LAs 187 181 * @is_configured: the CEC adapter is configured (i.e. has claimed LAs) 188 182 * @cec_pin_is_high: if true then the CEC pin is high. Only used with the 189 183 * CEC pin framework. ··· 227 217 struct list_head wait_queue; 228 218 struct cec_data *transmitting; 229 219 bool transmit_in_progress; 220 + bool transmit_in_progress_aborted; 221 + unsigned int xfer_timeout_ms; 230 222 231 223 struct task_struct *kthread_config; 232 224 struct completion config_completion; ··· 243 231 244 232 u16 phys_addr; 245 233 bool needs_hpd; 234 + bool is_enabled; 246 235 bool is_configuring; 236 + bool must_reconfigure; 247 237 bool is_configured; 248 238 bool cec_pin_is_high; 249 239 bool adap_controls_phys_addr;

+359 -323

include/media/dvb-usb-ids.h

··· 10 10 #ifndef _DVB_USB_IDS_H_ 11 11 #define _DVB_USB_IDS_H_ 12 12 13 + #include <linux/usb.h> 14 + 15 + #define DVB_USB_DEV(pid, vid) \ 16 + [vid] = { USB_DEVICE(USB_VID_ ## pid, USB_PID_ ## vid) } 17 + 18 + #define DVB_USB_DEV_VER(pid, vid, lo, hi) \ 19 + [vid] = { USB_DEVICE_VER(USB_VID_ ## pid, USB_PID_ ## vid, lo, hi) } 20 + 13 21 /* Vendor IDs */ 14 - #define USB_VID_ADSTECH 0x06e1 15 - #define USB_VID_AFATECH 0x15a4 22 + 23 + #define USB_VID_774 0x7a69 24 + #define USB_VID_ADSTECH 0x06e1 25 + #define USB_VID_AFATECH 0x15a4 16 26 #define USB_VID_ALCOR_MICRO 0x058f 17 27 #define USB_VID_ALINK 0x05e3 28 + #define USB_VID_AME 0x06be 18 29 #define USB_VID_AMT 0x1c73 19 30 #define USB_VID_ANCHOR 0x0547 20 - #define USB_VID_ANSONIC 0x10b9 31 + #define USB_VID_ANSONIC 0x10b9 21 32 #define USB_VID_ANUBIS_ELECTRONIC 0x10fd 22 33 #define USB_VID_ASUS 0x0b05 23 34 #define USB_VID_AVERMEDIA 0x07ca 35 + #define USB_VID_AZUREWAVE 0x13d3 24 36 #define USB_VID_COMPRO 0x185b 25 37 #define USB_VID_COMPRO_UNK 0x145f 26 38 #define USB_VID_CONEXANT 0x0572 27 - #define USB_VID_CYPRESS 0x04b4 28 - #define USB_VID_DEXATEK 0x1d19 39 + #define USB_VID_CYPRESS 0x04b4 40 + #define USB_VID_DEXATEK 0x1d19 29 41 #define USB_VID_DIBCOM 0x10b8 30 42 #define USB_VID_DPOSH 0x1498 31 43 #define USB_VID_DVICO 0x0fe9 32 44 #define USB_VID_E3C 0x18b4 33 45 #define USB_VID_ELGATO 0x0fd9 34 46 #define USB_VID_EMPIA 0xeb1a 47 + #define USB_VID_EVOLUTEPC 0x1e59 35 48 #define USB_VID_GENPIX 0x09c0 49 + #define USB_VID_GIGABYTE 0x1044 50 + #define USB_VID_GOTVIEW 0x1fe1 36 51 #define USB_VID_GRANDTEC 0x5032 37 52 #define USB_VID_GTEK 0x1f4d 38 - #define USB_VID_HANFTEK 0x15f4 53 + #define USB_VID_HAMA 0x147f 54 + #define USB_VID_HANFTEK 0x15f4 39 55 #define USB_VID_HAUPPAUGE 0x2040 56 + #define USB_VID_HUMAX_COEX 0x10b9 40 57 #define USB_VID_HYPER_PALTEK 0x1025 41 58 #define USB_VID_INTEL 0x8086 42 - #define USB_VID_ITETECH 0x048d 59 + #define USB_VID_ITETECH 0x048d 43 60 #define USB_VID_KWORLD 0xeb2a 44 61 #define USB_VID_KWORLD_2 0x1b80 45 62 #define USB_VID_KYE 0x0458 46 - #define USB_VID_LEADTEK 0x0413 63 + #define USB_VID_LEADTEK 0x0413 47 64 #define USB_VID_LITEON 0x04ca 48 65 #define USB_VID_MEDION 0x1660 66 + #define USB_VID_MICROSOFT 0x045e 49 67 #define USB_VID_MIGLIA 0x18f3 50 68 #define USB_VID_MSI 0x0db0 51 69 #define USB_VID_MSI_2 0x1462 52 70 #define USB_VID_OPERA1 0x695c 53 - #define USB_VID_PINNACLE 0x2304 54 71 #define USB_VID_PCTV 0x2013 72 + #define USB_VID_PINNACLE 0x2304 55 73 #define USB_VID_PIXELVIEW 0x1554 56 - #define USB_VID_REALTEK 0x0bda 74 + #define USB_VID_PROF_1 0x3011 75 + #define USB_VID_PROF_2 0x3034 76 + #define USB_VID_REALTEK 0x0bda 77 + #define USB_VID_SONY 0x1415 78 + #define USB_VID_TECHNISAT 0x14f7 57 79 #define USB_VID_TECHNOTREND 0x0b48 80 + #define USB_VID_TELESTAR 0x10b9 58 81 #define USB_VID_TERRATEC 0x0ccd 59 82 #define USB_VID_TERRATEC_2 0x153b 60 - #define USB_VID_TELESTAR 0x10b9 61 - #define USB_VID_VISIONPLUS 0x13d3 62 - #define USB_VID_SONY 0x1415 63 - #define USB_PID_TEVII_S421 0xd421 64 - #define USB_PID_TEVII_S480_1 0xd481 65 - #define USB_PID_TEVII_S480_2 0xd482 66 - #define USB_PID_TEVII_S630 0xd630 67 - #define USB_PID_TEVII_S632 0xd632 68 - #define USB_PID_TEVII_S650 0xd650 69 - #define USB_PID_TEVII_S660 0xd660 70 - #define USB_PID_TEVII_S662 0xd662 71 - #define USB_VID_TWINHAN 0x1822 83 + #define USB_VID_TEVII 0x9022 84 + #define USB_VID_TWINHAN 0x1822 72 85 #define USB_VID_ULTIMA_ELECTRONIC 0x05d8 73 - #define USB_VID_UNIWILL 0x1584 86 + #define USB_VID_UNIWILL 0x1584 87 + #define USB_VID_VISIONPLUS 0x13d3 74 88 #define USB_VID_WIDEVIEW 0x14aa 75 - #define USB_VID_GIGABYTE 0x1044 76 - #define USB_VID_YUAN 0x1164 77 89 #define USB_VID_XTENSIONS 0x1ae7 90 + #define USB_VID_YUAN 0x1164 78 91 #define USB_VID_ZYDAS 0x0ace 79 - #define USB_VID_HUMAX_COEX 0x10b9 80 - #define USB_VID_774 0x7a69 81 - #define USB_VID_EVOLUTEPC 0x1e59 82 - #define USB_VID_AZUREWAVE 0x13d3 83 - #define USB_VID_TECHNISAT 0x14f7 84 - #define USB_VID_HAMA 0x147f 85 - #define USB_VID_MICROSOFT 0x045e 86 92 87 93 /* Product IDs */ 94 + 88 95 #define USB_PID_ADSTECH_USB2_COLD 0xa333 89 96 #define USB_PID_ADSTECH_USB2_WARM 0xa334 90 97 #define USB_PID_AFATECH_AF9005 0x9020 ··· 102 95 #define USB_PID_AFATECH_AF9035_1002 0x1002 103 96 #define USB_PID_AFATECH_AF9035_1003 0x1003 104 97 #define USB_PID_AFATECH_AF9035_9035 0x9035 105 - #define USB_PID_TREKSTOR_DVBT 0x901b 106 - #define USB_PID_TREKSTOR_TERRES_2_0 0xC803 107 98 #define USB_PID_ALINK_DTU 0xf170 99 + #define USB_PID_AME_DTV5100 0xa232 100 + #define USB_PID_ANCHOR_NEBULA_DIGITV 0x0201 108 101 #define USB_PID_ANSONIC_DVBT_USB 0x6000 102 + #define USB_PID_ANUBIS_LIFEVIEW_TV_WALKER_TWIN_COLD 0x0514 103 + #define USB_PID_ANUBIS_LIFEVIEW_TV_WALKER_TWIN_WARM 0x0513 104 + #define USB_PID_ANUBIS_MSI_DIGI_VOX_MINI_II 0x1513 109 105 #define USB_PID_ANYSEE 0x861f 110 - #define USB_PID_AZUREWAVE_AD_TU700 0x3237 111 - #define USB_PID_AZUREWAVE_6007 0x0ccd 112 - #define USB_PID_AVERMEDIA_DVBT_USB_COLD 0x0001 113 - #define USB_PID_AVERMEDIA_DVBT_USB_WARM 0x0002 106 + #define USB_PID_ASUS_U3000 0x171f 107 + #define USB_PID_ASUS_U3000H 0x1736 108 + #define USB_PID_ASUS_U3100 0x173f 109 + #define USB_PID_ASUS_U3100MINI_PLUS 0x1779 110 + #define USB_PID_AVERMEDIA_1867 0x1867 111 + #define USB_PID_AVERMEDIA_A309 0xa309 112 + #define USB_PID_AVERMEDIA_A310 0xa310 113 + #define USB_PID_AVERMEDIA_A805 0xa805 114 + #define USB_PID_AVERMEDIA_A815M 0x815a 115 + #define USB_PID_AVERMEDIA_A835 0xa835 116 + #define USB_PID_AVERMEDIA_A835B_1835 0x1835 117 + #define USB_PID_AVERMEDIA_A835B_2835 0x2835 118 + #define USB_PID_AVERMEDIA_A835B_3835 0x3835 119 + #define USB_PID_AVERMEDIA_A835B_4835 0x4835 120 + #define USB_PID_AVERMEDIA_A850 0x850a 121 + #define USB_PID_AVERMEDIA_A850T 0x850b 122 + #define USB_PID_AVERMEDIA_A867 0xa867 123 + #define USB_PID_AVERMEDIA_B835 0xb835 114 124 #define USB_PID_AVERMEDIA_DVBT_USB2_COLD 0xa800 115 125 #define USB_PID_AVERMEDIA_DVBT_USB2_WARM 0xa801 126 + #define USB_PID_AVERMEDIA_EXPRESS 0xb568 127 + #define USB_PID_AVERMEDIA_H335 0x0335 128 + #define USB_PID_AVERMEDIA_HYBRID_ULTRA_USB_M039R 0x0039 129 + #define USB_PID_AVERMEDIA_HYBRID_ULTRA_USB_M039R_ATSC 0x1039 130 + #define USB_PID_AVERMEDIA_HYBRID_ULTRA_USB_M039R_DVBT 0x2039 131 + #define USB_PID_AVERMEDIA_MCE_USB_M038 0x1228 132 + #define USB_PID_AVERMEDIA_TD110 0xa110 133 + #define USB_PID_AVERMEDIA_TD310 0x1871 134 + #define USB_PID_AVERMEDIA_TWINSTAR 0x0825 135 + #define USB_PID_AVERMEDIA_VOLAR 0xa807 136 + #define USB_PID_AVERMEDIA_VOLAR_2 0xb808 137 + #define USB_PID_AVERMEDIA_VOLAR_A868R 0xa868 138 + #define USB_PID_AVERMEDIA_VOLAR_X 0xa815 139 + #define USB_PID_AVERMEDIA_VOLAR_X_2 0x8150 140 + #define USB_PID_AZUREWAVE_6007 0x0ccd 141 + #define USB_PID_AZUREWAVE_AD_TU700 0x3237 142 + #define USB_PID_AZUREWAVE_AZ6027 0x3275 143 + #define USB_PID_AZUREWAVE_TWINHAN_VP7049 0x3219 116 144 #define USB_PID_COMPRO_DVBU2000_COLD 0xd000 117 - #define USB_PID_COMPRO_DVBU2000_WARM 0xd001 118 145 #define USB_PID_COMPRO_DVBU2000_UNK_COLD 0x010c 119 146 #define USB_PID_COMPRO_DVBU2000_UNK_WARM 0x010d 147 + #define USB_PID_COMPRO_DVBU2000_WARM 0xd001 120 148 #define USB_PID_COMPRO_VIDEOMATE_U500 0x1e78 121 149 #define USB_PID_COMPRO_VIDEOMATE_U500_PC 0x1e80 122 150 #define USB_PID_CONCEPTRONIC_CTVDIGRCU 0xe397 123 151 #define USB_PID_CONEXANT_D680_DMB 0x86d6 124 - #define USB_PID_CREATIX_CTX1921 0x1921 152 + #define USB_PID_CPYTO_REDI_PC50A 0xa803 153 + #define USB_PID_CTVDIGDUAL_V2 0xe410 154 + #define USB_PID_CYPRESS_DW2101 0x2101 155 + #define USB_PID_CYPRESS_DW2102 0x2102 156 + #define USB_PID_CYPRESS_DW2104 0x2104 157 + #define USB_PID_CYPRESS_DW3101 0x3101 158 + #define USB_PID_CYPRESS_OPERA1_COLD 0x2830 125 159 #define USB_PID_DELOCK_USB2_DVBT 0xb803 160 + #define USB_PID_DIBCOM_ANCHOR_2135_COLD 0x2131 126 161 #define USB_PID_DIBCOM_HOOK_DEFAULT 0x0064 127 162 #define USB_PID_DIBCOM_HOOK_DEFAULT_REENUM 0x0065 128 163 #define USB_PID_DIBCOM_MOD3000_COLD 0x0bb8 129 164 #define USB_PID_DIBCOM_MOD3000_WARM 0x0bb9 130 165 #define USB_PID_DIBCOM_MOD3001_COLD 0x0bc6 131 166 #define USB_PID_DIBCOM_MOD3001_WARM 0x0bc7 132 - #define USB_PID_DIBCOM_STK7700P 0x1e14 133 - #define USB_PID_DIBCOM_STK7700P_PC 0x1e78 134 - #define USB_PID_DIBCOM_STK7700D 0x1ef0 135 - #define USB_PID_DIBCOM_STK7700_U7000 0x7001 136 - #define USB_PID_DIBCOM_STK7070P 0x1ebc 137 - #define USB_PID_DIBCOM_STK7070PD 0x1ebe 138 - #define USB_PID_DIBCOM_STK807XP 0x1f90 139 - #define USB_PID_DIBCOM_STK807XPVR 0x1f98 140 - #define USB_PID_DIBCOM_STK8096GP 0x1fa0 141 - #define USB_PID_DIBCOM_STK8096PVR 0x1faa 142 - #define USB_PID_DIBCOM_NIM8096MD 0x1fa8 143 - #define USB_PID_DIBCOM_TFE8096P 0x1f9C 144 - #define USB_PID_DIBCOM_ANCHOR_2135_COLD 0x2131 145 - #define USB_PID_DIBCOM_STK7770P 0x1e80 146 167 #define USB_PID_DIBCOM_NIM7090 0x1bb2 147 - #define USB_PID_DIBCOM_TFE7090PVR 0x1bb4 148 - #define USB_PID_DIBCOM_TFE7790P 0x1e6e 149 - #define USB_PID_DIBCOM_NIM9090M 0x2383 168 + #define USB_PID_DIBCOM_NIM8096MD 0x1fa8 169 + #define USB_PID_DIBCOM_NIM9090M 0x2383 150 170 #define USB_PID_DIBCOM_NIM9090MD 0x2384 171 + #define USB_PID_DIBCOM_STK7070P 0x1ebc 172 + #define USB_PID_DIBCOM_STK7070PD 0x1ebe 173 + #define USB_PID_DIBCOM_STK7700D 0x1ef0 174 + #define USB_PID_DIBCOM_STK7700P 0x1e14 175 + #define USB_PID_DIBCOM_STK7700P_PC 0x1e78 176 + #define USB_PID_DIBCOM_STK7700_U7000 0x7001 177 + #define USB_PID_DIBCOM_STK7770P 0x1e80 178 + #define USB_PID_DIBCOM_STK807XP 0x1f90 179 + #define USB_PID_DIBCOM_STK807XPVR 0x1f98 180 + #define USB_PID_DIBCOM_STK8096GP 0x1fa0 181 + #define USB_PID_DIBCOM_STK8096PVR 0x1faa 182 + #define USB_PID_DIBCOM_TFE7090PVR 0x1bb4 183 + #define USB_PID_DIBCOM_TFE7790P 0x1e6e 184 + #define USB_PID_DIBCOM_TFE8096P 0x1f9C 185 + #define USB_PID_DIGITALNOW_BLUEBIRD_DUAL_1_COLD 0xdb54 186 + #define USB_PID_DIGITALNOW_BLUEBIRD_DUAL_1_WARM 0xdb55 151 187 #define USB_PID_DPOSH_M9206_COLD 0x9206 152 188 #define USB_PID_DPOSH_M9206_WARM 0xa090 153 - #define USB_PID_E3C_EC168 0x1689 154 - #define USB_PID_E3C_EC168_2 0xfffa 155 - #define USB_PID_E3C_EC168_3 0xfffb 156 - #define USB_PID_E3C_EC168_4 0x1001 157 - #define USB_PID_E3C_EC168_5 0x1002 158 - #define USB_PID_FREECOM_DVBT 0x0160 159 - #define USB_PID_FREECOM_DVBT_2 0x0161 160 - #define USB_PID_UNIWILL_STK7700P 0x6003 161 - #define USB_PID_GENIUS_TVGO_DVB_T03 0x4012 162 - #define USB_PID_GRANDTEC_DVBT_USB_COLD 0x0fa0 163 - #define USB_PID_GRANDTEC_DVBT_USB_WARM 0x0fa1 164 - #define USB_PID_GOTVIEW_SAT_HD 0x5456 165 - #define USB_PID_INTEL_CE9500 0x9500 166 - #define USB_PID_ITETECH_IT9135 0x9135 167 - #define USB_PID_ITETECH_IT9135_9005 0x9005 168 - #define USB_PID_ITETECH_IT9135_9006 0x9006 169 - #define USB_PID_ITETECH_IT9303 0x9306 170 - #define USB_PID_KWORLD_399U 0xe399 171 - #define USB_PID_KWORLD_399U_2 0xe400 172 - #define USB_PID_KWORLD_395U 0xe396 173 - #define USB_PID_KWORLD_395U_2 0xe39b 174 - #define USB_PID_KWORLD_395U_3 0xe395 175 - #define USB_PID_KWORLD_395U_4 0xe39a 176 - #define USB_PID_KWORLD_MC810 0xc810 177 - #define USB_PID_KWORLD_PC160_2T 0xc160 178 - #define USB_PID_KWORLD_PC160_T 0xc161 179 - #define USB_PID_KWORLD_UB383_T 0xe383 180 - #define USB_PID_KWORLD_UB499_2T_T09 0xe409 181 - #define USB_PID_KWORLD_VSTREAM_COLD 0x17de 182 - #define USB_PID_KWORLD_VSTREAM_WARM 0x17df 183 - #define USB_PID_PROF_1100 0xb012 184 - #define USB_PID_TERRATEC_CINERGY_S 0x0064 185 - #define USB_PID_TERRATEC_CINERGY_T_USB_XE 0x0055 186 - #define USB_PID_TERRATEC_CINERGY_T_USB_XE_REV2 0x0069 187 - #define USB_PID_TERRATEC_CINERGY_T_STICK 0x0093 188 - #define USB_PID_TERRATEC_CINERGY_T_STICK_RC 0x0097 189 - #define USB_PID_TERRATEC_CINERGY_T_STICK_DUAL_RC 0x0099 190 - #define USB_PID_TERRATEC_CINERGY_T_STICK_BLACK_REV1 0x00a9 191 - #define USB_PID_TERRATEC_CINERGY_TC2_STICK 0x10b2 192 - #define USB_PID_TWINHAN_VP7041_COLD 0x3201 193 - #define USB_PID_TWINHAN_VP7041_WARM 0x3202 194 - #define USB_PID_TWINHAN_VP7020_COLD 0x3203 195 - #define USB_PID_TWINHAN_VP7020_WARM 0x3204 196 - #define USB_PID_TWINHAN_VP7045_COLD 0x3205 197 - #define USB_PID_TWINHAN_VP7045_WARM 0x3206 198 - #define USB_PID_TWINHAN_VP7021_COLD 0x3207 199 - #define USB_PID_TWINHAN_VP7021_WARM 0x3208 200 - #define USB_PID_TWINHAN_VP7049 0x3219 201 - #define USB_PID_TINYTWIN 0x3226 202 - #define USB_PID_TINYTWIN_2 0xe402 203 - #define USB_PID_TINYTWIN_3 0x9016 204 - #define USB_PID_DNTV_TINYUSB2_COLD 0x3223 205 - #define USB_PID_DNTV_TINYUSB2_WARM 0x3224 206 - #define USB_PID_ULTIMA_TVBOX_COLD 0x8105 207 - #define USB_PID_ULTIMA_TVBOX_WARM 0x8106 208 - #define USB_PID_ULTIMA_TVBOX_AN2235_COLD 0x8107 209 - #define USB_PID_ULTIMA_TVBOX_AN2235_WARM 0x8108 210 - #define USB_PID_ULTIMA_TVBOX_ANCHOR_COLD 0x2235 211 - #define USB_PID_ULTIMA_TVBOX_USB2_COLD 0x8109 212 - #define USB_PID_ULTIMA_TVBOX_USB2_WARM 0x810a 213 - #define USB_PID_ARTEC_T14_COLD 0x810b 214 - #define USB_PID_ARTEC_T14_WARM 0x810c 215 - #define USB_PID_ARTEC_T14BR 0x810f 216 - #define USB_PID_ULTIMA_TVBOX_USB2_FX_COLD 0x8613 217 - #define USB_PID_ULTIMA_TVBOX_USB2_FX_WARM 0x1002 218 - #define USB_PID_UNK_HYPER_PALTEK_COLD 0x005e 219 - #define USB_PID_UNK_HYPER_PALTEK_WARM 0x005f 220 - #define USB_PID_HANFTEK_UMT_010_COLD 0x0001 221 - #define USB_PID_HANFTEK_UMT_010_WARM 0x0015 222 - #define USB_PID_DTT200U_COLD 0x0201 223 - #define USB_PID_DTT200U_WARM 0x0301 224 - #define USB_PID_WT220U_ZAP250_COLD 0x0220 225 - #define USB_PID_WT220U_COLD 0x0222 226 - #define USB_PID_WT220U_WARM 0x0221 227 - #define USB_PID_WT220U_FC_COLD 0x0225 228 - #define USB_PID_WT220U_FC_WARM 0x0226 229 - #define USB_PID_WT220U_ZL0353_COLD 0x022a 230 - #define USB_PID_WT220U_ZL0353_WARM 0x022b 231 - #define USB_PID_WINTV_NOVA_T_USB2_COLD 0x9300 232 - #define USB_PID_WINTV_NOVA_T_USB2_WARM 0x9301 233 - #define USB_PID_HAUPPAUGE_NOVA_T_500 0x9941 234 - #define USB_PID_HAUPPAUGE_NOVA_T_500_2 0x9950 235 - #define USB_PID_HAUPPAUGE_NOVA_T_500_3 0x8400 236 - #define USB_PID_HAUPPAUGE_NOVA_T_STICK 0x7050 237 - #define USB_PID_HAUPPAUGE_NOVA_T_STICK_2 0x7060 238 - #define USB_PID_HAUPPAUGE_NOVA_T_STICK_3 0x7070 239 - #define USB_PID_HAUPPAUGE_MYTV_T 0x7080 240 - #define USB_PID_HAUPPAUGE_NOVA_TD_STICK 0x9580 241 - #define USB_PID_HAUPPAUGE_NOVA_TD_STICK_52009 0x5200 242 - #define USB_PID_HAUPPAUGE_TIGER_ATSC 0xb200 243 - #define USB_PID_HAUPPAUGE_TIGER_ATSC_B210 0xb210 244 - #define USB_PID_AVERMEDIA_EXPRESS 0xb568 245 - #define USB_PID_AVERMEDIA_VOLAR 0xa807 246 - #define USB_PID_AVERMEDIA_VOLAR_2 0xb808 247 - #define USB_PID_AVERMEDIA_VOLAR_A868R 0xa868 248 - #define USB_PID_AVERMEDIA_MCE_USB_M038 0x1228 249 - #define USB_PID_AVERMEDIA_HYBRID_ULTRA_USB_M039R 0x0039 250 - #define USB_PID_AVERMEDIA_HYBRID_ULTRA_USB_M039R_ATSC 0x1039 251 - #define USB_PID_AVERMEDIA_HYBRID_ULTRA_USB_M039R_DVBT 0x2039 252 - #define USB_PID_AVERMEDIA_VOLAR_X 0xa815 253 - #define USB_PID_AVERMEDIA_VOLAR_X_2 0x8150 254 - #define USB_PID_AVERMEDIA_A309 0xa309 255 - #define USB_PID_AVERMEDIA_A310 0xa310 256 - #define USB_PID_AVERMEDIA_A850 0x850a 257 - #define USB_PID_AVERMEDIA_A850T 0x850b 258 - #define USB_PID_AVERMEDIA_A805 0xa805 259 - #define USB_PID_AVERMEDIA_A815M 0x815a 260 - #define USB_PID_AVERMEDIA_A835 0xa835 261 - #define USB_PID_AVERMEDIA_B835 0xb835 262 - #define USB_PID_AVERMEDIA_A835B_1835 0x1835 263 - #define USB_PID_AVERMEDIA_A835B_2835 0x2835 264 - #define USB_PID_AVERMEDIA_A835B_3835 0x3835 265 - #define USB_PID_AVERMEDIA_A835B_4835 0x4835 266 - #define USB_PID_AVERMEDIA_1867 0x1867 267 - #define USB_PID_AVERMEDIA_A867 0xa867 268 - #define USB_PID_AVERMEDIA_H335 0x0335 269 - #define USB_PID_AVERMEDIA_TD110 0xa110 270 - #define USB_PID_AVERMEDIA_TD310 0x1871 271 - #define USB_PID_AVERMEDIA_TWINSTAR 0x0825 272 - #define USB_PID_TECHNOTREND_CONNECT_S2400 0x3006 273 - #define USB_PID_TECHNOTREND_CONNECT_S2400_8KEEPROM 0x3009 274 - #define USB_PID_TECHNOTREND_CONNECT_CT3650 0x300d 275 - #define USB_PID_TECHNOTREND_CONNECT_S2_4600 0x3011 276 - #define USB_PID_TECHNOTREND_CONNECT_CT2_4650_CI 0x3012 277 - #define USB_PID_TECHNOTREND_CONNECT_CT2_4650_CI_2 0x3015 278 - #define USB_PID_TECHNOTREND_TVSTICK_CT2_4400 0x3014 279 - #define USB_PID_TECHNOTREND_CONNECT_S2_4650_CI 0x3017 280 - #define USB_PID_TERRATEC_CINERGY_DT_XS_DIVERSITY 0x005a 281 - #define USB_PID_TERRATEC_CINERGY_DT_XS_DIVERSITY_2 0x0081 282 - #define USB_PID_TERRATEC_CINERGY_HT_USB_XE 0x0058 283 - #define USB_PID_TERRATEC_CINERGY_HT_EXPRESS 0x0060 284 - #define USB_PID_TERRATEC_CINERGY_T_EXPRESS 0x0062 285 - #define USB_PID_TERRATEC_CINERGY_T_XXS 0x0078 286 - #define USB_PID_TERRATEC_CINERGY_T_XXS_2 0x00ab 287 - #define USB_PID_TERRATEC_CINERGY_S2_R1 0x00a8 288 - #define USB_PID_TERRATEC_CINERGY_S2_R2 0x00b0 289 - #define USB_PID_TERRATEC_CINERGY_S2_R3 0x0102 290 - #define USB_PID_TERRATEC_CINERGY_S2_R4 0x0105 291 - #define USB_PID_TERRATEC_CINERGY_S2_1 0x1181 292 - #define USB_PID_TERRATEC_CINERGY_S2_2 0x1182 293 - #define USB_PID_TERRATEC_H7 0x10b4 294 - #define USB_PID_TERRATEC_H7_2 0x10a3 295 - #define USB_PID_TERRATEC_H7_3 0x10a5 296 - #define USB_PID_TERRATEC_T1 0x10ae 297 - #define USB_PID_TERRATEC_T3 0x10a0 298 - #define USB_PID_TERRATEC_T5 0x10a1 299 - #define USB_PID_NOXON_DAB_STICK 0x00b3 300 - #define USB_PID_NOXON_DAB_STICK_REV2 0x00e0 301 - #define USB_PID_NOXON_DAB_STICK_REV3 0x00b4 302 - #define USB_PID_PINNACLE_EXPRESSCARD_320CX 0x022e 303 - #define USB_PID_PINNACLE_PCTV2000E 0x022c 304 - #define USB_PID_PINNACLE_PCTV_DVB_T_FLASH 0x0228 305 - #define USB_PID_PINNACLE_PCTV_DUAL_DIVERSITY_DVB_T 0x0229 306 - #define USB_PID_PINNACLE_PCTV71E 0x022b 307 - #define USB_PID_PINNACLE_PCTV72E 0x0236 308 - #define USB_PID_PINNACLE_PCTV73E 0x0237 309 - #define USB_PID_PINNACLE_PCTV310E 0x3211 310 - #define USB_PID_PINNACLE_PCTV801E 0x023a 311 - #define USB_PID_PINNACLE_PCTV801E_SE 0x023b 312 - #define USB_PID_PINNACLE_PCTV340E 0x023d 313 - #define USB_PID_PINNACLE_PCTV340E_SE 0x023e 314 - #define USB_PID_PINNACLE_PCTV73A 0x0243 315 - #define USB_PID_PINNACLE_PCTV73ESE 0x0245 316 - #define USB_PID_PINNACLE_PCTV74E 0x0246 317 - #define USB_PID_PINNACLE_PCTV282E 0x0248 318 - #define USB_PID_PIXELVIEW_SBTVD 0x5010 319 - #define USB_PID_PCTV_200E 0x020e 320 - #define USB_PID_PCTV_400E 0x020f 321 - #define USB_PID_PCTV_450E 0x0222 322 - #define USB_PID_PCTV_452E 0x021f 323 - #define USB_PID_PCTV_78E 0x025a 324 - #define USB_PID_PCTV_79E 0x0262 325 - #define USB_PID_REALTEK_RTL2831U 0x2831 326 - #define USB_PID_REALTEK_RTL2832U 0x2832 327 - #define USB_PID_TECHNOTREND_CONNECT_S2_3600 0x3007 328 - #define USB_PID_TECHNOTREND_CONNECT_S2_3650_CI 0x300a 329 - #define USB_PID_NEBULA_DIGITV 0x0201 330 - #define USB_PID_DVICO_BLUEBIRD_LGDT 0xd820 331 - #define USB_PID_DVICO_BLUEBIRD_LG064F_COLD 0xd500 332 - #define USB_PID_DVICO_BLUEBIRD_LG064F_WARM 0xd501 333 - #define USB_PID_DVICO_BLUEBIRD_LGZ201_COLD 0xdb00 334 - #define USB_PID_DVICO_BLUEBIRD_LGZ201_WARM 0xdb01 335 - #define USB_PID_DVICO_BLUEBIRD_TH7579_COLD 0xdb10 336 - #define USB_PID_DVICO_BLUEBIRD_TH7579_WARM 0xdb11 337 189 #define USB_PID_DVICO_BLUEBIRD_DUAL_1_COLD 0xdb50 338 190 #define USB_PID_DVICO_BLUEBIRD_DUAL_1_WARM 0xdb51 339 191 #define USB_PID_DVICO_BLUEBIRD_DUAL_2_COLD 0xdb58 ··· 201 335 #define USB_PID_DVICO_BLUEBIRD_DUAL_4_REV_2 0xdb98 202 336 #define USB_PID_DVICO_BLUEBIRD_DVB_T_NANO_2 0xdb70 203 337 #define USB_PID_DVICO_BLUEBIRD_DVB_T_NANO_2_NFW_WARM 0xdb71 204 - #define USB_PID_DIGITALNOW_BLUEBIRD_DUAL_1_COLD 0xdb54 205 - #define USB_PID_DIGITALNOW_BLUEBIRD_DUAL_1_WARM 0xdb55 206 - #define USB_PID_MEDION_MD95700 0x0932 207 - #define USB_PID_MSI_MEGASKY580 0x5580 208 - #define USB_PID_MSI_MEGASKY580_55801 0x5581 209 - #define USB_PID_KYE_DVB_T_COLD 0x701e 210 - #define USB_PID_KYE_DVB_T_WARM 0x701f 211 - #define USB_PID_LITEON_DVB_T_COLD 0xf000 212 - #define USB_PID_LITEON_DVB_T_WARM 0xf001 213 - #define USB_PID_DIGIVOX_MINI_SL_COLD 0xe360 214 - #define USB_PID_DIGIVOX_MINI_SL_WARM 0xe361 215 - #define USB_PID_GRANDTEC_DVBT_USB2_COLD 0x0bc6 216 - #define USB_PID_GRANDTEC_DVBT_USB2_WARM 0x0bc7 217 - #define USB_PID_WINFAST_DTV2000DS 0x6a04 218 - #define USB_PID_WINFAST_DTV2000DS_PLUS 0x6f12 219 - #define USB_PID_WINFAST_DTV_DONGLE_COLD 0x6025 220 - #define USB_PID_WINFAST_DTV_DONGLE_WARM 0x6026 221 - #define USB_PID_WINFAST_DTV_DONGLE_STK7700P 0x6f00 222 - #define USB_PID_WINFAST_DTV_DONGLE_H 0x60f6 223 - #define USB_PID_WINFAST_DTV_DONGLE_STK7700P_2 0x6f01 224 - #define USB_PID_WINFAST_DTV_DONGLE_GOLD 0x6029 225 - #define USB_PID_WINFAST_DTV_DONGLE_MINID 0x6f0f 226 - #define USB_PID_GENPIX_8PSK_REV_1_COLD 0x0200 227 - #define USB_PID_GENPIX_8PSK_REV_1_WARM 0x0201 228 - #define USB_PID_GENPIX_8PSK_REV_2 0x0202 229 - #define USB_PID_GENPIX_SKYWALKER_1 0x0203 230 - #define USB_PID_GENPIX_SKYWALKER_CW3K 0x0204 231 - #define USB_PID_GENPIX_SKYWALKER_2 0x0206 232 - #define USB_PID_SIGMATEK_DVB_110 0x6610 233 - #define USB_PID_MSI_DIGI_VOX_MINI_II 0x1513 234 - #define USB_PID_MSI_DIGIVOX_DUO 0x8801 235 - #define USB_PID_OPERA1_COLD 0x2830 236 - #define USB_PID_OPERA1_WARM 0x3829 237 - #define USB_PID_LIFEVIEW_TV_WALKER_TWIN_COLD 0x0514 238 - #define USB_PID_LIFEVIEW_TV_WALKER_TWIN_WARM 0x0513 239 - #define USB_PID_GIGABYTE_U7000 0x7001 240 - #define USB_PID_GIGABYTE_U8000 0x7002 241 - #define USB_PID_ASUS_U3000 0x171f 242 - #define USB_PID_ASUS_U3000H 0x1736 243 - #define USB_PID_ASUS_U3100 0x173f 244 - #define USB_PID_ASUS_U3100MINI_PLUS 0x1779 245 - #define USB_PID_YUAN_EC372S 0x1edc 246 - #define USB_PID_YUAN_STK7700PH 0x1f08 247 - #define USB_PID_YUAN_PD378S 0x2edc 248 - #define USB_PID_YUAN_MC770 0x0871 249 - #define USB_PID_YUAN_STK7700D 0x1efc 250 - #define USB_PID_YUAN_STK7700D_2 0x1e8c 251 - #define USB_PID_DW2102 0x2102 252 - #define USB_PID_DW2104 0x2104 253 - #define USB_PID_DW3101 0x3101 254 - #define USB_PID_XTENSIONS_XD_380 0x0381 255 - #define USB_PID_TELESTAR_STARSTICK_2 0x8000 256 - #define USB_PID_MSI_DIGI_VOX_MINI_III 0x8807 257 - #define USB_PID_SONY_PLAYTV 0x0003 258 - #define USB_PID_MYGICA_D689 0xd811 259 - #define USB_PID_MYGICA_T230 0xc688 260 - #define USB_PID_MYGICA_T230C 0xc689 261 - #define USB_PID_MYGICA_T230C2 0xc68a 262 - #define USB_PID_MYGICA_T230C_LITE 0xc699 263 - #define USB_PID_MYGICA_T230C2_LITE 0xc69a 264 - #define USB_PID_MYGICA_T230A 0x689a 338 + #define USB_PID_DVICO_BLUEBIRD_LG064F_COLD 0xd500 339 + #define USB_PID_DVICO_BLUEBIRD_LG064F_WARM 0xd501 340 + #define USB_PID_DVICO_BLUEBIRD_LGDT 0xd820 341 + #define USB_PID_DVICO_BLUEBIRD_LGZ201_COLD 0xdb00 342 + #define USB_PID_DVICO_BLUEBIRD_LGZ201_WARM 0xdb01 343 + #define USB_PID_DVICO_BLUEBIRD_TH7579_COLD 0xdb10 344 + #define USB_PID_DVICO_BLUEBIRD_TH7579_WARM 0xdb11 345 + #define USB_PID_E3C_EC168 0x1689 346 + #define USB_PID_E3C_EC168_2 0xfffa 347 + #define USB_PID_E3C_EC168_3 0xfffb 348 + #define USB_PID_E3C_EC168_4 0x1001 349 + #define USB_PID_E3C_EC168_5 0x1002 265 350 #define USB_PID_ELGATO_EYETV_DIVERSITY 0x0011 266 351 #define USB_PID_ELGATO_EYETV_DTT 0x0021 267 352 #define USB_PID_ELGATO_EYETV_DTT_2 0x003f ··· 220 403 #define USB_PID_ELGATO_EYETV_SAT 0x002a 221 404 #define USB_PID_ELGATO_EYETV_SAT_V2 0x0025 222 405 #define USB_PID_ELGATO_EYETV_SAT_V3 0x0036 223 - #define USB_PID_DVB_T_USB_STICK_HIGH_SPEED_COLD 0x5000 224 - #define USB_PID_DVB_T_USB_STICK_HIGH_SPEED_WARM 0x5001 406 + #define USB_PID_EMPIA_DIGIVOX_MINI_SL_COLD 0xe360 407 + #define USB_PID_EMPIA_DIGIVOX_MINI_SL_WARM 0xe361 408 + #define USB_PID_EMPIA_VSTREAM_COLD 0x17de 409 + #define USB_PID_EMPIA_VSTREAM_WARM 0x17df 410 + #define USB_PID_EVOLUTEPC_TVWAY_PLUS 0x0002 411 + #define USB_PID_EVOLVEO_XTRATV_STICK 0xa115 412 + #define USB_PID_FREECOM_DVBT 0x0160 413 + #define USB_PID_FREECOM_DVBT_2 0x0161 225 414 #define USB_PID_FRIIO_WHITE 0x0001 226 - #define USB_PID_TVWAY_PLUS 0x0002 415 + #define USB_PID_GENIATECH_SU3000 0x3000 416 + #define USB_PID_GENIATECH_T220 0xd220 417 + #define USB_PID_GENIATECH_X3M_SPC1400HD 0x3100 418 + #define USB_PID_GENIUS_TVGO_DVB_T03 0x4012 419 + #define USB_PID_GENPIX_8PSK_REV_1_COLD 0x0200 420 + #define USB_PID_GENPIX_8PSK_REV_1_WARM 0x0201 421 + #define USB_PID_GENPIX_8PSK_REV_2 0x0202 422 + #define USB_PID_GENPIX_SKYWALKER_1 0x0203 423 + #define USB_PID_GENPIX_SKYWALKER_2 0x0206 424 + #define USB_PID_GENPIX_SKYWALKER_CW3K 0x0204 425 + #define USB_PID_GIGABYTE_U7000 0x7001 426 + #define USB_PID_GIGABYTE_U8000 0x7002 427 + #define USB_PID_GOTVIEW_SAT_HD 0x5456 428 + #define USB_PID_GRANDTEC_DVBT_USB2_COLD 0x0bc6 429 + #define USB_PID_GRANDTEC_DVBT_USB2_WARM 0x0bc7 430 + #define USB_PID_GRANDTEC_DVBT_USB_COLD 0x0fa0 431 + #define USB_PID_GRANDTEC_DVBT_USB_WARM 0x0fa1 432 + #define USB_PID_GRANDTEC_MOD3000_COLD 0x0bb8 433 + #define USB_PID_GRANDTEC_MOD3000_WARM 0x0bb9 434 + #define USB_PID_HAMA_DVBT_HYBRID 0x2758 435 + #define USB_PID_HANFTEK_UMT_010_COLD 0x0001 436 + #define USB_PID_HANFTEK_UMT_010_WARM 0x0015 437 + #define USB_PID_HAUPPAUGE_MAX_S2 0xd900 438 + #define USB_PID_HAUPPAUGE_MYTV_T 0x7080 439 + #define USB_PID_HAUPPAUGE_NOVA_TD_STICK 0x9580 440 + #define USB_PID_HAUPPAUGE_NOVA_TD_STICK_52009 0x5200 441 + #define USB_PID_HAUPPAUGE_NOVA_T_500 0x9941 442 + #define USB_PID_HAUPPAUGE_NOVA_T_500_2 0x9950 443 + #define USB_PID_HAUPPAUGE_NOVA_T_500_3 0x8400 444 + #define USB_PID_HAUPPAUGE_NOVA_T_STICK 0x7050 445 + #define USB_PID_HAUPPAUGE_NOVA_T_STICK_2 0x7060 446 + #define USB_PID_HAUPPAUGE_NOVA_T_STICK_3 0x7070 447 + #define USB_PID_HAUPPAUGE_TIGER_ATSC 0xb200 448 + #define USB_PID_HAUPPAUGE_TIGER_ATSC_B210 0xb210 449 + #define USB_PID_HAUPPAUGE_WINTV_NOVA_T_USB2_COLD 0x9300 450 + #define USB_PID_HAUPPAUGE_WINTV_NOVA_T_USB2_WARM 0x9301 451 + #define USB_PID_HUMAX_DVB_T_STICK_HIGH_SPEED_COLD 0x5000 452 + #define USB_PID_HUMAX_DVB_T_STICK_HIGH_SPEED_WARM 0x5001 453 + #define USB_PID_INTEL_CE9500 0x9500 454 + #define USB_PID_ITETECH_IT9135 0x9135 455 + #define USB_PID_ITETECH_IT9135_9005 0x9005 456 + #define USB_PID_ITETECH_IT9135_9006 0x9006 457 + #define USB_PID_ITETECH_IT9303 0x9306 458 + #define USB_PID_KWORLD_395U 0xe396 459 + #define USB_PID_KWORLD_395U_2 0xe39b 460 + #define USB_PID_KWORLD_395U_3 0xe395 461 + #define USB_PID_KWORLD_395U_4 0xe39a 462 + #define USB_PID_KWORLD_399U 0xe399 463 + #define USB_PID_KWORLD_399U_2 0xe400 464 + #define USB_PID_KWORLD_MC810 0xc810 465 + #define USB_PID_KWORLD_PC160_2T 0xc160 466 + #define USB_PID_KWORLD_PC160_T 0xc161 467 + #define USB_PID_KWORLD_UB383_T 0xe383 468 + #define USB_PID_KWORLD_UB499_2T_T09 0xe409 469 + #define USB_PID_KWORLD_VSTREAM_COLD 0x17de 470 + #define USB_PID_KYE_DVB_T_COLD 0x701e 471 + #define USB_PID_KYE_DVB_T_WARM 0x701f 472 + #define USB_PID_LEADTEK_WINFAST_DTV_DONGLE_COLD 0x6025 473 + #define USB_PID_LEADTEK_WINFAST_DTV_DONGLE_H 0x60f6 474 + #define USB_PID_LEADTEK_WINFAST_DTV_DONGLE_STK7700P 0x6f00 475 + #define USB_PID_LEADTEK_WINFAST_DTV_DONGLE_STK7700P_2 0x6f01 476 + #define USB_PID_LEADTEK_WINFAST_DTV_DONGLE_WARM 0x6026 477 + #define USB_PID_LITEON_DVB_T_COLD 0xf000 478 + #define USB_PID_LITEON_DVB_T_WARM 0xf001 479 + #define USB_PID_MEDION_CREATIX_CTX1921 0x1921 480 + #define USB_PID_MEDION_MD95700 0x0932 481 + #define USB_PID_MICROSOFT_XBOX_ONE_TUNER 0x02d5 482 + #define USB_PID_MIGLIA_WT220U_ZAP250_COLD 0x0220 483 + #define USB_PID_MSI_DIGIVOX_DUO 0x8801 484 + #define USB_PID_MSI_DIGI_VOX_MINI_III 0x8807 485 + #define USB_PID_MSI_MEGASKY580 0x5580 486 + #define USB_PID_MSI_MEGASKY580_55801 0x5581 487 + #define USB_PID_MYGICA_D689 0xd811 488 + #define USB_PID_MYGICA_T230 0xc688 489 + #define USB_PID_MYGICA_T230A 0x689a 490 + #define USB_PID_MYGICA_T230C 0xc689 491 + #define USB_PID_MYGICA_T230C2 0xc68a 492 + #define USB_PID_MYGICA_T230C2_LITE 0xc69a 493 + #define USB_PID_MYGICA_T230C_LITE 0xc699 494 + #define USB_PID_NOXON_DAB_STICK 0x00b3 495 + #define USB_PID_NOXON_DAB_STICK_REV2 0x00e0 496 + #define USB_PID_NOXON_DAB_STICK_REV3 0x00b4 497 + #define USB_PID_OPERA1_WARM 0x3829 498 + #define USB_PID_PCTV_2002E 0x025c 499 + #define USB_PID_PCTV_2002E_SE 0x025d 500 + #define USB_PID_PCTV_200E 0x020e 501 + #define USB_PID_PCTV_78E 0x025a 502 + #define USB_PID_PCTV_79E 0x0262 503 + #define USB_PID_PCTV_DIBCOM_STK8096PVR 0x1faa 504 + #define USB_PID_PCTV_PINNACLE_PCTV282E 0x0248 505 + #define USB_PID_PCTV_PINNACLE_PCTV73ESE 0x0245 506 + #define USB_PID_PINNACLE_EXPRESSCARD_320CX 0x022e 507 + #define USB_PID_PINNACLE_PCTV2000E 0x022c 508 + #define USB_PID_PINNACLE_PCTV282E 0x0248 509 + #define USB_PID_PINNACLE_PCTV340E 0x023d 510 + #define USB_PID_PINNACLE_PCTV340E_SE 0x023e 511 + #define USB_PID_PINNACLE_PCTV71E 0x022b 512 + #define USB_PID_PINNACLE_PCTV72E 0x0236 513 + #define USB_PID_PINNACLE_PCTV73A 0x0243 514 + #define USB_PID_PINNACLE_PCTV73E 0x0237 515 + #define USB_PID_PINNACLE_PCTV73ESE 0x0245 516 + #define USB_PID_PINNACLE_PCTV74E 0x0246 517 + #define USB_PID_PINNACLE_PCTV801E 0x023a 518 + #define USB_PID_PINNACLE_PCTV801E_SE 0x023b 519 + #define USB_PID_PINNACLE_PCTV_400E 0x020f 520 + #define USB_PID_PINNACLE_PCTV_450E 0x0222 521 + #define USB_PID_PINNACLE_PCTV_452E 0x021f 522 + #define USB_PID_PINNACLE_PCTV_DUAL_DIVERSITY_DVB_T 0x0229 523 + #define USB_PID_PINNACLE_PCTV_DVB_T_FLASH 0x0228 524 + #define USB_PID_PIXELVIEW_SBTVD 0x5010 525 + #define USB_PID_PROF_1100 0xb012 526 + #define USB_PID_PROF_7500 0x7500 527 + #define USB_PID_PROLECTRIX_DV107669 0xd803 528 + #define USB_PID_REALTEK_RTL2831U 0x2831 529 + #define USB_PID_REALTEK_RTL2832U 0x2832 530 + #define USB_PID_SIGMATEK_DVB_110 0x6610 531 + #define USB_PID_SONY_PLAYTV 0x0003 227 532 #define USB_PID_SVEON_STV20 0xe39d 228 533 #define USB_PID_SVEON_STV20_RTL2832U 0xd39d 229 534 #define USB_PID_SVEON_STV21 0xd3b0 230 535 #define USB_PID_SVEON_STV22 0xe401 231 536 #define USB_PID_SVEON_STV22_IT9137 0xe411 232 - #define USB_PID_AZUREWAVE_AZ6027 0x3275 233 - #define USB_PID_TERRATEC_DVBS2CI_V1 0x10a4 234 - #define USB_PID_TERRATEC_DVBS2CI_V2 0x10ac 537 + #define USB_PID_SVEON_STV27 0xd3af 538 + #define USB_PID_TECHNISAT_AIRSTAR_TELESTICK_2 0x0004 539 + #define USB_PID_TECHNISAT_USB2_CABLESTAR_HDCI 0x0003 540 + #define USB_PID_TECHNISAT_USB2_DVB_S2 0x0500 235 541 #define USB_PID_TECHNISAT_USB2_HDCI_V1 0x0001 236 542 #define USB_PID_TECHNISAT_USB2_HDCI_V2 0x0002 237 - #define USB_PID_TECHNISAT_USB2_CABLESTAR_HDCI 0x0003 238 - #define USB_PID_TECHNISAT_AIRSTAR_TELESTICK_2 0x0004 239 - #define USB_PID_TECHNISAT_USB2_DVB_S2 0x0500 240 - #define USB_PID_CPYTO_REDI_PC50A 0xa803 241 - #define USB_PID_CTVDIGDUAL_V2 0xe410 242 - #define USB_PID_PCTV_2002E 0x025c 243 - #define USB_PID_PCTV_2002E_SE 0x025d 244 - #define USB_PID_SVEON_STV27 0xd3af 245 - #define USB_PID_TURBOX_DTT_2000 0xd3a4 246 - #define USB_PID_WINTV_SOLOHD 0x0264 247 - #define USB_PID_WINTV_SOLOHD_2 0x8268 248 - #define USB_PID_EVOLVEO_XTRATV_STICK 0xa115 249 - #define USB_PID_HAMA_DVBT_HYBRID 0x2758 250 - #define USB_PID_XBOX_ONE_TUNER 0x02d5 251 - #define USB_PID_PROLECTRIX_DV107669 0xd803 543 + #define USB_PID_TECHNOTREND_CONNECT_CT2_4650_CI 0x3012 544 + #define USB_PID_TECHNOTREND_CONNECT_CT2_4650_CI_2 0x3015 545 + #define USB_PID_TECHNOTREND_CONNECT_CT3650 0x300d 546 + #define USB_PID_TECHNOTREND_CONNECT_S2400 0x3006 547 + #define USB_PID_TECHNOTREND_CONNECT_S2400_8KEEPROM 0x3009 548 + #define USB_PID_TECHNOTREND_CONNECT_S2_3600 0x3007 549 + #define USB_PID_TECHNOTREND_CONNECT_S2_3650_CI 0x300a 550 + #define USB_PID_TECHNOTREND_CONNECT_S2_4600 0x3011 551 + #define USB_PID_TECHNOTREND_CONNECT_S2_4650_CI 0x3017 552 + #define USB_PID_TECHNOTREND_TVSTICK_CT2_4400 0x3014 553 + #define USB_PID_TELESTAR_STARSTICK_2 0x8000 554 + #define USB_PID_TERRATEC_CINERGY_DT_XS_DIVERSITY 0x005a 555 + #define USB_PID_TERRATEC_CINERGY_DT_XS_DIVERSITY_2 0x0081 556 + #define USB_PID_TERRATEC_CINERGY_HT_EXPRESS 0x0060 557 + #define USB_PID_TERRATEC_CINERGY_HT_USB_XE 0x0058 558 + #define USB_PID_TERRATEC_CINERGY_S 0x0064 559 + #define USB_PID_TERRATEC_CINERGY_S2_1 0x1181 560 + #define USB_PID_TERRATEC_CINERGY_S2_2 0x1182 561 + #define USB_PID_TERRATEC_CINERGY_S2_BOX 0x0105 562 + #define USB_PID_TERRATEC_CINERGY_S2_R1 0x00a8 563 + #define USB_PID_TERRATEC_CINERGY_S2_R2 0x00b0 564 + #define USB_PID_TERRATEC_CINERGY_S2_R3 0x0102 565 + #define USB_PID_TERRATEC_CINERGY_S2_R4 0x0105 566 + #define USB_PID_TERRATEC_CINERGY_T2 0x0038 567 + #define USB_PID_TERRATEC_CINERGY_TC2_STICK 0x10b2 568 + #define USB_PID_TERRATEC_CINERGY_T_EXPRESS 0x0062 569 + #define USB_PID_TERRATEC_CINERGY_T_STICK 0x0093 570 + #define USB_PID_TERRATEC_CINERGY_T_STICK_BLACK_REV1 0x00a9 571 + #define USB_PID_TERRATEC_CINERGY_T_STICK_DUAL_RC 0x0099 572 + #define USB_PID_TERRATEC_CINERGY_T_STICK_RC 0x0097 573 + #define USB_PID_TERRATEC_CINERGY_T_USB_XE 0x0055 574 + #define USB_PID_TERRATEC_CINERGY_T_USB_XE_REV2 0x0069 575 + #define USB_PID_TERRATEC_CINERGY_T_XXS 0x0078 576 + #define USB_PID_TERRATEC_CINERGY_T_XXS_2 0x00ab 577 + #define USB_PID_TERRATEC_DVBS2CI_V1 0x10a4 578 + #define USB_PID_TERRATEC_DVBS2CI_V2 0x10ac 579 + #define USB_PID_TERRATEC_H7 0x10b4 580 + #define USB_PID_TERRATEC_H7_2 0x10a3 581 + #define USB_PID_TERRATEC_H7_3 0x10a5 582 + #define USB_PID_TERRATEC_T1 0x10ae 583 + #define USB_PID_TERRATEC_T3 0x10a0 584 + #define USB_PID_TERRATEC_T5 0x10a1 585 + #define USB_PID_TEVII_S421 0xd421 586 + #define USB_PID_TEVII_S480_1 0xd481 587 + #define USB_PID_TEVII_S480_2 0xd482 588 + #define USB_PID_TEVII_S482_1 0xd483 589 + #define USB_PID_TEVII_S482_2 0xd484 590 + #define USB_PID_TEVII_S630 0xd630 591 + #define USB_PID_TEVII_S632 0xd632 592 + #define USB_PID_TEVII_S650 0xd650 593 + #define USB_PID_TEVII_S660 0xd660 594 + #define USB_PID_TEVII_S662 0xd662 595 + #define USB_PID_TINYTWIN 0x3226 596 + #define USB_PID_TINYTWIN_2 0xe402 597 + #define USB_PID_TINYTWIN_3 0x9016 598 + #define USB_PID_TREKSTOR_DVBT 0x901b 599 + #define USB_PID_TREKSTOR_TERRES_2_0 0xC803 600 + #define USB_PID_TURBOX_DTT_2000 0xd3a4 601 + #define USB_PID_TWINHAN_VP7021_WARM 0x3208 602 + #define USB_PID_TWINHAN_VP7041_COLD 0x3201 603 + #define USB_PID_TWINHAN_VP7041_WARM 0x3202 604 + #define USB_PID_ULTIMA_ARTEC_T14BR 0x810f 605 + #define USB_PID_ULTIMA_ARTEC_T14_COLD 0x810b 606 + #define USB_PID_ULTIMA_ARTEC_T14_WARM 0x810c 607 + #define USB_PID_ULTIMA_TVBOX_AN2235_COLD 0x8107 608 + #define USB_PID_ULTIMA_TVBOX_AN2235_WARM 0x8108 609 + #define USB_PID_ULTIMA_TVBOX_ANCHOR_COLD 0x2235 610 + #define USB_PID_ULTIMA_TVBOX_COLD 0x8105 611 + #define USB_PID_ULTIMA_TVBOX_USB2_COLD 0x8109 612 + #define USB_PID_ULTIMA_TVBOX_USB2_FX_COLD 0x8613 613 + #define USB_PID_ULTIMA_TVBOX_USB2_FX_WARM 0x1002 614 + #define USB_PID_ULTIMA_TVBOX_USB2_WARM 0x810a 615 + #define USB_PID_ULTIMA_TVBOX_WARM 0x8106 616 + #define USB_PID_UNIWILL_STK7700P 0x6003 617 + #define USB_PID_UNK_HYPER_PALTEK_COLD 0x005e 618 + #define USB_PID_UNK_HYPER_PALTEK_WARM 0x005f 619 + #define USB_PID_VISIONPLUS_PINNACLE_PCTV310E 0x3211 620 + #define USB_PID_VISIONPLUS_TINYUSB2_COLD 0x3223 621 + #define USB_PID_VISIONPLUS_TINYUSB2_WARM 0x3224 622 + #define USB_PID_VISIONPLUS_VP7020_COLD 0x3203 623 + #define USB_PID_VISIONPLUS_VP7020_WARM 0x3204 624 + #define USB_PID_VISIONPLUS_VP7021_COLD 0x3207 625 + #define USB_PID_VISIONPLUS_VP7041_COLD 0x3201 626 + #define USB_PID_VISIONPLUS_VP7041_WARM 0x3202 627 + #define USB_PID_VISIONPLUS_VP7045_COLD 0x3205 628 + #define USB_PID_VISIONPLUS_VP7045_WARM 0x3206 629 + #define USB_PID_WIDEVIEW_DTT200U_COLD 0x0201 630 + #define USB_PID_WIDEVIEW_DTT200U_WARM 0x0301 631 + #define USB_PID_WIDEVIEW_DVBT_USB_COLD 0x0001 632 + #define USB_PID_WIDEVIEW_DVBT_USB_WARM 0x0002 633 + #define USB_PID_WIDEVIEW_WT220U_COLD 0x0222 634 + #define USB_PID_WIDEVIEW_WT220U_FC_COLD 0x0225 635 + #define USB_PID_WIDEVIEW_WT220U_FC_WARM 0x0226 636 + #define USB_PID_WIDEVIEW_WT220U_WARM 0x0221 637 + #define USB_PID_WIDEVIEW_WT220U_ZAP250_COLD 0x0220 638 + #define USB_PID_WIDEVIEW_WT220U_ZL0353_COLD 0x022a 639 + #define USB_PID_WIDEVIEW_WT220U_ZL0353_WARM 0x022b 640 + #define USB_PID_WINFAST_DTV2000DS 0x6a04 641 + #define USB_PID_WINFAST_DTV2000DS_PLUS 0x6f12 642 + #define USB_PID_WINFAST_DTV_DONGLE_GOLD 0x6029 643 + #define USB_PID_WINFAST_DTV_DONGLE_MINID 0x6f0f 644 + #define USB_PID_WINTV_SOLOHD 0x0264 645 + #define USB_PID_WINTV_SOLOHD_2 0x8268 646 + #define USB_PID_XTENSIONS_XD_380 0x0381 647 + #define USB_PID_YUAN_EC372S 0x1edc 648 + #define USB_PID_YUAN_MC770 0x0871 649 + #define USB_PID_YUAN_PD378S 0x2edc 650 + #define USB_PID_YUAN_STK7700D 0x1efc 651 + #define USB_PID_YUAN_STK7700D_2 0x1e8c 652 + #define USB_PID_YUAN_STK7700PH 0x1f08 653 + 252 654 #endif

+1 -1

include/media/i2c/mt9t112.h

+1 -1

include/media/i2c/wm8775.h

··· 23 23 24 24 struct wm8775_platform_data { 25 25 /* 26 - * FIXME: Instead, we should parametrize the params 26 + * FIXME: Instead, we should parameterize the params 27 27 * that need different settings between ivtv, pvrusb2, and Nova-S 28 28 */ 29 29 bool is_nova_s;

+40 -11

include/media/media-device.h

··· 13 13 14 14 #include <linux/list.h> 15 15 #include <linux/mutex.h> 16 + #include <linux/pci.h> 17 + #include <linux/platform_device.h> 16 18 17 19 #include <media/media-devnode.h> 18 20 #include <media/media-entity.h> 19 21 20 22 struct ida; 21 - struct device; 22 23 struct media_device; 23 24 24 25 /** ··· 182 181 atomic_t request_id; 183 182 }; 184 183 185 - /* We don't need to include pci.h or usb.h here */ 186 - struct pci_dev; 184 + /* We don't need to include usb.h here */ 187 185 struct usb_device; 188 186 189 187 #ifdef CONFIG_MEDIA_CONTROLLER ··· 219 219 * So drivers need to first initialize the media device, register any entity 220 220 * within the media device, create pad to pad links and then finally register 221 221 * the media device by calling media_device_register() as a final step. 222 + * 223 + * The caller is responsible for initializing the media device before 224 + * registration. The following fields must be set: 225 + * 226 + * - dev must point to the parent device 227 + * - model must be filled with the device model name 228 + * 229 + * The bus_info field is set by media_device_init() for PCI and platform devices 230 + * if the field begins with '\0'. 222 231 */ 223 232 void media_device_init(struct media_device *mdev); 224 233 ··· 252 243 * The caller is responsible for initializing the &media_device structure 253 244 * before registration. The following fields of &media_device must be set: 254 245 * 255 - * - &media_entity.dev must point to the parent device (usually a &pci_dev, 256 - * &usb_interface or &platform_device instance). 257 - * 258 - * - &media_entity.model must be filled with the device model name as a 246 + * - &media_device.model must be filled with the device model name as a 259 247 * NUL-terminated UTF-8 string. The device/model revision must not be 260 248 * stored in this field. 261 249 * 262 250 * The following fields are optional: 263 251 * 264 - * - &media_entity.serial is a unique serial number stored as a 252 + * - &media_device.serial is a unique serial number stored as a 265 253 * NUL-terminated ASCII string. The field is big enough to store a GUID 266 254 * in text form. If the hardware doesn't provide a unique serial number 267 255 * this field must be left empty. 268 256 * 269 - * - &media_entity.bus_info represents the location of the device in the 257 + * - &media_device.bus_info represents the location of the device in the 270 258 * system as a NUL-terminated ASCII string. For PCI/PCIe devices 271 - * &media_entity.bus_info must be set to "PCI:" (or "PCIe:") followed by 259 + * &media_device.bus_info must be set to "PCI:" (or "PCIe:") followed by 272 260 * the value of pci_name(). For USB devices,the usb_make_path() function 273 261 * must be used. This field is used by applications to distinguish between 274 262 * otherwise identical devices that don't provide a serial number. 275 263 * 276 - * - &media_entity.hw_revision is the hardware device revision in a 264 + * - &media_device.hw_revision is the hardware device revision in a 277 265 * driver-specific format. When possible the revision should be formatted 278 266 * with the KERNEL_VERSION() macro. 279 267 * ··· 501 495 */ 502 496 #define media_device_usb_init(mdev, udev, name) \ 503 497 __media_device_usb_init(mdev, udev, name, KBUILD_MODNAME) 498 + 499 + /** 500 + * media_set_bus_info() - Set bus_info field 501 + * 502 + * @bus_info: Variable where to write the bus info (char array) 503 + * @bus_info_size: Length of the bus_info 504 + * @dev: Related struct device 505 + * 506 + * Sets bus information based on &dev. This is currently done for PCI and 507 + * platform devices. dev is required to be non-NULL for this to happen. 508 + * 509 + * This function is not meant to be called from drivers. 510 + */ 511 + static inline void 512 + media_set_bus_info(char *bus_info, size_t bus_info_size, struct device *dev) 513 + { 514 + if (!dev) 515 + strscpy(bus_info, "no bus info", bus_info_size); 516 + else if (dev_is_platform(dev)) 517 + snprintf(bus_info, bus_info_size, "platform:%s", dev_name(dev)); 518 + else if (dev_is_pci(dev)) 519 + snprintf(bus_info, bus_info_size, "PCI:%s", dev_name(dev)); 520 + } 504 521 505 522 #endif

+20 -1

include/media/media-entity.h

··· 1030 1030 * removed. 1031 1031 */ 1032 1032 void media_devnode_remove(struct media_intf_devnode *devnode); 1033 - struct media_link * 1034 1033 1035 1034 /** 1036 1035 * media_create_intf_link() - creates a link between an entity and an interface ··· 1060 1061 * the interface and media_device_register_entity() should be called for the 1061 1062 * interface that will be part of the link. 1062 1063 */ 1064 + struct media_link * 1063 1065 __must_check media_create_intf_link(struct media_entity *entity, 1064 1066 struct media_interface *intf, 1065 1067 u32 flags); ··· 1120 1120 #define media_entity_call(entity, operation, args...) \ 1121 1121 (((entity)->ops && (entity)->ops->operation) ? \ 1122 1122 (entity)->ops->operation((entity) , ##args) : -ENOIOCTLCMD) 1123 + 1124 + /** 1125 + * media_create_ancillary_link() - create an ancillary link between two 1126 + * instances of &media_entity 1127 + * 1128 + * @primary: pointer to the primary &media_entity 1129 + * @ancillary: pointer to the ancillary &media_entity 1130 + * 1131 + * Create an ancillary link between two entities, indicating that they 1132 + * represent two connected pieces of hardware that form a single logical unit. 1133 + * A typical example is a camera lens controller being linked to the sensor that 1134 + * it is supporting. 1135 + * 1136 + * The function sets both MEDIA_LNK_FL_ENABLED and MEDIA_LNK_FL_IMMUTABLE for 1137 + * the new link. 1138 + */ 1139 + struct media_link * 1140 + media_create_ancillary_link(struct media_entity *primary, 1141 + struct media_entity *ancillary); 1123 1142 1124 1143 #endif

+1

include/media/mipi-csi2.h

··· 31 31 #define MIPI_CSI2_DT_RGB565 0x22 32 32 #define MIPI_CSI2_DT_RGB666 0x23 33 33 #define MIPI_CSI2_DT_RGB888 0x24 34 + #define MIPI_CSI2_DT_RAW28 0x26 34 35 #define MIPI_CSI2_DT_RAW24 0x27 35 36 #define MIPI_CSI2_DT_RAW6 0x28 36 37 #define MIPI_CSI2_DT_RAW7 0x29

+2

include/media/v4l2-fwnode.h

··· 173 173 * @V4L2_FWNODE_BUS_TYPE_CSI2_DPHY: MIPI CSI-2 bus, D-PHY physical layer 174 174 * @V4L2_FWNODE_BUS_TYPE_PARALLEL: Camera Parallel Interface bus 175 175 * @V4L2_FWNODE_BUS_TYPE_BT656: BT.656 video format bus-type 176 + * @V4L2_FWNODE_BUS_TYPE_DPI: Video Parallel Interface bus 176 177 * @NR_OF_V4L2_FWNODE_BUS_TYPE: Number of bus-types 177 178 */ 178 179 enum v4l2_fwnode_bus_type { ··· 184 183 V4L2_FWNODE_BUS_TYPE_CSI2_DPHY, 185 184 V4L2_FWNODE_BUS_TYPE_PARALLEL, 186 185 V4L2_FWNODE_BUS_TYPE_BT656, 186 + V4L2_FWNODE_BUS_TYPE_DPI, 187 187 NR_OF_V4L2_FWNODE_BUS_TYPE 188 188 }; 189 189

+18 -13

include/media/v4l2-h264.h

··· 15 15 /** 16 16 * struct v4l2_h264_reflist_builder - Reference list builder object 17 17 * 18 - * @refs.pic_order_count: reference picture order count 18 + * @refs.top_field_order_cnt: top field order count 19 + * @refs.bottom_field_order_cnt: bottom field order count 19 20 * @refs.frame_num: reference frame number 20 - * @refs.pic_num: reference picture number 21 21 * @refs.longterm: set to true for a long term reference 22 22 * @refs: array of references 23 23 * @cur_pic_order_count: picture order count of the frame being decoded 24 + * @cur_pic_fields: fields present in the frame being decoded 24 25 * @unordered_reflist: unordered list of references. Will be used to generate 25 26 * ordered P/B0/B1 lists 26 27 * @num_valid: number of valid references in the refs array ··· 32 31 */ 33 32 struct v4l2_h264_reflist_builder { 34 33 struct { 35 - s32 pic_order_count; 34 + s32 top_field_order_cnt; 35 + s32 bottom_field_order_cnt; 36 36 int frame_num; 37 - u32 pic_num; 38 37 u16 longterm : 1; 39 38 } refs[V4L2_H264_NUM_DPB_ENTRIES]; 39 + 40 40 s32 cur_pic_order_count; 41 - u8 unordered_reflist[V4L2_H264_NUM_DPB_ENTRIES]; 41 + u8 cur_pic_fields; 42 + 43 + struct v4l2_h264_reference unordered_reflist[V4L2_H264_REF_LIST_LEN]; 42 44 u8 num_valid; 43 45 }; 44 46 ··· 55 51 * v4l2_h264_build_b_ref_lists() - Build the B0/B1 reference lists 56 52 * 57 53 * @builder: reference list builder context 58 - * @b0_reflist: 16-bytes array used to store the B0 reference list. Each entry 59 - * is an index in the DPB 60 - * @b1_reflist: 16-bytes array used to store the B1 reference list. Each entry 61 - * is an index in the DPB 54 + * @b0_reflist: 32 sized array used to store the B0 reference list. Each entry 55 + * is a v4l2_h264_reference structure 56 + * @b1_reflist: 32 sized array used to store the B1 reference list. Each entry 57 + * is a v4l2_h264_reference structure 62 58 * 63 59 * This functions builds the B0/B1 reference lists. This procedure is described 64 60 * in section '8.2.4 Decoding process for reference picture lists construction' ··· 67 63 */ 68 64 void 69 65 v4l2_h264_build_b_ref_lists(const struct v4l2_h264_reflist_builder *builder, 70 - u8 *b0_reflist, u8 *b1_reflist); 66 + struct v4l2_h264_reference *b0_reflist, 67 + struct v4l2_h264_reference *b1_reflist); 71 68 72 69 /** 73 70 * v4l2_h264_build_p_ref_list() - Build the P reference list 74 71 * 75 72 * @builder: reference list builder context 76 - * @reflist: 16-bytes array used to store the P reference list. Each entry 77 - * is an index in the DPB 73 + * @reflist: 32 sized array used to store the P reference list. Each entry 74 + * is a v4l2_h264_reference structure 78 75 * 79 76 * This functions builds the P reference lists. This procedure is describe in 80 77 * section '8.2.4 Decoding process for reference picture lists construction' ··· 84 79 */ 85 80 void 86 81 v4l2_h264_build_p_ref_list(const struct v4l2_h264_reflist_builder *builder, 87 - u8 *reflist); 82 + struct v4l2_h264_reference *reflist); 88 83 89 84 #endif /* _MEDIA_V4L2_H264_H */

+2

include/media/v4l2-mediabus.h

··· 129 129 * @V4L2_MBUS_CCP2: CCP2 (Compact Camera Port 2) 130 130 * @V4L2_MBUS_CSI2_DPHY: MIPI CSI-2 serial interface, with D-PHY 131 131 * @V4L2_MBUS_CSI2_CPHY: MIPI CSI-2 serial interface, with C-PHY 132 + * @V4L2_MBUS_DPI: MIPI VIDEO DPI interface 132 133 * @V4L2_MBUS_INVALID: invalid bus type (keep as last) 133 134 */ 134 135 enum v4l2_mbus_type { ··· 140 139 V4L2_MBUS_CCP2, 141 140 V4L2_MBUS_CSI2_DPHY, 142 141 V4L2_MBUS_CSI2_CPHY, 142 + V4L2_MBUS_DPI, 143 143 V4L2_MBUS_INVALID, 144 144 }; 145 145

+266 -13

include/media/v4l2-subdev.h

··· 313 313 }; 314 314 315 315 /** 316 + * struct v4l2_mbus_frame_desc_entry_csi2 317 + * 318 + * @vc: CSI-2 virtual channel 319 + * @dt: CSI-2 data type ID 320 + */ 321 + struct v4l2_mbus_frame_desc_entry_csi2 { 322 + u8 vc; 323 + u8 dt; 324 + }; 325 + 326 + /** 316 327 * enum v4l2_mbus_frame_desc_flags - media bus frame description flags 317 328 * 318 329 * @V4L2_MBUS_FRAME_DESC_FL_LEN_MAX: ··· 346 335 * %FRAME_DESC_FL_BLOB is not set. 347 336 * @length: number of octets per frame, valid if @flags 348 337 * %V4L2_MBUS_FRAME_DESC_FL_LEN_MAX is set. 338 + * @bus: Bus-specific frame descriptor parameters 339 + * @bus.csi2: CSI-2-specific bus configuration 349 340 */ 350 341 struct v4l2_mbus_frame_desc_entry { 351 342 enum v4l2_mbus_frame_desc_flags flags; 352 343 u32 pixelcode; 353 344 u32 length; 345 + union { 346 + struct v4l2_mbus_frame_desc_entry_csi2 csi2; 347 + } bus; 354 348 }; 355 349 356 350 #define V4L2_FRAME_DESC_ENTRY_MAX 4 357 351 358 352 /** 353 + * enum v4l2_mbus_frame_desc_type - media bus frame description type 354 + * 355 + * @V4L2_MBUS_FRAME_DESC_TYPE_UNDEFINED: 356 + * Undefined frame desc type. Drivers should not use this, it is 357 + * for backwards compatibility. 358 + * @V4L2_MBUS_FRAME_DESC_TYPE_PARALLEL: 359 + * Parallel media bus. 360 + * @V4L2_MBUS_FRAME_DESC_TYPE_CSI2: 361 + * CSI-2 media bus. Frame desc parameters must be set in 362 + * &struct v4l2_mbus_frame_desc_entry->csi2. 363 + */ 364 + enum v4l2_mbus_frame_desc_type { 365 + V4L2_MBUS_FRAME_DESC_TYPE_UNDEFINED = 0, 366 + V4L2_MBUS_FRAME_DESC_TYPE_PARALLEL, 367 + V4L2_MBUS_FRAME_DESC_TYPE_CSI2, 368 + }; 369 + 370 + /** 359 371 * struct v4l2_mbus_frame_desc - media bus data frame description 372 + * @type: type of the bus (enum v4l2_mbus_frame_desc_type) 360 373 * @entry: frame descriptors array 361 374 * @num_entries: number of entries in @entry array 362 375 */ 363 376 struct v4l2_mbus_frame_desc { 377 + enum v4l2_mbus_frame_desc_type type; 364 378 struct v4l2_mbus_frame_desc_entry entry[V4L2_FRAME_DESC_ENTRY_MAX]; 365 379 unsigned short num_entries; 366 380 }; ··· 681 645 * This structure only needs to be passed to the pad op if the 'which' field 682 646 * of the main argument is set to %V4L2_SUBDEV_FORMAT_TRY. For 683 647 * %V4L2_SUBDEV_FORMAT_ACTIVE it is safe to pass %NULL. 648 + * 649 + * Note: This struct is also used in active state, and the 'try' prefix is 650 + * historical and to be removed. 684 651 */ 685 652 struct v4l2_subdev_pad_config { 686 653 struct v4l2_mbus_framefmt try_fmt; ··· 694 655 /** 695 656 * struct v4l2_subdev_state - Used for storing subdev state information. 696 657 * 658 + * @_lock: default for 'lock' 659 + * @lock: mutex for the state. May be replaced by the user. 697 660 * @pads: &struct v4l2_subdev_pad_config array 698 661 * 699 662 * This structure only needs to be passed to the pad op if the 'which' field ··· 703 662 * %V4L2_SUBDEV_FORMAT_ACTIVE it is safe to pass %NULL. 704 663 */ 705 664 struct v4l2_subdev_state { 665 + /* lock for the struct v4l2_subdev_state fields */ 666 + struct mutex _lock; 667 + struct mutex *lock; 706 668 struct v4l2_subdev_pad_config *pads; 707 669 }; 708 670 ··· 929 885 * @subdev_notifier: A sub-device notifier implicitly registered for the sub- 930 886 * device using v4l2_async_register_subdev_sensor(). 931 887 * @pdata: common part of subdevice platform data 888 + * @state_lock: A pointer to a lock used for all the subdev's states, set by the 889 + * driver. This is optional. If NULL, each state instance will get 890 + * a lock of its own. 891 + * @active_state: Active state for the subdev (NULL for subdevs tracking the 892 + * state internally). Initialized by calling 893 + * v4l2_subdev_init_finalize(). 932 894 * 933 895 * Each instance of a subdev driver should create this struct, either 934 896 * stand-alone or embedded in a larger struct. ··· 966 916 struct v4l2_async_notifier *notifier; 967 917 struct v4l2_async_notifier *subdev_notifier; 968 918 struct v4l2_subdev_platform_data *pdata; 919 + struct mutex *state_lock; 920 + 921 + /* 922 + * The fields below are private, and should only be accessed via 923 + * appropriate functions. 924 + */ 925 + 926 + /* 927 + * TODO: active_state should most likely be changed from a pointer to an 928 + * embedded field. For the time being it's kept as a pointer to more 929 + * easily catch uses of active_state in the cases where the driver 930 + * doesn't support it. 931 + */ 932 + struct v4l2_subdev_state *active_state; 969 933 }; 970 934 971 935 ··· 1034 970 #if defined(CONFIG_VIDEO_V4L2_SUBDEV_API) 1035 971 1036 972 /** 1037 - * v4l2_subdev_get_try_format - ancillary routine to call 973 + * v4l2_subdev_get_pad_format - ancillary routine to call 1038 974 * &struct v4l2_subdev_pad_config->try_fmt 1039 975 * 1040 976 * @sd: pointer to &struct v4l2_subdev ··· 1042 978 * @pad: index of the pad in the &struct v4l2_subdev_state->pads array 1043 979 */ 1044 980 static inline struct v4l2_mbus_framefmt * 1045 - v4l2_subdev_get_try_format(struct v4l2_subdev *sd, 981 + v4l2_subdev_get_pad_format(struct v4l2_subdev *sd, 1046 982 struct v4l2_subdev_state *state, 1047 983 unsigned int pad) 1048 984 { ··· 1052 988 } 1053 989 1054 990 /** 1055 - * v4l2_subdev_get_try_crop - ancillary routine to call 991 + * v4l2_subdev_get_pad_crop - ancillary routine to call 1056 992 * &struct v4l2_subdev_pad_config->try_crop 1057 993 * 1058 994 * @sd: pointer to &struct v4l2_subdev ··· 1060 996 * @pad: index of the pad in the &struct v4l2_subdev_state->pads array. 1061 997 */ 1062 998 static inline struct v4l2_rect * 1063 - v4l2_subdev_get_try_crop(struct v4l2_subdev *sd, 999 + v4l2_subdev_get_pad_crop(struct v4l2_subdev *sd, 1064 1000 struct v4l2_subdev_state *state, 1065 1001 unsigned int pad) 1066 1002 { ··· 1070 1006 } 1071 1007 1072 1008 /** 1073 - * v4l2_subdev_get_try_compose - ancillary routine to call 1009 + * v4l2_subdev_get_pad_compose - ancillary routine to call 1074 1010 * &struct v4l2_subdev_pad_config->try_compose 1075 1011 * 1076 1012 * @sd: pointer to &struct v4l2_subdev ··· 1078 1014 * @pad: index of the pad in the &struct v4l2_subdev_state->pads array. 1079 1015 */ 1080 1016 static inline struct v4l2_rect * 1081 - v4l2_subdev_get_try_compose(struct v4l2_subdev *sd, 1017 + v4l2_subdev_get_pad_compose(struct v4l2_subdev *sd, 1082 1018 struct v4l2_subdev_state *state, 1083 1019 unsigned int pad) 1084 1020 { ··· 1087 1023 return &state->pads[pad].try_compose; 1088 1024 } 1089 1025 1090 - #endif 1026 + /* 1027 + * Temprary helpers until uses of v4l2_subdev_get_try_* functions have been 1028 + * renamed 1029 + */ 1030 + #define v4l2_subdev_get_try_format(sd, state, pad) \ 1031 + v4l2_subdev_get_pad_format(sd, state, pad) 1032 + 1033 + #define v4l2_subdev_get_try_crop(sd, state, pad) \ 1034 + v4l2_subdev_get_pad_crop(sd, state, pad) 1035 + 1036 + #define v4l2_subdev_get_try_compose(sd, state, pad) \ 1037 + v4l2_subdev_get_pad_compose(sd, state, pad) 1038 + 1039 + #endif /* CONFIG_VIDEO_V4L2_SUBDEV_API */ 1091 1040 1092 1041 extern const struct v4l2_file_operations v4l2_subdev_fops; 1093 1042 ··· 1199 1122 int v4l2_subdev_link_validate(struct media_link *link); 1200 1123 1201 1124 /** 1202 - * v4l2_subdev_alloc_state - allocate v4l2_subdev_state 1125 + * __v4l2_subdev_state_alloc - allocate v4l2_subdev_state 1203 1126 * 1204 1127 * @sd: pointer to &struct v4l2_subdev for which the state is being allocated. 1128 + * @lock_name: name of the state lock 1129 + * @key: lock_class_key for the lock 1205 1130 * 1206 - * Must call v4l2_subdev_free_state() when state is no longer needed. 1131 + * Must call __v4l2_subdev_state_free() when state is no longer needed. 1132 + * 1133 + * Not to be called directly by the drivers. 1207 1134 */ 1208 - struct v4l2_subdev_state *v4l2_subdev_alloc_state(struct v4l2_subdev *sd); 1135 + struct v4l2_subdev_state *__v4l2_subdev_state_alloc(struct v4l2_subdev *sd, 1136 + const char *lock_name, 1137 + struct lock_class_key *key); 1209 1138 1210 1139 /** 1211 - * v4l2_subdev_free_state - free a v4l2_subdev_state 1140 + * __v4l2_subdev_state_free - free a v4l2_subdev_state 1212 1141 * 1213 1142 * @state: v4l2_subdev_state to be freed. 1143 + * 1144 + * Not to be called directly by the drivers. 1214 1145 */ 1215 - void v4l2_subdev_free_state(struct v4l2_subdev_state *state); 1146 + void __v4l2_subdev_state_free(struct v4l2_subdev_state *state); 1147 + 1148 + /** 1149 + * v4l2_subdev_init_finalize() - Finalizes the initialization of the subdevice 1150 + * @sd: The subdev 1151 + * 1152 + * This function finalizes the initialization of the subdev, including 1153 + * allocation of the active state for the subdev. 1154 + * 1155 + * This function must be called by the subdev drivers that use the centralized 1156 + * active state, after the subdev struct has been initialized and 1157 + * media_entity_pads_init() has been called, but before registering the 1158 + * subdev. 1159 + * 1160 + * The user must call v4l2_subdev_cleanup() when the subdev is being removed. 1161 + */ 1162 + #define v4l2_subdev_init_finalize(sd) \ 1163 + ({ \ 1164 + static struct lock_class_key __key; \ 1165 + const char *name = KBUILD_BASENAME \ 1166 + ":" __stringify(__LINE__) ":sd->active_state->lock"; \ 1167 + __v4l2_subdev_init_finalize(sd, name, &__key); \ 1168 + }) 1169 + 1170 + int __v4l2_subdev_init_finalize(struct v4l2_subdev *sd, const char *name, 1171 + struct lock_class_key *key); 1172 + 1173 + /** 1174 + * v4l2_subdev_cleanup() - Releases the resources allocated by the subdevice 1175 + * @sd: The subdevice 1176 + * 1177 + * This function will release the resources allocated in 1178 + * v4l2_subdev_init_finalize. 1179 + */ 1180 + void v4l2_subdev_cleanup(struct v4l2_subdev *sd); 1181 + 1182 + /** 1183 + * v4l2_subdev_lock_state() - Locks the subdev state 1184 + * @state: The subdevice state 1185 + * 1186 + * Locks the given subdev state. 1187 + * 1188 + * The state must be unlocked with v4l2_subdev_unlock_state() after use. 1189 + */ 1190 + static inline void v4l2_subdev_lock_state(struct v4l2_subdev_state *state) 1191 + { 1192 + mutex_lock(state->lock); 1193 + } 1194 + 1195 + /** 1196 + * v4l2_subdev_unlock_state() - Unlocks the subdev state 1197 + * @state: The subdevice state 1198 + * 1199 + * Unlocks the given subdev state. 1200 + */ 1201 + static inline void v4l2_subdev_unlock_state(struct v4l2_subdev_state *state) 1202 + { 1203 + mutex_unlock(state->lock); 1204 + } 1205 + 1206 + /** 1207 + * v4l2_subdev_get_unlocked_active_state() - Checks that the active subdev state 1208 + * is unlocked and returns it 1209 + * @sd: The subdevice 1210 + * 1211 + * Returns the active state for the subdevice, or NULL if the subdev does not 1212 + * support active state. If the state is not NULL, calls 1213 + * lockdep_assert_not_held() to issue a warning if the state is locked. 1214 + * 1215 + * This function is to be used e.g. when getting the active state for the sole 1216 + * purpose of passing it forward, without accessing the state fields. 1217 + */ 1218 + static inline struct v4l2_subdev_state * 1219 + v4l2_subdev_get_unlocked_active_state(struct v4l2_subdev *sd) 1220 + { 1221 + if (sd->active_state) 1222 + lockdep_assert_not_held(sd->active_state->lock); 1223 + return sd->active_state; 1224 + } 1225 + 1226 + /** 1227 + * v4l2_subdev_get_locked_active_state() - Checks that the active subdev state 1228 + * is locked and returns it 1229 + * 1230 + * @sd: The subdevice 1231 + * 1232 + * Returns the active state for the subdevice, or NULL if the subdev does not 1233 + * support active state. If the state is not NULL, calls lockdep_assert_held() 1234 + * to issue a warning if the state is not locked. 1235 + * 1236 + * This function is to be used when the caller knows that the active state is 1237 + * already locked. 1238 + */ 1239 + static inline struct v4l2_subdev_state * 1240 + v4l2_subdev_get_locked_active_state(struct v4l2_subdev *sd) 1241 + { 1242 + if (sd->active_state) 1243 + lockdep_assert_held(sd->active_state->lock); 1244 + return sd->active_state; 1245 + } 1246 + 1247 + /** 1248 + * v4l2_subdev_lock_and_get_active_state() - Locks and returns the active subdev 1249 + * state for the subdevice 1250 + * @sd: The subdevice 1251 + * 1252 + * Returns the locked active state for the subdevice, or NULL if the subdev 1253 + * does not support active state. 1254 + * 1255 + * The state must be unlocked with v4l2_subdev_unlock_state() after use. 1256 + */ 1257 + static inline struct v4l2_subdev_state * 1258 + v4l2_subdev_lock_and_get_active_state(struct v4l2_subdev *sd) 1259 + { 1260 + if (sd->active_state) 1261 + v4l2_subdev_lock_state(sd->active_state); 1262 + return sd->active_state; 1263 + } 1264 + 1265 + #if defined(CONFIG_VIDEO_V4L2_SUBDEV_API) 1266 + 1267 + /** 1268 + * v4l2_subdev_get_fmt() - Fill format based on state 1269 + * @sd: subdevice 1270 + * @state: subdevice state 1271 + * @format: pointer to &struct v4l2_subdev_format 1272 + * 1273 + * Fill @format->format field based on the information in the @format struct. 1274 + * 1275 + * This function can be used by the subdev drivers which support active state to 1276 + * implement v4l2_subdev_pad_ops.get_fmt if the subdev driver does not need to 1277 + * do anything special in their get_fmt op. 1278 + * 1279 + * Returns 0 on success, error value otherwise. 1280 + */ 1281 + int v4l2_subdev_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_state *state, 1282 + struct v4l2_subdev_format *format); 1283 + 1284 + #endif /* CONFIG_VIDEO_V4L2_SUBDEV_API */ 1216 1285 1217 1286 #endif /* CONFIG_MEDIA_CONTROLLER */ 1218 1287 ··· 1404 1181 }) 1405 1182 1406 1183 /** 1184 + * v4l2_subdev_call_state_active - call an operation of a v4l2_subdev which 1185 + * takes state as a parameter, passing the 1186 + * subdev its active state. 1187 + * 1188 + * @sd: pointer to the &struct v4l2_subdev 1189 + * @o: name of the element at &struct v4l2_subdev_ops that contains @f. 1190 + * Each element there groups a set of callbacks functions. 1191 + * @f: callback function to be called. 1192 + * The callback functions are defined in groups, according to 1193 + * each element at &struct v4l2_subdev_ops. 1194 + * @args: arguments for @f. 1195 + * 1196 + * This is similar to v4l2_subdev_call(), except that this version can only be 1197 + * used for ops that take a subdev state as a parameter. The macro will get the 1198 + * active state, lock it before calling the op and unlock it after the call. 1199 + */ 1200 + #define v4l2_subdev_call_state_active(sd, o, f, args...) \ 1201 + ({ \ 1202 + int __result; \ 1203 + struct v4l2_subdev_state *state; \ 1204 + state = v4l2_subdev_get_unlocked_active_state(sd); \ 1205 + if (state) \ 1206 + v4l2_subdev_lock_state(state); \ 1207 + __result = v4l2_subdev_call(sd, o, f, state, ##args); \ 1208 + if (state) \ 1209 + v4l2_subdev_unlock_state(state); \ 1210 + __result; \ 1211 + }) 1212 + 1213 + /** 1407 1214 * v4l2_subdev_has_op - Checks if a subdev defines a certain operation. 1408 1215 * 1409 1216 * @sd: pointer to the &struct v4l2_subdev ··· 1457 1204 void v4l2_subdev_notify_event(struct v4l2_subdev *sd, 1458 1205 const struct v4l2_event *ev); 1459 1206 1460 - #endif 1207 + #endif /* _V4L2_SUBDEV_H */

+21 -2

include/media/videobuf2-v4l2.h

··· 302 302 * The following functions are not part of the vb2 core API, but are simple 303 303 * helper functions that you can use in your struct v4l2_file_operations, 304 304 * struct v4l2_ioctl_ops and struct vb2_ops. They will serialize if vb2_queue->lock 305 - * or video_device->lock is set, and they will set and test vb2_queue->owner 306 - * to check if the calling filehandle is permitted to do the queuing operation. 305 + * or video_device->lock is set, and they will set and test the queue owner 306 + * (vb2_queue->owner) to check if the calling filehandle is permitted to do the 307 + * queuing operation. 307 308 */ 309 + 310 + /** 311 + * vb2_queue_is_busy() - check if the queue is busy 312 + * @q: pointer to &struct vb2_queue with videobuf2 queue. 313 + * @file: file through which the vb2 queue access is performed 314 + * 315 + * The queue is considered busy if it has an owner and the owner is not the 316 + * @file. 317 + * 318 + * Queue ownership is acquired and checked by some of the v4l2_ioctl_ops helpers 319 + * below. Drivers can also use this function directly when they need to 320 + * open-code ioctl handlers, for instance to add additional checks between the 321 + * queue ownership test and the call to the corresponding vb2 operation. 322 + */ 323 + static inline bool vb2_queue_is_busy(struct vb2_queue *q, struct file *file) 324 + { 325 + return q->owner && q->owner != file->private_data; 326 + } 308 327 309 328 /* struct v4l2_ioctl_ops helpers */ 310 329

+20

include/uapi/linux/cec.h

··· 142 142 msg->reply = msg->timeout = 0; 143 143 } 144 144 145 + /** 146 + * cec_msg_recv_is_tx_result - return true if this message contains the 147 + * result of an earlier non-blocking transmit 148 + * @msg: the message structure from CEC_RECEIVE 149 + */ 150 + static inline int cec_msg_recv_is_tx_result(const struct cec_msg *msg) 151 + { 152 + return msg->sequence && msg->tx_status && !msg->rx_status; 153 + } 154 + 155 + /** 156 + * cec_msg_recv_is_rx_result - return true if this message contains the 157 + * reply of an earlier non-blocking transmit 158 + * @msg: the message structure from CEC_RECEIVE 159 + */ 160 + static inline int cec_msg_recv_is_rx_result(const struct cec_msg *msg) 161 + { 162 + return msg->sequence && !msg->tx_status && msg->rx_status; 163 + } 164 + 145 165 /* cec_msg flags field */ 146 166 #define CEC_MSG_FL_REPLY_TO_FOLLOWERS (1 << 0) 147 167 #define CEC_MSG_FL_RAW (1 << 1)

+1 -3

include/uapi/linux/media.h

··· 20 20 #ifndef __LINUX_MEDIA_H 21 21 #define __LINUX_MEDIA_H 22 22 23 - #ifndef __KERNEL__ 24 - #include <stdint.h> 25 - #endif 26 23 #include <linux/ioctl.h> 27 24 #include <linux/types.h> 28 25 ··· 223 226 #define MEDIA_LNK_FL_LINK_TYPE (0xf << 28) 224 227 # define MEDIA_LNK_FL_DATA_LINK (0 << 28) 225 228 # define MEDIA_LNK_FL_INTERFACE_LINK (1 << 28) 229 + # define MEDIA_LNK_FL_ANCILLARY_LINK (2 << 28) 226 230 227 231 struct media_link_desc { 228 232 struct media_pad_desc source;

+5

include/uapi/linux/v4l2-controls.h

··· 449 449 #define V4L2_CID_MPEG_VIDEO_USE_LTR_FRAMES (V4L2_CID_CODEC_BASE+234) 450 450 #define V4L2_CID_MPEG_VIDEO_DEC_CONCEAL_COLOR (V4L2_CID_CODEC_BASE+235) 451 451 #define V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD (V4L2_CID_CODEC_BASE+236) 452 + #define V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE (V4L2_CID_CODEC_BASE+237) 453 + enum v4l2_mpeg_video_intra_refresh_period_type { 454 + V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM = 0, 455 + V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC = 1, 456 + }; 452 457 453 458 /* CIDs for the MPEG-2 Part 2 (H.262) codec */ 454 459 #define V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL (V4L2_CID_CODEC_BASE+270)

+4 -1

include/uapi/linux/videodev2.h

··· 569 569 /* Grey bit-packed formats */ 570 570 #define V4L2_PIX_FMT_Y10BPACK v4l2_fourcc('Y', '1', '0', 'B') /* 10 Greyscale bit-packed */ 571 571 #define V4L2_PIX_FMT_Y10P v4l2_fourcc('Y', '1', '0', 'P') /* 10 Greyscale, MIPI RAW10 packed */ 572 + #define V4L2_PIX_FMT_IPU3_Y10 v4l2_fourcc('i', 'p', '3', 'y') /* IPU3 packed 10-bit greyscale */ 572 573 573 574 /* Palette formats */ 574 575 #define V4L2_PIX_FMT_PAL8 v4l2_fourcc('P', 'A', 'L', '8') /* 8 8-bit palette */ ··· 747 746 #define V4L2_PIX_FMT_INZI v4l2_fourcc('I', 'N', 'Z', 'I') /* Intel Planar Greyscale 10-bit and Depth 16-bit */ 748 747 #define V4L2_PIX_FMT_CNF4 v4l2_fourcc('C', 'N', 'F', '4') /* Intel 4-bit packed depth confidence information */ 749 748 #define V4L2_PIX_FMT_HI240 v4l2_fourcc('H', 'I', '2', '4') /* BTTV 8-bit dithered RGB */ 749 + #define V4L2_PIX_FMT_QC08C v4l2_fourcc('Q', '0', '8', 'C') /* Qualcomm 8-bit compressed */ 750 + #define V4L2_PIX_FMT_QC10C v4l2_fourcc('Q', '1', '0', 'C') /* Qualcomm 10-bit compressed */ 750 751 751 - /* 10bit raw bayer packed, 32 bytes for every 25 pixels, last LSB 6 bits unused */ 752 + /* 10bit raw packed, 32 bytes for every 25 pixels, last LSB 6 bits unused */ 752 753 #define V4L2_PIX_FMT_IPU3_SBGGR10 v4l2_fourcc('i', 'p', '3', 'b') /* IPU3 packed 10-bit BGGR bayer */ 753 754 #define V4L2_PIX_FMT_IPU3_SGBRG10 v4l2_fourcc('i', 'p', '3', 'g') /* IPU3 packed 10-bit GBRG bayer */ 754 755 #define V4L2_PIX_FMT_IPU3_SGRBG10 v4l2_fourcc('i', 'p', '3', 'G') /* IPU3 packed 10-bit GRBG bayer */

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