Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 fixes from Catalin Marinas:
- Set the minimum GCC version to 5.1 for arm64 due to earlier compiler
bugs.
- Make atomic helpers __always_inline to avoid a section mismatch when
compiling with clang.
- Fix the CMA and crashkernel reservations to use ZONE_DMA (remove the
arm64_dma32_phys_limit variable, no longer needed with a dynamic
ZONE_DMA sizing in 5.11).
- Remove redundant IRQ flag tracing that was leaving lockdep
inconsistent with the hardware state.
- Revert perf events based hard lockup detector that was causing
smp_processor_id() to be called in preemptible context.
- Some trivial cleanups - spelling fix, renaming S_FRAME_SIZE to
PT_REGS_SIZE, function prototypes added.
* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64: selftests: Fix spelling of 'Mismatch'
arm64: syscall: include prototype for EL0 SVC functions
compiler.h: Raise minimum version of GCC to 5.1 for arm64
arm64: make atomic helpers __always_inline
arm64: rename S_FRAME_SIZE to PT_REGS_SIZE
Revert "arm64: Enable perf events based hard lockup detector"
arm64: entry: remove redundant IRQ flag tracing
arm64: Remove arm64_dma32_phys_limit and its uses
+56
-107
-2
arch/arm64/Kconfig
-2
arch/arm64/Kconfig
···
174
174
select HAVE_NMI
175
175
select HAVE_PATA_PLATFORM
176
176
select HAVE_PERF_EVENTS
177
-
select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI && HW_PERF_EVENTS
178
-
select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && HAVE_PERF_EVENTS_NMI
179
177
select HAVE_PERF_REGS
180
178
select HAVE_PERF_USER_STACK_DUMP
181
179
select HAVE_REGS_AND_STACK_ACCESS_API
+5
-5
arch/arm64/include/asm/atomic.h
+5
-5
arch/arm64/include/asm/atomic.h
···
17
17
#include <asm/lse.h>
18
18
19
19
#define ATOMIC_OP(op) \
20
-
static inline void arch_##op(int i, atomic_t *v) \
20
+
static __always_inline void arch_##op(int i, atomic_t *v) \
21
21
{ \
22
22
__lse_ll_sc_body(op, i, v); \
23
23
}
···
32
32
#undef ATOMIC_OP
33
33
34
34
#define ATOMIC_FETCH_OP(name, op) \
35
-
static inline int arch_##op##name(int i, atomic_t *v) \
35
+
static __always_inline int arch_##op##name(int i, atomic_t *v) \
36
36
{ \
37
37
return __lse_ll_sc_body(op##name, i, v); \
38
38
}
···
56
56
#undef ATOMIC_FETCH_OPS
57
57
58
58
#define ATOMIC64_OP(op) \
59
-
static inline void arch_##op(long i, atomic64_t *v) \
59
+
static __always_inline void arch_##op(long i, atomic64_t *v) \
60
60
{ \
61
61
__lse_ll_sc_body(op, i, v); \
62
62
}
···
71
71
#undef ATOMIC64_OP
72
72
73
73
#define ATOMIC64_FETCH_OP(name, op) \
74
-
static inline long arch_##op##name(long i, atomic64_t *v) \
74
+
static __always_inline long arch_##op##name(long i, atomic64_t *v) \
75
75
{ \
76
76
return __lse_ll_sc_body(op##name, i, v); \
77
77
}
···
94
94
#undef ATOMIC64_FETCH_OP
95
95
#undef ATOMIC64_FETCH_OPS
96
96
97
-
static inline long arch_atomic64_dec_if_positive(atomic64_t *v)
97
+
static __always_inline long arch_atomic64_dec_if_positive(atomic64_t *v)
98
98
{
99
99
return __lse_ll_sc_body(atomic64_dec_if_positive, v);
100
100
}
+1
-2
arch/arm64/include/asm/processor.h
+1
-2
arch/arm64/include/asm/processor.h
···
94
94
#endif /* CONFIG_ARM64_FORCE_52BIT */
95
95
96
96
extern phys_addr_t arm64_dma_phys_limit;
97
-
extern phys_addr_t arm64_dma32_phys_limit;
98
-
#define ARCH_LOW_ADDRESS_LIMIT ((arm64_dma_phys_limit ? : arm64_dma32_phys_limit) - 1)
97
+
#define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1)
99
98
100
99
struct debug_info {
101
100
#ifdef CONFIG_HAVE_HW_BREAKPOINT
+1
-1
arch/arm64/kernel/asm-offsets.c
+1
-1
arch/arm64/kernel/asm-offsets.c
···
75
75
DEFINE(S_SDEI_TTBR1, offsetof(struct pt_regs, sdei_ttbr1));
76
76
DEFINE(S_PMR_SAVE, offsetof(struct pt_regs, pmr_save));
77
77
DEFINE(S_STACKFRAME, offsetof(struct pt_regs, stackframe));
78
-
DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs));
78
+
DEFINE(PT_REGS_SIZE, sizeof(struct pt_regs));
79
79
BLANK();
80
80
#ifdef CONFIG_COMPAT
81
81
DEFINE(COMPAT_SIGFRAME_REGS_OFFSET, offsetof(struct compat_sigframe, uc.uc_mcontext.arm_r0));
+6
-6
arch/arm64/kernel/entry-ftrace.S
+6
-6
arch/arm64/kernel/entry-ftrace.S
···
35
35
*/
36
36
.macro ftrace_regs_entry, allregs=0
37
37
/* Make room for pt_regs, plus a callee frame */
38
-
sub sp, sp, #(S_FRAME_SIZE + 16)
38
+
sub sp, sp, #(PT_REGS_SIZE + 16)
39
39
40
40
/* Save function arguments (and x9 for simplicity) */
41
41
stp x0, x1, [sp, #S_X0]
···
61
61
.endif
62
62
63
63
/* Save the callsite's SP and LR */
64
-
add x10, sp, #(S_FRAME_SIZE + 16)
64
+
add x10, sp, #(PT_REGS_SIZE + 16)
65
65
stp x9, x10, [sp, #S_LR]
66
66
67
67
/* Save the PC after the ftrace callsite */
68
68
str x30, [sp, #S_PC]
69
69
70
70
/* Create a frame record for the callsite above pt_regs */
71
-
stp x29, x9, [sp, #S_FRAME_SIZE]
72
-
add x29, sp, #S_FRAME_SIZE
71
+
stp x29, x9, [sp, #PT_REGS_SIZE]
72
+
add x29, sp, #PT_REGS_SIZE
73
73
74
74
/* Create our frame record within pt_regs. */
75
75
stp x29, x30, [sp, #S_STACKFRAME]
···
120
120
ldr x9, [sp, #S_PC]
121
121
122
122
/* Restore the callsite's SP */
123
-
add sp, sp, #S_FRAME_SIZE + 16
123
+
add sp, sp, #PT_REGS_SIZE + 16
124
124
125
125
ret x9
126
126
SYM_CODE_END(ftrace_common)
···
130
130
ldr x0, [sp, #S_PC]
131
131
sub x0, x0, #AARCH64_INSN_SIZE // ip (callsite's BL insn)
132
132
add x1, sp, #S_LR // parent_ip (callsite's LR)
133
-
ldr x2, [sp, #S_FRAME_SIZE] // parent fp (callsite's FP)
133
+
ldr x2, [sp, #PT_REGS_SIZE] // parent fp (callsite's FP)
134
134
bl prepare_ftrace_return
135
135
b ftrace_common_return
136
136
SYM_CODE_END(ftrace_graph_caller)
+7
-7
arch/arm64/kernel/entry.S
+7
-7
arch/arm64/kernel/entry.S
···
75
75
.endif
76
76
#endif
77
77
78
-
sub sp, sp, #S_FRAME_SIZE
78
+
sub sp, sp, #PT_REGS_SIZE
79
79
#ifdef CONFIG_VMAP_STACK
80
80
/*
81
81
* Test whether the SP has overflowed, without corrupting a GPR.
···
96
96
* userspace, and can clobber EL0 registers to free up GPRs.
97
97
*/
98
98
99
-
/* Stash the original SP (minus S_FRAME_SIZE) in tpidr_el0. */
99
+
/* Stash the original SP (minus PT_REGS_SIZE) in tpidr_el0. */
100
100
msr tpidr_el0, x0
101
101
102
102
/* Recover the original x0 value and stash it in tpidrro_el0 */
···
253
253
254
254
scs_load tsk, x20
255
255
.else
256
-
add x21, sp, #S_FRAME_SIZE
256
+
add x21, sp, #PT_REGS_SIZE
257
257
get_current_task tsk
258
258
.endif /* \el == 0 */
259
259
mrs x22, elr_el1
···
377
377
ldp x26, x27, [sp, #16 * 13]
378
378
ldp x28, x29, [sp, #16 * 14]
379
379
ldr lr, [sp, #S_LR]
380
-
add sp, sp, #S_FRAME_SIZE // restore sp
380
+
add sp, sp, #PT_REGS_SIZE // restore sp
381
381
382
382
.if \el == 0
383
383
alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0
···
580
580
581
581
/*
582
582
* Store the original GPRs to the new stack. The orginal SP (minus
583
-
* S_FRAME_SIZE) was stashed in tpidr_el0 by kernel_ventry.
583
+
* PT_REGS_SIZE) was stashed in tpidr_el0 by kernel_ventry.
584
584
*/
585
-
sub sp, sp, #S_FRAME_SIZE
585
+
sub sp, sp, #PT_REGS_SIZE
586
586
kernel_entry 1
587
587
mrs x0, tpidr_el0
588
-
add x0, x0, #S_FRAME_SIZE
588
+
add x0, x0, #PT_REGS_SIZE
589
589
str x0, [sp, #S_SP]
590
590
591
591
/* Stash the regs for handle_bad_stack */
+2
-39
arch/arm64/kernel/perf_event.c
+2
-39
arch/arm64/kernel/perf_event.c
···
23
23
#include <linux/platform_device.h>
24
24
#include <linux/sched_clock.h>
25
25
#include <linux/smp.h>
26
-
#include <linux/nmi.h>
27
-
#include <linux/cpufreq.h>
28
26
29
27
/* ARMv8 Cortex-A53 specific event types. */
30
28
#define ARMV8_A53_PERFCTR_PREF_LINEFILL 0xC2
···
1248
1250
1249
1251
static int __init armv8_pmu_driver_init(void)
1250
1252
{
1251
-
int ret;
1252
-
1253
1253
if (acpi_disabled)
1254
-
ret = platform_driver_register(&armv8_pmu_driver);
1254
+
return platform_driver_register(&armv8_pmu_driver);
1255
1255
else
1256
-
ret = arm_pmu_acpi_probe(armv8_pmuv3_init);
1257
-
1258
-
/*
1259
-
* Try to re-initialize lockup detector after PMU init in
1260
-
* case PMU events are triggered via NMIs.
1261
-
*/
1262
-
if (ret == 0 && arm_pmu_irq_is_nmi())
1263
-
lockup_detector_init();
1264
-
1265
-
return ret;
1256
+
return arm_pmu_acpi_probe(armv8_pmuv3_init);
1266
1257
}
1267
1258
device_initcall(armv8_pmu_driver_init)
1268
1259
···
1309
1322
userpg->cap_user_time_zero = 1;
1310
1323
userpg->cap_user_time_short = 1;
1311
1324
}
1312
-
1313
-
#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
1314
-
/*
1315
-
* Safe maximum CPU frequency in case a particular platform doesn't implement
1316
-
* cpufreq driver. Although, architecture doesn't put any restrictions on
1317
-
* maximum frequency but 5 GHz seems to be safe maximum given the available
1318
-
* Arm CPUs in the market which are clocked much less than 5 GHz. On the other
1319
-
* hand, we can't make it much higher as it would lead to a large hard-lockup
1320
-
* detection timeout on parts which are running slower (eg. 1GHz on
1321
-
* Developerbox) and doesn't possess a cpufreq driver.
1322
-
*/
1323
-
#define SAFE_MAX_CPU_FREQ 5000000000UL // 5 GHz
1324
-
u64 hw_nmi_get_sample_period(int watchdog_thresh)
1325
-
{
1326
-
unsigned int cpu = smp_processor_id();
1327
-
unsigned long max_cpu_freq;
1328
-
1329
-
max_cpu_freq = cpufreq_get_hw_max_freq(cpu) * 1000UL;
1330
-
if (!max_cpu_freq)
1331
-
max_cpu_freq = SAFE_MAX_CPU_FREQ;
1332
-
1333
-
return (u64)max_cpu_freq * watchdog_thresh;
1334
-
}
1335
-
#endif
+3
-3
arch/arm64/kernel/probes/kprobes_trampoline.S
+3
-3
arch/arm64/kernel/probes/kprobes_trampoline.S
···
25
25
stp x24, x25, [sp, #S_X24]
26
26
stp x26, x27, [sp, #S_X26]
27
27
stp x28, x29, [sp, #S_X28]
28
-
add x0, sp, #S_FRAME_SIZE
28
+
add x0, sp, #PT_REGS_SIZE
29
29
stp lr, x0, [sp, #S_LR]
30
30
/*
31
31
* Construct a useful saved PSTATE
···
62
62
.endm
63
63
64
64
SYM_CODE_START(kretprobe_trampoline)
65
-
sub sp, sp, #S_FRAME_SIZE
65
+
sub sp, sp, #PT_REGS_SIZE
66
66
67
67
save_all_base_regs
68
68
···
76
76
77
77
restore_all_base_regs
78
78
79
-
add sp, sp, #S_FRAME_SIZE
79
+
add sp, sp, #PT_REGS_SIZE
80
80
ret
81
81
82
82
SYM_CODE_END(kretprobe_trampoline)
-7
arch/arm64/kernel/signal.c
-7
arch/arm64/kernel/signal.c
···
914
914
asmlinkage void do_notify_resume(struct pt_regs *regs,
915
915
unsigned long thread_flags)
916
916
{
917
-
/*
918
-
* The assembly code enters us with IRQs off, but it hasn't
919
-
* informed the tracing code of that for efficiency reasons.
920
-
* Update the trace code with the current status.
921
-
*/
922
-
trace_hardirqs_off();
923
-
924
917
do {
925
918
if (thread_flags & _TIF_NEED_RESCHED) {
926
919
/* Unmask Debug and SError for the next task */
+2
-8
arch/arm64/kernel/syscall.c
+2
-8
arch/arm64/kernel/syscall.c
···
9
9
10
10
#include <asm/daifflags.h>
11
11
#include <asm/debug-monitors.h>
12
+
#include <asm/exception.h>
12
13
#include <asm/fpsimd.h>
13
14
#include <asm/syscall.h>
14
15
#include <asm/thread_info.h>
···
166
165
if (!has_syscall_work(flags) && !IS_ENABLED(CONFIG_DEBUG_RSEQ)) {
167
166
local_daif_mask();
168
167
flags = current_thread_info()->flags;
169
-
if (!has_syscall_work(flags) && !(flags & _TIF_SINGLESTEP)) {
170
-
/*
171
-
* We're off to userspace, where interrupts are
172
-
* always enabled after we restore the flags from
173
-
* the SPSR.
174
-
*/
175
-
trace_hardirqs_on();
168
+
if (!has_syscall_work(flags) && !(flags & _TIF_SINGLESTEP))
176
169
return;
177
-
}
178
170
local_daif_restore(DAIF_PROCCTX);
179
171
}
180
172
+18
-15
arch/arm64/mm/init.c
+18
-15
arch/arm64/mm/init.c
···
53
53
EXPORT_SYMBOL(memstart_addr);
54
54
55
55
/*
56
-
* We create both ZONE_DMA and ZONE_DMA32. ZONE_DMA covers the first 1G of
57
-
* memory as some devices, namely the Raspberry Pi 4, have peripherals with
58
-
* this limited view of the memory. ZONE_DMA32 will cover the rest of the 32
59
-
* bit addressable memory area.
56
+
* If the corresponding config options are enabled, we create both ZONE_DMA
57
+
* and ZONE_DMA32. By default ZONE_DMA covers the 32-bit addressable memory
58
+
* unless restricted on specific platforms (e.g. 30-bit on Raspberry Pi 4).
59
+
* In such case, ZONE_DMA32 covers the rest of the 32-bit addressable memory,
60
+
* otherwise it is empty.
60
61
*/
61
62
phys_addr_t arm64_dma_phys_limit __ro_after_init;
62
-
phys_addr_t arm64_dma32_phys_limit __ro_after_init;
63
63
64
64
#ifdef CONFIG_KEXEC_CORE
65
65
/*
···
84
84
85
85
if (crash_base == 0) {
86
86
/* Current arm64 boot protocol requires 2MB alignment */
87
-
crash_base = memblock_find_in_range(0, arm64_dma32_phys_limit,
87
+
crash_base = memblock_find_in_range(0, arm64_dma_phys_limit,
88
88
crash_size, SZ_2M);
89
89
if (crash_base == 0) {
90
90
pr_warn("cannot allocate crashkernel (size:0x%llx)\n",
···
196
196
unsigned long max_zone_pfns[MAX_NR_ZONES] = {0};
197
197
unsigned int __maybe_unused acpi_zone_dma_bits;
198
198
unsigned int __maybe_unused dt_zone_dma_bits;
199
+
phys_addr_t __maybe_unused dma32_phys_limit = max_zone_phys(32);
199
200
200
201
#ifdef CONFIG_ZONE_DMA
201
202
acpi_zone_dma_bits = fls64(acpi_iort_dma_get_max_cpu_address());
···
206
205
max_zone_pfns[ZONE_DMA] = PFN_DOWN(arm64_dma_phys_limit);
207
206
#endif
208
207
#ifdef CONFIG_ZONE_DMA32
209
-
max_zone_pfns[ZONE_DMA32] = PFN_DOWN(arm64_dma32_phys_limit);
208
+
max_zone_pfns[ZONE_DMA32] = PFN_DOWN(dma32_phys_limit);
209
+
if (!arm64_dma_phys_limit)
210
+
arm64_dma_phys_limit = dma32_phys_limit;
210
211
#endif
212
+
if (!arm64_dma_phys_limit)
213
+
arm64_dma_phys_limit = PHYS_MASK + 1;
211
214
max_zone_pfns[ZONE_NORMAL] = max;
212
215
213
216
free_area_init(max_zone_pfns);
···
399
394
400
395
early_init_fdt_scan_reserved_mem();
401
396
402
-
if (IS_ENABLED(CONFIG_ZONE_DMA32))
403
-
arm64_dma32_phys_limit = max_zone_phys(32);
404
-
else
405
-
arm64_dma32_phys_limit = PHYS_MASK + 1;
406
-
407
397
reserve_elfcorehdr();
408
398
409
399
high_memory = __va(memblock_end_of_DRAM() - 1) + 1;
410
-
411
-
dma_contiguous_reserve(arm64_dma32_phys_limit);
412
400
}
413
401
414
402
void __init bootmem_init(void)
···
437
439
zone_sizes_init(min, max);
438
440
439
441
/*
442
+
* Reserve the CMA area after arm64_dma_phys_limit was initialised.
443
+
*/
444
+
dma_contiguous_reserve(arm64_dma_phys_limit);
445
+
446
+
/*
440
447
* request_standard_resources() depends on crashkernel's memory being
441
448
* reserved, so do it here.
442
449
*/
···
458
455
void __init mem_init(void)
459
456
{
460
457
if (swiotlb_force == SWIOTLB_FORCE ||
461
-
max_pfn > PFN_DOWN(arm64_dma_phys_limit ? : arm64_dma32_phys_limit))
458
+
max_pfn > PFN_DOWN(arm64_dma_phys_limit))
462
459
swiotlb_init(1);
463
460
else
464
461
swiotlb_force = SWIOTLB_NO_FORCE;
-5
drivers/perf/arm_pmu.c
-5
drivers/perf/arm_pmu.c
···
726
726
return per_cpu(hw_events->irq, cpu);
727
727
}
728
728
729
-
bool arm_pmu_irq_is_nmi(void)
730
-
{
731
-
return has_nmi;
732
-
}
733
-
734
729
/*
735
730
* PMU hardware loses all context when a CPU goes offline.
736
731
* When a CPU is hotplugged back in, since some hardware registers are
+3
-3
include/asm-generic/bitops/atomic.h
+3
-3
include/asm-generic/bitops/atomic.h
···
11
11
* See Documentation/atomic_bitops.txt for details.
12
12
*/
13
13
14
-
static inline void set_bit(unsigned int nr, volatile unsigned long *p)
14
+
static __always_inline void set_bit(unsigned int nr, volatile unsigned long *p)
15
15
{
16
16
p += BIT_WORD(nr);
17
17
atomic_long_or(BIT_MASK(nr), (atomic_long_t *)p);
18
18
}
19
19
20
-
static inline void clear_bit(unsigned int nr, volatile unsigned long *p)
20
+
static __always_inline void clear_bit(unsigned int nr, volatile unsigned long *p)
21
21
{
22
22
p += BIT_WORD(nr);
23
23
atomic_long_andnot(BIT_MASK(nr), (atomic_long_t *)p);
24
24
}
25
25
26
-
static inline void change_bit(unsigned int nr, volatile unsigned long *p)
26
+
static __always_inline void change_bit(unsigned int nr, volatile unsigned long *p)
27
27
{
28
28
p += BIT_WORD(nr);
29
29
atomic_long_xor(BIT_MASK(nr), (atomic_long_t *)p);
+6
include/linux/compiler-gcc.h
+6
include/linux/compiler-gcc.h
···
13
13
/* https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58145 */
14
14
#if GCC_VERSION < 40900
15
15
# error Sorry, your version of GCC is too old - please use 4.9 or newer.
16
+
#elif defined(CONFIG_ARM64) && GCC_VERSION < 50100
17
+
/*
18
+
* https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63293
19
+
* https://lore.kernel.org/r/20210107111841.GN1551@shell.armlinux.org.uk
20
+
*/
21
+
# error Sorry, your version of GCC is too old - please use 5.1 or newer.
16
22
#endif
17
23
18
24
/*
-2
include/linux/perf/arm_pmu.h
-2
include/linux/perf/arm_pmu.h
···
163
163
static inline int arm_pmu_acpi_probe(armpmu_init_fn init_fn) { return 0; }
164
164
#endif
165
165
166
-
bool arm_pmu_irq_is_nmi(void);
167
-
168
166
/* Internal functions only for core arm_pmu code */
169
167
struct arm_pmu *armpmu_alloc(void);
170
168
struct arm_pmu *armpmu_alloc_atomic(void);
+1
-1
tools/testing/selftests/arm64/fp/fpsimd-test.S
+1
-1
tools/testing/selftests/arm64/fp/fpsimd-test.S