+130 -16

Documentation/devicetree/bindings/display/msm/dp-controller.yaml

reviewed

··· 29 29 - qcom,sdm845-dp 30 30 - qcom,sm8350-dp 31 31 - qcom,sm8650-dp 32 32 + - qcom,x1e80100-dp 33 33 + 34 34 + - items: 35 35 + - enum: 36 36 + - qcom,sm6350-dp 37 37 + - const: qcom,sc7180-dp 38 38 + 39 39 + # deprecated entry for compatibility with old DT 40 40 + - items: 41 41 + - enum: 42 42 + - qcom,sm6350-dp 43 43 + - const: qcom,sm8350-dp 44 44 + deprecated: true 45 45 + 32 46 - items: 33 47 - enum: 34 48 - qcom,sar2130p-dp 35 35 - - qcom,sm6350-dp 49 49 + - qcom,sm7150-dp 36 50 - qcom,sm8150-dp 37 51 - qcom,sm8250-dp 38 52 - qcom,sm8450-dp 39 53 - qcom,sm8550-dp 40 54 - const: qcom,sm8350-dp 55 55 + 41 56 - items: 42 57 - enum: 43 58 - qcom,sm8750-dp ··· 66 51 - description: link register block 67 52 - description: p0 register block 68 53 - description: p1 register block 54 54 + - description: p2 register block 55 55 + - description: p3 register block 56 56 + - description: mst2link register block 57 57 + - description: mst3link register block 69 58 70 59 interrupts: 71 60 maxItems: 1 72 61 73 62 clocks: 63 63 + minItems: 5 74 64 items: 75 65 - description: AHB clock to enable register access 76 66 - description: Display Port AUX clock 77 67 - description: Display Port Link clock 78 68 - description: Link interface clock between DP and PHY 79 79 - - description: Display Port Pixel clock 69 69 + - description: Display Port stream 0 Pixel clock 70 70 + - description: Display Port stream 1 Pixel clock 71 71 + - description: Display Port stream 2 Pixel clock 72 72 + - description: Display Port stream 3 Pixel clock 80 73 81 74 clock-names: 75 75 + minItems: 5 82 76 items: 83 77 - const: core_iface 84 78 - const: core_aux 85 79 - const: ctrl_link 86 80 - const: ctrl_link_iface 87 81 - const: stream_pixel 88 88 - 89 89 - assigned-clocks: 90 90 - items: 91 91 - - description: link clock source 92 92 - - description: pixel clock source 93 93 - 94 94 - assigned-clock-parents: 95 95 - items: 96 96 - - description: phy 0 parent 97 97 - - description: phy 1 parent 82 82 + - const: stream_1_pixel 83 83 + - const: stream_2_pixel 84 84 + - const: stream_3_pixel 98 85 99 86 phys: 100 87 maxItems: 1 ··· 178 161 allOf: 179 162 # AUX BUS does not exist on DP controllers 180 163 # Audio output also is present only on DP output 181 181 - # p1 regions is present on DP, but not on eDP 182 164 - if: 183 165 properties: 184 166 compatible: ··· 190 174 properties: 191 175 "#sound-dai-cells": false 192 176 else: 177 177 + if: 178 178 + properties: 179 179 + compatible: 180 180 + contains: 181 181 + enum: 182 182 + - qcom,sa8775p-dp 183 183 + - qcom,x1e80100-dp 184 184 + then: 185 185 + oneOf: 186 186 + - required: 187 187 + - aux-bus 188 188 + - required: 189 189 + - "#sound-dai-cells" 190 190 + else: 191 191 + properties: 192 192 + aux-bus: false 193 193 + required: 194 194 + - "#sound-dai-cells" 195 195 + 196 196 + - if: 193 197 properties: 194 194 - aux-bus: false 198 198 + compatible: 199 199 + contains: 200 200 + enum: 201 201 + # these platforms support SST only 202 202 + - qcom,sc7180-dp 203 203 + - qcom,sc7280-dp 204 204 + - qcom,sc7280-edp 205 205 + - qcom,sc8180x-edp 206 206 + - qcom,sc8280xp-edp 207 207 + then: 208 208 + properties: 195 209 reg: 196 210 minItems: 5 197 197 - required: 198 198 - - "#sound-dai-cells" 211 211 + maxItems: 5 212 212 + clocks: 213 213 + minItems: 5 214 214 + maxItems: 5 215 215 + clocks-names: 216 216 + minItems: 5 217 217 + maxItems: 5 218 218 + 219 219 + - if: 220 220 + properties: 221 221 + compatible: 222 222 + contains: 223 223 + enum: 224 224 + # these platforms support 2 streams MST on some interfaces, 225 225 + # others are SST only 226 226 + - qcom,sc8280xp-dp 227 227 + - qcom,x1e80100-dp 228 228 + then: 229 229 + properties: 230 230 + reg: 231 231 + minItems: 5 232 232 + maxItems: 5 233 233 + clocks: 234 234 + minItems: 5 235 235 + maxItems: 6 236 236 + clocks-names: 237 237 + minItems: 5 238 238 + maxItems: 6 239 239 + 240 240 + - if: 241 241 + properties: 242 242 + compatible: 243 243 + contains: 244 244 + # 2 streams MST 245 245 + enum: 246 246 + - qcom,sc8180x-dp 247 247 + - qcom,sdm845-dp 248 248 + - qcom,sm8350-dp 249 249 + - qcom,sm8650-dp 250 250 + then: 251 251 + properties: 252 252 + reg: 253 253 + minItems: 5 254 254 + maxItems: 5 255 255 + clocks: 256 256 + minItems: 6 257 257 + maxItems: 6 258 258 + clocks-names: 259 259 + minItems: 6 260 260 + maxItems: 6 261 261 + 262 262 + - if: 263 263 + properties: 264 264 + compatible: 265 265 + contains: 266 266 + enum: 267 267 + # these platforms support 4 stream MST on first DP, 268 268 + # 2 streams MST on the second one. 269 269 + - qcom,sa8775p-dp 270 270 + then: 271 271 + properties: 272 272 + reg: 273 273 + minItems: 9 274 274 + maxItems: 9 275 275 + clocks: 276 276 + minItems: 6 277 277 + maxItems: 8 278 278 + clocks-names: 279 279 + minItems: 6 280 280 + maxItems: 8 199 281 200 282 additionalProperties: false 201 283

+2

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml

reviewed

··· 27 27 - qcom,sar2130p-dsi-ctrl 28 28 - qcom,sc7180-dsi-ctrl 29 29 - qcom,sc7280-dsi-ctrl 30 30 + - qcom,sc8180x-dsi-ctrl 30 31 - qcom,sdm660-dsi-ctrl 31 32 - qcom,sdm670-dsi-ctrl 32 33 - qcom,sdm845-dsi-ctrl ··· 333 332 - qcom,sar2130p-dsi-ctrl 334 333 - qcom,sc7180-dsi-ctrl 335 334 - qcom,sc7280-dsi-ctrl 335 335 + - qcom,sc8180x-dsi-ctrl 336 336 - qcom,sdm845-dsi-ctrl 337 337 - qcom,sm6115-dsi-ctrl 338 338 - qcom,sm6125-dsi-ctrl

+34

Documentation/devicetree/bindings/display/msm/gmu.yaml

reviewed

··· 124 124 contains: 125 125 enum: 126 126 - qcom,adreno-gmu-623.0 127 127 + then: 128 128 + properties: 129 129 + reg: 130 130 + items: 131 131 + - description: Core GMU registers 132 132 + - description: Resource controller registers 133 133 + - description: GMU PDC registers 134 134 + reg-names: 135 135 + items: 136 136 + - const: gmu 137 137 + - const: rscc 138 138 + - const: gmu_pdc 139 139 + clocks: 140 140 + items: 141 141 + - description: GMU clock 142 142 + - description: GPU CX clock 143 143 + - description: GPU AXI clock 144 144 + - description: GPU MEMNOC clock 145 145 + - description: GPU AHB clock 146 146 + - description: GPU HUB CX clock 147 147 + clock-names: 148 148 + items: 149 149 + - const: gmu 150 150 + - const: cxo 151 151 + - const: axi 152 152 + - const: memnoc 153 153 + - const: ahb 154 154 + - const: hub 155 155 + 156 156 + - if: 157 157 + properties: 158 158 + compatible: 159 159 + contains: 160 160 + enum: 127 161 - qcom,adreno-gmu-635.0 128 162 - qcom,adreno-gmu-660.1 129 163 - qcom,adreno-gmu-663.0

+201 -28

Documentation/devicetree/bindings/display/msm/gpu.yaml

reviewed

··· 146 146 properties: 147 147 compatible: 148 148 contains: 149 149 - pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]+$' 150 150 - 149 149 + oneOf: 150 150 + - pattern: '^qcom,adreno-305\.[0-9]+$' 151 151 + - pattern: '^qcom,adreno-330\.[0-9]+$' 151 152 then: 152 153 properties: 153 154 clocks: 154 154 - minItems: 2 155 155 - maxItems: 7 156 156 - 155 155 + minItems: 3 156 156 + maxItems: 3 157 157 clock-names: 158 158 items: 159 159 - anyOf: 160 160 - - const: core 161 161 - description: GPU Core clock 162 162 - - const: iface 163 163 - description: GPU Interface clock 164 164 - - const: mem 165 165 - description: GPU Memory clock 166 166 - - const: mem_iface 167 167 - description: GPU Memory Interface clock 168 168 - - const: alt_mem_iface 169 169 - description: GPU Alternative Memory Interface clock 170 170 - - const: gfx3d 171 171 - description: GPU 3D engine clock 172 172 - - const: rbbmtimer 173 173 - description: GPU RBBM Timer for Adreno 5xx series 174 174 - - const: rbcpr 175 175 - description: GPU RB Core Power Reduction clock 176 176 - minItems: 2 177 177 - maxItems: 7 159 159 + - const: core 160 160 + description: GPU Core clock 161 161 + - const: iface 162 162 + description: GPU Interface clock 163 163 + - const: mem_iface 164 164 + description: GPU Memory Interface clock 178 165 179 179 - required: 180 180 - - clocks 181 181 - - clock-names 166 166 + - if: 167 167 + properties: 168 168 + compatible: 169 169 + contains: 170 170 + pattern: '^qcom,adreno-306\.[0-9]+$' 171 171 + then: 172 172 + properties: 173 173 + clocks: 174 174 + minItems: 5 175 175 + maxItems: 6 176 176 + clock-names: 177 177 + oneOf: 178 178 + - items: 179 179 + - const: core 180 180 + description: GPU Core clock 181 181 + - const: iface 182 182 + description: GPU Interface clock 183 183 + - const: mem_iface 184 184 + description: GPU Memory Interface clock 185 185 + - const: alt_mem_iface 186 186 + description: GPU Alternative Memory Interface clock 187 187 + - const: gfx3d 188 188 + description: GPU 3D engine clock 189 189 + - items: 190 190 + - const: core 191 191 + description: GPU Core clock 192 192 + - const: iface 193 193 + description: GPU Interface clock 194 194 + - const: mem 195 195 + description: GPU Memory clock 196 196 + - const: mem_iface 197 197 + description: GPU Memory Interface clock 198 198 + - const: alt_mem_iface 199 199 + description: GPU Alternative Memory Interface clock 200 200 + - const: gfx3d 201 201 + description: GPU 3D engine clock 202 202 + 203 203 + - if: 204 204 + properties: 205 205 + compatible: 206 206 + contains: 207 207 + pattern: '^qcom,adreno-320\.[0-9]+$' 208 208 + then: 209 209 + properties: 210 210 + clocks: 211 211 + minItems: 4 212 212 + maxItems: 4 213 213 + clock-names: 214 214 + items: 215 215 + - const: core 216 216 + description: GPU Core clock 217 217 + - const: iface 218 218 + description: GPU Interface clock 219 219 + - const: mem 220 220 + description: GPU Memory clock 221 221 + - const: mem_iface 222 222 + description: GPU Memory Interface clock 223 223 + 224 224 + - if: 225 225 + properties: 226 226 + compatible: 227 227 + contains: 228 228 + pattern: '^qcom,adreno-405\.[0-9]+$' 229 229 + then: 230 230 + properties: 231 231 + clocks: 232 232 + minItems: 7 233 233 + maxItems: 7 234 234 + clock-names: 235 235 + items: 236 236 + - const: core 237 237 + description: GPU Core clock 238 238 + - const: iface 239 239 + description: GPU Interface clock 240 240 + - const: mem 241 241 + description: GPU Memory clock 242 242 + - const: mem_iface 243 243 + description: GPU Memory Interface clock 244 244 + - const: alt_mem_iface 245 245 + description: GPU Alternative Memory Interface clock 246 246 + - const: gfx3d 247 247 + description: GPU 3D engine clock 248 248 + - const: rbbmtimer 249 249 + description: GPU RBBM Timer for Adreno 5xx series 250 250 + 251 251 + - if: 252 252 + properties: 253 253 + compatible: 254 254 + contains: 255 255 + pattern: '^qcom,adreno-50[56]\.[0-9]+$' 256 256 + then: 257 257 + properties: 258 258 + clocks: 259 259 + minItems: 6 260 260 + maxItems: 6 261 261 + clock-names: 262 262 + items: 263 263 + - const: core 264 264 + description: GPU Core clock 265 265 + - const: iface 266 266 + description: GPU Interface clock 267 267 + - const: mem_iface 268 268 + description: GPU Memory Interface clock 269 269 + - const: alt_mem_iface 270 270 + description: GPU Alternative Memory Interface clock 271 271 + - const: rbbmtimer 272 272 + description: GPU RBBM Timer for Adreno 5xx series 273 273 + - const: alwayson 274 274 + description: GPU AON clock 275 275 + 276 276 + - if: 277 277 + properties: 278 278 + compatible: 279 279 + contains: 280 280 + oneOf: 281 281 + - pattern: '^qcom,adreno-508\.[0-9]+$' 282 282 + - pattern: '^qcom,adreno-509\.[0-9]+$' 283 283 + - pattern: '^qcom,adreno-512\.[0-9]+$' 284 284 + - pattern: '^qcom,adreno-540\.[0-9]+$' 285 285 + then: 286 286 + properties: 287 287 + clocks: 288 288 + minItems: 6 289 289 + maxItems: 6 290 290 + clock-names: 291 291 + items: 292 292 + - const: iface 293 293 + description: GPU Interface clock 294 294 + - const: rbbmtimer 295 295 + description: GPU RBBM Timer for Adreno 5xx series 296 296 + - const: mem 297 297 + description: GPU Memory clock 298 298 + - const: mem_iface 299 299 + description: GPU Memory Interface clock 300 300 + - const: rbcpr 301 301 + description: GPU RB Core Power Reduction clock 302 302 + - const: core 303 303 + description: GPU Core clock 304 304 + 305 305 + - if: 306 306 + properties: 307 307 + compatible: 308 308 + contains: 309 309 + pattern: '^qcom,adreno-510\.[0-9]+$' 310 310 + then: 311 311 + properties: 312 312 + clocks: 313 313 + minItems: 6 314 314 + maxItems: 6 315 315 + clock-names: 316 316 + items: 317 317 + - const: core 318 318 + description: GPU Core clock 319 319 + - const: iface 320 320 + description: GPU Interface clock 321 321 + - const: mem 322 322 + description: GPU Memory clock 323 323 + - const: mem_iface 324 324 + description: GPU Memory Interface clock 325 325 + - const: rbbmtimer 326 326 + description: GPU RBBM Timer for Adreno 5xx series 327 327 + - const: alwayson 328 328 + description: GPU AON clock 329 329 + 330 330 + - if: 331 331 + properties: 332 332 + compatible: 333 333 + contains: 334 334 + pattern: '^qcom,adreno-530\.[0-9]+$' 335 335 + then: 336 336 + properties: 337 337 + clocks: 338 338 + minItems: 5 339 339 + maxItems: 5 340 340 + clock-names: 341 341 + items: 342 342 + - const: core 343 343 + description: GPU Core clock 344 344 + - const: iface 345 345 + description: GPU Interface clock 346 346 + - const: rbbmtimer 347 347 + description: GPU RBBM Timer for Adreno 5xx series 348 348 + - const: mem 349 349 + description: GPU Memory clock 350 350 + - const: mem_iface 351 351 + description: GPU Memory Interface clock 182 352 183 353 - if: 184 354 properties: ··· 357 187 enum: 358 188 - qcom,adreno-610.0 359 189 - qcom,adreno-619.1 190 190 + - qcom,adreno-07000200 360 191 then: 361 192 properties: 362 193 clocks: ··· 393 222 properties: 394 223 compatible: 395 224 contains: 396 396 - pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]+$' 225 225 + oneOf: 226 226 + - pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]+$' 227 227 + - pattern: '^qcom,adreno-[0-9a-f]{8}$' 397 228 398 229 then: # Starting with A6xx, the clocks are usually defined in the GMU node 399 230 properties:

+21 -5

Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml

reviewed

··· 375 375 <0xaf54200 0x0c0>, 376 376 <0xaf55000 0x770>, 377 377 <0xaf56000 0x09c>, 378 378 - <0xaf57000 0x09c>; 378 378 + <0xaf57000 0x09c>, 379 379 + <0xaf58000 0x09c>, 380 380 + <0xaf59000 0x09c>, 381 381 + <0xaf5a000 0x23c>, 382 382 + <0xaf5b000 0x23c>; 379 383 380 384 interrupt-parent = <&mdss0>; 381 385 interrupts = <12>; ··· 388 384 <&dispcc_dptx0_aux_clk>, 389 385 <&dispcc_dptx0_link_clk>, 390 386 <&dispcc_dptx0_link_intf_clk>, 391 391 - <&dispcc_dptx0_pixel0_clk>; 387 387 + <&dispcc_dptx0_pixel0_clk>, 388 388 + <&dispcc_dptx0_pixel1_clk>, 389 389 + <&dispcc_dptx0_pixel2_clk>, 390 390 + <&dispcc_dptx0_pixel3_clk>; 392 391 clock-names = "core_iface", 393 392 "core_aux", 394 393 "ctrl_link", 395 394 "ctrl_link_iface", 396 396 - "stream_pixel"; 395 395 + "stream_pixel", 396 396 + "stream_1_pixel", 397 397 + "stream_2_pixel", 398 398 + "stream_3_pixel"; 397 399 398 400 assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>, 399 399 - <&dispcc_mdss_dptx0_pixel0_clk_src>; 400 400 - assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>; 401 401 + <&dispcc_mdss_dptx0_pixel0_clk_src>, 402 402 + <&dispcc_mdss_dptx0_pixel1_clk_src>, 403 403 + <&dispcc_mdss_dptx0_pixel2_clk_src>, 404 404 + <&dispcc_mdss_dptx0_pixel3_clk_src>; 405 405 + assigned-clock-parents = <&mdss0_dp0_phy 0>, 406 406 + <&mdss0_dp0_phy 1>, 407 407 + <&mdss0_dp0_phy 1>, 408 408 + <&mdss0_dp0_phy 1>; 401 409 402 410 phys = <&mdss0_dp0_phy>; 403 411 phy-names = "dp";

+7 -3

Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml

reviewed

··· 207 207 <&dispcc_disp_cc_mdss_dptx0_aux_clk>, 208 208 <&dispcc_disp_cc_mdss_dptx0_link_clk>, 209 209 <&dispcc_disp_cc_mdss_dptx0_link_intf_clk>, 210 210 - <&dispcc_disp_cc_mdss_dptx0_pixel0_clk>; 210 210 + <&dispcc_disp_cc_mdss_dptx0_pixel0_clk>, 211 211 + <&dispcc_disp_cc_mdss_dptx0_pixel1_clk>; 211 212 clock-names = "core_iface", 212 213 "core_aux", 213 214 "ctrl_link", 214 215 "ctrl_link_iface", 215 215 - "stream_pixel"; 216 216 + "stream_pixel", 217 217 + "stream_1_pixel"; 216 218 217 219 assigned-clocks = <&dispcc_disp_cc_mdss_dptx0_link_clk_src>, 218 218 - <&dispcc_disp_cc_mdss_dptx0_pixel0_clk_src>; 220 220 + <&dispcc_disp_cc_mdss_dptx0_pixel0_clk_src>, 221 221 + <&dispcc_disp_cc_mdss_dptx0_pixel1_clk_src>; 219 222 assigned-clock-parents = <&usb_dp_qmpphy_QMP_USB43DP_DP_LINK_CLK>, 223 223 + <&usb_dp_qmpphy_QMP_USB43DP_DP_VCO_DIV_CLK>, 220 224 <&usb_dp_qmpphy_QMP_USB43DP_DP_VCO_DIV_CLK>; 221 225 222 226 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;

+2 -1

Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml

reviewed

··· 281 281 reg = <0xaea0000 0x200>, 282 282 <0xaea0200 0x200>, 283 283 <0xaea0400 0xc00>, 284 284 - <0xaea1000 0x400>; 284 284 + <0xaea1000 0x400>, 285 285 + <0xaea1400 0x400>; 285 286 286 287 interrupt-parent = <&mdss>; 287 288 interrupts = <14>;

+103

Documentation/devicetree/bindings/display/msm/qcom,sc8180x-dpu.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/display/msm/qcom,sc8180x-dpu.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Qualcomm SC8180X Display DPU 8 8 + 9 9 + maintainers: 10 10 + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> 11 11 + 12 12 + $ref: /schemas/display/msm/dpu-common.yaml# 13 13 + 14 14 + properties: 15 15 + compatible: 16 16 + const: qcom,sc8180x-dpu 17 17 + 18 18 + reg: 19 19 + items: 20 20 + - description: Address offset and size for mdp register set 21 21 + - description: Address offset and size for vbif register set 22 22 + 23 23 + reg-names: 24 24 + items: 25 25 + - const: mdp 26 26 + - const: vbif 27 27 + 28 28 + clocks: 29 29 + items: 30 30 + - description: Display AHB clock 31 31 + - description: Display HF AXI clock 32 32 + - description: Display core clock 33 33 + - description: Display vsync clock 34 34 + - description: Display rotator clock 35 35 + - description: Display LUT clock 36 36 + 37 37 + clock-names: 38 38 + items: 39 39 + - const: iface 40 40 + - const: bus 41 41 + - const: core 42 42 + - const: vsync 43 43 + - const: rot 44 44 + - const: lut 45 45 + 46 46 + unevaluatedProperties: false 47 47 + 48 48 + examples: 49 49 + - | 50 50 + #include <dt-bindings/clock/qcom,dispcc-sm8250.h> 51 51 + #include <dt-bindings/clock/qcom,gcc-sc8180x.h> 52 52 + #include <dt-bindings/interrupt-controller/arm-gic.h> 53 53 + #include <dt-bindings/interconnect/qcom,sc8180x.h> 54 54 + #include <dt-bindings/power/qcom-rpmpd.h> 55 55 + 56 56 + display-controller@ae01000 { 57 57 + compatible = "qcom,sc8180x-dpu"; 58 58 + reg = <0x0ae01000 0x8f000>, 59 59 + <0x0aeb0000 0x2008>; 60 60 + reg-names = "mdp", "vbif"; 61 61 + 62 62 + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 63 63 + <&gcc GCC_DISP_HF_AXI_CLK>, 64 64 + <&dispcc DISP_CC_MDSS_MDP_CLK>, 65 65 + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 66 66 + <&dispcc DISP_CC_MDSS_ROT_CLK>, 67 67 + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; 68 68 + clock-names = "iface", 69 69 + "bus", 70 70 + "core", 71 71 + "vsync", 72 72 + "rot", 73 73 + "lut"; 74 74 + 75 75 + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 76 76 + assigned-clock-rates = <19200000>; 77 77 + 78 78 + operating-points-v2 = <&mdp_opp_table>; 79 79 + power-domains = <&rpmhpd SC8180X_MMCX>; 80 80 + 81 81 + interrupt-parent = <&mdss>; 82 82 + interrupts = <0>; 83 83 + 84 84 + ports { 85 85 + #address-cells = <1>; 86 86 + #size-cells = <0>; 87 87 + 88 88 + port@0 { 89 89 + reg = <0>; 90 90 + endpoint { 91 91 + remote-endpoint = <&dsi0_in>; 92 92 + }; 93 93 + }; 94 94 + 95 95 + port@1 { 96 96 + reg = <1>; 97 97 + endpoint { 98 98 + remote-endpoint = <&dsi1_in>; 99 99 + }; 100 100 + }; 101 101 + }; 102 102 + }; 103 103 + ...

+359

Documentation/devicetree/bindings/display/msm/qcom,sc8180x-mdss.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/display/msm/qcom,sc8180x-mdss.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Qualcomm SC8180X Display MDSS 8 8 + 9 9 + maintainers: 10 10 + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> 11 11 + 12 12 + description: 13 13 + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates 14 14 + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree 15 15 + bindings of MDSS are mentioned for SC8180X target. 16 16 + 17 17 + $ref: /schemas/display/msm/mdss-common.yaml# 18 18 + 19 19 + properties: 20 20 + compatible: 21 21 + items: 22 22 + - const: qcom,sc8180x-mdss 23 23 + 24 24 + clocks: 25 25 + items: 26 26 + - description: Display AHB clock from gcc 27 27 + - description: Display hf axi clock 28 28 + - description: Display sf axi clock 29 29 + - description: Display core clock 30 30 + 31 31 + clock-names: 32 32 + items: 33 33 + - const: iface 34 34 + - const: bus 35 35 + - const: nrt_bus 36 36 + - const: core 37 37 + 38 38 + iommus: 39 39 + maxItems: 1 40 40 + 41 41 + interconnects: 42 42 + maxItems: 3 43 43 + 44 44 + interconnect-names: 45 45 + maxItems: 3 46 46 + 47 47 + patternProperties: 48 48 + "^display-controller@[0-9a-f]+$": 49 49 + type: object 50 50 + additionalProperties: true 51 51 + 52 52 + properties: 53 53 + compatible: 54 54 + const: qcom,sc8180x-dpu 55 55 + 56 56 + "^displayport-controller@[0-9a-f]+$": 57 57 + type: object 58 58 + additionalProperties: true 59 59 + 60 60 + properties: 61 61 + compatible: 62 62 + enum: 63 63 + - qcom,sc8180x-dp 64 64 + - qcom,sc8180x-edp 65 65 + 66 66 + "^dsi@[0-9a-f]+$": 67 67 + type: object 68 68 + additionalProperties: true 69 69 + 70 70 + properties: 71 71 + compatible: 72 72 + contains: 73 73 + const: qcom,sc8180x-dsi-ctrl 74 74 + 75 75 + "^phy@[0-9a-f]+$": 76 76 + type: object 77 77 + additionalProperties: true 78 78 + 79 79 + properties: 80 80 + compatible: 81 81 + const: qcom,dsi-phy-7nm 82 82 + 83 83 + unevaluatedProperties: false 84 84 + 85 85 + examples: 86 86 + - | 87 87 + #include <dt-bindings/clock/qcom,dispcc-sm8250.h> 88 88 + #include <dt-bindings/clock/qcom,gcc-sc8180x.h> 89 89 + #include <dt-bindings/clock/qcom,rpmh.h> 90 90 + #include <dt-bindings/interrupt-controller/arm-gic.h> 91 91 + #include <dt-bindings/interconnect/qcom,sc8180x.h> 92 92 + #include <dt-bindings/power/qcom-rpmpd.h> 93 93 + 94 94 + display-subsystem@ae00000 { 95 95 + compatible = "qcom,sc8180x-mdss"; 96 96 + reg = <0x0ae00000 0x1000>; 97 97 + reg-names = "mdss"; 98 98 + 99 99 + interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 100 100 + <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>, 101 101 + <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>; 102 102 + interconnect-names = "mdp0-mem", 103 103 + "mdp1-mem", 104 104 + "cpu-cfg"; 105 105 + 106 106 + power-domains = <&dispcc MDSS_GDSC>; 107 107 + 108 108 + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 109 109 + <&gcc GCC_DISP_HF_AXI_CLK>, 110 110 + <&gcc GCC_DISP_SF_AXI_CLK>, 111 111 + <&dispcc DISP_CC_MDSS_MDP_CLK>; 112 112 + clock-names = "iface", "bus", "nrt_bus", "core"; 113 113 + 114 114 + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 115 115 + interrupt-controller; 116 116 + #interrupt-cells = <1>; 117 117 + 118 118 + iommus = <&apps_smmu 0x800 0x420>; 119 119 + 120 120 + #address-cells = <1>; 121 121 + #size-cells = <1>; 122 122 + ranges; 123 123 + 124 124 + display-controller@ae01000 { 125 125 + compatible = "qcom,sc8180x-dpu"; 126 126 + reg = <0x0ae01000 0x8f000>, 127 127 + <0x0aeb0000 0x2008>; 128 128 + reg-names = "mdp", "vbif"; 129 129 + 130 130 + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 131 131 + <&gcc GCC_DISP_HF_AXI_CLK>, 132 132 + <&dispcc DISP_CC_MDSS_MDP_CLK>, 133 133 + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 134 134 + <&dispcc DISP_CC_MDSS_ROT_CLK>, 135 135 + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; 136 136 + clock-names = "iface", 137 137 + "bus", 138 138 + "core", 139 139 + "vsync", 140 140 + "rot", 141 141 + "lut"; 142 142 + 143 143 + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 144 144 + assigned-clock-rates = <19200000>; 145 145 + 146 146 + operating-points-v2 = <&mdp_opp_table>; 147 147 + power-domains = <&rpmhpd SC8180X_MMCX>; 148 148 + 149 149 + interrupt-parent = <&mdss>; 150 150 + interrupts = <0>; 151 151 + 152 152 + ports { 153 153 + #address-cells = <1>; 154 154 + #size-cells = <0>; 155 155 + 156 156 + port@0 { 157 157 + reg = <0>; 158 158 + dpu_intf1_out: endpoint { 159 159 + remote-endpoint = <&dsi0_in>; 160 160 + }; 161 161 + }; 162 162 + 163 163 + port@1 { 164 164 + reg = <1>; 165 165 + dpu_intf2_out: endpoint { 166 166 + remote-endpoint = <&dsi1_in>; 167 167 + }; 168 168 + }; 169 169 + }; 170 170 + 171 171 + mdp_opp_table: opp-table { 172 172 + compatible = "operating-points-v2"; 173 173 + 174 174 + opp-171428571 { 175 175 + opp-hz = /bits/ 64 <171428571>; 176 176 + required-opps = <&rpmhpd_opp_low_svs>; 177 177 + }; 178 178 + 179 179 + opp-300000000 { 180 180 + opp-hz = /bits/ 64 <300000000>; 181 181 + required-opps = <&rpmhpd_opp_svs>; 182 182 + }; 183 183 + 184 184 + opp-345000000 { 185 185 + opp-hz = /bits/ 64 <345000000>; 186 186 + required-opps = <&rpmhpd_opp_svs_l1>; 187 187 + }; 188 188 + 189 189 + opp-460000000 { 190 190 + opp-hz = /bits/ 64 <460000000>; 191 191 + required-opps = <&rpmhpd_opp_nom>; 192 192 + }; 193 193 + }; 194 194 + }; 195 195 + 196 196 + dsi@ae94000 { 197 197 + compatible = "qcom,sc8180x-dsi-ctrl", 198 198 + "qcom,mdss-dsi-ctrl"; 199 199 + reg = <0x0ae94000 0x400>; 200 200 + reg-names = "dsi_ctrl"; 201 201 + 202 202 + interrupt-parent = <&mdss>; 203 203 + interrupts = <4>; 204 204 + 205 205 + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 206 206 + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 207 207 + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 208 208 + <&dispcc DISP_CC_MDSS_ESC0_CLK>, 209 209 + <&dispcc DISP_CC_MDSS_AHB_CLK>, 210 210 + <&gcc GCC_DISP_HF_AXI_CLK>; 211 211 + clock-names = "byte", 212 212 + "byte_intf", 213 213 + "pixel", 214 214 + "core", 215 215 + "iface", 216 216 + "bus"; 217 217 + 218 218 + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 219 219 + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 220 220 + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 221 221 + 222 222 + operating-points-v2 = <&dsi_opp_table>; 223 223 + power-domains = <&rpmhpd SC8180X_MMCX>; 224 224 + 225 225 + phys = <&dsi0_phy>; 226 226 + phy-names = "dsi"; 227 227 + 228 228 + #address-cells = <1>; 229 229 + #size-cells = <0>; 230 230 + 231 231 + ports { 232 232 + #address-cells = <1>; 233 233 + #size-cells = <0>; 234 234 + 235 235 + port@0 { 236 236 + reg = <0>; 237 237 + dsi0_in: endpoint { 238 238 + remote-endpoint = <&dpu_intf1_out>; 239 239 + }; 240 240 + }; 241 241 + 242 242 + port@1 { 243 243 + reg = <1>; 244 244 + dsi0_out: endpoint { 245 245 + }; 246 246 + }; 247 247 + }; 248 248 + 249 249 + dsi_opp_table: opp-table { 250 250 + compatible = "operating-points-v2"; 251 251 + 252 252 + opp-187500000 { 253 253 + opp-hz = /bits/ 64 <187500000>; 254 254 + required-opps = <&rpmhpd_opp_low_svs>; 255 255 + }; 256 256 + 257 257 + opp-300000000 { 258 258 + opp-hz = /bits/ 64 <300000000>; 259 259 + required-opps = <&rpmhpd_opp_svs>; 260 260 + }; 261 261 + 262 262 + opp-358000000 { 263 263 + opp-hz = /bits/ 64 <358000000>; 264 264 + required-opps = <&rpmhpd_opp_svs_l1>; 265 265 + }; 266 266 + }; 267 267 + }; 268 268 + 269 269 + dsi0_phy: phy@ae94400 { 270 270 + compatible = "qcom,dsi-phy-7nm"; 271 271 + reg = <0x0ae94400 0x200>, 272 272 + <0x0ae94600 0x280>, 273 273 + <0x0ae94900 0x260>; 274 274 + reg-names = "dsi_phy", 275 275 + "dsi_phy_lane", 276 276 + "dsi_pll"; 277 277 + 278 278 + #clock-cells = <1>; 279 279 + #phy-cells = <0>; 280 280 + 281 281 + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 282 282 + <&rpmhcc RPMH_CXO_CLK>; 283 283 + clock-names = "iface", "ref"; 284 284 + vdds-supply = <&vreg_dsi_phy>; 285 285 + }; 286 286 + 287 287 + dsi@ae96000 { 288 288 + compatible = "qcom,sc8180x-dsi-ctrl", 289 289 + "qcom,mdss-dsi-ctrl"; 290 290 + reg = <0x0ae96000 0x400>; 291 291 + reg-names = "dsi_ctrl"; 292 292 + 293 293 + interrupt-parent = <&mdss>; 294 294 + interrupts = <5>; 295 295 + 296 296 + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 297 297 + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 298 298 + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 299 299 + <&dispcc DISP_CC_MDSS_ESC1_CLK>, 300 300 + <&dispcc DISP_CC_MDSS_AHB_CLK>, 301 301 + <&gcc GCC_DISP_HF_AXI_CLK>; 302 302 + clock-names = "byte", 303 303 + "byte_intf", 304 304 + "pixel", 305 305 + "core", 306 306 + "iface", 307 307 + "bus"; 308 308 + 309 309 + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 310 310 + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 311 311 + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 312 312 + 313 313 + operating-points-v2 = <&dsi_opp_table>; 314 314 + power-domains = <&rpmhpd SC8180X_MMCX>; 315 315 + 316 316 + phys = <&dsi1_phy>; 317 317 + phy-names = "dsi"; 318 318 + 319 319 + #address-cells = <1>; 320 320 + #size-cells = <0>; 321 321 + 322 322 + ports { 323 323 + #address-cells = <1>; 324 324 + #size-cells = <0>; 325 325 + 326 326 + port@0 { 327 327 + reg = <0>; 328 328 + dsi1_in: endpoint { 329 329 + remote-endpoint = <&dpu_intf2_out>; 330 330 + }; 331 331 + }; 332 332 + 333 333 + port@1 { 334 334 + reg = <1>; 335 335 + dsi1_out: endpoint { 336 336 + }; 337 337 + }; 338 338 + }; 339 339 + }; 340 340 + 341 341 + dsi1_phy: phy@ae96400 { 342 342 + compatible = "qcom,dsi-phy-7nm"; 343 343 + reg = <0x0ae96400 0x200>, 344 344 + <0x0ae96600 0x280>, 345 345 + <0x0ae96900 0x260>; 346 346 + reg-names = "dsi_phy", 347 347 + "dsi_phy_lane", 348 348 + "dsi_pll"; 349 349 + 350 350 + #clock-cells = <1>; 351 351 + #phy-cells = <0>; 352 352 + 353 353 + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 354 354 + <&rpmhcc RPMH_CXO_CLK>; 355 355 + clock-names = "iface", "ref"; 356 356 + vdds-supply = <&vreg_dsi_phy>; 357 357 + }; 358 358 + }; 359 359 + ...

+11 -5

Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml

reviewed

··· 61 61 additionalProperties: true 62 62 properties: 63 63 compatible: 64 64 - const: qcom,sm7150-dp 64 64 + contains: 65 65 + const: qcom,sm7150-dp 65 66 66 67 "^dsi@[0-9a-f]+$": 67 68 type: object ··· 379 378 }; 380 379 381 380 displayport-controller@ae90000 { 382 382 - compatible = "qcom,sm7150-dp"; 381 381 + compatible = "qcom,sm7150-dp", 382 382 + "qcom,sm8350-dp"; 383 383 reg = <0xae90000 0x200>, 384 384 <0xae90200 0x200>, 385 385 <0xae90400 0xc00>, ··· 394 392 <&dispcc_mdss_dp_aux_clk>, 395 393 <&dispcc_mdss_dp_link_clk>, 396 394 <&dispcc_mdss_dp_link_intf_clk>, 397 397 - <&dispcc_mdss_dp_pixel_clk>; 395 395 + <&dispcc_mdss_dp_pixel_clk>, 396 396 + <&dispcc_mdss_dp_pixel1_clk>; 398 397 clock-names = "core_iface", 399 398 "core_aux", 400 399 "ctrl_link", 401 400 "ctrl_link_iface", 402 402 - "stream_pixel"; 401 401 + "stream_pixel", 402 402 + "stream_1_pixel"; 403 403 404 404 assigned-clocks = <&dispcc_mdss_dp_link_clk_src>, 405 405 - <&dispcc_mdss_dp_pixel_clk_src>; 405 405 + <&dispcc_mdss_dp_pixel_clk_src>, 406 406 + <&dispcc_mdss_dp_pixel1_clk_src>; 406 407 assigned-clock-parents = <&dp_phy 0>, 408 408 + <&dp_phy 1>, 407 409 <&dp_phy 1>; 408 410 409 411 operating-points-v2 = <&dp_opp_table>;

+7 -3

Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml

reviewed

··· 401 401 <&disp_cc_mdss_dptx0_aux_clk>, 402 402 <&disp_cc_mdss_dptx0_link_clk>, 403 403 <&disp_cc_mdss_dptx0_link_intf_clk>, 404 404 - <&disp_cc_mdss_dptx0_pixel0_clk>; 404 404 + <&disp_cc_mdss_dptx0_pixel0_clk>, 405 405 + <&disp_cc_mdss_dptx0_pixel1_clk>; 405 406 clock-names = "core_iface", 406 407 "core_aux", 407 408 "ctrl_link", 408 409 "ctrl_link_iface", 409 409 - "stream_pixel"; 410 410 + "stream_pixel", 411 411 + "stream_1_pixel"; 410 412 411 413 assigned-clocks = <&disp_cc_mdss_dptx0_link_clk_src>, 412 412 - <&disp_cc_mdss_dptx0_pixel0_clk_src>; 414 414 + <&disp_cc_mdss_dptx0_pixel0_clk_src>, 415 415 + <&disp_cc_mdss_dptx0_pixel1_clk_src>; 413 416 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 417 417 + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 414 418 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 415 419 416 420 operating-points-v2 = <&dp_opp_table>;

+12 -8

Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml

reviewed

··· 170 170 171 171 displayport-controller@ae90000 { 172 172 compatible = "qcom,x1e80100-dp"; 173 173 - reg = <0 0xae90000 0 0x200>, 174 174 - <0 0xae90200 0 0x200>, 175 175 - <0 0xae90400 0 0x600>, 176 176 - <0 0xae91000 0 0x400>, 177 177 - <0 0xae91400 0 0x400>; 173 173 + reg = <0xae90000 0x200>, 174 174 + <0xae90200 0x200>, 175 175 + <0xae90400 0x600>, 176 176 + <0xae91000 0x400>, 177 177 + <0xae91400 0x400>; 178 178 179 179 interrupt-parent = <&mdss>; 180 180 interrupts = <12>; ··· 183 183 <&dispcc_dptx0_aux_clk>, 184 184 <&dispcc_dptx0_link_clk>, 185 185 <&dispcc_dptx0_link_intf_clk>, 186 186 - <&dispcc_dptx0_pixel0_clk>; 186 186 + <&dispcc_dptx0_pixel0_clk>, 187 187 + <&dispcc_dptx0_pixel1_clk>; 187 188 clock-names = "core_iface", "core_aux", 188 189 "ctrl_link", 189 190 "ctrl_link_iface", 190 190 - "stream_pixel"; 191 191 + "stream_pixel", 192 192 + "stream_1_pixel"; 191 193 192 194 assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>, 193 193 - <&dispcc_mdss_dptx0_pixel0_clk_src>; 195 195 + <&dispcc_mdss_dptx0_pixel0_clk_src>, 196 196 + <&dispcc_mdss_dptx0_pixel1_clk_src>; 194 197 assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 198 198 + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 195 199 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 196 200 197 201 operating-points-v2 = <&mdss_dp0_opp_table>;

+90 -2

drivers/gpu/drm/msm/adreno/a6xx_catalog.c

reviewed

··· 913 913 { /* sentinel */ }, 914 914 }, 915 915 }, 916 916 + .speedbins = ADRENO_SPEEDBINS( 917 917 + { 0, 0 }, 918 918 + { 185, 0 }, 919 919 + { 127, 1 }, 920 920 + ), 916 921 }, { 917 922 .chip_ids = ADRENO_CHIP_IDS( 918 923 0x06030001, ··· 1029 1024 .gmu_cgc_mode = 0x00020200, 1030 1025 .prim_fifo_threshold = 0x00300200, 1031 1026 }, 1027 1027 + .speedbins = ADRENO_SPEEDBINS( 1028 1028 + { 0, 0 }, 1029 1029 + { 169, 0 }, 1030 1030 + { 113, 1 }, 1031 1031 + ), 1032 1032 }, { 1033 1033 .chip_ids = ADRENO_CHIP_IDS(0x06030500), 1034 1034 .family = ADRENO_6XX_GEN4, ··· 1353 1343 1354 1344 DECLARE_ADRENO_REGLIST_LIST(a7xx_pwrup_reglist); 1355 1345 1346 1346 + /* Applicable for X185, A750 */ 1347 1347 + static const u32 a750_ifpc_reglist_regs[] = { 1348 1348 + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(0), 1349 1349 + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(1), 1350 1350 + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(2), 1351 1351 + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(3), 1352 1352 + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(4), 1353 1353 + REG_A6XX_TPL1_NC_MODE_CNTL, 1354 1354 + REG_A6XX_SP_NC_MODE_CNTL, 1355 1355 + REG_A6XX_CP_DBG_ECO_CNTL, 1356 1356 + REG_A6XX_CP_PROTECT_CNTL, 1357 1357 + REG_A6XX_CP_PROTECT(0), 1358 1358 + REG_A6XX_CP_PROTECT(1), 1359 1359 + REG_A6XX_CP_PROTECT(2), 1360 1360 + REG_A6XX_CP_PROTECT(3), 1361 1361 + REG_A6XX_CP_PROTECT(4), 1362 1362 + REG_A6XX_CP_PROTECT(5), 1363 1363 + REG_A6XX_CP_PROTECT(6), 1364 1364 + REG_A6XX_CP_PROTECT(7), 1365 1365 + REG_A6XX_CP_PROTECT(8), 1366 1366 + REG_A6XX_CP_PROTECT(9), 1367 1367 + REG_A6XX_CP_PROTECT(10), 1368 1368 + REG_A6XX_CP_PROTECT(11), 1369 1369 + REG_A6XX_CP_PROTECT(12), 1370 1370 + REG_A6XX_CP_PROTECT(13), 1371 1371 + REG_A6XX_CP_PROTECT(14), 1372 1372 + REG_A6XX_CP_PROTECT(15), 1373 1373 + REG_A6XX_CP_PROTECT(16), 1374 1374 + REG_A6XX_CP_PROTECT(17), 1375 1375 + REG_A6XX_CP_PROTECT(18), 1376 1376 + REG_A6XX_CP_PROTECT(19), 1377 1377 + REG_A6XX_CP_PROTECT(20), 1378 1378 + REG_A6XX_CP_PROTECT(21), 1379 1379 + REG_A6XX_CP_PROTECT(22), 1380 1380 + REG_A6XX_CP_PROTECT(23), 1381 1381 + REG_A6XX_CP_PROTECT(24), 1382 1382 + REG_A6XX_CP_PROTECT(25), 1383 1383 + REG_A6XX_CP_PROTECT(26), 1384 1384 + REG_A6XX_CP_PROTECT(27), 1385 1385 + REG_A6XX_CP_PROTECT(28), 1386 1386 + REG_A6XX_CP_PROTECT(29), 1387 1387 + REG_A6XX_CP_PROTECT(30), 1388 1388 + REG_A6XX_CP_PROTECT(31), 1389 1389 + REG_A6XX_CP_PROTECT(32), 1390 1390 + REG_A6XX_CP_PROTECT(33), 1391 1391 + REG_A6XX_CP_PROTECT(34), 1392 1392 + REG_A6XX_CP_PROTECT(35), 1393 1393 + REG_A6XX_CP_PROTECT(36), 1394 1394 + REG_A6XX_CP_PROTECT(37), 1395 1395 + REG_A6XX_CP_PROTECT(38), 1396 1396 + REG_A6XX_CP_PROTECT(39), 1397 1397 + REG_A6XX_CP_PROTECT(40), 1398 1398 + REG_A6XX_CP_PROTECT(41), 1399 1399 + REG_A6XX_CP_PROTECT(42), 1400 1400 + REG_A6XX_CP_PROTECT(43), 1401 1401 + REG_A6XX_CP_PROTECT(44), 1402 1402 + REG_A6XX_CP_PROTECT(45), 1403 1403 + REG_A6XX_CP_PROTECT(46), 1404 1404 + REG_A6XX_CP_PROTECT(47), 1405 1405 + }; 1406 1406 + 1407 1407 + DECLARE_ADRENO_REGLIST_LIST(a750_ifpc_reglist); 1408 1408 + 1356 1409 static const struct adreno_info a7xx_gpus[] = { 1357 1410 { 1358 1411 .chip_ids = ADRENO_CHIP_IDS(0x07000200), ··· 1505 1432 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 1506 1433 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 1507 1434 ADRENO_QUIRK_HAS_HW_APRIV | 1508 1508 - ADRENO_QUIRK_PREEMPTION, 1435 1435 + ADRENO_QUIRK_PREEMPTION | 1436 1436 + ADRENO_QUIRK_IFPC, 1509 1437 .init = a6xx_gpu_init, 1510 1438 .a6xx = &(const struct a6xx_info) { 1511 1439 .hwcg = a740_hwcg, 1512 1440 .protect = &a730_protect, 1513 1441 .pwrup_reglist = &a7xx_pwrup_reglist, 1442 1442 + .ifpc_reglist = &a750_ifpc_reglist, 1514 1443 .gmu_chipid = 0x7050001, 1515 1444 .gmu_cgc_mode = 0x00020202, 1445 1445 + .bcms = (const struct a6xx_bcm[]) { 1446 1446 + { .name = "SH0", .buswidth = 16 }, 1447 1447 + { .name = "MC0", .buswidth = 4 }, 1448 1448 + { 1449 1449 + .name = "ACV", 1450 1450 + .fixed = true, 1451 1451 + .perfmode = BIT(3), 1452 1452 + .perfmode_bw = 16500000, 1453 1453 + }, 1454 1454 + { /* sentinel */ }, 1455 1455 + }, 1516 1456 }, 1517 1457 .preempt_record_size = 4192 * SZ_1K, 1518 1458 .speedbins = ADRENO_SPEEDBINS( ··· 1546 1460 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 1547 1461 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 1548 1462 ADRENO_QUIRK_HAS_HW_APRIV | 1549 1549 - ADRENO_QUIRK_PREEMPTION, 1463 1463 + ADRENO_QUIRK_PREEMPTION | 1464 1464 + ADRENO_QUIRK_IFPC, 1550 1465 .init = a6xx_gpu_init, 1551 1466 .zapfw = "gen70900_zap.mbn", 1552 1467 .a6xx = &(const struct a6xx_info) { 1553 1468 .protect = &a730_protect, 1554 1469 .pwrup_reglist = &a7xx_pwrup_reglist, 1470 1470 + .ifpc_reglist = &a750_ifpc_reglist, 1555 1471 .gmu_chipid = 0x7090100, 1556 1472 .gmu_cgc_mode = 0x00020202, 1557 1473 .bcms = (const struct a6xx_bcm[]) {

+89 -19

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

reviewed

··· 93 93 /* Check to see if the GX rail is still powered */ 94 94 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu) 95 95 { 96 96 + struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 97 97 + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 96 98 u32 val; 97 99 98 100 /* This can be called from gpu state code so make sure GMU is valid */ 99 101 if (!gmu->initialized) 100 102 return false; 101 103 104 104 + /* If GMU is absent, then GX power domain is ON as long as GPU is in active state */ 105 105 + if (adreno_has_gmu_wrapper(adreno_gpu)) 106 106 + return true; 107 107 + 102 108 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); 109 109 + 110 110 + if (adreno_is_a7xx(adreno_gpu)) 111 111 + return !(val & 112 112 + (A7XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF | 113 113 + A7XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF)); 103 114 104 115 return !(val & 105 116 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF | ··· 283 272 if (ret) 284 273 DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n"); 285 274 275 275 + set_bit(GMU_STATUS_FW_START, &gmu->status); 276 276 + 286 277 return ret; 287 278 } 288 279 ··· 416 403 int ret; 417 404 u32 val; 418 405 419 419 - if (!gmu->legacy) 406 406 + WARN_ON(!gmu->legacy); 407 407 + 408 408 + /* Nothing to do if GMU does the power management */ 409 409 + if (gmu->idle_level > GMU_IDLE_STATE_ACTIVE) 420 410 return 0; 421 411 422 412 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000); ··· 534 518 int ret; 535 519 u32 val; 536 520 521 521 + if (!test_and_clear_bit(GMU_STATUS_PDC_SLEEP, &gmu->status)) 522 522 + return 0; 523 523 + 537 524 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, BIT(1)); 538 525 539 526 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val, ··· 564 545 int ret; 565 546 u32 val; 566 547 548 548 + if (test_and_clear_bit(GMU_STATUS_FW_START, &gmu->status)) 549 549 + return; 550 550 + 567 551 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1); 568 552 569 553 ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, ··· 575 553 DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n"); 576 554 577 555 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); 556 556 + 557 557 + set_bit(GMU_STATUS_PDC_SLEEP, &gmu->status); 578 558 } 579 559 580 560 static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value) ··· 704 680 705 681 /* ensure no writes happen before the uCode is fully written */ 706 682 wmb(); 707 707 - 708 708 - a6xx_rpmh_stop(gmu); 709 683 710 684 err: 711 685 if (!IS_ERR_OR_NULL(pdcptr)) ··· 864 842 else 865 843 gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1); 866 844 867 867 - if (state == GMU_WARM_BOOT) { 868 868 - ret = a6xx_rpmh_start(gmu); 869 869 - if (ret) 870 870 - return ret; 871 871 - } else { 845 845 + ret = a6xx_rpmh_start(gmu); 846 846 + if (ret) 847 847 + return ret; 848 848 + 849 849 + if (state == GMU_COLD_BOOT) { 872 850 if (WARN(!adreno_gpu->fw[ADRENO_FW_GMU], 873 851 "GMU firmware is not loaded\n")) 874 852 return -ENOENT; 875 875 - 876 876 - ret = a6xx_rpmh_start(gmu); 877 877 - if (ret) 878 878 - return ret; 879 853 880 854 ret = a6xx_gmu_fw_load(gmu); 881 855 if (ret) ··· 943 925 ret = a6xx_gmu_gfx_rail_on(gmu); 944 926 if (ret) 945 927 return ret; 946 946 - } 947 928 948 948 - /* Enable SPTP_PC if the CPU is responsible for it */ 949 949 - if (gmu->idle_level < GMU_IDLE_STATE_SPTP) { 950 929 ret = a6xx_sptprac_enable(gmu); 951 930 if (ret) 952 931 return ret; ··· 995 980 val, (val & 1), 100, 10000); 996 981 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS + seqmem_off, 997 982 val, (val & 1), 100, 1000); 983 983 + 984 984 + if (!adreno_is_a740_family(adreno_gpu)) 985 985 + return; 986 986 + 987 987 + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS4_DRV0_STATUS + seqmem_off, 988 988 + val, (val & 1), 100, 10000); 989 989 + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS5_DRV0_STATUS + seqmem_off, 990 990 + val, (val & 1), 100, 10000); 991 991 + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS6_DRV0_STATUS + seqmem_off, 992 992 + val, (val & 1), 100, 10000); 993 993 + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS7_DRV0_STATUS + seqmem_off, 994 994 + val, (val & 1), 100, 1000); 995 995 + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS8_DRV0_STATUS + seqmem_off, 996 996 + val, (val & 1), 100, 10000); 997 997 + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS9_DRV0_STATUS + seqmem_off, 998 998 + val, (val & 1), 100, 1000); 998 999 } 999 1000 1000 1001 /* Force the GMU off in case it isn't responsive */ ··· 1054 1023 1055 1024 /* Reset GPU core blocks */ 1056 1025 a6xx_gpu_sw_reset(gpu, true); 1026 1026 + 1027 1027 + a6xx_rpmh_stop(gmu); 1057 1028 } 1058 1029 1059 1030 static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu) ··· 1161 1128 /* Set the GPU to the current freq */ 1162 1129 a6xx_gmu_set_initial_freq(gpu, gmu); 1163 1130 1131 1131 + if (refcount_read(&gpu->sysprof_active) > 1) { 1132 1132 + ret = a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET); 1133 1133 + if (!ret) 1134 1134 + set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status); 1135 1135 + } 1164 1136 out: 1165 1137 /* On failure, shut down the GMU to leave it in a good state */ 1166 1138 if (ret) { ··· 1212 1174 1213 1175 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 1214 1176 } 1177 1177 + 1178 1178 + if (test_and_clear_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) 1179 1179 + a6xx_gmu_clear_oob(gmu, GMU_OOB_PERFCOUNTER_SET); 1215 1180 1216 1181 ret = a6xx_gmu_wait_for_idle(gmu); 1217 1182 ··· 1359 1318 struct msm_mmu *mmu; 1360 1319 1361 1320 mmu = msm_iommu_new(gmu->dev, 0); 1362 1362 - if (!mmu) 1363 1363 - return -ENODEV; 1364 1321 if (IS_ERR(mmu)) 1365 1322 return PTR_ERR(mmu); 1366 1323 ··· 1731 1692 u32 val; 1732 1693 1733 1694 freq = gmu->gpu_freqs[i]; 1695 1695 + /* This is unlikely to fail because we are passing back a known freq */ 1734 1696 opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, freq, true); 1735 1697 np = dev_pm_opp_get_of_node(opp); 1736 1698 ··· 1828 1788 } 1829 1789 1830 1790 return irq; 1791 1791 + } 1792 1792 + 1793 1793 + void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu) 1794 1794 + { 1795 1795 + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1796 1796 + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1797 1797 + struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1798 1798 + unsigned int sysprof_active; 1799 1799 + 1800 1800 + /* Nothing to do if GPU is suspended. We will handle this during GMU resume */ 1801 1801 + if (!pm_runtime_get_if_active(&gpu->pdev->dev)) 1802 1802 + return; 1803 1803 + 1804 1804 + mutex_lock(&gmu->lock); 1805 1805 + 1806 1806 + sysprof_active = refcount_read(&gpu->sysprof_active); 1807 1807 + 1808 1808 + /* 1809 1809 + * 'Perfcounter select' register values are lost during IFPC collapse. To avoid that, 1810 1810 + * use the currently unused perfcounter oob vote to block IFPC when sysprof is active 1811 1811 + */ 1812 1812 + if ((sysprof_active > 1) && !test_and_set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) 1813 1813 + a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET); 1814 1814 + else if ((sysprof_active == 1) && test_and_clear_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) 1815 1815 + a6xx_gmu_clear_oob(gmu, GMU_OOB_PERFCOUNTER_SET); 1816 1816 + 1817 1817 + mutex_unlock(&gmu->lock); 1818 1818 + 1819 1819 + pm_runtime_put(&gpu->pdev->dev); 1831 1820 } 1832 1821 1833 1822 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) ··· 2001 1932 if (ret) 2002 1933 return ret; 2003 1934 2004 2004 - /* Fow now, don't do anything fancy until we get our feet under us */ 2005 2005 - gmu->idle_level = GMU_IDLE_STATE_ACTIVE; 1935 1935 + /* Set GMU idle level */ 1936 1936 + gmu->idle_level = (adreno_gpu->info->quirks & ADRENO_QUIRK_IFPC) ? 1937 1937 + GMU_IDLE_STATE_IFPC : GMU_IDLE_STATE_ACTIVE; 2006 1938 2007 1939 pm_runtime_enable(gmu->dev); 2008 1940

+14

drivers/gpu/drm/msm/adreno/a6xx_gmu.h

reviewed

··· 50 50 /* The GMU does not do any idle state management */ 51 51 #define GMU_IDLE_STATE_ACTIVE 0 52 52 53 53 + /* Unknown power state. Not exposed by the firmware. For documentation purpose only */ 54 54 + #define GMU_IDLE_STATE_RESERVED 1 55 55 + 53 56 /* The GMU manages SPTP power collapse */ 54 57 #define GMU_IDLE_STATE_SPTP 2 55 58 ··· 120 117 121 118 struct qmp *qmp; 122 119 struct a6xx_hfi_msg_bw_table *bw_table; 120 120 + 121 121 + /* To check if we can trigger sleep seq at PDC. Cleared in a6xx_rpmh_stop() */ 122 122 + #define GMU_STATUS_FW_START 0 123 123 + /* To track if PDC sleep seq was done */ 124 124 + #define GMU_STATUS_PDC_SLEEP 1 125 125 + /* To track Perfcounter OOB set status */ 126 126 + #define GMU_STATUS_OOB_PERF_SET 2 127 127 + unsigned long status; 123 128 }; 124 129 125 130 static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset) ··· 168 157 169 158 #define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) \ 170 159 readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \ 160 160 + interval, timeout) 161 161 + #define gmu_poll_timeout_atomic(gmu, addr, val, cond, interval, timeout) \ 162 162 + readl_poll_timeout_atomic((gmu)->mmio + ((addr) << 2), val, cond, \ 171 163 interval, timeout) 172 164 173 165 static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset)

+195 -47

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

reviewed

··· 16 16 17 17 #define GPU_PAS_ID 13 18 18 19 19 + static u64 read_gmu_ao_counter(struct a6xx_gpu *a6xx_gpu) 20 20 + { 21 21 + u64 count_hi, count_lo, temp; 22 22 + 23 23 + do { 24 24 + count_hi = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H); 25 25 + count_lo = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L); 26 26 + temp = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H); 27 27 + } while (unlikely(count_hi != temp)); 28 28 + 29 29 + return (count_hi << 32) | count_lo; 30 30 + } 31 31 + 32 32 + static bool fence_status_check(struct msm_gpu *gpu, u32 offset, u32 value, u32 status, u32 mask) 33 33 + { 34 34 + /* Success if !writedropped0/1 */ 35 35 + if (!(status & mask)) 36 36 + return true; 37 37 + 38 38 + udelay(10); 39 39 + 40 40 + /* Try to update fenced register again */ 41 41 + gpu_write(gpu, offset, value); 42 42 + 43 43 + /* We can't do a posted write here because the power domain could be 44 44 + * in collapse state. So use the heaviest barrier instead 45 45 + */ 46 46 + mb(); 47 47 + return false; 48 48 + } 49 49 + 50 50 + static int fenced_write(struct a6xx_gpu *a6xx_gpu, u32 offset, u32 value, u32 mask) 51 51 + { 52 52 + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 53 53 + struct msm_gpu *gpu = &adreno_gpu->base; 54 54 + struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 55 55 + u32 status; 56 56 + 57 57 + gpu_write(gpu, offset, value); 58 58 + 59 59 + /* Nothing else to be done in the case of no-GMU */ 60 60 + if (adreno_has_gmu_wrapper(adreno_gpu)) 61 61 + return 0; 62 62 + 63 63 + /* We can't do a posted write here because the power domain could be 64 64 + * in collapse state. So use the heaviest barrier instead 65 65 + */ 66 66 + mb(); 67 67 + 68 68 + if (!gmu_poll_timeout(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS, status, 69 69 + fence_status_check(gpu, offset, value, status, mask), 0, 1000)) 70 70 + return 0; 71 71 + 72 72 + /* Try again for another 1ms before failing */ 73 73 + gpu_write(gpu, offset, value); 74 74 + mb(); 75 75 + 76 76 + if (!gmu_poll_timeout(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS, status, 77 77 + fence_status_check(gpu, offset, value, status, mask), 0, 1000)) { 78 78 + /* 79 79 + * The 'delay' warning is here because the pause to print this 80 80 + * warning will allow gpu to move to power collapse which 81 81 + * defeats the purpose of continuous polling for 2 ms 82 82 + */ 83 83 + dev_err_ratelimited(gmu->dev, "delay in fenced register write (0x%x)\n", 84 84 + offset); 85 85 + return 0; 86 86 + } 87 87 + 88 88 + dev_err_ratelimited(gmu->dev, "fenced register write (0x%x) fail\n", 89 89 + offset); 90 90 + 91 91 + return -ETIMEDOUT; 92 92 + } 93 93 + 94 94 + int a6xx_fenced_write(struct a6xx_gpu *a6xx_gpu, u32 offset, u64 value, u32 mask, bool is_64b) 95 95 + { 96 96 + int ret; 97 97 + 98 98 + ret = fenced_write(a6xx_gpu, offset, lower_32_bits(value), mask); 99 99 + if (ret) 100 100 + return ret; 101 101 + 102 102 + if (!is_64b) 103 103 + return 0; 104 104 + 105 105 + ret = fenced_write(a6xx_gpu, offset + 1, upper_32_bits(value), mask); 106 106 + 107 107 + return ret; 108 108 + } 109 109 + 19 110 static inline bool _a6xx_check_idle(struct msm_gpu *gpu) 20 111 { 21 112 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); ··· 177 86 /* Update HW if this is the current ring and we are not in preempt*/ 178 87 if (!a6xx_in_preempt(a6xx_gpu)) { 179 88 if (a6xx_gpu->cur_ring == ring) 180 180 - gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); 89 89 + a6xx_fenced_write(a6xx_gpu, REG_A6XX_CP_RB_WPTR, wptr, BIT(0), false); 181 90 else 182 91 ring->restore_wptr = true; 183 92 } else { ··· 264 173 * Needed for preemption 265 174 */ 266 175 OUT_PKT7(ring, CP_MEM_WRITE, 5); 267 267 - OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr))); 268 268 - OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr))); 176 176 + OUT_RING(ring, A5XX_CP_MEM_WRITE_ADDR_LO(lower_32_bits(memptr))); 177 177 + OUT_RING(ring, A5XX_CP_MEM_WRITE_ADDR_HI(upper_32_bits(memptr))); 269 178 OUT_RING(ring, lower_32_bits(ttbr)); 270 179 OUT_RING(ring, upper_32_bits(ttbr)); 271 180 OUT_RING(ring, ctx->seqno); ··· 295 204 */ 296 205 OUT_PKT7(ring, CP_WAIT_REG_MEM, 6); 297 206 OUT_RING(ring, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ)); 298 298 - OUT_RING(ring, CP_WAIT_REG_MEM_1_POLL_ADDR_LO( 207 207 + OUT_RING(ring, CP_WAIT_REG_MEM_POLL_ADDR_LO( 299 208 REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS)); 300 300 - OUT_RING(ring, CP_WAIT_REG_MEM_2_POLL_ADDR_HI(0)); 209 209 + OUT_RING(ring, CP_WAIT_REG_MEM_POLL_ADDR_HI(0)); 301 210 OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(0x1)); 302 211 OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(0x1)); 303 212 OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(0)); ··· 389 298 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); 390 299 OUT_RING(ring, submit->seqno); 391 300 392 392 - trace_msm_gpu_submit_flush(submit, 393 393 - gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER)); 301 301 + trace_msm_gpu_submit_flush(submit, read_gmu_ao_counter(a6xx_gpu)); 394 302 395 303 a6xx_flush(gpu, ring); 396 304 } ··· 589 499 } 590 500 591 501 592 592 - trace_msm_gpu_submit_flush(submit, 593 593 - gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER)); 502 502 + trace_msm_gpu_submit_flush(submit, read_gmu_ao_counter(a6xx_gpu)); 594 503 595 504 a6xx_flush(gpu, ring); 596 505 ··· 828 739 u32 *dest = (u32 *)&lock->regs[0]; 829 740 int i; 830 741 831 831 - reglist = adreno_gpu->info->a6xx->pwrup_reglist; 832 832 - 833 742 lock->gpu_req = lock->cpu_req = lock->turn = 0; 834 834 - lock->ifpc_list_len = 0; 835 835 - lock->preemption_list_len = reglist->count; 743 743 + 744 744 + reglist = adreno_gpu->info->a6xx->ifpc_reglist; 745 745 + lock->ifpc_list_len = reglist->count; 836 746 837 747 /* 838 748 * For each entry in each of the lists, write the offset and the current 839 749 * register value into the GPU buffer 840 750 */ 751 751 + for (i = 0; i < reglist->count; i++) { 752 752 + *dest++ = reglist->regs[i]; 753 753 + *dest++ = gpu_read(gpu, reglist->regs[i]); 754 754 + } 755 755 + 756 756 + reglist = adreno_gpu->info->a6xx->pwrup_reglist; 757 757 + lock->preemption_list_len = reglist->count; 758 758 + 841 759 for (i = 0; i < reglist->count; i++) { 842 760 *dest++ = reglist->regs[i]; 843 761 *dest++ = gpu_read(gpu, reglist->regs[i]); ··· 1337 1241 1338 1242 /* Set weights for bicubic filtering */ 1339 1243 if (adreno_is_a650_family(adreno_gpu) || adreno_is_x185(adreno_gpu)) { 1340 1340 - gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0); 1341 1341 - gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, 1244 1244 + gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(0), 0); 1245 1245 + gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(1), 1342 1246 0x3fe05ff4); 1343 1343 - gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2, 1247 1247 + gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(2), 1344 1248 0x3fa0ebee); 1345 1345 - gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3, 1249 1249 + gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(3), 1346 1250 0x3f5193ed); 1347 1347 - gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4, 1251 1251 + gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(4), 1348 1252 0x3f0243f0); 1349 1253 } 1350 1254 ··· 1544 1448 1545 1449 adreno_dump_info(gpu); 1546 1450 1547 1547 - for (i = 0; i < 8; i++) 1548 1548 - DRM_DEV_INFO(&gpu->pdev->dev, "CP_SCRATCH_REG%d: %u\n", i, 1549 1549 - gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i))); 1451 1451 + if (a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) { 1452 1452 + /* Sometimes crashstate capture is skipped, so SQE should be halted here again */ 1453 1453 + gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 3); 1550 1454 1551 1551 - if (hang_debug) 1552 1552 - a6xx_dump(gpu); 1455 1455 + for (i = 0; i < 8; i++) 1456 1456 + DRM_DEV_INFO(&gpu->pdev->dev, "CP_SCRATCH_REG%d: %u\n", i, 1457 1457 + gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i))); 1458 1458 + 1459 1459 + if (hang_debug) 1460 1460 + a6xx_dump(gpu); 1461 1461 + 1462 1462 + } 1553 1463 1554 1464 /* 1555 1465 * To handle recovery specific sequences during the rpm suspend we are 1556 1466 * about to trigger 1557 1467 */ 1558 1558 - a6xx_gpu->hung = true; 1559 1468 1560 1560 - /* Halt SQE first */ 1561 1561 - gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 3); 1469 1469 + a6xx_gpu->hung = true; 1562 1470 1563 1471 pm_runtime_dont_use_autosuspend(&gpu->pdev->dev); 1564 1472 ··· 1793 1693 1794 1694 static void a6xx_fault_detect_irq(struct msm_gpu *gpu) 1795 1695 { 1796 1796 - struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1797 1797 - struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1798 1696 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); 1799 1697 1800 1698 /* ··· 1803 1705 */ 1804 1706 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS3) & A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT) 1805 1707 return; 1806 1806 - 1807 1807 - /* 1808 1808 - * Force the GPU to stay on until after we finish 1809 1809 - * collecting information 1810 1810 - */ 1811 1811 - if (!adreno_has_gmu_wrapper(adreno_gpu)) 1812 1812 - gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1); 1813 1708 1814 1709 DRM_DEV_ERROR(&gpu->pdev->dev, 1815 1710 "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n", ··· 1817 1726 1818 1727 /* Turn off the hangcheck timer to keep it from bothering us */ 1819 1728 timer_delete(&gpu->hangcheck_timer); 1729 1729 + 1730 1730 + /* Turn off interrupts to avoid triggering recovery again */ 1731 1731 + gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, 0); 1820 1732 1821 1733 kthread_queue_work(gpu->worker, &gpu->recover_work); 1822 1734 } ··· 1845 1751 } 1846 1752 } 1847 1753 1754 1754 + static void a6xx_gpu_keepalive_vote(struct msm_gpu *gpu, bool on) 1755 1755 + { 1756 1756 + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1757 1757 + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1758 1758 + 1759 1759 + if (adreno_has_gmu_wrapper(adreno_gpu)) 1760 1760 + return; 1761 1761 + 1762 1762 + gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, on); 1763 1763 + } 1764 1764 + 1765 1765 + static int irq_poll_fence(struct msm_gpu *gpu) 1766 1766 + { 1767 1767 + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1768 1768 + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1769 1769 + struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1770 1770 + u32 status; 1771 1771 + 1772 1772 + if (adreno_has_gmu_wrapper(adreno_gpu)) 1773 1773 + return 0; 1774 1774 + 1775 1775 + if (gmu_poll_timeout_atomic(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, status, !status, 1, 100)) { 1776 1776 + u32 rbbm_unmasked = gmu_read(gmu, REG_A6XX_GMU_RBBM_INT_UNMASKED_STATUS); 1777 1777 + 1778 1778 + dev_err_ratelimited(&gpu->pdev->dev, 1779 1779 + "irq fence poll timeout, fence_ctrl=0x%x, unmasked_status=0x%x\n", 1780 1780 + status, rbbm_unmasked); 1781 1781 + return -ETIMEDOUT; 1782 1782 + } 1783 1783 + 1784 1784 + return 0; 1785 1785 + } 1786 1786 + 1848 1787 static irqreturn_t a6xx_irq(struct msm_gpu *gpu) 1849 1788 { 1850 1789 struct msm_drm_private *priv = gpu->dev->dev_private; 1790 1790 + 1791 1791 + /* Set keepalive vote to avoid power collapse after RBBM_INT_0_STATUS is read */ 1792 1792 + a6xx_gpu_keepalive_vote(gpu, true); 1793 1793 + 1794 1794 + if (irq_poll_fence(gpu)) 1795 1795 + goto done; 1796 1796 + 1851 1797 u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS); 1852 1798 1853 1799 gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status); ··· 1923 1789 1924 1790 if (status & A6XX_RBBM_INT_0_MASK_CP_SW) 1925 1791 a6xx_preempt_irq(gpu); 1792 1792 + 1793 1793 + done: 1794 1794 + a6xx_gpu_keepalive_vote(gpu, false); 1926 1795 1927 1796 return IRQ_HANDLED; 1928 1797 } ··· 2316 2179 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2317 2180 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2318 2181 2319 2319 - mutex_lock(&a6xx_gpu->gmu.lock); 2320 2320 - 2321 2321 - /* Force the GPU power on so we can read this register */ 2322 2322 - a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); 2323 2323 - 2324 2324 - *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER); 2325 2325 - 2326 2326 - a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); 2327 2327 - 2328 2328 - mutex_unlock(&a6xx_gpu->gmu.lock); 2182 2182 + *value = read_gmu_ao_counter(a6xx_gpu); 2329 2183 2330 2184 return 0; 2331 2185 } ··· 2426 2298 if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) 2427 2299 return a6xx_gpu->shadow[ring->id]; 2428 2300 2301 2301 + /* 2302 2302 + * This is true only on an A6XX_GEN1 with GMU, has IFPC enabled and a super old SQE firmware 2303 2303 + * without 'whereami' support 2304 2304 + */ 2305 2305 + WARN_ONCE((to_adreno_gpu(gpu)->info->quirks & ADRENO_QUIRK_IFPC), 2306 2306 + "Can't read CP_RB_RPTR register reliably\n"); 2307 2307 + 2429 2308 return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR); 2430 2309 } 2431 2310 2432 2311 static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 2433 2312 { 2434 2434 - struct msm_cp_state cp_state = { 2313 2313 + struct msm_cp_state cp_state; 2314 2314 + bool progress; 2315 2315 + 2316 2316 + /* 2317 2317 + * With IFPC, KMD doesn't know whether GX power domain is collapsed 2318 2318 + * or not. So, we can't blindly read the below registers in GX domain. 2319 2319 + * Lets trust the hang detection in HW and lie to the caller that 2320 2320 + * there was progress. 2321 2321 + */ 2322 2322 + if (to_adreno_gpu(gpu)->info->quirks & ADRENO_QUIRK_IFPC) 2323 2323 + return true; 2324 2324 + 2325 2325 + cp_state = (struct msm_cp_state) { 2435 2326 .ib1_base = gpu_read64(gpu, REG_A6XX_CP_IB1_BASE), 2436 2327 .ib2_base = gpu_read64(gpu, REG_A6XX_CP_IB2_BASE), 2437 2328 .ib1_rem = gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE), 2438 2329 .ib2_rem = gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE), 2439 2330 }; 2440 2440 - bool progress; 2441 2331 2442 2332 /* 2443 2333 * Adjust the remaining data to account for what has already been ··· 2554 2408 .create_private_vm = a6xx_create_private_vm, 2555 2409 .get_rptr = a6xx_get_rptr, 2556 2410 .progress = a6xx_progress, 2411 2411 + .sysprof_setup = a6xx_gmu_sysprof_setup, 2557 2412 }, 2558 2413 .get_timestamp = a6xx_gmu_get_timestamp, 2559 2414 }; ··· 2615 2468 .create_private_vm = a6xx_create_private_vm, 2616 2469 .get_rptr = a6xx_get_rptr, 2617 2470 .progress = a6xx_progress, 2471 2471 + .sysprof_setup = a6xx_gmu_sysprof_setup, 2618 2472 }, 2619 2473 .get_timestamp = a6xx_gmu_get_timestamp, 2620 2474 };

+3

drivers/gpu/drm/msm/adreno/a6xx_gpu.h

reviewed

··· 45 45 const struct adreno_reglist *hwcg; 46 46 const struct adreno_protect *protect; 47 47 const struct adreno_reglist_list *pwrup_reglist; 48 48 + const struct adreno_reglist_list *ifpc_reglist; 48 49 u32 gmu_chipid; 49 50 u32 gmu_cgc_mode; 50 51 u32 prim_fifo_threshold; ··· 255 254 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); 256 255 int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); 257 256 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); 257 257 + void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu); 258 258 259 259 void a6xx_preempt_init(struct msm_gpu *gpu); 260 260 void a6xx_preempt_hw_init(struct msm_gpu *gpu); ··· 297 295 298 296 void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool gx_off); 299 297 void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert); 298 298 + int a6xx_fenced_write(struct a6xx_gpu *gpu, u32 offset, u64 value, u32 mask, bool is_64b); 300 299 301 300 #endif /* __A6XX_GPU_H__ */

+7 -3

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c

reviewed

··· 1586 1586 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1587 1587 struct a6xx_gpu_state *a6xx_state = kzalloc(sizeof(*a6xx_state), 1588 1588 GFP_KERNEL); 1589 1589 - bool stalled = !!(gpu_read(gpu, REG_A6XX_RBBM_STATUS3) & 1590 1590 - A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT); 1589 1589 + bool stalled; 1591 1590 1592 1591 if (!a6xx_state) 1593 1592 return ERR_PTR(-ENOMEM); ··· 1607 1608 } 1608 1609 1609 1610 /* If GX isn't on the rest of the data isn't going to be accessible */ 1610 1610 - if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) 1611 1611 + if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) 1611 1612 return &a6xx_state->base; 1613 1613 + 1614 1614 + /* Halt SQE first */ 1615 1615 + gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 3); 1612 1616 1613 1617 /* Get the banks of indexed registers */ 1614 1618 if (adreno_is_a7xx(adreno_gpu)) ··· 1619 1617 else 1620 1618 a6xx_get_indexed_registers(gpu, a6xx_state); 1621 1619 1620 1620 + stalled = !!(gpu_read(gpu, REG_A6XX_RBBM_STATUS3) & 1621 1621 + A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT); 1622 1622 /* 1623 1623 * Try to initialize the crashdumper, if we are not dumping state 1624 1624 * with the SMMU stalled. The crashdumper needs memory access to

+28 -6

drivers/gpu/drm/msm/adreno/a6xx_hfi.c

reviewed

··· 21 21 HFI_MSG_ID(HFI_H2F_MSG_PERF_TABLE), 22 22 HFI_MSG_ID(HFI_H2F_MSG_TEST), 23 23 HFI_MSG_ID(HFI_H2F_MSG_START), 24 24 + HFI_MSG_ID(HFI_H2F_FEATURE_CTRL), 24 25 HFI_MSG_ID(HFI_H2F_MSG_CORE_FW_START), 25 26 HFI_MSG_ID(HFI_H2F_MSG_GX_BW_PERF_VOTE), 26 27 HFI_MSG_ID(HFI_H2F_MSG_PREPARE_SLUMBER), ··· 766 765 NULL, 0); 767 766 } 768 767 768 768 + static int a6xx_hfi_feature_ctrl_msg(struct a6xx_gmu *gmu, u32 feature, u32 enable, u32 data) 769 769 + { 770 770 + struct a6xx_hfi_msg_feature_ctrl msg = { 771 771 + .feature = feature, 772 772 + .enable = enable, 773 773 + .data = data, 774 774 + }; 775 775 + 776 776 + return a6xx_hfi_send_msg(gmu, HFI_H2F_FEATURE_CTRL, &msg, sizeof(msg), NULL, 0); 777 777 + } 778 778 + 779 779 + #define HFI_FEATURE_IFPC 9 780 780 + #define IFPC_LONG_HYST 0x1680 781 781 + 782 782 + static int a6xx_hfi_enable_ifpc(struct a6xx_gmu *gmu) 783 783 + { 784 784 + if (gmu->idle_level != GMU_IDLE_STATE_IFPC) 785 785 + return 0; 786 786 + 787 787 + return a6xx_hfi_feature_ctrl_msg(gmu, HFI_FEATURE_IFPC, 1, IFPC_LONG_HYST); 788 788 + } 789 789 + 769 790 #define HFI_FEATURE_ACD 12 770 791 771 792 static int a6xx_hfi_enable_acd(struct a6xx_gmu *gmu) 772 793 { 773 794 struct a6xx_hfi_acd_table *acd_table = &gmu->acd_table; 774 774 - struct a6xx_hfi_msg_feature_ctrl msg = { 775 775 - .feature = HFI_FEATURE_ACD, 776 776 - .enable = 1, 777 777 - .data = 0, 778 778 - }; 779 795 int ret; 780 796 781 797 if (!acd_table->enable_by_level) 782 798 return 0; 783 799 784 800 /* Enable ACD feature at GMU */ 785 785 - ret = a6xx_hfi_send_msg(gmu, HFI_H2F_FEATURE_CTRL, &msg, sizeof(msg), NULL, 0); 801 801 + ret = a6xx_hfi_feature_ctrl_msg(gmu, HFI_FEATURE_ACD, 1, 0); 786 802 if (ret) { 787 803 DRM_DEV_ERROR(gmu->dev, "Unable to enable ACD (%d)\n", ret); 788 804 return ret; ··· 913 895 return ret; 914 896 915 897 ret = a6xx_hfi_enable_acd(gmu); 898 898 + if (ret) 899 899 + return ret; 900 900 + 901 901 + ret = a6xx_hfi_enable_ifpc(gmu); 916 902 if (ret) 917 903 return ret; 918 904

+32 -12

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

reviewed

··· 41 41 } 42 42 43 43 /* Write the most recent wptr for the given ring into the hardware */ 44 44 - static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 44 44 + static inline void update_wptr(struct a6xx_gpu *a6xx_gpu, struct msm_ringbuffer *ring) 45 45 { 46 46 unsigned long flags; 47 47 uint32_t wptr; ··· 51 51 if (ring->restore_wptr) { 52 52 wptr = get_wptr(ring); 53 53 54 54 - gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); 54 54 + a6xx_fenced_write(a6xx_gpu, REG_A6XX_CP_RB_WPTR, wptr, BIT(0), false); 55 55 56 56 ring->restore_wptr = false; 57 57 } ··· 111 111 112 112 postamble[count++] = PKT7(CP_WAIT_REG_MEM, 6); 113 113 postamble[count++] = CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ); 114 114 - postamble[count++] = CP_WAIT_REG_MEM_1_POLL_ADDR_LO( 114 114 + postamble[count++] = CP_WAIT_REG_MEM_POLL_ADDR_LO( 115 115 REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS); 116 116 - postamble[count++] = CP_WAIT_REG_MEM_2_POLL_ADDR_HI(0); 116 116 + postamble[count++] = CP_WAIT_REG_MEM_POLL_ADDR_HI(0); 117 117 postamble[count++] = CP_WAIT_REG_MEM_3_REF(0x1); 118 118 postamble[count++] = CP_WAIT_REG_MEM_4_MASK(0x1); 119 119 postamble[count++] = CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(0); ··· 134 134 *postamble = PKT7(CP_NOP, (a6xx_gpu->preempt_postamble_len - 1)); 135 135 136 136 a6xx_gpu->postamble_enabled = false; 137 137 + } 138 138 + 139 139 + /* 140 140 + * Set preemption keepalive vote. Please note that this vote is different from the one used in 141 141 + * a6xx_irq() 142 142 + */ 143 143 + static void a6xx_preempt_keepalive_vote(struct msm_gpu *gpu, bool on) 144 144 + { 145 145 + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 146 146 + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 147 147 + 148 148 + if (adreno_has_gmu_wrapper(adreno_gpu)) 149 149 + return; 150 150 + 151 151 + gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_PWR_COL_PREEMPT_KEEPALIVE, on); 137 152 } 138 153 139 154 void a6xx_preempt_irq(struct msm_gpu *gpu) ··· 187 172 188 173 set_preempt_state(a6xx_gpu, PREEMPT_FINISH); 189 174 190 190 - update_wptr(gpu, a6xx_gpu->cur_ring); 175 175 + update_wptr(a6xx_gpu, a6xx_gpu->cur_ring); 191 176 192 177 set_preempt_state(a6xx_gpu, PREEMPT_NONE); 178 178 + 179 179 + a6xx_preempt_keepalive_vote(gpu, false); 193 180 194 181 trace_msm_gpu_preemption_irq(a6xx_gpu->cur_ring->id); 195 182 ··· 285 268 */ 286 269 if (!ring || (a6xx_gpu->cur_ring == ring)) { 287 270 set_preempt_state(a6xx_gpu, PREEMPT_FINISH); 288 288 - update_wptr(gpu, a6xx_gpu->cur_ring); 271 271 + update_wptr(a6xx_gpu, a6xx_gpu->cur_ring); 289 272 set_preempt_state(a6xx_gpu, PREEMPT_NONE); 290 273 spin_unlock_irqrestore(&a6xx_gpu->eval_lock, flags); 291 274 return; ··· 319 302 320 303 spin_unlock_irqrestore(&ring->preempt_lock, flags); 321 304 322 322 - gpu_write64(gpu, 323 323 - REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO, 324 324 - a6xx_gpu->preempt_smmu_iova[ring->id]); 305 305 + /* Set the keepalive bit to keep the GPU ON until preemption is complete */ 306 306 + a6xx_preempt_keepalive_vote(gpu, true); 325 307 326 326 - gpu_write64(gpu, 308 308 + a6xx_fenced_write(a6xx_gpu, 309 309 + REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO, a6xx_gpu->preempt_smmu_iova[ring->id], 310 310 + BIT(1), true); 311 311 + 312 312 + a6xx_fenced_write(a6xx_gpu, 327 313 REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR, 328 328 - a6xx_gpu->preempt_iova[ring->id]); 314 314 + a6xx_gpu->preempt_iova[ring->id], BIT(1), true); 329 315 330 316 a6xx_gpu->next_ring = ring; 331 317 ··· 348 328 set_preempt_state(a6xx_gpu, PREEMPT_TRIGGERED); 349 329 350 330 /* Trigger the preemption */ 351 351 - gpu_write(gpu, REG_A6XX_CP_CONTEXT_SWITCH_CNTL, cntl); 331 331 + a6xx_fenced_write(a6xx_gpu, REG_A6XX_CP_CONTEXT_SWITCH_CNTL, cntl, BIT(1), false); 352 332 } 353 333 354 334 static int preempt_init_ring(struct a6xx_gpu *a6xx_gpu,

+13

drivers/gpu/drm/msm/adreno/adreno_device.c

reviewed

··· 24 24 MODULE_PARM_DESC(disable_acd, "Forcefully disable GPU ACD"); 25 25 module_param_unsafe(disable_acd, bool, 0400); 26 26 27 27 + static bool skip_gpu; 28 28 + MODULE_PARM_DESC(no_gpu, "Disable GPU driver register (0=enable GPU driver register (default), 1=skip GPU driver register"); 29 29 + module_param(skip_gpu, bool, 0400); 30 30 + 27 31 extern const struct adreno_gpulist a2xx_gpulist; 28 32 extern const struct adreno_gpulist a3xx_gpulist; 29 33 extern const struct adreno_gpulist a4xx_gpulist; ··· 187 183 const struct adreno_info *info; 188 184 uint32_t chip_id; 189 185 int ret; 186 186 + 187 187 + if (skip_gpu) 188 188 + return false; 190 189 191 190 ret = find_chipid(node, &chip_id); 192 191 if (ret) ··· 411 404 412 405 void __init adreno_register(void) 413 406 { 407 407 + if (skip_gpu) 408 408 + return; 409 409 + 414 410 platform_driver_register(&adreno_driver); 415 411 } 416 412 417 413 void __exit adreno_unregister(void) 418 414 { 415 415 + if (skip_gpu) 416 416 + return; 417 417 + 419 418 platform_driver_unregister(&adreno_driver); 420 419 }

+6 -15

drivers/gpu/drm/msm/adreno/adreno_gpu.c

reviewed

··· 10 10 #include <linux/interconnect.h> 11 11 #include <linux/firmware/qcom/qcom_scm.h> 12 12 #include <linux/kernel.h> 13 13 - #include <linux/of_address.h> 13 13 + #include <linux/of_reserved_mem.h> 14 14 #include <linux/pm_opp.h> 15 15 #include <linux/slab.h> 16 16 #include <linux/soc/qcom/mdt_loader.h> ··· 33 33 struct device *dev = &gpu->pdev->dev; 34 34 const struct firmware *fw; 35 35 const char *signed_fwname = NULL; 36 36 - struct device_node *np, *mem_np; 36 36 + struct device_node *np; 37 37 struct resource r; 38 38 phys_addr_t mem_phys; 39 39 ssize_t mem_size; ··· 51 51 return -ENODEV; 52 52 } 53 53 54 54 - mem_np = of_parse_phandle(np, "memory-region", 0); 55 55 - of_node_put(np); 56 56 - if (!mem_np) { 54 54 + ret = of_reserved_mem_region_to_resource(np, 0, &r); 55 55 + if (ret) { 57 56 zap_available = false; 58 58 - return -EINVAL; 59 59 - } 60 60 - 61 61 - ret = of_address_to_resource(mem_np, 0, &r); 62 62 - of_node_put(mem_np); 63 63 - if (ret) 64 57 return ret; 65 65 - 58 58 + } 66 59 mem_phys = r.start; 67 60 68 61 /* ··· 202 209 u64 start, size; 203 210 204 211 mmu = msm_iommu_gpu_new(&pdev->dev, gpu, quirks); 205 205 - if (!mmu) 206 206 - return ERR_PTR(-ENODEV); 207 207 - else if (IS_ERR_OR_NULL(mmu)) 212 212 + if (IS_ERR(mmu)) 208 213 return ERR_CAST(mmu); 209 214 210 215 geometry = msm_iommu_get_geometry(mmu);

+1

drivers/gpu/drm/msm/adreno/adreno_gpu.h

reviewed

··· 59 59 #define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4) 60 60 #define ADRENO_QUIRK_PREEMPTION BIT(5) 61 61 #define ADRENO_QUIRK_4GB_VA BIT(6) 62 62 + #define ADRENO_QUIRK_IFPC BIT(7) 62 63 63 64 /* Helper for formating the chip_id in the way that userspace tools like 64 65 * crashdec expect.

+24 -11

drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c

reviewed

··· 32 32 }; 33 33 34 34 /** 35 35 + * dpu_core_perf_adjusted_mode_clk - Adjust given mode clock rate according to 36 36 + * the perf clock factor. 37 37 + * @crtc_clk_rate - Unadjusted mode clock rate 38 38 + * @perf_cfg: performance configuration 39 39 + */ 40 40 + u64 dpu_core_perf_adjusted_mode_clk(u64 mode_clk_rate, 41 41 + const struct dpu_perf_cfg *perf_cfg) 42 42 + { 43 43 + u32 clk_factor; 44 44 + 45 45 + clk_factor = perf_cfg->clk_inefficiency_factor; 46 46 + if (clk_factor) { 47 47 + mode_clk_rate *= clk_factor; 48 48 + do_div(mode_clk_rate, 100); 49 49 + } 50 50 + 51 51 + return mode_clk_rate; 52 52 + } 53 53 + 54 54 + /** 35 55 * _dpu_core_perf_calc_bw() - to calculate BW per crtc 36 56 * @perf_cfg: performance configuration 37 57 * @crtc: pointer to a crtc ··· 95 75 struct drm_plane *plane; 96 76 struct dpu_plane_state *pstate; 97 77 struct drm_display_mode *mode; 98 98 - u64 crtc_clk; 99 99 - u32 clk_factor; 78 78 + u64 mode_clk; 100 79 101 80 mode = &state->adjusted_mode; 102 81 103 103 - crtc_clk = (u64)mode->vtotal * mode->hdisplay * drm_mode_vrefresh(mode); 82 82 + mode_clk = (u64)mode->vtotal * mode->hdisplay * drm_mode_vrefresh(mode); 104 83 105 84 drm_atomic_crtc_for_each_plane(plane, crtc) { 106 85 pstate = to_dpu_plane_state(plane->state); 107 86 if (!pstate) 108 87 continue; 109 88 110 110 - crtc_clk = max(pstate->plane_clk, crtc_clk); 89 89 + mode_clk = max(pstate->plane_clk, mode_clk); 111 90 } 112 91 113 113 - clk_factor = perf_cfg->clk_inefficiency_factor; 114 114 - if (clk_factor) { 115 115 - crtc_clk *= clk_factor; 116 116 - do_div(crtc_clk, 100); 117 117 - } 118 118 - 119 119 - return crtc_clk; 92 92 + return dpu_core_perf_adjusted_mode_clk(mode_clk, perf_cfg); 120 93 } 121 94 122 95 static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)

+3

drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h

reviewed

··· 54 54 u32 fix_core_ab_vote; 55 55 }; 56 56 57 57 + u64 dpu_core_perf_adjusted_mode_clk(u64 clk_rate, 58 58 + const struct dpu_perf_cfg *perf_cfg); 59 59 + 57 60 int dpu_core_perf_crtc_check(struct drm_crtc *crtc, 58 61 struct drm_crtc_state *state); 59 62

+14 -3

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

reviewed

··· 377 377 static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc) 378 378 { 379 379 struct dpu_crtc_state *crtc_state; 380 380 - int lm_idx, lm_horiz_position; 380 380 + int lm_idx; 381 381 382 382 crtc_state = to_dpu_crtc_state(crtc->state); 383 383 384 384 - lm_horiz_position = 0; 385 384 for (lm_idx = 0; lm_idx < crtc_state->num_mixers; lm_idx++) { 386 385 const struct drm_rect *lm_roi = &crtc_state->lm_bounds[lm_idx]; 387 386 struct dpu_hw_mixer *hw_lm = crtc_state->mixers[lm_idx].hw_lm; ··· 391 392 392 393 cfg.out_width = drm_rect_width(lm_roi); 393 394 cfg.out_height = drm_rect_height(lm_roi); 394 394 - cfg.right_mixer = lm_horiz_position++; 395 395 + cfg.right_mixer = lm_idx & 0x1; 395 396 cfg.flags = 0; 396 397 hw_lm->ops.setup_mixer_out(hw_lm, &cfg); 397 398 } ··· 1533 1534 const struct drm_display_mode *mode) 1534 1535 { 1535 1536 struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); 1537 1537 + u64 adjusted_mode_clk; 1536 1538 1537 1539 /* if there is no 3d_mux block we cannot merge LMs so we cannot 1538 1540 * split the large layer into 2 LMs, filter out such modes ··· 1541 1541 if (!dpu_kms->catalog->caps->has_3d_merge && 1542 1542 mode->hdisplay > dpu_kms->catalog->caps->max_mixer_width) 1543 1543 return MODE_BAD_HVALUE; 1544 1544 + 1545 1545 + adjusted_mode_clk = dpu_core_perf_adjusted_mode_clk(mode->clock, 1546 1546 + dpu_kms->perf.perf_cfg); 1547 1547 + 1548 1548 + /* 1549 1549 + * The given mode, adjusted for the perf clock factor, should not exceed 1550 1550 + * the max core clock rate 1551 1551 + */ 1552 1552 + if (dpu_kms->perf.max_core_clk_rate < adjusted_mode_clk * 1000) 1553 1553 + return MODE_CLOCK_HIGH; 1554 1554 + 1544 1555 /* 1545 1556 * max crtc width is equal to the max mixer width * 2 and max height is 4K 1546 1557 */

+1 -1

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c

reviewed

··· 446 446 static int dpu_encoder_phys_wb_wait_for_commit_done( 447 447 struct dpu_encoder_phys *phys_enc) 448 448 { 449 449 - unsigned long ret; 449 449 + int ret; 450 450 struct dpu_encoder_wait_info wait_info; 451 451 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc); 452 452

-5

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c

reviewed

··· 338 338 *************************************************************/ 339 339 340 340 static const struct dpu_lm_sub_blks msm8998_lm_sblk = { 341 341 - .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 342 341 .maxblendstages = 7, /* excluding base layer */ 343 342 .blendstage_base = { /* offsets relative to mixer base */ 344 343 0x20, 0x50, 0x80, 0xb0, 0x230, ··· 346 347 }; 347 348 348 349 static const struct dpu_lm_sub_blks sdm845_lm_sblk = { 349 349 - .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 350 350 .maxblendstages = 11, /* excluding base layer */ 351 351 .blendstage_base = { /* offsets relative to mixer base */ 352 352 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, ··· 354 356 }; 355 357 356 358 static const struct dpu_lm_sub_blks sc7180_lm_sblk = { 357 357 - .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 358 359 .maxblendstages = 7, /* excluding base layer */ 359 360 .blendstage_base = { /* offsets relative to mixer base */ 360 361 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 0xb0 ··· 361 364 }; 362 365 363 366 static const struct dpu_lm_sub_blks sm8750_lm_sblk = { 364 364 - .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 365 367 .maxblendstages = 11, /* excluding base layer */ 366 368 .blendstage_base = { /* offsets relative to mixer base */ 367 369 /* 0x40 + n*0x30 */ ··· 370 374 }; 371 375 372 376 static const struct dpu_lm_sub_blks qcm2290_lm_sblk = { 373 373 - .maxwidth = DEFAULT_DPU_LINE_WIDTH, 374 377 .maxblendstages = 4, /* excluding base layer */ 375 378 .blendstage_base = { /* offsets relative to mixer base */ 376 379 0x20, 0x38, 0x50, 0x68

-1

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h

reviewed

··· 307 307 * @blendstage_base: Blend-stage register base offset 308 308 */ 309 309 struct dpu_lm_sub_blks { 310 310 - u32 maxwidth; 311 310 u32 maxblendstages; 312 311 u32 blendstage_base[MAX_BLOCKS]; 313 312 };

+1 -1

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

reviewed

··· 1110 1110 { 1111 1111 struct drm_gpuvm *vm; 1112 1112 1113 1113 - vm = msm_kms_init_vm(dpu_kms->dev); 1113 1113 + vm = msm_kms_init_vm(dpu_kms->dev, dpu_kms->dev->dev->parent); 1114 1114 if (IS_ERR(vm)) 1115 1115 return PTR_ERR(vm); 1116 1116

+4

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

reviewed

··· 922 922 if (MSM_FORMAT_IS_YUV(fmt)) 923 923 return false; 924 924 925 925 + if (!sspp) 926 926 + return true; 927 927 + 925 928 if (!test_bit(DPU_SSPP_SMART_DMA_V1, &sspp->cap->features) && 926 929 !test_bit(DPU_SSPP_SMART_DMA_V2, &sspp->cap->features)) 927 930 return false; ··· 1031 1028 prev_pipe->multirect_mode != DPU_SSPP_MULTIRECT_NONE) 1032 1029 return false; 1033 1030 1031 1031 + /* Do not validate SSPP of current plane when it is not ready */ 1034 1032 if (!dpu_plane_is_multirect_capable(pipe->sspp, pipe_cfg, fmt) || 1035 1033 !dpu_plane_is_multirect_capable(prev_pipe->sspp, prev_pipe_cfg, prev_fmt)) 1036 1034 return false;

+19 -4

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c

reviewed

··· 865 865 ARRAY_SIZE(global_state->sspp_to_crtc_id), crtc_id); 866 866 } 867 867 868 868 + static char *dpu_hw_blk_type_name[] = { 869 869 + [DPU_HW_BLK_TOP] = "TOP", 870 870 + [DPU_HW_BLK_SSPP] = "SSPP", 871 871 + [DPU_HW_BLK_LM] = "LM", 872 872 + [DPU_HW_BLK_CTL] = "CTL", 873 873 + [DPU_HW_BLK_PINGPONG] = "pingpong", 874 874 + [DPU_HW_BLK_INTF] = "INTF", 875 875 + [DPU_HW_BLK_WB] = "WB", 876 876 + [DPU_HW_BLK_DSPP] = "DSPP", 877 877 + [DPU_HW_BLK_MERGE_3D] = "merge_3d", 878 878 + [DPU_HW_BLK_DSC] = "DSC", 879 879 + [DPU_HW_BLK_CDM] = "CDM", 880 880 + [DPU_HW_BLK_MAX] = "unknown", 881 881 + }; 882 882 + 868 883 /** 869 884 * dpu_rm_get_assigned_resources - Get hw resources of the given type that are 870 885 * assigned to this encoder ··· 961 946 } 962 947 963 948 if (num_blks == blks_size) { 964 964 - DPU_ERROR("More than %d resources assigned to crtc %d\n", 965 965 - blks_size, crtc_id); 949 949 + DPU_ERROR("More than %d %s assigned to crtc %d\n", 950 950 + blks_size, dpu_hw_blk_type_name[type], crtc_id); 966 951 break; 967 952 } 968 953 if (!hw_blks[i]) { 969 969 - DPU_ERROR("Allocated resource %d unavailable to assign to crtc %d\n", 970 970 - type, crtc_id); 954 954 + DPU_ERROR("%s unavailable to assign to crtc %d\n", 955 955 + dpu_hw_blk_type_name[type], crtc_id); 971 956 break; 972 957 } 973 958 blks[num_blks++] = hw_blks[i];

+3 -7

drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c

reviewed

··· 80 80 static const struct drm_connector_funcs dpu_wb_conn_funcs = { 81 81 .reset = drm_atomic_helper_connector_reset, 82 82 .fill_modes = drm_helper_probe_single_connector_modes, 83 83 - .destroy = drm_connector_cleanup, 84 83 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 85 84 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 86 85 }; ··· 130 131 131 132 drm_connector_helper_add(&dpu_wb_conn->base.base, &dpu_wb_conn_helper_funcs); 132 133 133 133 - /* DPU initializes the encoder and sets it up completely for writeback 134 134 - * cases and hence should use the new API drm_writeback_connector_init_with_encoder 135 135 - * to initialize the writeback connector 136 136 - */ 137 137 - rc = drm_writeback_connector_init_with_encoder(dev, &dpu_wb_conn->base, enc, 138 138 - &dpu_wb_conn_funcs, format_list, num_formats); 134 134 + rc = drmm_writeback_connector_init(dev, &dpu_wb_conn->base, 135 135 + &dpu_wb_conn_funcs, enc, 136 136 + format_list, num_formats); 139 137 140 138 if (!rc) 141 139 dpu_wb_conn->wb_enc = enc;

+6 -23

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

reviewed

··· 391 391 392 392 static int mdp4_kms_init(struct drm_device *dev) 393 393 { 394 394 - struct platform_device *pdev = to_platform_device(dev->dev); 395 394 struct msm_drm_private *priv = dev->dev_private; 396 395 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(priv->kms)); 397 396 struct msm_kms *kms = NULL; 398 398 - struct msm_mmu *mmu; 399 397 struct drm_gpuvm *vm; 400 398 int ret; 401 399 u32 major, minor; ··· 456 458 mdp4_disable(mdp4_kms); 457 459 mdelay(16); 458 460 459 459 - mmu = msm_iommu_new(&pdev->dev, 0); 460 460 - if (IS_ERR(mmu)) { 461 461 - ret = PTR_ERR(mmu); 461 461 + vm = msm_kms_init_vm(mdp4_kms->dev, NULL); 462 462 + if (IS_ERR(vm)) { 463 463 + ret = PTR_ERR(vm); 462 464 goto fail; 463 463 - } else if (!mmu) { 464 464 - DRM_DEV_INFO(dev->dev, "no iommu, fallback to phys " 465 465 - "contig buffers for scanout\n"); 466 466 - vm = NULL; 467 467 - } else { 468 468 - vm = msm_gem_vm_create(dev, mmu, "mdp4", 469 469 - 0x1000, 0x100000000 - 0x1000, 470 470 - true); 471 471 - 472 472 - if (IS_ERR(vm)) { 473 473 - if (!IS_ERR(mmu)) 474 474 - mmu->funcs->destroy(mmu); 475 475 - ret = PTR_ERR(vm); 476 476 - goto fail; 477 477 - } 478 478 - 479 479 - kms->vm = vm; 480 465 } 466 466 + 467 467 + kms->vm = vm; 481 468 482 469 ret = modeset_init(mdp4_kms); 483 470 if (ret) { ··· 512 529 513 530 mdp4_kms = devm_kzalloc(dev, sizeof(*mdp4_kms), GFP_KERNEL); 514 531 if (!mdp4_kms) 515 515 - return dev_err_probe(dev, -ENOMEM, "failed to allocate kms\n"); 532 532 + return -ENOMEM; 516 533 517 534 mdp4_kms->mmio = msm_ioremap(pdev, NULL); 518 535 if (IS_ERR(mdp4_kms->mmio))

+1 -1

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h

reviewed

··· 202 202 } 203 203 #endif 204 204 205 205 - struct clk *mpd4_get_lcdc_clock(struct drm_device *dev); 205 205 + struct clk *mdp4_get_lcdc_clock(struct drm_device *dev); 206 206 207 207 #endif /* __MDP4_KMS_H__ */

+1 -1

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

reviewed

··· 375 375 376 376 drm_encoder_helper_add(encoder, &mdp4_lcdc_encoder_helper_funcs); 377 377 378 378 - mdp4_lcdc_encoder->lcdc_clk = mpd4_get_lcdc_clock(dev); 378 378 + mdp4_lcdc_encoder->lcdc_clk = mdp4_get_lcdc_clock(dev); 379 379 if (IS_ERR(mdp4_lcdc_encoder->lcdc_clk)) { 380 380 DRM_DEV_ERROR(dev->dev, "failed to get lvds_clk\n"); 381 381 return ERR_CAST(mdp4_lcdc_encoder->lcdc_clk);

+25 -22

drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c

reviewed

··· 54 54 return &freqtbl[i-1]; 55 55 } 56 56 57 57 - static int mpd4_lvds_pll_enable(struct clk_hw *hw) 57 57 + static int mdp4_lvds_pll_enable(struct clk_hw *hw) 58 58 { 59 59 struct mdp4_lvds_pll *lvds_pll = to_mdp4_lvds_pll(hw); 60 60 struct mdp4_kms *mdp4_kms = get_kms(lvds_pll); ··· 80 80 return 0; 81 81 } 82 82 83 83 - static void mpd4_lvds_pll_disable(struct clk_hw *hw) 83 83 + static void mdp4_lvds_pll_disable(struct clk_hw *hw) 84 84 { 85 85 struct mdp4_lvds_pll *lvds_pll = to_mdp4_lvds_pll(hw); 86 86 struct mdp4_kms *mdp4_kms = get_kms(lvds_pll); ··· 91 91 mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_CTRL_0, 0x0); 92 92 } 93 93 94 94 - static unsigned long mpd4_lvds_pll_recalc_rate(struct clk_hw *hw, 94 94 + static unsigned long mdp4_lvds_pll_recalc_rate(struct clk_hw *hw, 95 95 unsigned long parent_rate) 96 96 { 97 97 struct mdp4_lvds_pll *lvds_pll = to_mdp4_lvds_pll(hw); 98 98 return lvds_pll->pixclk; 99 99 } 100 100 101 101 - static long mpd4_lvds_pll_round_rate(struct clk_hw *hw, unsigned long rate, 102 102 - unsigned long *parent_rate) 101 101 + static int mdp4_lvds_pll_determine_rate(struct clk_hw *hw, 102 102 + struct clk_rate_request *req) 103 103 { 104 104 - const struct pll_rate *pll_rate = find_rate(rate); 105 105 - return pll_rate->rate; 104 104 + const struct pll_rate *pll_rate = find_rate(req->rate); 105 105 + 106 106 + req->rate = pll_rate->rate; 107 107 + 108 108 + return 0; 106 109 } 107 110 108 108 - static int mpd4_lvds_pll_set_rate(struct clk_hw *hw, unsigned long rate, 111 111 + static int mdp4_lvds_pll_set_rate(struct clk_hw *hw, unsigned long rate, 109 112 unsigned long parent_rate) 110 113 { 111 114 struct mdp4_lvds_pll *lvds_pll = to_mdp4_lvds_pll(hw); ··· 117 114 } 118 115 119 116 120 120 - static const struct clk_ops mpd4_lvds_pll_ops = { 121 121 - .enable = mpd4_lvds_pll_enable, 122 122 - .disable = mpd4_lvds_pll_disable, 123 123 - .recalc_rate = mpd4_lvds_pll_recalc_rate, 124 124 - .round_rate = mpd4_lvds_pll_round_rate, 125 125 - .set_rate = mpd4_lvds_pll_set_rate, 117 117 + static const struct clk_ops mdp4_lvds_pll_ops = { 118 118 + .enable = mdp4_lvds_pll_enable, 119 119 + .disable = mdp4_lvds_pll_disable, 120 120 + .recalc_rate = mdp4_lvds_pll_recalc_rate, 121 121 + .determine_rate = mdp4_lvds_pll_determine_rate, 122 122 + .set_rate = mdp4_lvds_pll_set_rate, 126 123 }; 127 124 128 128 - static const struct clk_parent_data mpd4_lvds_pll_parents[] = { 125 125 + static const struct clk_parent_data mdp4_lvds_pll_parents[] = { 129 126 { .fw_name = "pxo", .name = "pxo", }, 130 127 }; 131 128 132 129 static struct clk_init_data pll_init = { 133 133 - .name = "mpd4_lvds_pll", 134 134 - .ops = &mpd4_lvds_pll_ops, 135 135 - .parent_data = mpd4_lvds_pll_parents, 136 136 - .num_parents = ARRAY_SIZE(mpd4_lvds_pll_parents), 130 130 + .name = "mdp4_lvds_pll", 131 131 + .ops = &mdp4_lvds_pll_ops, 132 132 + .parent_data = mdp4_lvds_pll_parents, 133 133 + .num_parents = ARRAY_SIZE(mdp4_lvds_pll_parents), 137 134 }; 138 135 139 139 - static struct clk_hw *mpd4_lvds_pll_init(struct drm_device *dev) 136 136 + static struct clk_hw *mdp4_lvds_pll_init(struct drm_device *dev) 140 137 { 141 138 struct mdp4_lvds_pll *lvds_pll; 142 139 int ret; ··· 159 156 return &lvds_pll->pll_hw; 160 157 } 161 158 162 162 - struct clk *mpd4_get_lcdc_clock(struct drm_device *dev) 159 159 + struct clk *mdp4_get_lcdc_clock(struct drm_device *dev) 163 160 { 164 161 struct clk_hw *hw; 165 162 struct clk *clk; 166 163 167 164 168 165 /* TODO: do we need different pll in other cases? */ 169 169 - hw = mpd4_lvds_pll_init(dev); 166 166 + hw = mdp4_lvds_pll_init(dev); 170 167 if (IS_ERR(hw)) { 171 168 DRM_DEV_ERROR(dev->dev, "failed to register LVDS PLL\n"); 172 169 return ERR_CAST(hw);

+1 -1

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

reviewed

··· 534 534 } 535 535 mdelay(16); 536 536 537 537 - vm = msm_kms_init_vm(mdp5_kms->dev); 537 537 + vm = msm_kms_init_vm(mdp5_kms->dev, pdev->dev.parent); 538 538 if (IS_ERR(vm)) { 539 539 ret = PTR_ERR(vm); 540 540 goto fail;

+1

drivers/gpu/drm/msm/dsi/phy/dsi_phy.h

reviewed

··· 109 109 struct msm_dsi_dphy_timing timing; 110 110 const struct msm_dsi_phy_cfg *cfg; 111 111 void *tuning_cfg; 112 112 + void *pll_data; 112 113 113 114 enum msm_dsi_phy_usecase usecase; 114 115 bool regulator_ldo_mode;

+7 -9

drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c

reviewed

··· 444 444 return (unsigned long)vco_rate; 445 445 } 446 446 447 447 - static long dsi_pll_10nm_clk_round_rate(struct clk_hw *hw, 448 448 - unsigned long rate, unsigned long *parent_rate) 447 447 + static int dsi_pll_10nm_clk_determine_rate(struct clk_hw *hw, 448 448 + struct clk_rate_request *req) 449 449 { 450 450 struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw); 451 451 452 452 - if (rate < pll_10nm->phy->cfg->min_pll_rate) 453 453 - return pll_10nm->phy->cfg->min_pll_rate; 454 454 - else if (rate > pll_10nm->phy->cfg->max_pll_rate) 455 455 - return pll_10nm->phy->cfg->max_pll_rate; 456 456 - else 457 457 - return rate; 452 452 + req->rate = clamp_t(unsigned long, req->rate, 453 453 + pll_10nm->phy->cfg->min_pll_rate, pll_10nm->phy->cfg->max_pll_rate); 454 454 + 455 455 + return 0; 458 456 } 459 457 460 458 static const struct clk_ops clk_ops_dsi_pll_10nm_vco = { 461 461 - .round_rate = dsi_pll_10nm_clk_round_rate, 459 459 + .determine_rate = dsi_pll_10nm_clk_determine_rate, 462 460 .set_rate = dsi_pll_10nm_vco_set_rate, 463 461 .recalc_rate = dsi_pll_10nm_vco_recalc_rate, 464 462 .prepare = dsi_pll_10nm_vco_prepare,

+17 -17

drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c

reviewed

··· 578 578 pll_14nm->phy->pll_on = false; 579 579 } 580 580 581 581 - static long dsi_pll_14nm_clk_round_rate(struct clk_hw *hw, 582 582 - unsigned long rate, unsigned long *parent_rate) 581 581 + static int dsi_pll_14nm_clk_determine_rate(struct clk_hw *hw, 582 582 + struct clk_rate_request *req) 583 583 { 584 584 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw); 585 585 586 586 - if (rate < pll_14nm->phy->cfg->min_pll_rate) 587 587 - return pll_14nm->phy->cfg->min_pll_rate; 588 588 - else if (rate > pll_14nm->phy->cfg->max_pll_rate) 589 589 - return pll_14nm->phy->cfg->max_pll_rate; 590 590 - else 591 591 - return rate; 586 586 + req->rate = clamp_t(unsigned long, req->rate, 587 587 + pll_14nm->phy->cfg->min_pll_rate, pll_14nm->phy->cfg->max_pll_rate); 588 588 + 589 589 + return 0; 592 590 } 593 591 594 592 static const struct clk_ops clk_ops_dsi_pll_14nm_vco = { 595 595 - .round_rate = dsi_pll_14nm_clk_round_rate, 593 593 + .determine_rate = dsi_pll_14nm_clk_determine_rate, 596 594 .set_rate = dsi_pll_14nm_vco_set_rate, 597 595 .recalc_rate = dsi_pll_14nm_vco_recalc_rate, 598 596 .prepare = dsi_pll_14nm_vco_prepare, ··· 620 622 postdiv->flags, width); 621 623 } 622 624 623 623 - static long dsi_pll_14nm_postdiv_round_rate(struct clk_hw *hw, 624 624 - unsigned long rate, 625 625 - unsigned long *prate) 625 625 + static int dsi_pll_14nm_postdiv_determine_rate(struct clk_hw *hw, 626 626 + struct clk_rate_request *req) 626 627 { 627 628 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); 628 629 struct dsi_pll_14nm *pll_14nm = postdiv->pll; 629 630 630 630 - DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, rate); 631 631 + DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, req->rate); 631 632 632 632 - return divider_round_rate(hw, rate, prate, NULL, 633 633 - postdiv->width, 634 634 - postdiv->flags); 633 633 + req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate, 634 634 + NULL, 635 635 + postdiv->width, 636 636 + postdiv->flags); 637 637 + 638 638 + return 0; 635 639 } 636 640 637 641 static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, ··· 680 680 681 681 static const struct clk_ops clk_ops_dsi_pll_14nm_postdiv = { 682 682 .recalc_rate = dsi_pll_14nm_postdiv_recalc_rate, 683 683 - .round_rate = dsi_pll_14nm_postdiv_round_rate, 683 683 + .determine_rate = dsi_pll_14nm_postdiv_determine_rate, 684 684 .set_rate = dsi_pll_14nm_postdiv_set_rate, 685 685 }; 686 686

+10 -11

drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c

reviewed

··· 533 533 pll_28nm->phy->pll_on = false; 534 534 } 535 535 536 536 - static long dsi_pll_28nm_clk_round_rate(struct clk_hw *hw, 537 537 - unsigned long rate, unsigned long *parent_rate) 536 536 + static int dsi_pll_28nm_clk_determine_rate(struct clk_hw *hw, 537 537 + struct clk_rate_request *req) 538 538 { 539 539 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); 540 540 541 541 - if (rate < pll_28nm->phy->cfg->min_pll_rate) 542 542 - return pll_28nm->phy->cfg->min_pll_rate; 543 543 - else if (rate > pll_28nm->phy->cfg->max_pll_rate) 544 544 - return pll_28nm->phy->cfg->max_pll_rate; 545 545 - else 546 546 - return rate; 541 541 + req->rate = clamp_t(unsigned long, req->rate, 542 542 + pll_28nm->phy->cfg->min_pll_rate, 543 543 + pll_28nm->phy->cfg->max_pll_rate); 544 544 + 545 545 + return 0; 547 546 } 548 547 549 548 static const struct clk_ops clk_ops_dsi_pll_28nm_vco_hpm = { 550 550 - .round_rate = dsi_pll_28nm_clk_round_rate, 549 549 + .determine_rate = dsi_pll_28nm_clk_determine_rate, 551 550 .set_rate = dsi_pll_28nm_clk_set_rate, 552 551 .recalc_rate = dsi_pll_28nm_clk_recalc_rate, 553 552 .prepare = dsi_pll_28nm_vco_prepare_hpm, ··· 555 556 }; 556 557 557 558 static const struct clk_ops clk_ops_dsi_pll_28nm_vco_lp = { 558 558 - .round_rate = dsi_pll_28nm_clk_round_rate, 559 559 + .determine_rate = dsi_pll_28nm_clk_determine_rate, 559 560 .set_rate = dsi_pll_28nm_clk_set_rate, 560 561 .recalc_rate = dsi_pll_28nm_clk_recalc_rate, 561 562 .prepare = dsi_pll_28nm_vco_prepare_lp, ··· 564 565 }; 565 566 566 567 static const struct clk_ops clk_ops_dsi_pll_28nm_vco_8226 = { 567 567 - .round_rate = dsi_pll_28nm_clk_round_rate, 568 568 + .determine_rate = dsi_pll_28nm_clk_determine_rate, 568 569 .set_rate = dsi_pll_28nm_clk_set_rate, 569 570 .recalc_rate = dsi_pll_28nm_clk_recalc_rate, 570 571 .prepare = dsi_pll_28nm_vco_prepare_8226,

+16 -16

drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c

reviewed

··· 231 231 pll_28nm->phy->pll_on = false; 232 232 } 233 233 234 234 - static long dsi_pll_28nm_clk_round_rate(struct clk_hw *hw, 235 235 - unsigned long rate, unsigned long *parent_rate) 234 234 + static int dsi_pll_28nm_clk_determine_rate(struct clk_hw *hw, 235 235 + struct clk_rate_request *req) 236 236 { 237 237 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); 238 238 239 239 - if (rate < pll_28nm->phy->cfg->min_pll_rate) 240 240 - return pll_28nm->phy->cfg->min_pll_rate; 241 241 - else if (rate > pll_28nm->phy->cfg->max_pll_rate) 242 242 - return pll_28nm->phy->cfg->max_pll_rate; 243 243 - else 244 244 - return rate; 239 239 + req->rate = clamp_t(unsigned long, req->rate, 240 240 + pll_28nm->phy->cfg->min_pll_rate, pll_28nm->phy->cfg->max_pll_rate); 241 241 + 242 242 + return 0; 245 243 } 246 244 247 245 static const struct clk_ops clk_ops_dsi_pll_28nm_vco = { 248 248 - .round_rate = dsi_pll_28nm_clk_round_rate, 246 246 + .determine_rate = dsi_pll_28nm_clk_determine_rate, 249 247 .set_rate = dsi_pll_28nm_clk_set_rate, 250 248 .recalc_rate = dsi_pll_28nm_clk_recalc_rate, 251 249 .prepare = dsi_pll_28nm_vco_prepare, ··· 294 296 return 8; 295 297 } 296 298 297 297 - static long clk_bytediv_round_rate(struct clk_hw *hw, unsigned long rate, 298 298 - unsigned long *prate) 299 299 + static int clk_bytediv_determine_rate(struct clk_hw *hw, 300 300 + struct clk_rate_request *req) 299 301 { 300 302 unsigned long best_parent; 301 303 unsigned int factor; 302 304 303 303 - factor = get_vco_mul_factor(rate); 305 305 + factor = get_vco_mul_factor(req->rate); 304 306 305 305 - best_parent = rate * factor; 306 306 - *prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent); 307 307 + best_parent = req->rate * factor; 308 308 + req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent); 307 309 308 308 - return *prate / factor; 310 310 + req->rate = req->best_parent_rate / factor; 311 311 + 312 312 + return 0; 309 313 } 310 314 311 315 static int clk_bytediv_set_rate(struct clk_hw *hw, unsigned long rate, ··· 328 328 329 329 /* Our special byte clock divider ops */ 330 330 static const struct clk_ops clk_bytediv_ops = { 331 331 - .round_rate = clk_bytediv_round_rate, 331 331 + .determine_rate = clk_bytediv_determine_rate, 332 332 .set_rate = clk_bytediv_set_rate, 333 333 .recalc_rate = clk_bytediv_recalc_rate, 334 334 };

+81 -14

drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c

reviewed

··· 90 90 /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG1 register */ 91 91 spinlock_t pclk_mux_lock; 92 92 93 93 + /* 94 94 + * protects REG_DSI_7nm_PHY_CMN_CTRL_0 register and pll_enable_cnt 95 95 + * member 96 96 + */ 97 97 + spinlock_t pll_enable_lock; 98 98 + int pll_enable_cnt; 99 99 + 93 100 struct pll_7nm_cached_state cached_state; 94 101 95 102 struct dsi_pll_7nm *slave; ··· 109 102 * mode, where the master PLL's clk_ops needs access the slave's private data 110 103 */ 111 104 static struct dsi_pll_7nm *pll_7nm_list[DSI_MAX]; 105 105 + 106 106 + static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll); 107 107 + static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll); 112 108 113 109 static void dsi_pll_setup_config(struct dsi_pll_config *config) 114 110 { ··· 350 340 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw); 351 341 struct dsi_pll_config config; 352 342 343 343 + dsi_pll_enable_pll_bias(pll_7nm); 353 344 DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_7nm->phy->id, rate, 354 345 parent_rate); 355 346 ··· 368 357 369 358 dsi_pll_ssc_commit(pll_7nm, &config); 370 359 360 360 + dsi_pll_disable_pll_bias(pll_7nm); 371 361 /* flush, ensure all register writes are done*/ 372 362 wmb(); 373 363 ··· 397 385 398 386 static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll) 399 387 { 400 400 - u32 data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); 388 388 + unsigned long flags; 389 389 + u32 data; 401 390 391 391 + spin_lock_irqsave(&pll->pll_enable_lock, flags); 392 392 + --pll->pll_enable_cnt; 393 393 + if (pll->pll_enable_cnt < 0) { 394 394 + spin_unlock_irqrestore(&pll->pll_enable_lock, flags); 395 395 + DRM_DEV_ERROR_RATELIMITED(&pll->phy->pdev->dev, 396 396 + "bug: imbalance in disabling PLL bias\n"); 397 397 + return; 398 398 + } else if (pll->pll_enable_cnt > 0) { 399 399 + spin_unlock_irqrestore(&pll->pll_enable_lock, flags); 400 400 + return; 401 401 + } /* else: == 0 */ 402 402 + 403 403 + data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); 404 404 + data &= ~DSI_7nm_PHY_CMN_CTRL_0_PLL_SHUTDOWNB; 402 405 writel(0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES); 403 403 - writel(data & ~BIT(5), pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); 406 406 + writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); 407 407 + spin_unlock_irqrestore(&pll->pll_enable_lock, flags); 404 408 ndelay(250); 405 409 } 406 410 407 411 static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll) 408 412 { 409 409 - u32 data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); 413 413 + unsigned long flags; 414 414 + u32 data; 410 415 411 411 - writel(data | BIT(5), pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); 416 416 + spin_lock_irqsave(&pll->pll_enable_lock, flags); 417 417 + if (pll->pll_enable_cnt++) { 418 418 + spin_unlock_irqrestore(&pll->pll_enable_lock, flags); 419 419 + WARN_ON(pll->pll_enable_cnt == INT_MAX); 420 420 + return; 421 421 + } 422 422 + 423 423 + data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); 424 424 + data |= DSI_7nm_PHY_CMN_CTRL_0_PLL_SHUTDOWNB; 425 425 + writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); 426 426 + 412 427 writel(0xc0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES); 428 428 + spin_unlock_irqrestore(&pll->pll_enable_lock, flags); 413 429 ndelay(250); 414 430 } 415 431 ··· 531 491 if (pll_7nm->slave) 532 492 dsi_pll_enable_global_clk(pll_7nm->slave); 533 493 494 494 + writel(0x1, pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL); 495 495 + if (pll_7nm->slave) 496 496 + writel(0x1, pll_7nm->slave->phy->base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL); 497 497 + 534 498 error: 535 499 return rc; 536 500 } ··· 578 534 u32 dec; 579 535 u64 pll_freq, tmp64; 580 536 537 537 + dsi_pll_enable_pll_bias(pll_7nm); 581 538 dec = readl(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1); 582 539 dec &= 0xff; 583 540 ··· 603 558 DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x", 604 559 pll_7nm->phy->id, (unsigned long)vco_rate, dec, frac); 605 560 561 561 + dsi_pll_disable_pll_bias(pll_7nm); 562 562 + 606 563 return (unsigned long)vco_rate; 607 564 } 608 565 609 609 - static long dsi_pll_7nm_clk_round_rate(struct clk_hw *hw, 610 610 - unsigned long rate, unsigned long *parent_rate) 566 566 + static int dsi_pll_7nm_clk_determine_rate(struct clk_hw *hw, 567 567 + struct clk_rate_request *req) 611 568 { 612 569 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw); 613 570 614 614 - if (rate < pll_7nm->phy->cfg->min_pll_rate) 615 615 - return pll_7nm->phy->cfg->min_pll_rate; 616 616 - else if (rate > pll_7nm->phy->cfg->max_pll_rate) 617 617 - return pll_7nm->phy->cfg->max_pll_rate; 618 618 - else 619 619 - return rate; 571 571 + req->rate = clamp_t(unsigned long, req->rate, 572 572 + pll_7nm->phy->cfg->min_pll_rate, pll_7nm->phy->cfg->max_pll_rate); 573 573 + 574 574 + return 0; 620 575 } 621 576 622 577 static const struct clk_ops clk_ops_dsi_pll_7nm_vco = { 623 623 - .round_rate = dsi_pll_7nm_clk_round_rate, 578 578 + .determine_rate = dsi_pll_7nm_clk_determine_rate, 624 579 .set_rate = dsi_pll_7nm_vco_set_rate, 625 580 .recalc_rate = dsi_pll_7nm_vco_recalc_rate, 626 581 .prepare = dsi_pll_7nm_vco_prepare, ··· 638 593 void __iomem *phy_base = pll_7nm->phy->base; 639 594 u32 cmn_clk_cfg0, cmn_clk_cfg1; 640 595 596 596 + dsi_pll_enable_pll_bias(pll_7nm); 641 597 cached->pll_out_div = readl(pll_7nm->phy->pll_base + 642 598 REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE); 643 599 cached->pll_out_div &= 0x3; ··· 650 604 cmn_clk_cfg1 = readl(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); 651 605 cached->pll_mux = FIELD_GET(DSI_7nm_PHY_CMN_CLK_CFG1_DSICLK_SEL__MASK, cmn_clk_cfg1); 652 606 607 607 + dsi_pll_disable_pll_bias(pll_7nm); 653 608 DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x", 654 609 pll_7nm->phy->id, cached->pll_out_div, cached->bit_clk_div, 655 610 cached->pix_clk_div, cached->pll_mux); ··· 873 826 874 827 spin_lock_init(&pll_7nm->postdiv_lock); 875 828 spin_lock_init(&pll_7nm->pclk_mux_lock); 829 829 + spin_lock_init(&pll_7nm->pll_enable_lock); 876 830 877 831 pll_7nm->phy = phy; 832 832 + phy->pll_data = pll_7nm; 878 833 879 834 ret = pll_7nm_register(pll_7nm, phy->provided_clocks->hws); 880 835 if (ret) { ··· 888 839 889 840 /* TODO: Remove this when we have proper display handover support */ 890 841 msm_dsi_phy_pll_save_state(phy); 842 842 + /* 843 843 + * Store also proper vco_current_rate, because its value will be used in 844 844 + * dsi_7nm_pll_restore_state(). 845 845 + */ 846 846 + if (!dsi_pll_7nm_vco_recalc_rate(&pll_7nm->clk_hw, VCO_REF_CLK_RATE)) 847 847 + pll_7nm->vco_current_rate = pll_7nm->phy->cfg->min_pll_rate; 891 848 892 849 return 0; 893 850 } ··· 965 910 u32 const delay_us = 5; 966 911 u32 const timeout_us = 1000; 967 912 struct msm_dsi_dphy_timing *timing = &phy->timing; 913 913 + struct dsi_pll_7nm *pll = phy->pll_data; 968 914 void __iomem *base = phy->base; 969 915 bool less_than_1500_mhz; 916 916 + unsigned long flags; 970 917 u32 vreg_ctrl_0, vreg_ctrl_1, lane_ctrl0; 971 918 u32 glbl_pemph_ctrl_0; 972 919 u32 glbl_str_swi_cal_sel_ctrl, glbl_hstx_str_ctrl_0; ··· 1090 1033 glbl_rescode_bot_ctrl = 0x3c; 1091 1034 } 1092 1035 1036 1036 + spin_lock_irqsave(&pll->pll_enable_lock, flags); 1037 1037 + pll->pll_enable_cnt = 1; 1093 1038 /* de-assert digital and pll power down */ 1094 1094 - data = BIT(6) | BIT(5); 1039 1039 + data = DSI_7nm_PHY_CMN_CTRL_0_DIGTOP_PWRDN_B | 1040 1040 + DSI_7nm_PHY_CMN_CTRL_0_PLL_SHUTDOWNB; 1095 1041 writel(data, base + REG_DSI_7nm_PHY_CMN_CTRL_0); 1042 1042 + spin_unlock_irqrestore(&pll->pll_enable_lock, flags); 1096 1043 1097 1044 /* Assert PLL core reset */ 1098 1045 writel(0x00, base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL); ··· 1209 1148 1210 1149 static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy) 1211 1150 { 1151 1151 + struct dsi_pll_7nm *pll = phy->pll_data; 1212 1152 void __iomem *base = phy->base; 1153 1153 + unsigned long flags; 1213 1154 u32 data; 1214 1155 1215 1156 DBG(""); ··· 1238 1175 writel(data, base + REG_DSI_7nm_PHY_CMN_CTRL_0); 1239 1176 writel(0, base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0); 1240 1177 1178 1178 + spin_lock_irqsave(&pll->pll_enable_lock, flags); 1179 1179 + pll->pll_enable_cnt = 0; 1241 1180 /* Turn off all PHY blocks */ 1242 1181 writel(0x00, base + REG_DSI_7nm_PHY_CMN_CTRL_0); 1182 1182 + spin_unlock_irqrestore(&pll->pll_enable_lock, flags); 1183 1183 + 1243 1184 /* make sure phy is turned off */ 1244 1185 wmb(); 1245 1186

+6 -10

drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c

reviewed

··· 629 629 return 0; 630 630 } 631 631 632 632 - static long hdmi_8996_pll_round_rate(struct clk_hw *hw, 633 633 - unsigned long rate, 634 634 - unsigned long *parent_rate) 632 632 + static int hdmi_8996_pll_determine_rate(struct clk_hw *hw, 633 633 + struct clk_rate_request *req) 635 634 { 636 636 - if (rate < HDMI_PCLK_MIN_FREQ) 637 637 - return HDMI_PCLK_MIN_FREQ; 638 638 - else if (rate > HDMI_PCLK_MAX_FREQ) 639 639 - return HDMI_PCLK_MAX_FREQ; 640 640 - else 641 641 - return rate; 635 635 + req->rate = clamp_t(unsigned long, req->rate, HDMI_PCLK_MIN_FREQ, HDMI_PCLK_MAX_FREQ); 636 636 + 637 637 + return 0; 642 638 } 643 639 644 640 static unsigned long hdmi_8996_pll_recalc_rate(struct clk_hw *hw, ··· 680 684 681 685 static const struct clk_ops hdmi_8996_pll_ops = { 682 686 .set_rate = hdmi_8996_pll_set_clk_rate, 683 683 - .round_rate = hdmi_8996_pll_round_rate, 687 687 + .determine_rate = hdmi_8996_pll_determine_rate, 684 688 .recalc_rate = hdmi_8996_pll_recalc_rate, 685 689 .prepare = hdmi_8996_pll_prepare, 686 690 .unprepare = hdmi_8996_pll_unprepare,

+6 -10

drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c

reviewed

··· 646 646 return 0; 647 647 } 648 648 649 649 - static long hdmi_8998_pll_round_rate(struct clk_hw *hw, 650 650 - unsigned long rate, 651 651 - unsigned long *parent_rate) 649 649 + static int hdmi_8998_pll_determine_rate(struct clk_hw *hw, 650 650 + struct clk_rate_request *req) 652 651 { 653 653 - if (rate < HDMI_PCLK_MIN_FREQ) 654 654 - return HDMI_PCLK_MIN_FREQ; 655 655 - else if (rate > HDMI_PCLK_MAX_FREQ) 656 656 - return HDMI_PCLK_MAX_FREQ; 657 657 - else 658 658 - return rate; 652 652 + req->rate = clamp_t(unsigned long, req->rate, HDMI_PCLK_MIN_FREQ, HDMI_PCLK_MAX_FREQ); 653 653 + 654 654 + return 0; 659 655 } 660 656 661 657 static unsigned long hdmi_8998_pll_recalc_rate(struct clk_hw *hw, ··· 684 688 685 689 static const struct clk_ops hdmi_8998_pll_ops = { 686 690 .set_rate = hdmi_8998_pll_set_clk_rate, 687 687 - .round_rate = hdmi_8998_pll_round_rate, 691 691 + .determine_rate = hdmi_8998_pll_determine_rate, 688 692 .recalc_rate = hdmi_8998_pll_recalc_rate, 689 693 .prepare = hdmi_8998_pll_prepare, 690 694 .unprepare = hdmi_8998_pll_unprepare,

+7 -5

drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c

reviewed

··· 373 373 return pll->pixclk; 374 374 } 375 375 376 376 - static long hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate, 377 377 - unsigned long *parent_rate) 376 376 + static int hdmi_pll_determine_rate(struct clk_hw *hw, 377 377 + struct clk_rate_request *req) 378 378 { 379 379 - const struct pll_rate *pll_rate = find_rate(rate); 379 379 + const struct pll_rate *pll_rate = find_rate(req->rate); 380 380 381 381 - return pll_rate->rate; 381 381 + req->rate = pll_rate->rate; 382 382 + 383 383 + return 0; 382 384 } 383 385 384 386 static int hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, ··· 404 402 .enable = hdmi_pll_enable, 405 403 .disable = hdmi_pll_disable, 406 404 .recalc_rate = hdmi_pll_recalc_rate, 407 407 - .round_rate = hdmi_pll_round_rate, 405 405 + .determine_rate = hdmi_pll_determine_rate, 408 406 .set_rate = hdmi_pll_set_rate, 409 407 }; 410 408

+1

drivers/gpu/drm/msm/msm_drv.c

reviewed

··· 826 826 827 827 #define DRIVER_FEATURES_KMS ( \ 828 828 DRIVER_GEM | \ 829 829 + DRIVER_GEM_GPUVA | \ 829 830 DRIVER_ATOMIC | \ 830 831 DRIVER_MODESET | \ 831 832 0 )

+1 -1

drivers/gpu/drm/msm/msm_drv.h

reviewed

··· 229 229 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); 230 230 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu); 231 231 232 232 - struct drm_gpuvm *msm_kms_init_vm(struct drm_device *dev); 232 232 + struct drm_gpuvm *msm_kms_init_vm(struct drm_device *dev, struct device *mdss_dev); 233 233 bool msm_use_mmu(struct drm_device *dev); 234 234 235 235 int msm_ioctl_gem_submit(struct drm_device *dev, void *data,

+10 -11

drivers/gpu/drm/msm/msm_gem.c

reviewed

··· 191 191 if (!msm_obj->pages) { 192 192 struct drm_device *dev = obj->dev; 193 193 struct page **p; 194 194 - int npages = obj->size >> PAGE_SHIFT; 194 194 + size_t npages = obj->size >> PAGE_SHIFT; 195 195 196 196 p = drm_gem_get_pages(obj); 197 197 ··· 1148 1148 1149 1149 /* convenience method to construct a GEM buffer object, and userspace handle */ 1150 1150 int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file, 1151 1151 - uint32_t size, uint32_t flags, uint32_t *handle, 1151 1151 + size_t size, uint32_t flags, uint32_t *handle, 1152 1152 char *name) 1153 1153 { 1154 1154 struct drm_gem_object *obj; ··· 1214 1214 .vm_ops = &vm_ops, 1215 1215 }; 1216 1216 1217 1217 - static int msm_gem_new_impl(struct drm_device *dev, 1218 1218 - uint32_t size, uint32_t flags, 1219 1219 - struct drm_gem_object **obj) 1217 1217 + static int msm_gem_new_impl(struct drm_device *dev, uint32_t flags, 1218 1218 + struct drm_gem_object **obj) 1220 1219 { 1221 1220 struct msm_drm_private *priv = dev->dev_private; 1222 1221 struct msm_gem_object *msm_obj; ··· 1249 1250 return 0; 1250 1251 } 1251 1252 1252 1252 - struct drm_gem_object *msm_gem_new(struct drm_device *dev, uint32_t size, uint32_t flags) 1253 1253 + struct drm_gem_object *msm_gem_new(struct drm_device *dev, size_t size, uint32_t flags) 1253 1254 { 1254 1255 struct msm_drm_private *priv = dev->dev_private; 1255 1256 struct msm_gem_object *msm_obj; ··· 1264 1265 if (size == 0) 1265 1266 return ERR_PTR(-EINVAL); 1266 1267 1267 1267 - ret = msm_gem_new_impl(dev, size, flags, &obj); 1268 1268 + ret = msm_gem_new_impl(dev, flags, &obj); 1268 1269 if (ret) 1269 1270 return ERR_PTR(ret); 1270 1271 ··· 1304 1305 struct msm_drm_private *priv = dev->dev_private; 1305 1306 struct msm_gem_object *msm_obj; 1306 1307 struct drm_gem_object *obj; 1307 1307 - uint32_t size; 1308 1308 - int ret, npages; 1308 1308 + size_t size, npages; 1309 1309 + int ret; 1309 1310 1310 1311 size = PAGE_ALIGN(dmabuf->size); 1311 1312 1312 1312 - ret = msm_gem_new_impl(dev, size, MSM_BO_WC, &obj); 1313 1313 + ret = msm_gem_new_impl(dev, MSM_BO_WC, &obj); 1313 1314 if (ret) 1314 1315 return ERR_PTR(ret); 1315 1316 ··· 1352 1353 return ERR_PTR(ret); 1353 1354 } 1354 1355 1355 1355 - void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size, uint32_t flags, 1356 1356 + void *msm_gem_kernel_new(struct drm_device *dev, size_t size, uint32_t flags, 1356 1357 struct drm_gpuvm *vm, struct drm_gem_object **bo, 1357 1358 uint64_t *iova) 1358 1359 {

+3 -3

drivers/gpu/drm/msm/msm_gem.h

reviewed

··· 297 297 int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout); 298 298 int msm_gem_cpu_fini(struct drm_gem_object *obj); 299 299 int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file, 300 300 - uint32_t size, uint32_t flags, uint32_t *handle, char *name); 300 300 + size_t size, uint32_t flags, uint32_t *handle, char *name); 301 301 struct drm_gem_object *msm_gem_new(struct drm_device *dev, 302 302 - uint32_t size, uint32_t flags); 303 303 - void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size, uint32_t flags, 302 302 + size_t size, uint32_t flags); 303 303 + void *msm_gem_kernel_new(struct drm_device *dev, size_t size, uint32_t flags, 304 304 struct drm_gpuvm *vm, struct drm_gem_object **bo, 305 305 uint64_t *iova); 306 306 void msm_gem_kernel_put(struct drm_gem_object *bo, struct drm_gpuvm *vm);

+1 -1

drivers/gpu/drm/msm/msm_gem_prime.c

reviewed

··· 15 15 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj) 16 16 { 17 17 struct msm_gem_object *msm_obj = to_msm_bo(obj); 18 18 - int npages = obj->size >> PAGE_SHIFT; 18 18 + size_t npages = obj->size >> PAGE_SHIFT; 19 19 20 20 if (msm_obj->flags & MSM_BO_NO_SHARE) 21 21 return ERR_PTR(-EINVAL);

+25 -6

drivers/gpu/drm/msm/msm_gem_vma.c

reviewed

··· 1030 1030 struct drm_device *dev = job->vm->drm; 1031 1031 int ret = 0; 1032 1032 int cnt = 0; 1033 1033 + int i = -1; 1033 1034 1034 1035 if (args->nr_ops == 1) { 1035 1036 /* Single op case, the op is inlined: */ ··· 1064 1063 1065 1064 spin_lock(&file->table_lock); 1066 1065 1067 1067 - for (unsigned i = 0; i < args->nr_ops; i++) { 1066 1066 + for (i = 0; i < args->nr_ops; i++) { 1067 1067 + struct msm_vm_bind_op *op = &job->ops[i]; 1068 1068 struct drm_gem_object *obj; 1069 1069 1070 1070 - if (!job->ops[i].handle) { 1071 1071 - job->ops[i].obj = NULL; 1070 1070 + if (!op->handle) { 1071 1071 + op->obj = NULL; 1072 1072 continue; 1073 1073 } 1074 1074 ··· 1077 1075 * normally use drm_gem_object_lookup(), but for bulk lookup 1078 1076 * all under single table_lock just hit object_idr directly: 1079 1077 */ 1080 1080 - obj = idr_find(&file->object_idr, job->ops[i].handle); 1078 1078 + obj = idr_find(&file->object_idr, op->handle); 1081 1079 if (!obj) { 1082 1082 - ret = UERR(EINVAL, dev, "invalid handle %u at index %u\n", job->ops[i].handle, i); 1080 1080 + ret = UERR(EINVAL, dev, "invalid handle %u at index %u\n", op->handle, i); 1083 1081 goto out_unlock; 1084 1082 } 1085 1083 1086 1084 drm_gem_object_get(obj); 1087 1085 1088 1088 - job->ops[i].obj = obj; 1086 1086 + op->obj = obj; 1089 1087 cnt++; 1088 1088 + 1089 1089 + if ((op->range + op->obj_offset) > obj->size) { 1090 1090 + ret = UERR(EINVAL, dev, "invalid range: %016llx + %016llx > %016zx\n", 1091 1091 + op->range, op->obj_offset, obj->size); 1092 1092 + goto out_unlock; 1093 1093 + } 1090 1094 } 1091 1095 1092 1096 *nr_bos = cnt; ··· 1100 1092 out_unlock: 1101 1093 spin_unlock(&file->table_lock); 1102 1094 1095 1095 + if (ret) { 1096 1096 + for (; i >= 0; i--) { 1097 1097 + struct msm_vm_bind_op *op = &job->ops[i]; 1098 1098 + 1099 1099 + if (!op->obj) 1100 1100 + continue; 1101 1101 + 1102 1102 + drm_gem_object_put(op->obj); 1103 1103 + op->obj = NULL; 1104 1104 + } 1105 1105 + } 1103 1106 out: 1104 1107 return ret; 1105 1108 }

+1 -1

drivers/gpu/drm/msm/msm_gpu.c

reviewed

··· 304 304 sizeof(struct msm_gpu_state_bo), GFP_KERNEL); 305 305 306 306 for (int i = 0; state->bos && i < submit->nr_bos; i++) { 307 307 - struct drm_gem_object *obj = submit->bos[i].obj;; 307 307 + struct drm_gem_object *obj = submit->bos[i].obj; 308 308 bool dump = rd_full || (submit->bos[i].flags & MSM_SUBMIT_BO_DUMP); 309 309 310 310 msm_gem_lock(obj);

+9

drivers/gpu/drm/msm/msm_gpu.h

reviewed

··· 16 16 17 17 #include "msm_drv.h" 18 18 #include "msm_fence.h" 19 19 + #include "msm_gpu_trace.h" 19 20 #include "msm_ringbuffer.h" 20 21 #include "msm_gem.h" 21 22 ··· 92 91 * for cmdstream that is buffered in this FIFO upstream of the CP fw. 93 92 */ 94 93 bool (*progress)(struct msm_gpu *gpu, struct msm_ringbuffer *ring); 94 94 + void (*sysprof_setup)(struct msm_gpu *gpu); 95 95 }; 96 96 97 97 /* Additional state for iommu faults: */ ··· 615 613 616 614 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data) 617 615 { 616 616 + trace_msm_gpu_regaccess(reg); 618 617 writel(data, gpu->mmio + (reg << 2)); 619 618 } 620 619 621 620 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg) 622 621 { 622 622 + trace_msm_gpu_regaccess(reg); 623 623 return readl(gpu->mmio + (reg << 2)); 624 624 } 625 625 626 626 static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or) 627 627 { 628 628 + trace_msm_gpu_regaccess(reg); 628 629 msm_rmw(gpu->mmio + (reg << 2), mask, or); 629 630 } 630 631 ··· 649 644 * when the lo is read, so make sure to read the lo first to trigger 650 645 * that 651 646 */ 647 647 + trace_msm_gpu_regaccess(reg); 652 648 val = (u64) readl(gpu->mmio + (reg << 2)); 649 649 + trace_msm_gpu_regaccess(reg+1); 653 650 val |= ((u64) readl(gpu->mmio + ((reg + 1) << 2)) << 32); 654 651 655 652 return val; ··· 659 652 660 653 static inline void gpu_write64(struct msm_gpu *gpu, u32 reg, u64 val) 661 654 { 655 655 + trace_msm_gpu_regaccess(reg); 662 656 /* Why not a writeq here? Read the screed above */ 663 657 writel(lower_32_bits(val), gpu->mmio + (reg << 2)); 658 658 + trace_msm_gpu_regaccess(reg+1); 664 659 writel(upper_32_bits(val), gpu->mmio + ((reg + 1) << 2)); 665 660 } 666 661

+12

drivers/gpu/drm/msm/msm_gpu_trace.h

reviewed

··· 219 219 TP_printk("count=%u, remaining=%u", __entry->count, __entry->remaining) 220 220 ); 221 221 222 222 + TRACE_EVENT(msm_gpu_regaccess, 223 223 + TP_PROTO(u32 offset), 224 224 + TP_ARGS(offset), 225 225 + TP_STRUCT__entry( 226 226 + __field(u32, offset) 227 227 + ), 228 228 + TP_fast_assign( 229 229 + __entry->offset = offset; 230 230 + ), 231 231 + TP_printk("offset=0x%x", __entry->offset) 232 232 + ); 233 233 + 222 234 #endif 223 235 224 236 #undef TRACE_INCLUDE_PATH

+4 -4

drivers/gpu/drm/msm/msm_iommu.c

reviewed

··· 721 721 int ret; 722 722 723 723 if (!device_iommu_mapped(dev)) 724 724 - return NULL; 724 724 + return ERR_PTR(-ENODEV); 725 725 726 726 domain = iommu_paging_domain_alloc(dev); 727 727 if (IS_ERR(domain)) ··· 756 756 struct msm_mmu *mmu; 757 757 758 758 mmu = msm_iommu_new(dev, quirks); 759 759 - if (IS_ERR_OR_NULL(mmu)) 759 759 + if (IS_ERR(mmu)) 760 760 return mmu; 761 761 762 762 iommu = to_msm_iommu(mmu); ··· 772 772 struct msm_mmu *mmu; 773 773 774 774 mmu = msm_iommu_new(dev, quirks); 775 775 - if (IS_ERR_OR_NULL(mmu)) 775 775 + if (IS_ERR(mmu)) 776 776 return mmu; 777 777 778 778 iommu = to_msm_iommu(mmu); 779 779 - if (adreno_smmu && adreno_smmu->cookie) { 779 779 + if (adreno_smmu->cookie) { 780 780 const struct io_pgtable_cfg *cfg = 781 781 adreno_smmu->get_ttbr1_cfg(adreno_smmu->cookie); 782 782 size_t tblsz = get_tblsz(cfg);

+6 -8

drivers/gpu/drm/msm/msm_kms.c

reviewed

··· 177 177 return -ENOSYS; 178 178 } 179 179 180 180 - struct drm_gpuvm *msm_kms_init_vm(struct drm_device *dev) 180 180 + struct drm_gpuvm *msm_kms_init_vm(struct drm_device *dev, struct device *mdss_dev) 181 181 { 182 182 struct drm_gpuvm *vm; 183 183 struct msm_mmu *mmu; 184 184 struct device *mdp_dev = dev->dev; 185 185 - struct device *mdss_dev = mdp_dev->parent; 186 185 struct msm_drm_private *priv = dev->dev_private; 187 186 struct msm_kms *kms = priv->kms; 188 187 struct device *iommu_dev; ··· 192 193 */ 193 194 if (device_iommu_mapped(mdp_dev)) 194 195 iommu_dev = mdp_dev; 195 195 - else 196 196 + else if (mdss_dev && device_iommu_mapped(mdss_dev)) 196 197 iommu_dev = mdss_dev; 198 198 + else { 199 199 + drm_info(dev, "no IOMMU, bailing out\n"); 200 200 + return ERR_PTR(-ENODEV); 201 201 + } 197 202 198 203 mmu = msm_iommu_disp_new(iommu_dev, 0); 199 204 if (IS_ERR(mmu)) 200 205 return ERR_CAST(mmu); 201 201 - 202 202 - if (!mmu) { 203 203 - drm_info(dev, "no IOMMU, fallback to phys contig buffers for scanout\n"); 204 204 - return NULL; 205 205 - } 206 206 207 207 vm = msm_gem_vm_create(dev, mmu, "mdp_kms", 208 208 0x1000, 0x100000000 - 0x1000, true);

+1 -2

drivers/gpu/drm/msm/msm_mdss.c

reviewed

··· 154 154 155 155 dev = msm_mdss->dev; 156 156 157 157 - domain = irq_domain_create_linear(of_fwnode_handle(dev->of_node), 32, 158 158 - &msm_mdss_irqdomain_ops, msm_mdss); 157 157 + domain = irq_domain_create_linear(dev_fwnode(dev), 32, &msm_mdss_irqdomain_ops, msm_mdss); 159 158 if (!domain) { 160 159 dev_err(dev, "failed to add irq_domain\n"); 161 160 return -EINVAL;

+4

drivers/gpu/drm/msm/msm_submitqueue.c

reviewed

··· 40 40 break; 41 41 } 42 42 43 43 + /* Some gpu families require additional setup for sysprof */ 44 44 + if (gpu->funcs->sysprof_setup) 45 45 + gpu->funcs->sysprof_setup(gpu); 46 46 + 43 47 ctx->sysprof = sysprof; 44 48 45 49 return 0;

+416 -310

drivers/gpu/drm/msm/registers/adreno/a6xx.xml

reviewed

··· 814 814 <bitfield name="Y" low="16" high="29" type="uint"/> 815 815 </bitset> 816 816 817 817 - <reg32 offset="0x8000" name="GRAS_CL_CNTL" usage="rp_blit"> 817 817 + <bitset name="a6xx_gras_cl_cntl" inline="yes"> 818 818 <bitfield name="CLIP_DISABLE" pos="0" type="boolean"/> 819 819 <bitfield name="ZNEAR_CLIP_DISABLE" pos="1" type="boolean"/> 820 820 <bitfield name="ZFAR_CLIP_DISABLE" pos="2" type="boolean"/> ··· 826 826 <bitfield name="VP_CLIP_CODE_IGNORE" pos="7" type="boolean"/> 827 827 <bitfield name="VP_XFORM_DISABLE" pos="8" type="boolean"/> 828 828 <bitfield name="PERSP_DIVISION_DISABLE" pos="9" type="boolean"/> 829 829 - </reg32> 829 829 + </bitset> 830 830 + 831 831 + <reg32 offset="0x8000" name="GRAS_CL_CNTL" type="a6xx_gras_cl_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 830 832 831 833 <bitset name="a6xx_gras_xs_clip_cull_distance" inline="yes"> 832 834 <bitfield name="CLIP_MASK" low="0" high="7"/> 833 835 <bitfield name="CULL_MASK" low="8" high="15"/> 834 836 </bitset> 835 835 - <reg32 offset="0x8001" name="GRAS_CL_VS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit"/> 836 836 - <reg32 offset="0x8002" name="GRAS_CL_DS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit"/> 837 837 - <reg32 offset="0x8003" name="GRAS_CL_GS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit"/> 838 838 - <reg32 offset="0x8004" name="GRAS_CL_ARRAY_SIZE" low="0" high="10" type="uint" usage="rp_blit"/> 837 837 + <reg32 offset="0x8001" name="GRAS_CL_VS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit" variants="A6XX-A7XX" /> 838 838 + <reg32 offset="0x8002" name="GRAS_CL_DS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit" variants="A6XX-A7XX" /> 839 839 + <reg32 offset="0x8003" name="GRAS_CL_GS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit" variants="A6XX-A7XX" /> 840 840 + <reg32 offset="0x8004" name="GRAS_CL_ARRAY_SIZE" low="0" high="10" type="uint" usage="rp_blit" variants="A6XX-A7XX" /> 839 841 840 840 - <reg32 offset="0x8005" name="GRAS_CL_INTERP_CNTL" usage="rp_blit"> 842 842 + <bitset name="a6xx_gras_cl_interp_cntl" inline="yes"> 841 843 <!-- see also RB_INTERP_CNTL --> 842 844 <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/> 843 845 <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/> ··· 850 848 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/> 851 849 <bitfield name="UNK10" pos="10" type="boolean" variants="A7XX-"/> 852 850 <bitfield name="UNK11" pos="11" type="boolean" variants="A7XX-"/> 853 853 - </reg32> 854 854 - <reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ" usage="rp_blit"> 851 851 + </bitset> 852 852 + 853 853 + <reg32 offset="0x8005" name="GRAS_CL_INTERP_CNTL" type="a6xx_gras_cl_interp_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 854 854 + 855 855 + <bitset name="a6xx_gras_cl_guardband_clip_adj" inline="true"> 855 856 <bitfield name="HORZ" low="0" high="8" type="uint"/> 856 857 <bitfield name="VERT" low="10" high="18" type="uint"/> 857 857 - </reg32> 858 858 + </bitset> 859 859 + 860 860 + <reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ" type="a6xx_gras_cl_guardband_clip_adj" variants="A6XX-A7XX" usage="rp_blit"/> 858 861 859 862 <!-- Something connected to depth-stencil attachment size --> 860 863 <reg32 offset="0x8007" name="GRAS_UNKNOWN_8007" variants="A7XX-" usage="rp_blit"/> 861 864 862 862 - <reg32 offset="0x8008" name="GRAS_UNKNOWN_8008" variants="A7XX-" usage="cmd"/> 865 865 + <!-- the scale/offset is per view, with up to 6 views --> 866 866 + <bitset name="a6xx_gras_bin_foveat" inline="yes"> 867 867 + <bitfield name="BINSCALEEN" pos="6" type="boolean"/> 868 868 + <enum name="a7xx_bin_scale"> 869 869 + <value value="0" name="NOSCALE"/> 870 870 + <value value="1" name="SCALE2X"/> 871 871 + <value value="2" name="SCALE4X"/> 872 872 + </enum> 873 873 + <bitfield name="XSCALE_0" low="8" high="9" type="a7xx_bin_scale"/> 874 874 + <bitfield name="YSCALE_0" low="10" high="11" type="a7xx_bin_scale"/> 875 875 + <bitfield name="XSCALE_1" low="12" high="13" type="a7xx_bin_scale"/> 876 876 + <bitfield name="YSCALE_1" low="14" high="15" type="a7xx_bin_scale"/> 877 877 + <bitfield name="XSCALE_2" low="16" high="17" type="a7xx_bin_scale"/> 878 878 + <bitfield name="YSCALE_2" low="18" high="19" type="a7xx_bin_scale"/> 879 879 + <bitfield name="XSCALE_3" low="20" high="21" type="a7xx_bin_scale"/> 880 880 + <bitfield name="YSCALE_3" low="22" high="23" type="a7xx_bin_scale"/> 881 881 + <bitfield name="XSCALE_4" low="24" high="25" type="a7xx_bin_scale"/> 882 882 + <bitfield name="YSCALE_4" low="26" high="27" type="a7xx_bin_scale"/> 883 883 + <bitfield name="XSCALE_5" low="28" high="29" type="a7xx_bin_scale"/> 884 884 + <bitfield name="YSCALE_5" low="30" high="31" type="a7xx_bin_scale"/> 885 885 + </bitset> 863 886 864 864 - <reg32 offset="0x8009" name="GRAS_UNKNOWN_8009" variants="A7XX-" usage="cmd"/> 865 865 - <reg32 offset="0x800a" name="GRAS_UNKNOWN_800A" variants="A7XX-" usage="cmd"/> 866 866 - <reg32 offset="0x800b" name="GRAS_UNKNOWN_800B" variants="A7XX-" usage="cmd"/> 867 867 - <reg32 offset="0x800c" name="GRAS_UNKNOWN_800C" variants="A7XX-" usage="cmd"/> 887 887 + <reg32 offset="0x8008" name="GRAS_BIN_FOVEAT" type="a6xx_gras_bin_foveat" variants="A7XX" usage="cmd"/> 888 888 + 889 889 + <reg32 offset="0x8009" name="GRAS_BIN_FOVEAT_OFFSET_0" variants="A7XX-" usage="cmd"> 890 890 + <bitfield name="XOFFSET_0" low="0" high="9" shr="2" type="uint"/> 891 891 + <bitfield name="XOFFSET_1" low="10" high="19" shr="2" type="uint"/> 892 892 + <bitfield name="XOFFSET_2" low="20" high="29" shr="2" type="uint"/> 893 893 + </reg32> 894 894 + <reg32 offset="0x800a" name="GRAS_BIN_FOVEAT_OFFSET_1" variants="A7XX-" usage="cmd"> 895 895 + <bitfield name="XOFFSET_3" low="0" high="9" shr="2" type="uint"/> 896 896 + <bitfield name="XOFFSET_4" low="10" high="19" shr="2" type="uint"/> 897 897 + <bitfield name="XOFFSET_5" low="20" high="29" shr="2" type="uint"/> 898 898 + </reg32> 899 899 + <reg32 offset="0x800b" name="GRAS_BIN_FOVEAT_OFFSET_2" variants="A7XX-" usage="cmd"> 900 900 + <bitfield name="YOFFSET_0" low="0" high="9" shr="2" type="uint"/> 901 901 + <bitfield name="YOFFSET_1" low="10" high="19" shr="2" type="uint"/> 902 902 + <bitfield name="YOFFSET_2" low="20" high="29" shr="2" type="uint"/> 903 903 + </reg32> 904 904 + <reg32 offset="0x800c" name="GRAS_BIN_FOVEAT_OFFSET_3" variants="A7XX-" usage="cmd"> 905 905 + <bitfield name="YOFFSET_3" low="0" high="9" shr="2" type="uint"/> 906 906 + <bitfield name="YOFFSET_4" low="10" high="19" shr="2" type="uint"/> 907 907 + <bitfield name="YOFFSET_5" low="20" high="29" shr="2" type="uint"/> 908 908 + </reg32> 868 909 869 910 <!-- <reg32 offset="0x80f0" name="GRAS_UNKNOWN_80F0" type="a6xx_reg_xy"/> --> 870 911 871 912 <!-- 0x8006-0x800f invalid --> 872 872 - <array offset="0x8010" name="GRAS_CL_VIEWPORT" stride="6" length="16" usage="rp_blit"> 913 913 + <array offset="0x8010" name="GRAS_CL_VIEWPORT" stride="6" length="16" variants="A6XX-A7XX" usage="rp_blit"> 873 914 <reg32 offset="0" name="XOFFSET" type="float"/> 874 915 <reg32 offset="1" name="XSCALE" type="float"/> 875 916 <reg32 offset="2" name="YOFFSET" type="float"/> ··· 920 875 <reg32 offset="4" name="ZOFFSET" type="float"/> 921 876 <reg32 offset="5" name="ZSCALE" type="float"/> 922 877 </array> 923 923 - <array offset="0x8070" name="GRAS_CL_VIEWPORT_ZCLAMP" stride="2" length="16" usage="rp_blit"> 878 878 + 879 879 + <array offset="0x8070" name="GRAS_CL_VIEWPORT_ZCLAMP" stride="2" length="16" variants="A6XX-A7XX" usage="rp_blit"> 924 880 <reg32 offset="0" name="MIN" type="float"/> 925 881 <reg32 offset="1" name="MAX" type="float"/> 926 882 </array> 927 883 928 928 - <reg32 offset="0x8090" name="GRAS_SU_CNTL" usage="rp_blit"> 884 884 + <bitset name="a6xx_gras_su_cntl" varset="chip"> 929 885 <bitfield name="CULL_FRONT" pos="0" type="boolean"/> 930 886 <bitfield name="CULL_BACK" pos="1" type="boolean"/> 931 887 <bitfield name="FRONT_CW" pos="2" type="boolean"/> ··· 936 890 <bitfield name="LINE_MODE" pos="13" type="a5xx_line_mode"/> 937 891 <bitfield name="UNK15" low="15" high="16"/> 938 892 <!-- 939 939 - On gen1 only MULTIVIEW_ENABLE exists. On gen3 we have 940 940 - the ability to add the view index to either the RT array 941 941 - index or the viewport index, and it seems that 942 942 - MULTIVIEW_ENABLE doesn't do anything, instead we need to 943 943 - set at least one of RENDERTARGETINDEXINCR or 944 944 - VIEWPORTINDEXINCR to enable multiview. The blob still 945 945 - sets MULTIVIEW_ENABLE regardless. 946 946 - TODO: what about gen2 (a640)? 893 893 + On gen1 only MULTIVIEW_ENABLE exists. On gen3 we have 894 894 + the ability to add the view index to either the RT array 895 895 + index or the viewport index, and it seems that 896 896 + MULTIVIEW_ENABLE doesn't do anything, instead we need to 897 897 + set at least one of RENDERTARGETINDEXINCR or 898 898 + VIEWPORTINDEXINCR to enable multiview. The blob still 899 899 + sets MULTIVIEW_ENABLE regardless. 900 900 + TODO: what about gen2 (a640)? 947 901 --> 948 902 <bitfield name="MULTIVIEW_ENABLE" pos="17" type="boolean"/> 949 949 - <bitfield name="RENDERTARGETINDEXINCR" pos="18" type="boolean"/> 950 950 - <bitfield name="VIEWPORTINDEXINCR" pos="19" type="boolean"/> 951 951 - <bitfield name="UNK20" low="20" high="22"/> 952 952 - </reg32> 953 953 - <reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX" usage="rp_blit"> 903 903 + <bitfield name="RENDERTARGETINDEXINCR" pos="18" type="boolean" variants="A6XX-A7XX"/> 904 904 + <bitfield name="VIEWPORTINDEXINCR" pos="19" type="boolean" variants="A6XX-A7XX"/> 905 905 + <bitfield name="UNK20" low="20" high="22" variants="A6XX-A7XX"/> 906 906 + </bitset> 907 907 + <reg32 offset="0x8090" name="GRAS_SU_CNTL" type="a6xx_gras_su_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 908 908 + 909 909 + <bitset name="a6xx_gras_su_point_minmax" inline="yes"> 954 910 <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/> 955 911 <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/> 956 956 - </reg32> 957 957 - <reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" low="0" high="15" type="fixed" radix="4" usage="rp_blit"/> 912 912 + </bitset> 913 913 + 914 914 + <reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX" type="a6xx_gras_su_point_minmax" variants="A6XX-A7XX" usage="rp_blit"/> 915 915 + <reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" low="0" high="15" type="fixed" radix="4" variants="A6XX-A7XX" usage="rp_blit"/> 916 916 + 917 917 + <bitset name="a6xx_gras_su_depth_cntl" inline="yes"> 918 918 + <bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/> 919 919 + </bitset> 920 920 + 921 921 + <reg32 offset="0x8114" name="GRAS_SU_DEPTH_CNTL" variants="A6XX-A7XX" type="a6xx_gras_su_depth_cntl" usage="rp_blit"/> 922 922 + 923 923 + <bitset name="a6xx_gras_su_stencil_cntl" inline="yes"> 924 924 + <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/> 925 925 + </bitset> 926 926 + 927 927 + <reg32 offset="0x8115" name="GRAS_SU_STENCIL_CNTL" type="a6xx_gras_su_stencil_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 928 928 + 929 929 + <bitset name="a6xx_gras_su_render_cntl" inline="yes"> 930 930 + <bitfield name="FS_DISABLE" pos="7" type="boolean"/> 931 931 + </bitset> 932 932 + 933 933 + <reg32 offset="0x8116" name="GRAS_SU_RENDER_CNTL" type="a6xx_gras_su_render_cntl" variants="A7XX" usage="rp_blit"/> 934 934 + 958 935 <!-- 0x8093 invalid --> 959 959 - <reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL" usage="rp_blit"> 936 936 + <bitset name="a6xx_depth_plane_cntl" inline="yes"> 960 937 <bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/> 961 961 - </reg32> 962 962 - <reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float" usage="rp_blit"/> 963 963 - <reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float" usage="rp_blit"/> 964 964 - <reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float" usage="rp_blit"/> 965 965 - <!-- duplicates RB_DEPTH_BUFFER_INFO: --> 966 966 - <reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO" usage="rp_blit"> 938 938 + </bitset> 939 939 + 940 940 + <reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL" type="a6xx_depth_plane_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 941 941 + <reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float" variants="A6XX-A7XX" usage="rp_blit"/> 942 942 + <reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float" variants="A6XX-A7XX" usage="rp_blit"/> 943 943 + <reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float" variants="A6XX-A7XX" usage="rp_blit"/> 944 944 + <bitset name="a6xx_depth_buffer_info" inline="yes"> 967 945 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/> 968 946 <bitfield name="UNK3" pos="3"/> 969 969 - </reg32> 947 947 + </bitset> 970 948 971 971 - <reg32 offset="0x8099" name="GRAS_SU_CONSERVATIVE_RAS_CNTL" usage="cmd"> 949 949 + <!-- duplicates RB_DEPTH_BUFFER_INFO: --> 950 950 + <reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO" type="a6xx_depth_buffer_info" variants="A6XX-A7XX" usage="rp_blit"/> 951 951 + 952 952 + <bitset name="a6xx_gras_su_conservative_ras_cntl" inline="yes"> 972 953 <bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/> 973 954 <enum name="a6xx_shift_amount"> 974 955 <value value="0" name="NO_SHIFT"/> ··· 1005 932 <bitfield name="SHIFTAMOUNT" low="1" high="2" type="a6xx_shift_amount"/> 1006 933 <bitfield name="INNERCONSERVATIVERASEN" pos="3" type="boolean"/> 1007 934 <bitfield name="UNK4" low="4" high="5"/> 1008 1008 - </reg32> 935 935 + </bitset> 936 936 + 937 937 + <reg32 offset="0x8099" name="GRAS_SU_CONSERVATIVE_RAS_CNTL" type="a6xx_gras_su_conservative_ras_cntl" variants="A6XX-A7XX" usage="cmd"/> 938 938 + 1009 939 <reg32 offset="0x809a" name="GRAS_SU_PATH_RENDERING_CNTL"> 1010 940 <bitfield name="UNK0" pos="0" type="boolean"/> 1011 941 <bitfield name="LINELENGTHEN" pos="1" type="boolean"/> ··· 1018 942 <bitfield name="WRITES_LAYER" pos="0" type="boolean"/> 1019 943 <bitfield name="WRITES_VIEW" pos="1" type="boolean"/> 1020 944 </bitset> 1021 1021 - <reg32 offset="0x809b" name="GRAS_SU_VS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" usage="rp_blit"/> 1022 1022 - <reg32 offset="0x809c" name="GRAS_SU_GS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" usage="rp_blit"/> 1023 1023 - <reg32 offset="0x809d" name="GRAS_SU_DS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" usage="rp_blit"/> 1024 1024 - <!-- 0x809e/0x809f invalid --> 945 945 + <reg32 offset="0x809b" name="GRAS_SU_VS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 946 946 + <reg32 offset="0x809c" name="GRAS_SU_GS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 947 947 + <reg32 offset="0x809d" name="GRAS_SU_DS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 948 948 + 949 949 + <bitset name="a6xx_rast_cntl" inline="yes"> 950 950 + <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> 951 951 + </bitset> 1025 952 1026 953 <enum name="a6xx_sequenced_thread_dist"> 1027 954 <value value="0x0" name="DIST_SCREEN_COORD"/> ··· 1072 993 <value value="0x3" name="RB_BT"/> 1073 994 </enum> 1074 995 1075 1075 - <reg32 offset="0x80a0" name="GRAS_SC_CNTL" usage="rp_blit"> 996 996 + <bitset name="a6xx_gras_sc_cntl" inline="yes"> 1076 997 <bitfield name="CCUSINGLECACHELINESIZE" low="0" high="2"/> 1077 998 <bitfield name="SINGLE_PRIM_MODE" low="3" high="4" type="a6xx_single_prim_mode"/> 1078 999 <bitfield name="RASTER_MODE" pos="5" type="a6xx_raster_mode"/> ··· 1082 1003 <bitfield name="UNK9" pos="9" type="boolean"/> 1083 1004 <bitfield name="ROTATION" low="10" high="11" type="uint"/> 1084 1005 <bitfield name="EARLYVIZOUTEN" pos="12" type="boolean"/> 1085 1085 - </reg32> 1006 1006 + </bitset> 1007 1007 + 1008 1008 + <reg32 offset="0x80a0" name="GRAS_SC_CNTL" type="a6xx_gras_sc_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1086 1009 1087 1010 <enum name="a6xx_render_mode"> 1088 1011 <value value="0x0" name="RENDERING_PASS"/> ··· 1105 1024 <value value="0x4" name="LRZ_FEEDBACK_LATE_Z"/> 1106 1025 </enum> 1107 1026 1108 1108 - <reg32 offset="0x80a1" name="GRAS_SC_BIN_CNTL" usage="rp_blit"> 1027 1027 + <bitset name="a6xx_bin_cntl" inline="yes"> 1109 1028 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> 1110 1029 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> 1111 1030 <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/> ··· 1118 1037 In sysmem mode GRAS_LRZ_CNTL.LRZ_WRITE is not considered. 1119 1038 </doc> 1120 1039 <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26" type="a6xx_lrz_feedback_mask"/> 1121 1121 - <bitfield name="UNK27" pos="27"/> 1122 1122 - </reg32> 1040 1040 + <bitfield name="FORCE_LRZ_DIS" pos="27" type="boolean"/> 1041 1041 + </bitset> 1123 1042 1124 1124 - <reg32 offset="0x80a2" name="GRAS_SC_RAS_MSAA_CNTL" usage="rp_blit"> 1043 1043 + <reg32 offset="0x80a1" name="GRAS_SC_BIN_CNTL" type="a6xx_bin_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1044 1044 + 1045 1045 + <bitset name="a6xx_gras_sc_ras_msaa_cntl" inline="yes"> 1125 1046 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 1126 1047 <bitfield name="UNK2" pos="2"/> 1127 1048 <bitfield name="UNK3" pos="3"/> 1128 1128 - </reg32> 1129 1129 - <reg32 offset="0x80a3" name="GRAS_SC_DEST_MSAA_CNTL" usage="rp_blit"> 1049 1049 + </bitset> 1050 1050 + 1051 1051 + <reg32 offset="0x80a2" name="GRAS_SC_RAS_MSAA_CNTL" type="a6xx_gras_sc_ras_msaa_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1052 1052 + 1053 1053 + <bitset name="a6xx_gras_sc_dest_msaa_cntl" inline="yes"> 1130 1054 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 1131 1055 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/> 1132 1132 - </reg32> 1056 1056 + </bitset> 1057 1057 + 1058 1058 + <reg32 offset="0x80a3" name="GRAS_SC_DEST_MSAA_CNTL" type="a6xx_gras_sc_dest_msaa_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1133 1059 1134 1060 <bitset name="a6xx_msaa_sample_pos_cntl" inline="yes"> 1135 1061 <bitfield name="UNK0" pos="0"/> ··· 1154 1066 <bitfield name="SAMPLE_3_Y" low="28" high="31" radix="4" type="fixed"/> 1155 1067 </bitset> 1156 1068 1157 1157 - <reg32 offset="0x80a4" name="GRAS_SC_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" usage="rp_blit"/> 1158 1158 - <reg32 offset="0x80a5" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> 1159 1159 - <reg32 offset="0x80a6" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> 1069 1069 + <reg32 offset="0x80a4" name="GRAS_SC_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1070 1070 + <reg32 offset="0x80a5" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" variants="A6XX-A7XX" usage="rp_blit"/> 1071 1071 + <reg32 offset="0x80a6" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" variants="A6XX-A7XX" usage="rp_blit"/> 1160 1072 1161 1161 - <reg32 offset="0x80a7" name="GRAS_UNKNOWN_80A7" variants="A7XX-" usage="cmd"/> 1073 1073 + <reg32 offset="0x80a7" name="GRAS_ROTATION_CNTL" variants="A7XX" usage="cmd"/> 1162 1074 1163 1163 - <!-- 0x80a7-0x80ae invalid --> 1164 1164 - <reg32 offset="0x80af" name="GRAS_UNKNOWN_80AF" pos="0" usage="cmd"/> 1075 1075 + <bitset name="a6xx_screen_scissor_cntl" inline="yes"> 1076 1076 + <bitfield name="SCISSOR_DISABLE" pos="0" type="boolean"/> 1077 1077 + </bitset> 1078 1078 + 1079 1079 + <reg32 offset="0x80af" name="GRAS_SC_SCREEN_SCISSOR_CNTL" type="a6xx_screen_scissor_cntl" variants="A6XX-A7XX" pos="0" usage="cmd"/> 1165 1080 1166 1081 <bitset name="a6xx_scissor_xy" inline="yes"> 1167 1082 <bitfield name="X" low="0" high="15" type="uint"/> 1168 1083 <bitfield name="Y" low="16" high="31" type="uint"/> 1169 1084 </bitset> 1170 1170 - <array offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR" stride="2" length="16" usage="rp_blit"> 1171 1171 - <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/> 1172 1172 - <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/> 1173 1173 - </array> 1174 1174 - <array offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR" stride="2" length="16" usage="rp_blit"> 1085 1085 + 1086 1086 + <array offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR" stride="2" length="16" variants="A6XX-A7XX" usage="rp_blit"> 1175 1087 <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/> 1176 1088 <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/> 1177 1089 </array> 1178 1090 1179 1179 - <reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy" usage="rp_blit"/> 1180 1180 - <reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy" usage="rp_blit"/> 1091 1091 + <array offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR" stride="2" length="16" variants="A6XX-A7XX" usage="rp_blit"> 1092 1092 + <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/> 1093 1093 + <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/> 1094 1094 + </array> 1095 1095 + 1096 1096 + <reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="rp_blit"/> 1097 1097 + <reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="rp_blit"/> 1181 1098 1182 1099 <enum name="a6xx_fsr_combiner"> 1183 1100 <value value="0" name="FSR_COMBINER_OP_KEEP"/> ··· 1192 1099 <value value="4" name="FSR_COMBINER_OP_MUL"/> 1193 1100 </enum> 1194 1101 1195 1195 - <reg32 offset="0x80f4" name="GRAS_VRS_CONFIG" variants="A7XX-" usage="rp_blit"> 1102 1102 + <bitset name="a6xx_gras_vrs_config"> 1196 1103 <bitfield name="PIPELINE_FSR_ENABLE" pos="0" type="boolean"/> 1197 1104 <bitfield name="FRAG_SIZE_X" low="1" high="2" type="uint"/> 1198 1105 <bitfield name="FRAG_SIZE_Y" low="3" high="4" type="uint"/> ··· 1200 1107 <bitfield name="COMBINER_OP_2" low="8" high="10" type="a6xx_fsr_combiner"/> 1201 1108 <bitfield name="ATTACHMENT_FSR_ENABLE" pos="13" type="boolean"/> 1202 1109 <bitfield name="PRIMITIVE_FSR_ENABLE" pos="20" type="boolean"/> 1203 1203 - </reg32> 1204 1204 - <reg32 offset="0x80f5" name="GRAS_QUALITY_BUFFER_INFO" variants="A7XX-" usage="rp_blit"> 1110 1110 + </bitset> 1111 1111 + 1112 1112 + <reg32 offset="0x80f4" name="GRAS_VRS_CONFIG" type="a6xx_gras_vrs_config" variants="A7XX" usage="rp_blit"/> 1113 1113 + 1114 1114 + <bitset name="a6xx_gras_quality_buffer_info" inline="yes"> 1205 1115 <bitfield name="LAYERED" pos="0" type="boolean"/> 1206 1116 <bitfield name="TILE_MODE" low="1" high="2" type="a6xx_tile_mode"/> 1207 1207 - </reg32> 1208 1208 - <reg32 offset="0x80f6" name="GRAS_QUALITY_BUFFER_DIMENSION" variants="A7XX-" usage="rp_blit"> 1117 1117 + </bitset> 1118 1118 + 1119 1119 + <reg32 offset="0x80f5" name="GRAS_QUALITY_BUFFER_INFO" type="a6xx_gras_quality_buffer_info" variants="A7XX" usage="rp_blit"/> 1120 1120 + 1121 1121 + <bitset name="a6xx_gras_quality_buffer_dimension" inline="yes"> 1209 1122 <bitfield name="WIDTH" low="0" high="15" type="uint"/> 1210 1123 <bitfield name="HEIGHT" low="16" high="31" type="uint"/> 1211 1211 - </reg32> 1212 1212 - <reg64 offset="0x80f8" name="GRAS_QUALITY_BUFFER_BASE" variants="A7XX-" type="waddress" usage="rp_blit"/> 1213 1213 - <reg32 offset="0x80fa" name="GRAS_QUALITY_BUFFER_PITCH" variants="A7XX-" usage="rp_blit"> 1124 1124 + </bitset> 1125 1125 + 1126 1126 + <reg32 offset="0x80f6" name="GRAS_QUALITY_BUFFER_DIMENSION" type="a6xx_gras_quality_buffer_dimension" variants="A7XX" usage="rp_blit"/> 1127 1127 + 1128 1128 + <reg64 offset="0x80f8" name="GRAS_QUALITY_BUFFER_BASE" variants="A7XX" type="waddress" usage="rp_blit"/> 1129 1129 + 1130 1130 + <bitset name="a6xx_gras_quality_buffer_pitch" inline="yes"> 1214 1131 <bitfield name="PITCH" shr="6" low="0" high="7" type="uint"/> 1215 1132 <bitfield name="ARRAY_PITCH" shr="6" low="10" high="28" type="uint"/> 1216 1216 - </reg32> 1133 1133 + </bitset> 1134 1134 + 1135 1135 + <reg32 offset="0x80fa" name="GRAS_QUALITY_BUFFER_PITCH" type="a6xx_gras_quality_buffer_pitch" variants="A7XX" usage="rp_blit"/> 1217 1136 1218 1137 <enum name="a6xx_lrz_dir_status"> 1219 1138 <value value="0x1" name="LRZ_DIR_LE"/> ··· 1233 1128 <value value="0x3" name="LRZ_DIR_INVALID"/> 1234 1129 </enum> 1235 1130 1236 1236 - <reg32 offset="0x8100" name="GRAS_LRZ_CNTL" usage="rp_blit"> 1131 1131 + <bitset name="a6xx_gras_lrz_cntl" inline="yes"> 1237 1132 <bitfield name="ENABLE" pos="0" type="boolean"/> 1238 1133 <doc>LRZ write also disabled for blend/etc.</doc> 1239 1134 <bitfield name="LRZ_WRITE" pos="1" type="boolean"/> ··· 1260 1155 </doc> 1261 1156 <bitfield name="DISABLE_ON_WRONG_DIR" pos="9" type="boolean" variants="A6XX"/> 1262 1157 <bitfield name="Z_FUNC" low="11" high="13" type="adreno_compare_func" variants="A7XX-"/> 1263 1263 - </reg32> 1158 1158 + </bitset> 1159 1159 + 1160 1160 + <reg32 offset="0x8100" name="GRAS_LRZ_CNTL" type="a6xx_gras_lrz_cntl" usage="rp_blit" variants="A6XX-A7XX"/> 1264 1161 1265 1162 <enum name="a6xx_fragcoord_sample_mode"> 1266 1163 <value value="0" name="FRAGCOORD_CENTER"/> 1267 1164 <value value="3" name="FRAGCOORD_SAMPLE"/> 1268 1165 </enum> 1269 1166 1270 1270 - <reg32 offset="0x8101" name="GRAS_LRZ_PS_INPUT_CNTL" low="0" high="2" usage="rp_blit"> 1167 1167 + <bitset name="a6xx_gras_lrz_ps_input_cntl" inline="yes"> 1271 1168 <bitfield name="SAMPLEID" pos="0" type="boolean"/> 1272 1169 <bitfield name="FRAGCOORDSAMPLEMODE" low="1" high="2" type="a6xx_fragcoord_sample_mode"/> 1273 1273 - </reg32> 1170 1170 + </bitset> 1274 1171 1275 1275 - <reg32 offset="0x8102" name="GRAS_LRZ_MRT_BUFFER_INFO_0" usage="rp_blit"> 1172 1172 + <reg32 offset="0x8101" name="GRAS_LRZ_PS_INPUT_CNTL" type="a6xx_gras_lrz_ps_input_cntl" usage="rp_blit" variants="A6XX-A7XX"/> 1173 1173 + 1174 1174 + <bitset name="a6xx_gras_lrz_mrt_buffer_info_0" inline="yes"> 1276 1175 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 1277 1277 - </reg32> 1278 1278 - <reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress" usage="rp_blit"/> 1279 1279 - <reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH" usage="rp_blit"> 1176 1176 + </bitset> 1177 1177 + 1178 1178 + <reg32 offset="0x8102" name="GRAS_LRZ_MRT_BUFFER_INFO_0" type="a6xx_gras_lrz_mrt_buffer_info_0" usage="rp_blit" variants="A6XX-A7XX"/> 1179 1179 + 1180 1180 + <reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress" usage="rp_blit" variants="A6XX-A7XX"/> 1181 1181 + 1182 1182 + <bitset name="a6xx_gras_lrz_buffer_pitch" inline="yes"> 1280 1183 <bitfield name="PITCH" low="0" high="7" shr="5" type="uint"/> 1281 1184 <bitfield name="ARRAY_PITCH" low="10" high="28" shr="8" type="uint"/> 1282 1282 - </reg32> 1185 1185 + </bitset> 1186 1186 + 1187 1187 + <reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH" type="a6xx_gras_lrz_buffer_pitch" usage="rp_blit" variants="A6XX-A7XX"/> 1283 1188 1284 1189 <!-- 1285 1190 The LRZ "fast clear" buffer is initialized to zero's by blob, and ··· 1322 1207 not. 1323 1208 --> 1324 1209 <reg64 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" align="64" type="waddress" usage="rp_blit"/> 1325 1325 - <!-- 0x8108 invalid --> 1326 1210 <reg32 offset="0x8109" name="GRAS_LRZ_PS_SAMPLEFREQ_CNTL" usage="rp_blit"> 1327 1211 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/> 1328 1212 </reg32> ··· 1346 1232 1347 1233 <!-- 0x810c-0x810f invalid --> 1348 1234 1349 1349 - <reg32 offset="0x8110" name="GRAS_UNKNOWN_8110" low="0" high="1" usage="cmd"/> 1235 1235 + <reg32 offset="0x8110" name="GRAS_MODE_CNTL" low="0" high="1" variants="A6XX-A7XX" usage="cmd"/> 1350 1236 1351 1237 <!-- A bit tentative but it's a color and it is followed by LRZ_CLEAR --> 1352 1352 - <reg32 offset="0x8111" name="GRAS_LRZ_DEPTH_CLEAR" type="float" variants="A7XX-"/> 1238 1238 + <reg32 offset="0x8111" name="GRAS_LRZ_DEPTH_CLEAR" type="float" variants="A7XX"/> 1353 1239 1354 1354 - <reg32 offset="0x8113" name="GRAS_LRZ_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit"> 1240 1240 + <bitset name="a6xx_gras_lrz_depth_buffer_info" inline="yes"> 1355 1241 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/> 1356 1242 <bitfield name="UNK3" pos="3"/> 1357 1357 - </reg32> 1243 1243 + </bitset> 1358 1244 1359 1359 - <!-- Always written together and always equal 09510840 00000a62 --> 1360 1360 - <reg32 offset="0x8120" name="GRAS_UNKNOWN_8120" variants="A7XX-" usage="cmd"/> 1361 1361 - <reg32 offset="0x8121" name="GRAS_UNKNOWN_8121" variants="A7XX-" usage="cmd"/> 1245 1245 + <reg32 offset="0x8113" name="GRAS_LRZ_DEPTH_BUFFER_INFO" type="a6xx_gras_lrz_depth_buffer_info" variants="A7XX" usage="rp_blit"/> 1246 1246 + 1247 1247 + <doc>LUT used to convert quality buffer values to HW shading rate values. An array of 4-bit values.</doc> 1248 1248 + <array offset="0x8120" name="GRAS_LRZ_QUALITY_LOOKUP_TABLE" variants="A7XX-" stride="1" length="2"/> 1362 1249 1363 1250 <!-- 0x8112-0x83ff invalid --> 1364 1251 ··· 1384 1269 <bitfield name="D24S8" pos="19" type="boolean"/> 1385 1270 <!-- some sort of channel mask, disabled channels are set to zero ? --> 1386 1271 <bitfield name="MASK" low="20" high="23"/> 1387 1387 - <bitfield name="IFMT" low="24" high="28" type="a6xx_2d_ifmt"/> 1272 1272 + <bitfield name="IFMT" low="24" high="26" type="a6xx_2d_ifmt"/> 1273 1273 + <bitfield name="UNK27" pos="27" type="boolean"/> 1274 1274 + <bitfield name="UNK28" pos="28" type="boolean"/> 1388 1275 <bitfield name="RASTER_MODE" pos="29" type="a6xx_raster_mode"/> 1389 1389 - <bitfield name="UNK30" pos="30" type="boolean" variants="A7XX-"/> 1276 1276 + <bitfield name="COPY" pos="30" type="boolean" variants="A7XX-"/> 1390 1277 </bitset> 1391 1278 1392 1392 - <reg32 offset="0x8400" name="GRAS_A2D_BLT_CNTL" type="a6xx_a2d_bit_cntl" usage="rp_blit"/> 1279 1279 + <reg32 offset="0x8400" name="GRAS_A2D_BLT_CNTL" type="a6xx_a2d_bit_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1393 1280 <!-- note: the low 8 bits for src coords are valid, probably fixed point 1394 1281 it would be a bit weird though, since we subtract 1 from BR coords 1395 1282 apparently signed, gallium driver uses negative coords and it works? 1396 1283 --> 1397 1397 - <reg32 offset="0x8401" name="GRAS_A2D_SRC_XMIN" low="8" high="24" type="int" usage="rp_blit"/> 1398 1398 - <reg32 offset="0x8402" name="GRAS_A2D_SRC_XMAX" low="8" high="24" type="int" usage="rp_blit"/> 1399 1399 - <reg32 offset="0x8403" name="GRAS_A2D_SRC_YMIN" low="8" high="24" type="int" usage="rp_blit"/> 1400 1400 - <reg32 offset="0x8404" name="GRAS_A2D_SRC_YMAX" low="8" high="24" type="int" usage="rp_blit"/> 1401 1401 - <reg32 offset="0x8405" name="GRAS_A2D_DEST_TL" type="a6xx_reg_xy" usage="rp_blit"/> 1402 1402 - <reg32 offset="0x8406" name="GRAS_A2D_DEST_BR" type="a6xx_reg_xy" usage="rp_blit"/> 1284 1284 + <reg32 offset="0x8401" name="GRAS_A2D_SRC_XMIN" low="8" high="24" type="int" variants="A6XX-A7XX" usage="rp_blit"/> 1285 1285 + <reg32 offset="0x8402" name="GRAS_A2D_SRC_XMAX" low="8" high="24" type="int" variants="A6XX-A7XX" usage="rp_blit"/> 1286 1286 + <reg32 offset="0x8403" name="GRAS_A2D_SRC_YMIN" low="8" high="24" type="int" variants="A6XX-A7XX" usage="rp_blit"/> 1287 1287 + <reg32 offset="0x8404" name="GRAS_A2D_SRC_YMAX" low="8" high="24" type="int" variants="A6XX-A7XX" usage="rp_blit"/> 1288 1288 + <reg32 offset="0x8405" name="GRAS_A2D_DEST_TL" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="rp_blit"/> 1289 1289 + <reg32 offset="0x8406" name="GRAS_A2D_DEST_BR" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="rp_blit"/> 1403 1290 <reg32 offset="0x8407" name="GRAS_2D_UNKNOWN_8407" low="0" high="31"/> 1404 1291 <reg32 offset="0x8408" name="GRAS_2D_UNKNOWN_8408" low="0" high="31"/> 1405 1292 <reg32 offset="0x8409" name="GRAS_2D_UNKNOWN_8409" low="0" high="31"/> 1406 1406 - <reg32 offset="0x840a" name="GRAS_A2D_SCISSOR_TL" type="a6xx_reg_xy" usage="rp_blit"/> 1407 1407 - <reg32 offset="0x840b" name="GRAS_A2D_SCISSOR_BR" type="a6xx_reg_xy" usage="rp_blit"/> 1408 1408 - <!-- 0x840c-0x85ff invalid --> 1293 1293 + <reg32 offset="0x840a" name="GRAS_A2D_SCISSOR_TL" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="rp_blit"/> 1294 1294 + <reg32 offset="0x840b" name="GRAS_A2D_SCISSOR_BR" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="rp_blit"/> 1409 1295 1410 1296 <!-- always 0x880 ? (and 0 in a640/a650 traces?) --> 1411 1297 <reg32 offset="0x8600" name="GRAS_DBG_ECO_CNTL" usage="cmd"> ··· 1424 1308 --> 1425 1309 1426 1310 <!-- same as GRAS_BIN_CONTROL, but without bit 27: --> 1427 1427 - <reg32 offset="0x8800" name="RB_CNTL" variants="A6XX" usage="rp_blit"> 1428 1428 - <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> 1429 1429 - <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> 1430 1430 - <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/> 1431 1431 - <bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/> 1432 1432 - <bitfield name="BUFFERS_LOCATION" low="22" high="23" type="a6xx_buffers_location"/> 1433 1433 - <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26" type="a6xx_lrz_feedback_mask"/> 1434 1434 - </reg32> 1435 1435 - 1436 1436 - <reg32 offset="0x8800" name="RB_CNTL" variants="A7XX-" usage="rp_blit"> 1437 1437 - <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> 1438 1438 - <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> 1439 1439 - <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/> 1440 1440 - <bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/> 1441 1441 - <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26" type="a6xx_lrz_feedback_mask"/> 1442 1442 - </reg32> 1311 1311 + <reg32 offset="0x8800" name="RB_CNTL" variants="A6XX-A7XX" type="a6xx_bin_cntl" usage="rp_blit"/> 1443 1312 1444 1313 <reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A6XX" usage="rp_blit"> 1445 1314 <bitfield name="CCUSINGLECACHELINESIZE" low="3" high="5"/> ··· 1447 1346 <bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/> 1448 1347 <bitfield name="CONSERVATIVERASEN" pos="11" type="boolean"/> 1449 1348 <bitfield name="INNERCONSERVATIVERASEN" pos="12" type="boolean"/> 1450 1450 - </reg32> 1451 1451 - <reg32 offset="0x8116" name="GRAS_SU_RENDER_CNTL" variants="A7XX-" usage="rp_blit"> 1452 1452 - <bitfield name="FS_DISABLE" pos="7" type="boolean"/> 1453 1349 </reg32> 1454 1350 1455 1351 <reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL" usage="rp_blit"> ··· 1614 1516 <bitfield name="SAMPLE_MASK" low="16" high="31"/> 1615 1517 </reg32> 1616 1518 <!-- 0x8866-0x886f invalid --> 1617 1617 - <reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL" usage="rp_blit"> 1618 1618 - <bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/> 1619 1619 - </reg32> 1519 1519 + <reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL" type="a6xx_depth_plane_cntl" usage="rp_blit"/> 1620 1520 1621 1521 <reg32 offset="0x8871" name="RB_DEPTH_CNTL" usage="rp_blit"> 1622 1522 <bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/> ··· 1628 1532 <bitfield name="Z_READ_ENABLE" pos="6" type="boolean"/> 1629 1533 <bitfield name="Z_BOUNDS_ENABLE" pos="7" type="boolean"/> 1630 1534 </reg32> 1631 1631 - <reg32 offset="0x8114" name="GRAS_SU_DEPTH_CNTL" usage="rp_blit"> 1632 1632 - <bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/> 1633 1633 - </reg32> 1535 1535 + 1634 1536 <!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: --> 1635 1635 - <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" variants="A6XX" usage="rp_blit"> 1636 1636 - <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/> 1637 1637 - <bitfield name="UNK3" low="3" high="4"/> 1638 1638 - </reg32> 1537 1537 + <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" variants="A6XX" type="a6xx_depth_buffer_info" usage="rp_blit"/> 1639 1538 <!-- first 4 bits duplicates GRAS_SU_DEPTH_BUFFER_INFO --> 1640 1539 <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit"> 1641 1540 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/> ··· 1666 1575 <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/> 1667 1576 <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/> 1668 1577 </reg32> 1669 1669 - <reg32 offset="0x8115" name="GRAS_SU_STENCIL_CNTL" usage="rp_blit"> 1670 1670 - <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/> 1671 1671 - </reg32> 1578 1578 + 1672 1579 <reg32 offset="0x8881" name="RB_STENCIL_BUFFER_INFO" variants="A6XX" usage="rp_blit"> 1673 1580 <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/> 1674 1581 <bitfield name="UNK1" pos="1" type="boolean"/> ··· 1705 1616 <reg32 offset="0x8899" name="RB_UNKNOWN_8899" variants="A7XX-" usage="cmd"/> 1706 1617 <!-- 0x8899-0x88bf invalid --> 1707 1618 <!-- clamps depth value for depth test/write --> 1708 1708 - <reg32 offset="0x88c0" name="RB_VIEWPORT_ZCLAMP_MIN" type="float" usage="rp_blit"/> 1709 1709 - <reg32 offset="0x88c1" name="RB_VIEWPORT_ZCLAMP_MAX" type="float" usage="rp_blit"/> 1619 1619 + <reg32 offset="0x88c0" name="RB_VIEWPORT_ZCLAMP_MIN" type="float" usage="rp_blit" variants="A6XX-A7XX"/> 1620 1620 + <reg32 offset="0x88c1" name="RB_VIEWPORT_ZCLAMP_MAX" type="float" usage="rp_blit" variants="A6XX-A7XX"/> 1621 1621 + 1710 1622 <!-- 0x88c2-0x88cf invalid--> 1711 1623 <reg32 offset="0x88d0" name="RB_RESOLVE_CNTL_0" usage="rp_blit"> 1712 1624 <bitfield name="UNK0" low="0" high="12"/> ··· 1716 1626 <reg32 offset="0x88d1" name="RB_RESOLVE_CNTL_1" type="a6xx_reg_xy" usage="rp_blit"/> 1717 1627 <reg32 offset="0x88d2" name="RB_RESOLVE_CNTL_2" type="a6xx_reg_xy" usage="rp_blit"/> 1718 1628 <!-- weird to duplicate other regs from same block?? --> 1719 1719 - <reg32 offset="0x88d3" name="RB_RESOLVE_CNTL_3" usage="rp_blit"> 1629 1629 + <reg32 offset="0x88d3" name="RB_RESOLVE_CNTL_3" variants="A6XX-A7XX" usage="rp_blit"> 1720 1630 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> 1721 1631 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> 1722 1632 </reg32> ··· 1740 1650 <!-- array-pitch is size of layer --> 1741 1651 <reg32 offset="0x88db" name="RB_RESOLVE_SYSTEM_BUFFER_ARRAY_PITCH" low="0" high="28" shr="6" type="uint" usage="rp_blit"/> 1742 1652 <reg64 offset="0x88dc" name="RB_RESOLVE_SYSTEM_FLAG_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> 1743 1743 - <reg32 offset="0x88de" name="RB_RESOLVE_SYSTEM_FLAG_BUFFER_PITCH" usage="rp_blit"> 1653 1653 + 1654 1654 + <bitset name="a6xx_flag_buffer_pitch" inline="yes"> 1744 1655 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> 1745 1745 - <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/> 1746 1746 - </reg32> 1656 1656 + <bitfield name="ARRAY_PITCH" low="11" high="28" shr="7" type="uint"/> 1657 1657 + </bitset> 1658 1658 + 1659 1659 + <reg32 offset="0x88de" name="RB_RESOLVE_SYSTEM_FLAG_BUFFER_PITCH" type="a6xx_flag_buffer_pitch" usage="rp_blit"/> 1747 1660 1748 1661 <reg32 offset="0x88df" name="RB_RESOLVE_CLEAR_COLOR_DW0" usage="rp_blit"/> 1749 1662 <reg32 offset="0x88e0" name="RB_RESOLVE_CLEAR_COLOR_DW1" usage="rp_blit"/> ··· 1819 1726 <reg32 offset="0x88f0" name="RB_UNKNOWN_88F0" low="0" high="11" usage="cmd"/> 1820 1727 <!-- could be for separate stencil? (or may not be a flag buffer at all) --> 1821 1728 <reg64 offset="0x88f1" name="RB_UNK_FLAG_BUFFER_BASE" type="waddress" align="64"/> 1822 1822 - <reg32 offset="0x88f3" name="RB_UNK_FLAG_BUFFER_PITCH"> 1823 1823 - <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> 1824 1824 - <bitfield name="ARRAY_PITCH" low="11" high="23" shr="7" type="uint"/> 1825 1825 - </reg32> 1729 1729 + <reg32 offset="0x88f3" name="RB_UNK_FLAG_BUFFER_PITCH" type="a6xx_flag_buffer_pitch"/> 1826 1730 1827 1731 <reg32 offset="0x88f4" name="RB_VRS_CONFIG" usage="rp_blit"> 1828 1732 <bitfield name="UNK2" pos="2" type="boolean"/> ··· 1827 1737 <bitfield name="ATTACHMENT_FSR_ENABLE" pos="5" type="boolean"/> 1828 1738 <bitfield name="PRIMITIVE_FSR_ENABLE" pos="18" type="boolean"/> 1829 1739 </reg32> 1830 1830 - <!-- Connected to VK_EXT_fragment_density_map? --> 1831 1831 - <reg32 offset="0x88f5" name="RB_UNKNOWN_88F5" variants="A7XX-"/> 1740 1740 + <reg32 offset="0x88f5" name="RB_BIN_FOVEAT" variants="A7XX-" usage="cmd"> 1741 1741 + <bitfield name="BINSCALEEN" pos="6" type="boolean"/> 1742 1742 + </reg32> 1832 1743 <!-- 0x88f6-0x88ff invalid --> 1833 1744 <reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> 1834 1745 <reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH" usage="rp_blit"> ··· 1838 1747 <bitfield name="UNK8" low="8" high="10"/> 1839 1748 <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/> 1840 1749 </reg32> 1750 1750 + 1841 1751 <array offset="0x8903" name="RB_COLOR_FLAG_BUFFER" stride="3" length="8" usage="rp_blit"> 1842 1752 <reg64 offset="0" name="ADDR" type="waddress" align="64"/> 1843 1843 - <reg32 offset="2" name="PITCH"> 1844 1844 - <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> 1845 1845 - <bitfield name="ARRAY_PITCH" low="11" high="28" shr="7" type="uint"/> 1846 1846 - </reg32> 1753 1753 + <reg32 offset="2" name="PITCH" type="a6xx_flag_buffer_pitch"/> 1847 1754 </array> 1848 1755 <!-- 0x891b-0x8926 invalid --> 1849 1756 <doc> ··· 1904 1815 <reg64 offset="0x8c1e" name="RB_A2D_DEST_BUFFER_BASE_2" type="waddress" align="64" usage="rp_blit"/> 1905 1816 1906 1817 <reg64 offset="0x8c20" name="RB_A2D_DEST_FLAG_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> 1907 1907 - <reg32 offset="0x8c22" name="RB_A2D_DEST_FLAG_BUFFER_PITCH" low="0" high="7" shr="6" type="uint" usage="rp_blit"/> 1818 1818 + <reg32 offset="0x8c22" name="RB_A2D_DEST_FLAG_BUFFER_PITCH" type="a6xx_flag_buffer_pitch" usage="rp_blit"/> 1908 1819 <!-- this is a guess but seems likely (for NV12 with UBWC): --> 1909 1820 <reg64 offset="0x8c23" name="RB_A2D_DEST_FLAG_BUFFER_BASE_1" type="waddress" align="64" usage="rp_blit"/> 1910 1821 <reg32 offset="0x8c25" name="RB_A2D_DEST_FLAG_BUFFER_PITCH_1" low="0" high="7" shr="6" type="uint" usage="rp_blit"/> ··· 2010 1921 <bitfield name="CLIP_DIST_03_LOC" low="8" high="15" type="uint"/> 2011 1922 <bitfield name="CLIP_DIST_47_LOC" low="16" high="23" type="uint"/> 2012 1923 </bitset> 2013 2013 - <reg32 offset="0x9101" name="VPC_VS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 2014 2014 - <reg32 offset="0x9102" name="VPC_GS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 2015 2015 - <reg32 offset="0x9103" name="VPC_DS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 1924 1924 + <reg32 offset="0x9101" name="VPC_VS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1925 1925 + <reg32 offset="0x9102" name="VPC_GS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1926 1926 + <reg32 offset="0x9103" name="VPC_DS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2016 1927 2017 2017 - <reg32 offset="0x9311" name="VPC_VS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 2018 2018 - <reg32 offset="0x9312" name="VPC_GS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 2019 2019 - <reg32 offset="0x9313" name="VPC_DS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 1928 1928 + <reg32 offset="0x9311" name="VPC_VS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1929 1929 + <reg32 offset="0x9312" name="VPC_GS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1930 1930 + <reg32 offset="0x9313" name="VPC_DS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2020 1931 2021 1932 <bitset name="a6xx_vpc_xs_siv_cntl" inline="yes"> 2022 1933 <bitfield name="LAYERLOC" low="0" high="7" type="uint"/> ··· 2024 1935 <bitfield name="SHADINGRATELOC" low="16" high="23" type="uint" variants="A7XX-"/> 2025 1936 </bitset> 2026 1937 2027 2027 - <reg32 offset="0x9104" name="VPC_VS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> 2028 2028 - <reg32 offset="0x9105" name="VPC_GS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> 2029 2029 - <reg32 offset="0x9106" name="VPC_DS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> 1938 1938 + <reg32 offset="0x9104" name="VPC_VS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1939 1939 + <reg32 offset="0x9105" name="VPC_GS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1940 1940 + <reg32 offset="0x9106" name="VPC_DS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2030 1941 2031 2031 - <reg32 offset="0x9314" name="VPC_VS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> 2032 2032 - <reg32 offset="0x9315" name="VPC_GS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> 2033 2033 - <reg32 offset="0x9316" name="VPC_DS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> 1942 1942 + 1943 1943 + <reg32 offset="0x9314" name="VPC_VS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1944 1944 + <reg32 offset="0x9315" name="VPC_GS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1945 1945 + <reg32 offset="0x9316" name="VPC_DS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1946 1946 + 1947 1947 + <bitset name="a6xx_vpc_rast_stream_cntl" inline="yes"> 1948 1948 + <!-- which stream to send to GRAS --> 1949 1949 + <bitfield name="STREAM" low="0" high="1" type="uint"/> 1950 1950 + <!-- discard primitives before rasterization --> 1951 1951 + <bitfield name="DISCARD" pos="2" type="boolean"/> 1952 1952 + </bitset> 1953 1953 + 1954 1954 + <reg32 offset="0x9980" name="VPC_RAST_STREAM_CNTL" type="a6xx_vpc_rast_stream_cntl" variants="A6XX" usage="rp_blit"/> 1955 1955 + <reg32 offset="0x9107" name="VPC_RAST_STREAM_CNTL" type="a6xx_vpc_rast_stream_cntl" variants="A7XX" usage="rp_blit"/> 1956 1956 + <reg32 offset="0x9317" name="VPC_RAST_STREAM_CNTL_V2" type="a6xx_vpc_rast_stream_cntl" variants="A7XX" usage="rp_blit"/> 2034 1957 2035 1958 <reg32 offset="0x9107" name="VPC_UNKNOWN_9107" variants="A6XX" usage="rp_blit"> 2036 1959 <!-- this mirrors VPC_RAST_STREAM_CNTL::DISCARD, although it seems it's unused --> 2037 1960 <bitfield name="RASTER_DISCARD" pos="0" type="boolean"/> 2038 1961 <bitfield name="UNK2" pos="2" type="boolean"/> 2039 1962 </reg32> 2040 2040 - <reg32 offset="0x9108" name="VPC_RAST_CNTL" usage="rp_blit"> 2041 2041 - <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> 2042 2042 - </reg32> 2043 1963 1964 1964 + <reg32 offset="0x9108" name="VPC_RAST_CNTL" type="a6xx_rast_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2044 1965 <bitset name="a6xx_pc_cntl" inline="yes"> 2045 1966 <bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/> 2046 1967 <bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/> ··· 2090 1991 <bitfield name="VIEWS" low="2" high="6" type="uint"/> 2091 1992 </bitset> 2092 1993 2093 2093 - <reg32 offset="0x9109" name="VPC_PC_CNTL" type="a6xx_pc_cntl" variants="A7XX-" usage="rp_blit"/> 2094 2094 - <reg32 offset="0x910a" name="VPC_GS_PARAM_0" type="a6xx_gs_param_0" variants="A7XX-" usage="rp_blit"/> 2095 2095 - <reg32 offset="0x910b" name="VPC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" variants="A7XX-" usage="rp_blit"/> 2096 2096 - <reg32 offset="0x910c" name="VPC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" variants="A7XX-" usage="rp_blit"/> 1994 1994 + <reg32 offset="0x9109" name="VPC_PC_CNTL" type="a6xx_pc_cntl" variants="A7XX" usage="rp_blit"/> 1995 1995 + <reg32 offset="0x910a" name="VPC_GS_PARAM_0" type="a6xx_gs_param_0" variants="A7XX" usage="rp_blit"/> 1996 1996 + <reg32 offset="0x910b" name="VPC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" variants="A7XX" usage="rp_blit"/> 1997 1997 + <reg32 offset="0x910c" name="VPC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" variants="A7XX" usage="rp_blit"/> 2097 1998 2098 1999 <enum name="a6xx_varying_interp_mode"> 2099 2000 <value value="0" name="INTERP_SMOOTH"/> ··· 2110 2011 </enum> 2111 2012 2112 2013 <!-- 0x9109-0x91ff invalid --> 2113 2113 - <array offset="0x9200" name="VPC_VARYING_INTERP_MODE" stride="1" length="8" usage="rp_blit"> 2014 2014 + <array offset="0x9200" name="VPC_VARYING_INTERP_MODE" stride="1" length="8" variants="A6XX-A7XX" usage="rp_blit"> 2114 2015 <doc>Packed array of a6xx_varying_interp_mode</doc> 2115 2016 <reg32 offset="0x0" name="MODE"/> 2116 2017 </array> 2117 2117 - <array offset="0x9208" name="VPC_VARYING_REPLACE_MODE_0" stride="1" length="8" usage="rp_blit"> 2018 2018 + <array offset="0x9208" name="VPC_VARYING_REPLACE_MODE" stride="1" length="8" variants="A6XX-A7XX" usage="rp_blit"> 2118 2019 <doc>Packed array of a6xx_varying_ps_repl_mode</doc> 2119 2020 <reg32 offset="0x0" name="MODE"/> 2120 2021 </array> ··· 2123 2024 <reg32 offset="0x9210" name="VPC_UNKNOWN_9210" low="0" high="31" variants="A6XX" usage="cmd"/> 2124 2025 <reg32 offset="0x9211" name="VPC_UNKNOWN_9211" low="0" high="31" variants="A6XX" usage="cmd"/> 2125 2026 2126 2126 - <array offset="0x9212" name="VPC_VARYING_LM_TRANSFER_CNTL_0" stride="1" length="4" usage="rp_blit"> 2027 2027 + <array offset="0x9212" name="VPC_VARYING_LM_TRANSFER_CNTL" stride="1" length="4" variants="A6XX-A7XX" usage="rp_blit"> 2127 2028 <!-- one bit per varying component: --> 2128 2029 <reg32 offset="0" name="DISABLE"/> 2129 2030 </array> 2130 2031 2131 2131 - <reg32 offset="0x9216" name="VPC_SO_MAPPING_WPTR" usage="rp_blit"> 2032 2032 + <bitset name="a6xx_vpc_so_mapping_wptr" inline="yes"> 2132 2033 <!-- 2133 2034 Choose which DWORD to write to. There is an array of 2134 2035 (4 * 64) DWORD's, dumped in the devcoredump at ··· 2155 2056 <bitfield name="ADDR" low="0" high="7" type="hex"/> 2156 2057 <!-- clear all A_EN and B_EN bits for all DWORD's --> 2157 2058 <bitfield name="RESET" pos="16" type="boolean"/> 2158 2158 - </reg32> 2159 2159 - <!-- special register, write multiple times to load SO program (not readable) --> 2160 2160 - <reg32 offset="0x9217" name="VPC_SO_MAPPING_PORT" usage="rp_blit"> 2059 2059 + </bitset> 2060 2060 + 2061 2061 + <reg32 offset="0x9216" name="VPC_SO_MAPPING_WPTR" type="a6xx_vpc_so_mapping_wptr" variants="A6XX-A7XX" usage="rp_blit"/> 2062 2062 + 2063 2063 + <bitset name="a6xx_vpc_so_mapping_port" inline="yes"> 2161 2064 <bitfield name="A_BUF" low="0" high="1" type="uint"/> 2162 2065 <bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/> 2163 2066 <bitfield name="A_EN" pos="11" type="boolean"/> 2164 2067 <bitfield name="B_BUF" low="12" high="13" type="uint"/> 2165 2068 <bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/> 2166 2069 <bitfield name="B_EN" pos="23" type="boolean"/> 2167 2167 - </reg32> 2070 2070 + </bitset> 2168 2071 2169 2169 - <reg64 offset="0x9218" name="VPC_SO_QUERY_BASE" type="waddress" align="32" usage="cmd"/> 2072 2072 + <!-- special register, write multiple times to load SO program (not readable) --> 2073 2073 + <reg32 offset="0x9217" name="VPC_SO_MAPPING_PORT" type="a6xx_vpc_so_mapping_port" variants="A6XX-A7XX" usage="rp_blit"/> 2170 2074 2171 2171 - <array offset="0x921a" name="VPC_SO" stride="7" length="4" usage="cmd"> 2075 2075 + <reg64 offset="0x9218" name="VPC_SO_QUERY_BASE" type="waddress" align="32" variants="A6XX-A7XX" usage="cmd"/> 2076 2076 + 2077 2077 + <array offset="0x921a" name="VPC_SO" stride="7" length="4" variants="A6XX-A7XX" usage="cmd"> 2172 2078 <reg64 offset="0" name="BUFFER_BASE" type="waddress" align="32"/> 2173 2079 <reg32 offset="2" name="BUFFER_SIZE" low="2" high="31" shr="2"/> 2174 2080 <reg32 offset="3" name="BUFFER_STRIDE" low="0" high="9" shr="2"/> ··· 2181 2077 <reg64 offset="5" name="FLUSH_BASE" type="waddress" align="32"/> 2182 2078 </array> 2183 2079 2184 2184 - <reg32 offset="0x9236" name="VPC_REPLACE_MODE_CNTL" usage="cmd"> 2080 2080 + <bitset name="a6xx_vpc_replace_mode_cntl" inline="yes"> 2185 2081 <bitfield name="INVERT" pos="0" type="boolean"/> 2186 2186 - </reg32> 2187 2187 - <!-- 0x9237-0x92ff invalid --> 2188 2188 - <!-- always 0x0 ? --> 2189 2189 - <reg32 offset="0x9300" name="VPC_UNKNOWN_9300" low="0" high="2" usage="cmd"/> 2082 2082 + </bitset> 2083 2083 + 2084 2084 + <reg32 offset="0x9236" name="VPC_REPLACE_MODE_CNTL" type="a6xx_vpc_replace_mode_cntl" variants="A6XX-A7XX" usage="cmd"/> 2085 2085 + 2086 2086 + <reg32 offset="0x9300" name="VPC_ROTATION_CNTL" low="0" high="2" variants="A6XX-A7XX" usage="cmd"/> 2190 2087 2191 2088 <bitset name="a6xx_vpc_xs_cntl" inline="yes"> 2192 2089 <doc> ··· 2206 2101 </doc> 2207 2102 </bitfield> 2208 2103 </bitset> 2209 2209 - <reg32 offset="0x9301" name="VPC_VS_CNTL" type="a6xx_vpc_xs_cntl" usage="rp_blit"/> 2210 2210 - <reg32 offset="0x9302" name="VPC_GS_CNTL" type="a6xx_vpc_xs_cntl" usage="rp_blit"/> 2211 2211 - <reg32 offset="0x9303" name="VPC_DS_CNTL" type="a6xx_vpc_xs_cntl" usage="rp_blit"/> 2212 2104 2213 2213 - <reg32 offset="0x9304" name="VPC_PS_CNTL" usage="rp_blit"> 2105 2105 + <reg32 offset="0x9301" name="VPC_VS_CNTL" type="a6xx_vpc_xs_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2106 2106 + <reg32 offset="0x9302" name="VPC_GS_CNTL" type="a6xx_vpc_xs_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2107 2107 + <reg32 offset="0x9303" name="VPC_DS_CNTL" type="a6xx_vpc_xs_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2108 2108 + 2109 2109 + <bitset name="a6xx_vpc_ps_cntl" inline="yes"> 2214 2110 <bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/> 2215 2111 <!-- for fixed-function (i.e. no GS) gl_PrimitiveID in FS --> 2216 2112 <bitfield name="PRIMIDLOC" low="8" high="15" type="uint"/> ··· 2228 2122 ViewID through the VS. 2229 2123 </doc> 2230 2124 </bitfield> 2231 2231 - </reg32> 2125 2125 + </bitset> 2232 2126 2233 2233 - <reg32 offset="0x9305" name="VPC_SO_CNTL" usage="rp_blit"> 2127 2127 + <reg32 offset="0x9304" name="VPC_PS_CNTL" type="a6xx_vpc_ps_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2128 2128 + 2129 2129 + <bitset name="a6xx_vpc_so_cntl" inline="yes"> 2234 2130 <!-- 2235 2131 It's offset by 1, and 0 means "disabled" 2236 2132 --> ··· 2241 2133 <bitfield name="BUF2_STREAM" low="6" high="8" type="uint"/> 2242 2134 <bitfield name="BUF3_STREAM" low="9" high="11" type="uint"/> 2243 2135 <bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/> 2244 2244 - </reg32> 2245 2245 - <reg32 offset="0x9306" name="VPC_SO_OVERRIDE" usage="rp_blit"> 2136 2136 + </bitset> 2137 2137 + 2138 2138 + <reg32 offset="0x9305" name="VPC_SO_CNTL" type="a6xx_vpc_so_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2139 2139 + 2140 2140 + <bitset name="a6xx_so_override" inline="yes"> 2246 2141 <bitfield name="DISABLE" pos="0" type="boolean"/> 2247 2247 - </reg32> 2248 2248 - <reg32 offset="0x9307" name="VPC_PS_RAST_CNTL" variants="A6XX-" usage="rp_blit"> <!-- A702 + A7xx --> 2249 2249 - <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> 2250 2250 - </reg32> 2251 2251 - <reg32 offset="0x9308" name="VPC_ATTR_BUF_GMEM_SIZE" variants="A7XX-" usage="rp_blit"> 2252 2252 - <bitfield name="SIZE_GMEM" low="0" high="31"/> 2253 2253 - </reg32> 2254 2254 - <reg32 offset="0x9309" name="VPC_ATTR_BUF_GMEM_BASE" variants="A7XX-" usage="rp_blit"> 2255 2255 - <bitfield name="BASE_GMEM" low="0" high="31"/> 2256 2256 - </reg32> 2257 2257 - <reg32 offset="0x9b09" name="PC_ATTR_BUF_GMEM_SIZE" variants="A7XX-" usage="rp_blit"> 2258 2258 - <bitfield name="SIZE_GMEM" low="0" high="31"/> 2259 2259 - </reg32> 2142 2142 + </bitset> 2143 2143 + 2144 2144 + <reg32 offset="0x9306" name="VPC_SO_OVERRIDE" type="a6xx_so_override" variants="A6XX-A7XX" usage="rp_blit"/> 2145 2145 + 2146 2146 + <reg32 offset="0x9807" name="PC_DGEN_SO_OVERRIDE" type="a6xx_so_override" variants="A7XX" usage="rp_blit"/> 2147 2147 + 2148 2148 + <reg32 offset="0x9307" name="VPC_PS_RAST_CNTL" type="a6xx_rast_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2149 2149 + 2150 2150 + <reg32 offset="0x9308" name="VPC_ATTR_BUF_GMEM_SIZE" variants="A7XX" type="uint" usage="rp_blit"/> 2151 2151 + <reg32 offset="0x9309" name="VPC_ATTR_BUF_GMEM_BASE" variants="A7XX" type="uint" usage="rp_blit"/> 2152 2152 + 2153 2153 + <reg32 offset="0x9b09" name="PC_ATTR_BUF_GMEM_SIZE" variants="A7XX" type="uint" usage="rp_blit"/> 2154 2154 + 2155 2155 + <reg32 offset="0x930a" name="VPC_UNKNOWN_930A" variants="A7XX"/> 2156 2156 + 2157 2157 + <reg32 offset="0x960a" name="VPC_FLATSHADE_MODE_CNTL" variants="A7XX"/> 2260 2158 2261 2159 <!-- 0x9307-0x95ff invalid --> 2262 2160 ··· 2277 2163 <!-- TODO: regs from 0x9624-0x963a --> 2278 2164 <!-- 0x963b-0x97ff invalid --> 2279 2165 2280 2280 - <reg32 offset="0x9800" name="PC_HS_PARAM_0" low="0" high="5" type="uint" usage="rp_blit"/> 2166 2166 + <reg32 offset="0x9800" name="PC_HS_PARAM_0" low="0" high="5" type="uint" variants="A6XX-A7XX" usage="rp_blit"/> 2281 2167 2282 2282 - <!-- always 0x0 ? --> 2283 2283 - <reg32 offset="0x9801" name="PC_HS_PARAM_1" usage="rp_blit"> 2168 2168 + <bitset name="a6xx_pc_hs_param_1" inline="yes"> 2284 2169 <bitfield name="SIZE" low="0" high="10" type="uint"/> 2285 2170 <bitfield name="UNK13" pos="13"/> 2286 2286 - </reg32> 2171 2171 + </bitset> 2287 2172 2288 2288 - <reg32 offset="0x9802" name="PC_DS_PARAM" usage="rp_blit"> 2173 2173 + <reg32 offset="0x9801" name="PC_HS_PARAM_1" type="a6xx_pc_hs_param_1" variants="A6XX-A7XX" usage="rp_blit"/> 2174 2174 + 2175 2175 + <bitset name="a6xx_pc_ds_param" inline="yes"> 2289 2176 <bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/> 2290 2177 <bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/> 2291 2291 - </reg32> 2178 2178 + </bitset> 2292 2179 2293 2293 - <reg32 offset="0x9803" name="PC_RESTART_INDEX" low="0" high="31" type="uint" usage="rp_blit"/> 2294 2294 - <reg32 offset="0x9804" name="PC_MODE_CNTL" low="0" high="7" usage="rp_blit"/> 2180 2180 + <reg32 offset="0x9802" name="PC_DS_PARAM" type="a6xx_pc_ds_param" variants="A6XX-A7XX" usage="rp_blit"/> 2181 2181 + 2182 2182 + <reg32 offset="0x9803" name="PC_RESTART_INDEX" low="0" high="31" type="uint" variants="A6XX-A7XX" usage="rp_blit"/> 2183 2183 + 2184 2184 + <reg32 offset="0x9804" name="PC_MODE_CNTL" low="0" high="7" variants="A6XX-A7XX" usage="rp_blit"/> 2295 2185 2296 2186 <reg32 offset="0x9805" name="PC_POWER_CNTL" low="0" high="2" usage="rp_blit"/> 2297 2187 2298 2298 - <reg32 offset="0x9806" name="PC_PS_CNTL" usage="rp_blit"> 2188 2188 + <bitset name="a6xx_pc_ps_cntl" inline="yes"> 2299 2189 <bitfield name="PRIMITIVEIDEN" pos="0" type="boolean"/> 2300 2300 - </reg32> 2190 2190 + </bitset> 2191 2191 + 2192 2192 + <reg32 offset="0x9806" name="PC_PS_CNTL" type="a6xx_pc_ps_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2193 2193 + 2194 2194 + <bitset name="a6xx_pc_dgen_so_cntl" inline="yes"> 2195 2195 + <bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/> 2196 2196 + </bitset> 2301 2197 2302 2198 <!-- New in a6xx gen3+ --> 2303 2303 - <reg32 offset="0x9808" name="PC_DGEN_SO_CNTL" usage="rp_blit"> 2304 2304 - <bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/> 2305 2305 - </reg32> 2199 2199 + <reg32 offset="0x9808" name="PC_DGEN_SO_CNTL" type="a6xx_pc_dgen_so_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2306 2200 2307 2307 - <reg32 offset="0x980a" name="PC_DGEN_SU_CONSERVATIVE_RAS_CNTL"> 2201 2201 + <bitset name="a6xx_pc_dgen_su_conservative_ras_cntl" inline="yes"> 2308 2202 <bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/> 2309 2309 - </reg32> 2310 2310 - <!-- 0x980b-0x983f invalid --> 2203 2203 + </bitset> 2204 2204 + 2205 2205 + <reg32 offset="0x980a" name="PC_DGEN_SU_CONSERVATIVE_RAS_CNTL" type="a6xx_pc_dgen_su_conservative_ras_cntl" variants="A6XX-A7XX"/> 2311 2206 2312 2207 <!-- 0x9840 - 0x9842 are not readable --> 2313 2313 - <reg32 offset="0x9840" name="PC_DRAW_INITIATOR"> 2208 2208 + <bitset name="a6xx_draw_initiator" inline="yes"> 2314 2209 <bitfield name="STATE_ID" low="0" high="7"/> 2315 2315 - </reg32> 2210 2210 + </bitset> 2316 2211 2317 2317 - <reg32 offset="0x9841" name="PC_KERNEL_INITIATOR"> 2318 2318 - <bitfield name="STATE_ID" low="0" high="7"/> 2319 2319 - </reg32> 2212 2212 + <reg32 offset="0x9840" name="PC_DRAW_INITIATOR" type="a6xx_draw_initiator" variants="A6XX-A7XX"/> 2213 2213 + <reg32 offset="0x9841" name="PC_KERNEL_INITIATOR" type="a6xx_draw_initiator" variants="A6XX-A7XX"/> 2320 2214 2321 2321 - <reg32 offset="0x9842" name="PC_EVENT_INITIATOR"> 2215 2215 + <bitset name="a6xx_event_initiator" inline="yes"> 2322 2216 <!-- I think only the low bit is actually used? --> 2323 2217 <bitfield name="STATE_ID" low="16" high="23"/> 2324 2218 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 2325 2325 - </reg32> 2219 2219 + </bitset> 2220 2220 + 2221 2221 + <reg32 offset="0x9842" name="PC_EVENT_INITIATOR" type="a6xx_event_initiator" variants="A6XX-A7XX"/> 2326 2222 2327 2223 <!-- 2328 2224 0x9880 written in a lot of places by SQE, same value gets written ··· 2343 2219 2344 2220 <!-- 0x9843-0x997f invalid --> 2345 2221 2346 2346 - <reg32 offset="0x9981" name="PC_DGEN_RAST_CNTL" variants="A6XX" usage="rp_blit"> 2347 2347 - <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> 2348 2348 - </reg32> 2349 2349 - <reg32 offset="0x9809" name="PC_DGEN_RAST_CNTL" variants="A7XX-" usage="rp_blit"> 2350 2350 - <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> 2351 2351 - </reg32> 2352 2352 - 2353 2353 - <reg32 offset="0x9980" name="VPC_RAST_STREAM_CNTL" variants="A6XX" usage="rp_blit"> 2354 2354 - <!-- which stream to send to GRAS --> 2355 2355 - <bitfield name="STREAM" low="0" high="1" type="uint"/> 2356 2356 - <!-- discard primitives before rasterization --> 2357 2357 - <bitfield name="DISCARD" pos="2" type="boolean"/> 2358 2358 - </reg32> 2359 2359 - <!-- VPC_RAST_STREAM_CNTL --> 2360 2360 - <reg32 offset="0x9107" name="VPC_RAST_STREAM_CNTL" variants="A7XX-" usage="rp_blit"> 2361 2361 - <!-- which stream to send to GRAS --> 2362 2362 - <bitfield name="STREAM" low="0" high="1" type="uint"/> 2363 2363 - <!-- discard primitives before rasterization --> 2364 2364 - <bitfield name="DISCARD" pos="2" type="boolean"/> 2365 2365 - </reg32> 2366 2366 - <reg32 offset="0x9317" name="VPC_RAST_STREAM_CNTL_V2" variants="A7XX-" usage="rp_blit"> 2367 2367 - <!-- which stream to send to GRAS --> 2368 2368 - <bitfield name="STREAM" low="0" high="1" type="uint"/> 2369 2369 - <!-- discard primitives before rasterization --> 2370 2370 - <bitfield name="DISCARD" pos="2" type="boolean"/> 2371 2371 - </reg32> 2222 2222 + <reg32 offset="0x9981" name="PC_DGEN_RAST_CNTL" type="a6xx_rast_cntl" variants="A6XX" usage="rp_blit"/> 2223 2223 + <reg32 offset="0x9809" name="PC_DGEN_RAST_CNTL" type="a6xx_rast_cntl" variants="A7XX" usage="rp_blit"/> 2372 2224 2373 2225 <!-- Both are a750+. 2374 2226 Probably needed to correctly overlap execution of several draws. 2375 2227 --> 2376 2376 - <reg32 offset="0x9885" name="PC_HS_BUFFER_SIZE" variants="A7XX-" usage="cmd"/> 2228 2228 + <reg32 offset="0x9885" name="PC_HS_BUFFER_SIZE" variants="A7XX" usage="cmd"/> 2377 2229 <!-- Blob adds a bit more space {0x10, 0x20, 0x30, 0x40} bytes, but the meaning of 2378 2230 this additional space is not known. 2379 2231 --> 2380 2380 - <reg32 offset="0x9886" name="PC_TF_BUFFER_SIZE" variants="A7XX-" usage="cmd"/> 2232 2232 + <reg32 offset="0x9886" name="PC_TF_BUFFER_SIZE" variants="A7XX" usage="cmd"/> 2381 2233 2382 2234 <!-- 0x9982-0x9aff invalid --> 2383 2235 2384 2384 - <reg32 offset="0x9b00" name="PC_CNTL" type="a6xx_pc_cntl" usage="rp_blit"/> 2236 2236 + <reg32 offset="0x9b00" name="PC_CNTL" type="a6xx_pc_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2385 2237 2386 2238 <bitset name="a6xx_pc_xs_cntl" inline="yes"> 2387 2239 <doc> ··· 2370 2270 <bitfield name="LAYER" pos="9" type="boolean"/> 2371 2271 <bitfield name="VIEW" pos="10" type="boolean"/> 2372 2272 <!-- note: PC_VS_CNTL doesn't have the PRIMITIVE_ID bit --> 2273 2273 + <!-- since HS can't output anything, only PRIMITIVE_ID is valid --> 2373 2274 <bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/> 2374 2275 <bitfield name="CLIP_MASK" low="16" high="23" type="uint"/> 2375 2276 <bitfield name="SHADINGRATE" pos="24" type="boolean" variants="A7XX-"/> 2376 2277 </bitset> 2377 2278 2378 2378 - <reg32 offset="0x9b01" name="PC_VS_CNTL" type="a6xx_pc_xs_cntl" usage="rp_blit"/> 2379 2379 - <reg32 offset="0x9b02" name="PC_GS_CNTL" type="a6xx_pc_xs_cntl" usage="rp_blit"/> 2380 2380 - <!-- since HS can't output anything, only PRIMITIVE_ID is valid --> 2381 2381 - <reg32 offset="0x9b03" name="PC_HS_CNTL" type="a6xx_pc_xs_cntl" usage="rp_blit"/> 2382 2382 - <reg32 offset="0x9b04" name="PC_DS_CNTL" type="a6xx_pc_xs_cntl" usage="rp_blit"/> 2279 2279 + <reg32 offset="0x9b01" name="PC_VS_CNTL" type="a6xx_pc_xs_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2280 2280 + <reg32 offset="0x9b02" name="PC_GS_CNTL" type="a6xx_pc_xs_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2281 2281 + <reg32 offset="0x9b03" name="PC_HS_CNTL" type="a6xx_pc_xs_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2282 2282 + <reg32 offset="0x9b04" name="PC_DS_CNTL" type="a6xx_pc_xs_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2383 2283 2384 2384 - <reg32 offset="0x9b05" name="PC_GS_PARAM_0" type="a6xx_gs_param_0" usage="rp_blit"/> 2284 2284 + <reg32 offset="0x9b05" name="PC_GS_PARAM_0" type="a6xx_gs_param_0" variants="A6XX-A7XX" usage="rp_blit"/> 2385 2285 2386 2286 <reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6" variants="A6XX" usage="rp_blit"> 2387 2287 <doc> ··· 2390 2290 <bitfield name="STRIDE_IN_VPC" low="0" high="10" type="uint"/> 2391 2291 </reg32> 2392 2292 2393 2393 - <reg32 offset="0x9b07" name="PC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" usage="rp_blit"/> 2293 2293 + <reg32 offset="0x9b07" name="PC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2394 2294 <!-- mask of enabled views, doesn't exist on A630 --> 2395 2395 - <reg32 offset="0x9b08" name="PC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" usage="rp_blit"/> 2295 2295 + <reg32 offset="0x9b08" name="PC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" variants="A6XX-A7XX" usage="rp_blit"/> 2396 2296 <!-- 0x9b09-0x9bff invalid --> 2397 2297 <reg32 offset="0x9c00" name="PC_2D_EVENT_CMD"> 2398 2298 <!-- special register (but note first 8 bits can be written/read) --> ··· 2403 2303 <!-- TODO: 0x9e00-0xa000 range incomplete --> 2404 2304 <reg32 offset="0x9e00" name="PC_DBG_ECO_CNTL"/> 2405 2305 <reg32 offset="0x9e01" name="PC_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 2406 2406 - <reg64 offset="0x9e04" name="PC_DMA_BASE"/> 2407 2407 - <reg32 offset="0x9e06" name="PC_DMA_OFFSET" type="uint"/> 2408 2408 - <reg32 offset="0x9e07" name="PC_DMA_SIZE" type="uint"/> 2409 2409 - <reg64 offset="0x9e08" name="PC_TESS_BASE" variants="A6XX" type="waddress" align="32" usage="cmd"/> 2410 2410 - <reg64 offset="0x9810" name="PC_TESS_BASE" variants="A7XX-" type="waddress" align="32" usage="cmd"/> 2306 2306 + <reg64 offset="0x9e04" name="PC_DMA_BASE" type="address" variants="A6XX-A7XX"/> 2307 2307 + <reg32 offset="0x9e06" name="PC_DMA_OFFSET" type="uint" variants="A6XX-A7XX"/> 2308 2308 + <reg32 offset="0x9e07" name="PC_DMA_SIZE" type="uint" variants="A6XX-A7XX"/> 2411 2309 2412 2412 - <reg32 offset="0x9e0b" name="PC_DRAWCALL_CNTL" type="vgt_draw_initiator_a4xx"> 2310 2310 + <reg64 offset="0x9e08" name="PC_TESS_BASE" variants="A6XX" type="waddress" align="32" usage="cmd"/> 2311 2311 + <reg64 offset="0x9810" name="PC_TESS_BASE" variants="A7XX" type="waddress" align="32" usage="cmd"/> 2312 2312 + 2313 2313 + <reg32 offset="0x9e0b" name="PC_DRAWCALL_CNTL" type="vgt_draw_initiator_a4xx" variants="A6XX-A7XX"> 2413 2314 <doc> 2414 2315 Possibly not really "initiating" the draw but the layout is similar 2415 2316 to VGT_DRAW_INITIATOR on older gens 2416 2317 </doc> 2417 2318 </reg32> 2418 2418 - <reg32 offset="0x9e0c" name="PC_DRAWCALL_INSTANCE_NUM" type="uint"/> 2419 2419 - <reg32 offset="0x9e0d" name="PC_DRAWCALL_SIZE" type="uint"/> 2319 2319 + <reg32 offset="0x9e0c" name="PC_DRAWCALL_INSTANCE_NUM" type="uint" variants="A6XX-A7XX"/> 2320 2320 + <reg32 offset="0x9e0d" name="PC_DRAWCALL_SIZE" type="uint" variants="A6XX-A7XX"/> 2420 2321 2421 2322 <!-- These match the contents of CP_SET_BIN_DATA (not written directly) --> 2422 2422 - <reg32 offset="0x9e11" name="PC_VIS_STREAM_CNTL"> 2323 2323 + <bitset name="a6xx_pc_vis_stream_cntl" inline="yes"> 2423 2324 <bitfield name="UNK0" low="0" high="15"/> 2424 2325 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/> 2425 2326 <bitfield name="VSC_N" low="22" high="26" type="uint"/> 2426 2426 - </reg32> 2427 2427 - <reg64 offset="0x9e12" name="PC_PVIS_STREAM_BIN_BASE" type="waddress" align="32"/> 2428 2428 - <reg64 offset="0x9e14" name="PC_DVIS_STREAM_BIN_BASE" type="waddress" align="32"/> 2327 2327 + </bitset> 2429 2328 2430 2430 - <reg32 offset="0x9e1c" name="PC_DRAWCALL_CNTL_OVERRIDE"> 2329 2329 + <reg32 offset="0x9e11" name="PC_VIS_STREAM_CNTL" type="a6xx_pc_vis_stream_cntl" variants="A6XX-A7XX"/> 2330 2330 + <reg64 offset="0x9e12" name="PC_PVIS_STREAM_BIN_BASE" type="waddress" align="32" variants="A6XX-A7XX"/> 2331 2331 + <reg64 offset="0x9e14" name="PC_DVIS_STREAM_BIN_BASE" type="waddress" align="32" variants="A6XX-A7XX"/> 2332 2332 + 2333 2333 + <bitset name="a6xx_pc_drawcall_cntl_override" inline="yes"> 2431 2334 <doc>Written by CP_SET_VISIBILITY_OVERRIDE handler</doc> 2432 2335 <bitfield name="OVERRIDE" pos="0" type="boolean"/> 2433 2433 - </reg32> 2336 2336 + </bitset> 2337 2337 + 2338 2338 + <reg32 offset="0x9e1c" name="PC_DRAWCALL_CNTL_OVERRIDE" type="a6xx_pc_drawcall_cntl_override" variants="A6XX-A7XX"/> 2434 2339 2435 2340 <reg32 offset="0x9e24" name="PC_UNKNOWN_9E24" variants="A7XX-" usage="cmd"/> 2436 2341 ··· 3041 2936 <reg32 offset="0xa9b3" name="SP_CS_PROGRAM_COUNTER_OFFSET" type="uint" usage="cmd"/> 3042 2937 <reg64 offset="0xa9b4" name="SP_CS_BASE" type="address" align="32" usage="cmd"/> 3043 2938 <reg32 offset="0xa9b6" name="SP_CS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="cmd"/> 3044 3044 - <reg64 offset="0xa9b7" name="SP_CS_PVT_MEM_BASE" align="32" usage="cmd"/> 2939 2939 + <reg64 offset="0xa9b7" name="SP_CS_PVT_MEM_BASE" type="waddress" align="32" usage="cmd"/> 3045 2940 <reg32 offset="0xa9b9" name="SP_CS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="cmd"/> 3046 2941 <reg32 offset="0xa9ba" name="SP_CS_TSIZE" low="0" high="7" type="uint" usage="cmd"/> 3047 2942 <reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config" usage="cmd"/> ··· 3126 3021 UAV state for compute shader: 3127 3022 --> 3128 3023 <reg64 offset="0xa9f2" name="SP_CS_UAV_BASE" type="address" align="16" variants="A6XX"/> 3129 3129 - <reg64 offset="0xa9f8" name="SP_CS_UAV_BASE" type="address" align="16" variants="A7XX"/> 3024 3024 + <reg64 offset="0xa9f8" name="SP_CS_UAV_BASE" type="address" align="16" variants="A7XX-"/> 3130 3025 <reg32 offset="0xaa00" name="SP_CS_USIZE" low="0" high="6" type="uint"/> 3131 3026 3132 3027 <!-- Correlated with avgs/uvgs usage in FS --> ··· 3209 3104 instructions VS/HS/DS/GS/FS. See SP_CS_UAV_BASE_* for compute shaders. 3210 3105 --> 3211 3106 <reg64 offset="0xab1a" name="SP_GFX_UAV_BASE" type="address" align="16" usage="cmd"/> 3212 3212 - <reg32 offset="0xab20" name="SP_GFX_USIZE" low="0" high="6" type="uint" usage="cmd"/> 3107 3107 + <reg32 offset="0xab20" name="SP_GFX_USIZE" low="0" high="6" type="uint" variants="A6XX-A7XX" usage="cmd"/> 3213 3108 3214 3214 - <reg32 offset="0xab22" name="SP_UNKNOWN_AB22" variants="A7XX-" usage="cmd"/> 3109 3109 + <reg32 offset="0xab22" name="SP_UNKNOWN_AB22" variants="A7XX" usage="cmd"/> 3110 3110 + 3111 3111 + <enum name="a6xx_sp_a2d_output_ifmt_type"> 3112 3112 + <value name="OUTPUT_IFMT_2D_FLOAT" value="0"/> 3113 3113 + <value name="OUTPUT_IFMT_2D_SINT" value="1"/> 3114 3114 + <value name="OUTPUT_IFMT_2D_UINT" value="2"/> 3115 3115 + </enum> 3215 3116 3216 3117 <bitset name="a6xx_sp_a2d_output_info" inline="yes"> 3217 3217 - <bitfield name="NORM" pos="0" type="boolean"/> 3218 3218 - <bitfield name="SINT" pos="1" type="boolean"/> 3219 3219 - <bitfield name="UINT" pos="2" type="boolean"/> 3118 3118 + <bitfield name="HALF_PRECISION" pos="0" type="boolean"/> 3119 3119 + <bitfield name="IFMT_TYPE" low="1" high="2" type="a6xx_sp_a2d_output_ifmt_type"/> 3220 3120 <!-- looks like HW only cares about the base type of this format, 3221 3121 which matches the ifmt? --> 3222 3122 <bitfield name="COLOR_FORMAT" low="3" high="10" type="a6xx_format"/> ··· 3266 3156 <reg32 offset="0xae6b" name="SP_UNKNOWN_AE6B" variants="A7XX-" usage="cmd"/> 3267 3157 <reg32 offset="0xae6c" name="SP_HLSQ_DBG_ECO_CNTL" variants="A7XX-" usage="cmd"/> 3268 3158 <reg32 offset="0xae6d" name="SP_READ_SEL" variants="A7XX-"> 3269 3269 - <bitfield name="LOCATION" low="18" high="19" type="a7xx_state_location"/> 3159 3159 + <bitfield name="LOCATION" low="18" high="20" type="a7xx_state_location"/> 3270 3160 <bitfield name="PIPE" low="16" high="17" type="a7xx_pipe"/> 3271 3161 <bitfield name="STATETYPE" low="8" high="15" type="a7xx_statetype_id"/> 3272 3162 <bitfield name="USPTP" low="4" high="7"/> ··· 3302 3192 3303 3193 <!-- looks to work in the same way as a5xx: --> 3304 3194 <reg64 offset="0xb302" name="TPL1_GFX_BORDER_COLOR_BASE" type="address" align="128" usage="cmd"/> 3305 3305 - <reg32 offset="0xb304" name="TPL1_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" usage="rp_blit"/> 3195 3195 + <reg32 offset="0xb304" name="TPL1_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 3306 3196 <reg32 offset="0xb305" name="TPL1_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> 3307 3197 <reg32 offset="0xb306" name="TPL1_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> 3308 3198 <reg32 offset="0xb307" name="TPL1_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/> ··· 3342 3232 </reg32> 3343 3233 3344 3234 <reg32 offset="0xb2c0" name="TPL1_A2D_SRC_TEXTURE_INFO" type="a6xx_a2d_src_texture_info" variants="A7XX-" usage="rp_blit"/> 3345 3345 - <reg32 offset="0xb2c1" name="TPL1_A2D_SRC_TEXTURE_SIZE" variants="A7XX"> 3235 3235 + <reg32 offset="0xb2c1" name="TPL1_A2D_SRC_TEXTURE_SIZE" variants="A7XX-"> 3346 3236 <bitfield name="WIDTH" low="0" high="14" type="uint"/> 3347 3237 <bitfield name="HEIGHT" low="15" high="29" type="uint"/> 3348 3238 </reg32> 3349 3239 <reg64 offset="0xb2c2" name="TPL1_A2D_SRC_TEXTURE_BASE" type="address" align="16" variants="A7XX-" usage="rp_blit"/> 3350 3350 - <reg32 offset="0xb2c4" name="TPL1_A2D_SRC_TEXTURE_PITCH" variants="A7XX"> 3240 3240 + <reg32 offset="0xb2c4" name="TPL1_A2D_SRC_TEXTURE_PITCH" variants="A7XX-"> 3351 3241 <!-- 3352 3242 Bits from 3..9 must be zero unless 'TPL1_A2D_BLT_CNTL::TYPE' 3353 3243 is A6XX_TEX_IMG_BUFFER, which allows for lower alignment. ··· 3380 3270 <reg32 offset="0xb2ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A7XX"/> 3381 3271 <reg32 offset="0xb2cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30" variants="A7XX"/> 3382 3272 <reg32 offset="0xb2d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29" variants="A7XX"/> 3383 3383 - <reg32 offset="0xb2d1" name="TPL1_A2D_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX"/> 3273 3273 + <reg32 offset="0xb2d1" name="TPL1_A2D_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX-"/> 3384 3274 <reg32 offset="0xb2d2" name="TPL1_A2D_BLT_CNTL" variants="A7XX-" usage="rp_blit"> 3385 3275 <bitfield name="RAW_COPY" pos="0" type="boolean"/> 3386 3276 <bitfield name="START_OFFSET_TEXELS" low="16" high="21"/> 3387 3277 <bitfield name="TYPE" low="29" high="31" type="a6xx_tex_type"/> 3388 3278 </reg32> 3389 3389 - <reg32 offset="0xab21" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX-" usage="rp_blit"/> 3279 3279 + <reg32 offset="0xab21" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX" usage="rp_blit"/> 3390 3280 3391 3281 <!-- always 0x100000 or 0x1000000? --> 3392 3282 <reg32 offset="0xb600" name="TPL1_DBG_ECO_CNTL" low="0" high="25" usage="cmd"/> ··· 3406 3296 </reg32> 3407 3297 <reg32 offset="0xb605" name="TPL1_UNKNOWN_B605" low="0" high="7" type="uint" variants="A6XX" usage="cmd"/> <!-- always 0x0 or 0x44 ? --> 3408 3298 3409 3409 - <reg32 offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0" low="0" high="29" variants="A6XX"/> 3410 3410 - <reg32 offset="0xb609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1" low="0" high="29" variants="A6XX"/> 3411 3411 - <reg32 offset="0xb60a" name="TPL1_BICUBIC_WEIGHTS_TABLE_2" low="0" high="29" variants="A6XX"/> 3412 3412 - <reg32 offset="0xb60b" name="TPL1_BICUBIC_WEIGHTS_TABLE_3" low="0" high="29" variants="A6XX"/> 3413 3413 - <reg32 offset="0xb60c" name="TPL1_BICUBIC_WEIGHTS_TABLE_4" low="0" high="29" variants="A6XX"/> 3299 3299 + <array offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE" stride="1" length="5" variants="A6XX"> 3300 3300 + <reg32 offset="0" name="REG" low="0" high="29"/> 3301 3301 + </array> 3414 3302 3415 3415 - <reg32 offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0" low="0" high="29" variants="A7XX" usage="cmd"/> 3416 3416 - <reg32 offset="0xb609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1" low="0" high="29" variants="A7XX" usage="cmd"/> 3417 3417 - <reg32 offset="0xb60a" name="TPL1_BICUBIC_WEIGHTS_TABLE_2" low="0" high="29" variants="A7XX" usage="cmd"/> 3418 3418 - <reg32 offset="0xb60b" name="TPL1_BICUBIC_WEIGHTS_TABLE_3" low="0" high="29" variants="A7XX" usage="cmd"/> 3419 3419 - <reg32 offset="0xb60c" name="TPL1_BICUBIC_WEIGHTS_TABLE_4" low="0" high="29" variants="A7XX" usage="cmd"/> 3303 3303 + <array offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE" stride="1" length="5" variants="A7XX"> 3304 3304 + <reg32 offset="0" name="REG" low="0" high="29" usage="cmd"/> 3305 3305 + </array> 3420 3306 3421 3307 <array offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="12" variants="A6XX"/> 3422 3308 <array offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="18" variants="A7XX"/> ··· 3744 3638 <reg32 offset="0xbb10" name="SP_PS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="rp_blit"/> 3745 3639 <reg32 offset="0xab03" name="SP_PS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="rp_blit"/> 3746 3640 3747 3747 - <array offset="0xab40" name="SP_SHARED_CONSTANT_GFX_0" stride="1" length="64" variants="A7XX-"/> 3641 3641 + <array offset="0xab40" name="SP_SHARED_CONSTANT_GFX" stride="1" length="64" variants="A7XX"/> 3748 3642 3749 3643 <reg32 offset="0xbb11" name="HLSQ_SHARED_CONSTS" variants="A6XX" usage="cmd"> 3750 3644 <doc> ··· 3906 3800 <reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/> 3907 3801 </domain> 3908 3802 3909 3909 - <domain name="A7XX_CX_DBGC" width="32"> 3803 3803 + <domain name="A7XX_CX_DBGC" width="32" varset="chip"> 3910 3804 <!-- Bitfields shifted, but otherwise the same: --> 3911 3805 <reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A" variants="A7XX-"> 3912 3806 <bitfield high="7" low="0" name="PING_INDEX"/>

-40

drivers/gpu/drm/msm/registers/adreno/a6xx_descriptors.xml

reviewed

··· 9 9 10 10 <domain name="A6XX_TEX_SAMP" width="32"> 11 11 <doc>Texture sampler dwords</doc> 12 12 - <enum name="a6xx_tex_filter"> <!-- same as a4xx? --> 13 13 - <value name="A6XX_TEX_NEAREST" value="0"/> 14 14 - <value name="A6XX_TEX_LINEAR" value="1"/> 15 15 - <value name="A6XX_TEX_ANISO" value="2"/> 16 16 - <value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only --> 17 17 - </enum> 18 18 - <enum name="a6xx_tex_clamp"> <!-- same as a4xx? --> 19 19 - <value name="A6XX_TEX_REPEAT" value="0"/> 20 20 - <value name="A6XX_TEX_CLAMP_TO_EDGE" value="1"/> 21 21 - <value name="A6XX_TEX_MIRROR_REPEAT" value="2"/> 22 22 - <value name="A6XX_TEX_CLAMP_TO_BORDER" value="3"/> 23 23 - <value name="A6XX_TEX_MIRROR_CLAMP" value="4"/> 24 24 - </enum> 25 25 - <enum name="a6xx_tex_aniso"> <!-- same as a4xx? --> 26 26 - <value name="A6XX_TEX_ANISO_1" value="0"/> 27 27 - <value name="A6XX_TEX_ANISO_2" value="1"/> 28 28 - <value name="A6XX_TEX_ANISO_4" value="2"/> 29 29 - <value name="A6XX_TEX_ANISO_8" value="3"/> 30 30 - <value name="A6XX_TEX_ANISO_16" value="4"/> 31 31 - </enum> 32 32 - <enum name="a6xx_reduction_mode"> 33 33 - <value name="A6XX_REDUCTION_MODE_AVERAGE" value="0"/> 34 34 - <value name="A6XX_REDUCTION_MODE_MIN" value="1"/> 35 35 - <value name="A6XX_REDUCTION_MODE_MAX" value="2"/> 36 36 - </enum> 37 37 - <enum name="a6xx_fast_border_color"> 38 38 - <!-- R B G A --> 39 39 - <value name="A6XX_BORDER_COLOR_0_0_0_0" value="0"/> 40 40 - <value name="A6XX_BORDER_COLOR_0_0_0_1" value="1"/> 41 41 - <value name="A6XX_BORDER_COLOR_1_1_1_0" value="2"/> 42 42 - <value name="A6XX_BORDER_COLOR_1_1_1_1" value="3"/> 43 43 - </enum> 44 12 45 13 <reg32 offset="0" name="0"> 46 14 <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/> ··· 47 79 48 80 <domain name="A6XX_TEX_CONST" width="32" varset="chip"> 49 81 <doc>Texture constant dwords</doc> 50 50 - <enum name="a6xx_tex_swiz"> <!-- same as a4xx? --> 51 51 - <value name="A6XX_TEX_X" value="0"/> 52 52 - <value name="A6XX_TEX_Y" value="1"/> 53 53 - <value name="A6XX_TEX_Z" value="2"/> 54 54 - <value name="A6XX_TEX_W" value="3"/> 55 55 - <value name="A6XX_TEX_ZERO" value="4"/> 56 56 - <value name="A6XX_TEX_ONE" value="5"/> 57 57 - </enum> 58 82 <reg32 offset="0" name="0"> 59 83 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/> 60 84 <bitfield name="SRGB" pos="2" type="boolean"/>

+48 -2

drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml

reviewed

··· 320 320 16b float: 3 321 321 --> 322 322 <enum name="a6xx_2d_ifmt"> 323 323 - <value value="0x10" name="R2D_UNORM8"/> 324 323 <value value="0x7" name="R2D_INT32"/> 325 324 <value value="0x6" name="R2D_INT16"/> 326 325 <value value="0x5" name="R2D_INT8"/> 327 326 <value value="0x4" name="R2D_FLOAT32"/> 328 327 <value value="0x3" name="R2D_FLOAT16"/> 328 328 + <value value="0x2" name="R2D_SNORM8"/> 329 329 <value value="0x1" name="R2D_UNORM8_SRGB"/> 330 330 - <value value="0x0" name="R2D_RAW"/> 330 330 + <value value="0x0" name="R2D_UNORM8"/> 331 331 </enum> 332 332 333 333 <enum name="a6xx_tex_type"> ··· 378 378 <value value="0x1" name="TESS_LINES"/> 379 379 <value value="0x2" name="TESS_CW_TRIS"/> 380 380 <value value="0x3" name="TESS_CCW_TRIS"/> 381 381 + </enum> 382 382 + 383 383 + <enum name="a6xx_tex_filter"> <!-- same as a4xx? --> 384 384 + <value name="A6XX_TEX_NEAREST" value="0"/> 385 385 + <value name="A6XX_TEX_LINEAR" value="1"/> 386 386 + <value name="A6XX_TEX_ANISO" value="2"/> 387 387 + <value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only --> 388 388 + </enum> 389 389 + 390 390 + <enum name="a6xx_tex_clamp"> <!-- same as a4xx? --> 391 391 + <value name="A6XX_TEX_REPEAT" value="0"/> 392 392 + <value name="A6XX_TEX_CLAMP_TO_EDGE" value="1"/> 393 393 + <value name="A6XX_TEX_MIRROR_REPEAT" value="2"/> 394 394 + <value name="A6XX_TEX_CLAMP_TO_BORDER" value="3"/> 395 395 + <value name="A6XX_TEX_MIRROR_CLAMP" value="4"/> 396 396 + </enum> 397 397 + 398 398 + <enum name="a6xx_tex_aniso"> <!-- same as a4xx? --> 399 399 + <value name="A6XX_TEX_ANISO_1" value="0"/> 400 400 + <value name="A6XX_TEX_ANISO_2" value="1"/> 401 401 + <value name="A6XX_TEX_ANISO_4" value="2"/> 402 402 + <value name="A6XX_TEX_ANISO_8" value="3"/> 403 403 + <value name="A6XX_TEX_ANISO_16" value="4"/> 404 404 + </enum> 405 405 + 406 406 + <enum name="a6xx_reduction_mode"> 407 407 + <value name="A6XX_REDUCTION_MODE_AVERAGE" value="0"/> 408 408 + <value name="A6XX_REDUCTION_MODE_MIN" value="1"/> 409 409 + <value name="A6XX_REDUCTION_MODE_MAX" value="2"/> 410 410 + </enum> 411 411 + 412 412 + <enum name="a6xx_fast_border_color"> 413 413 + <!-- R B G A --> 414 414 + <value name="A6XX_BORDER_COLOR_0_0_0_0" value="0"/> 415 415 + <value name="A6XX_BORDER_COLOR_0_0_0_1" value="1"/> 416 416 + <value name="A6XX_BORDER_COLOR_1_1_1_0" value="2"/> 417 417 + <value name="A6XX_BORDER_COLOR_1_1_1_1" value="3"/> 418 418 + </enum> 419 419 + 420 420 + <enum name="a6xx_tex_swiz"> <!-- same as a4xx? --> 421 421 + <value name="A6XX_TEX_X" value="0"/> 422 422 + <value name="A6XX_TEX_Y" value="1"/> 423 423 + <value name="A6XX_TEX_Z" value="2"/> 424 424 + <value name="A6XX_TEX_W" value="3"/> 425 425 + <value name="A6XX_TEX_ZERO" value="4"/> 426 426 + <value name="A6XX_TEX_ONE" value="5"/> 381 427 </enum> 382 428 383 429 </database>

+11

drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml

reviewed

··· 99 99 <bitfield name="GX_HM_GDSC_POWER_OFF" pos="6" type="boolean"/> 100 100 <bitfield name="GX_HM_CLK_OFF" pos="7" type="boolean"/> 101 101 </reg32> 102 102 + <reg32 offset="0x50d0" name="GMU_SPTPRAC_PWR_CLK_STATUS" variants="A7XX"> 103 103 + <bitfield name="GX_HM_GDSC_POWER_OFF" pos="0" type="boolean"/> 104 104 + <bitfield name="GX_HM_CLK_OFF" pos="1" type="boolean"/> 105 105 + </reg32> 102 106 <reg32 offset="0x50e4" name="GMU_GPU_NAP_CTRL"> 103 107 <bitfield name="HW_NAP_ENABLE" pos="0"/> 104 108 <bitfield name="SID" low="4" high="8"/> ··· 131 127 <reg32 offset="0x5088" name="GMU_ALWAYS_ON_COUNTER_L"/> 132 128 <reg32 offset="0x5089" name="GMU_ALWAYS_ON_COUNTER_H"/> 133 129 <reg32 offset="0x50c3" name="GMU_GMU_PWR_COL_KEEPALIVE"/> 130 130 + <reg32 offset="0x50c4" name="GMU_PWR_COL_PREEMPT_KEEPALIVE"/> 134 131 <reg32 offset="0x5180" name="GMU_HFI_CTRL_STATUS"/> 135 132 <reg32 offset="0x5181" name="GMU_HFI_VERSION_INFO"/> 136 133 <reg32 offset="0x5182" name="GMU_HFI_SFR_ADDR"/> ··· 233 228 <reg32 offset="0x03ee" name="RSCC_TCS1_DRV0_STATUS"/> 234 229 <reg32 offset="0x0496" name="RSCC_TCS2_DRV0_STATUS"/> 235 230 <reg32 offset="0x053e" name="RSCC_TCS3_DRV0_STATUS"/> 231 231 + <reg32 offset="0x05e6" name="RSCC_TCS4_DRV0_STATUS" variants="A7XX"/> 232 232 + <reg32 offset="0x068e" name="RSCC_TCS5_DRV0_STATUS" variants="A7XX"/> 233 233 + <reg32 offset="0x0736" name="RSCC_TCS6_DRV0_STATUS" variants="A7XX"/> 234 234 + <reg32 offset="0x07de" name="RSCC_TCS7_DRV0_STATUS" variants="A7XX"/> 235 235 + <reg32 offset="0x0886" name="RSCC_TCS8_DRV0_STATUS" variants="A7XX"/> 236 236 + <reg32 offset="0x092e" name="RSCC_TCS9_DRV0_STATUS" variants="A7XX"/> 236 237 </domain> 237 238 238 239 </database>

+48 -131

drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml

reviewed

··· 120 120 <value name="LRZ_FLUSH" value="38" variants="A5XX-"/> 121 121 <value name="BLIT_OP_FILL_2D" value="39" variants="A5XX-"/> 122 122 <value name="BLIT_OP_COPY_2D" value="40" variants="A5XX-A6XX"/> 123 123 - <value name="UNK_40" value="40" variants="A7XX"/> 123 123 + <value name="LRZ_CACHE_INVALIDATE" value="40" variants="A7XX"/> 124 124 <value name="LRZ_Q_CACHE_INVALIDATE" value="41" variants="A7XX"/> 125 125 <value name="BLIT_OP_SCALE_2D" value="42" variants="A5XX-"/> 126 126 <value name="CONTEXT_DONE_2D" value="43" variants="A5XX-"/> 127 127 - <value name="UNK_2C" value="44" variants="A5XX-"/> 128 128 - <value name="UNK_2D" value="45" variants="A5XX-"/> 127 127 + <value name="VSC_BINNING_START" value="44" variants="A5XX-"/> 128 128 + <value name="VSC_BINNING_END" value="45" variants="A5XX-"/> 129 129 130 130 <!-- a6xx events --> 131 131 <doc> ··· 523 523 <!-- 524 524 Seems to set the mode flags which control which CP_SET_DRAW_STATE 525 525 packets are executed, based on their ENABLE_MASK values 526 526 - 526 526 + 527 527 CP_SET_MODE w/ payload of 0x1 seems to cause CP_SET_DRAW_STATE 528 528 packets w/ ENABLE_MASK & 0x6 to execute immediately 529 529 --> ··· 640 640 <value name="CP_BV_BR_COUNT_OPS" value="0x1b" variants="A7XX-"/> 641 641 <doc> Clears, adds to local, or adds to global timestamp </doc> 642 642 <value name="CP_MODIFY_TIMESTAMP" value="0x1c" variants="A7XX-"/> 643 643 - <!-- similar to CP_CONTEXT_REG_BUNCH, but discards first two dwords?? --> 644 644 - <value name="CP_CONTEXT_REG_BUNCH2" value="0x5d" variants="A7XX-"/> 643 643 + <value name="CP_NON_CONTEXT_REG_BUNCH" value="0x5d" variants="A7XX-"/> 645 644 <doc> 646 645 Write to a scratch memory that is read by CP_REG_TEST with 647 646 SOURCE_SCRATCH_MEM set. It's not the same scratch as scratch registers. ··· 917 918 </reg32> 918 919 919 920 <stripe varset="chip" variants="A5XX-"> 920 920 - <reg32 offset="4" name="4"> 921 921 - <bitfield name="INDX_BASE_LO" low="0" high="31"/> 922 922 - </reg32> 923 923 - <reg32 offset="5" name="5"> 924 924 - <bitfield name="INDX_BASE_HI" low="0" high="31"/> 925 925 - </reg32> 926 921 <reg64 offset="4" name="INDX_BASE" type="address"/> 927 922 <reg32 offset="6" name="6"> 928 923 <!-- max # of elements in index buffer --> ··· 1092 1099 <bitfield name="BINNING" pos="20" varset="chip" variants="A6XX-" type="boolean"/> 1093 1100 <bitfield name="GMEM" pos="21" varset="chip" variants="A6XX-" type="boolean"/> 1094 1101 <bitfield name="SYSMEM" pos="22" varset="chip" variants="A6XX-" type="boolean"/> 1095 1095 - <bitfield name="GROUP_ID" low="24" high="28" type="uint"/> 1102 1102 + <!-- high bit is 28 until a750: --> 1103 1103 + <bitfield name="GROUP_ID" low="24" high="29" type="uint"/> 1096 1104 </reg32> 1105 1105 + <reg64 offset="1" name="ADDR" type="address"/> 1097 1106 <reg32 offset="1" name="1"> 1098 1107 <bitfield name="ADDR_LO" low="0" high="31" type="hex"/> 1099 1108 </reg32> ··· 1161 1166 </reg32> 1162 1167 <stripe varset="a7xx_abs_mask_mode" variants="NO_ABS_MASK"> 1163 1168 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> 1164 1164 - <reg32 offset="1" name="1"> 1165 1165 - <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/> 1166 1166 - </reg32> 1167 1167 - <reg32 offset="2" name="2"> 1168 1168 - <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/> 1169 1169 - </reg32> 1169 1169 + <reg64 offset="1" name="BIN_DATA_ADDR" type="address"/> 1170 1170 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> 1171 1171 - <reg32 offset="3" name="3"> 1172 1172 - <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/> 1173 1173 - </reg32> 1174 1174 - <reg32 offset="4" name="4"> 1175 1175 - <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/> 1176 1176 - </reg32> 1171 1171 + <reg64 offset="3" name="BIN_SIZE_ADDR" type="address"/> 1177 1172 <!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: --> 1178 1178 - <reg32 offset="5" name="5"> 1179 1179 - <bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/> 1180 1180 - </reg32> 1181 1181 - <reg32 offset="6" name="6"> 1182 1182 - <bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/> 1183 1183 - </reg32> 1173 1173 + <reg64 offset="5" name="BIN_PRIM_STRM" type="address"/> 1184 1174 <!-- 1185 1175 a7xx adds a few more addresses to the end of the pkt 1186 1176 --> ··· 1175 1195 <stripe varset="a7xx_abs_mask_mode" variants="ABS_MASK"> 1176 1196 <reg32 offset="1" name="ABS_MASK"/> 1177 1197 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> 1178 1178 - <reg32 offset="2" name="2"> 1179 1179 - <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/> 1180 1180 - </reg32> 1181 1181 - <reg32 offset="3" name="3"> 1182 1182 - <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/> 1183 1183 - </reg32> 1198 1198 + <reg64 offset="2" name="BIN_DATA_ADDR" type="address"/> 1184 1199 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> 1185 1185 - <reg32 offset="4" name="4"> 1186 1186 - <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/> 1187 1187 - </reg32> 1188 1188 - <reg32 offset="5" name="5"> 1189 1189 - <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/> 1190 1190 - </reg32> 1200 1200 + <reg64 offset="4" name="BIN_SIZE_ADDR" type="address"/> 1191 1201 <!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: --> 1192 1192 - <reg32 offset="6" name="6"> 1193 1193 - <bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/> 1194 1194 - </reg32> 1195 1195 - <reg32 offset="7" name="7"> 1196 1196 - <bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/> 1197 1197 - </reg32> 1202 1202 + <reg64 offset="6" name="BIN_PRIM_STRM" type="address"/> 1198 1203 <!-- 1199 1204 a7xx adds a few more addresses to the end of the pkt 1200 1205 --> ··· 1265 1300 </reg32> 1266 1301 </domain> 1267 1302 1268 1268 - <domain name="CP_REG_TO_MEM" width="32"> 1303 1303 + <domain name="CP_REG_TO_MEM" width="32" prefix="chip"> 1269 1304 <reg32 offset="0" name="0"> 1270 1305 <bitfield name="REG" low="0" high="17" type="hex"/> 1271 1306 <!-- number of registers/dwords copied is max(CNT, 1). --> ··· 1273 1308 <bitfield name="64B" pos="30" type="boolean"/> 1274 1309 <bitfield name="ACCUMULATE" pos="31" type="boolean"/> 1275 1310 </reg32> 1276 1276 - <reg32 offset="1" name="1"> 1277 1277 - <bitfield name="DEST" low="0" high="31"/> 1278 1278 - </reg32> 1279 1279 - <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 1280 1280 - <bitfield name="DEST_HI" low="0" high="31"/> 1281 1281 - </reg32> 1311 1311 + <stripe varset="chip" variants="A2XX-A4XX"> 1312 1312 + <reg32 offset="1" name="DEST" type="address"/> 1313 1313 + </stripe> 1314 1314 + <stripe varset="chip" variants="A5XX-"> 1315 1315 + <reg64 offset="1" name="DEST" type="address"/> 1316 1316 + </stripe> 1282 1317 </domain> 1283 1318 1284 1319 <domain name="CP_REG_TO_MEM_OFFSET_REG" width="32"> ··· 1294 1329 <bitfield name="64B" pos="30" type="boolean"/> 1295 1330 <bitfield name="ACCUMULATE" pos="31" type="boolean"/> 1296 1331 </reg32> 1297 1297 - <reg32 offset="1" name="1"> 1298 1298 - <bitfield name="DEST" low="0" high="31"/> 1299 1299 - </reg32> 1300 1300 - <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 1301 1301 - <bitfield name="DEST_HI" low="0" high="31"/> 1302 1302 - </reg32> 1332 1332 + <reg64 offset="1" name="DEST" type="waddress"/> 1303 1333 <reg32 offset="3" name="3"> 1304 1334 <bitfield name="OFFSET0" low="0" high="17" type="hex"/> 1305 1335 <bitfield name="OFFSET0_SCRATCH" pos="19" type="boolean"/> ··· 1314 1354 <bitfield name="64B" pos="30" type="boolean"/> 1315 1355 <bitfield name="ACCUMULATE" pos="31" type="boolean"/> 1316 1356 </reg32> 1317 1317 - <reg32 offset="1" name="1"> 1318 1318 - <bitfield name="DEST" low="0" high="31"/> 1319 1319 - </reg32> 1320 1320 - <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 1321 1321 - <bitfield name="DEST_HI" low="0" high="31"/> 1322 1322 - </reg32> 1323 1323 - <reg32 offset="3" name="3"> 1324 1324 - <bitfield name="OFFSET_LO" low="0" high="31" type="hex"/> 1325 1325 - </reg32> 1326 1326 - <reg32 offset="4" name="4"> 1327 1327 - <bitfield name="OFFSET_HI" low="0" high="31" type="hex"/> 1328 1328 - </reg32> 1357 1357 + <reg64 offset="1" name="DEST" type="waddress"/> 1358 1358 + <reg64 offset="3" name="OFFSET" type="waddress"/> 1329 1359 </domain> 1330 1360 1331 1361 <domain name="CP_MEM_TO_REG" width="32"> ··· 1328 1378 <!-- does the same thing as CP_MEM_TO_MEM::UNK31 --> 1329 1379 <bitfield name="UNK31" pos="31" type="boolean"/> 1330 1380 </reg32> 1331 1331 - <reg32 offset="1" name="1"> 1332 1332 - <bitfield name="SRC" low="0" high="31"/> 1333 1333 - </reg32> 1334 1334 - <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 1335 1335 - <bitfield name="SRC_HI" low="0" high="31"/> 1336 1336 - </reg32> 1381 1381 + <stripe varset="chip" variants="A2XX-A4XX"> 1382 1382 + <reg32 offset="1" name="SRC" type="address"/> 1383 1383 + </stripe> 1384 1384 + <stripe varset="chip" variants="A5XX-"> 1385 1385 + <reg64 offset="1" name="SRC" type="address"/> 1386 1386 + </stripe> 1337 1387 </domain> 1338 1388 1339 1389 <domain name="CP_MEM_TO_MEM" width="32"> ··· 1353 1403 <!-- some other kind of wait --> 1354 1404 <bitfield name="UNK31" pos="31" type="boolean"/> 1355 1405 </reg32> 1406 1406 + <reg64 offset="1" name="DST" type="waddress"/> 1407 1407 + <reg64 offset="3" name="SRC_A" type="address"/> 1408 1408 + <reg64 offset="5" name="SRC_B" type="address"/> 1409 1409 + <reg64 offset="7" name="SRC_C" type="address"/> 1356 1410 <!-- 1357 1411 followed by sequence of addresses.. the first is the 1358 1412 destination and the rest are N src addresses which are ··· 1415 1461 </domain> 1416 1462 1417 1463 <domain name="CP_MEM_WRITE" width="32"> 1418 1418 - <reg32 offset="0" name="0"> 1419 1419 - <bitfield name="ADDR_LO" low="0" high="31"/> 1420 1420 - </reg32> 1421 1421 - <reg32 offset="1" name="1"> 1422 1422 - <bitfield name="ADDR_HI" low="0" high="31"/> 1423 1423 - </reg32> 1464 1464 + <stripe varset="chip" variants="A2XX-A4XX"> 1465 1465 + <reg32 offset="0" name="ADDR" type="address"/> 1466 1466 + </stripe> 1467 1467 + <stripe varset="chip" variants="A5XX-"> 1468 1468 + <reg64 offset="0" name="ADDR" type="address"/> 1469 1469 + </stripe> 1424 1470 <!-- followed by the DWORDs to write --> 1425 1471 </domain> 1426 1472 ··· 1472 1518 <bitfield name="POLL" low="4" high="5" type="poll_memory_type"/> 1473 1519 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/> 1474 1520 </reg32> 1475 1475 - <reg32 offset="1" name="1"> 1476 1476 - <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/> 1477 1477 - </reg32> 1478 1478 - <reg32 offset="2" name="2"> 1479 1479 - <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/> 1480 1480 - </reg32> 1521 1521 + <reg64 offset="1" name="POLL_ADDR" type="address"/> 1481 1522 <reg32 offset="3" name="3"> 1482 1523 <bitfield name="REF" low="0" high="31"/> 1483 1524 </reg32> 1484 1525 <reg32 offset="4" name="4"> 1485 1526 <bitfield name="MASK" low="0" high="31"/> 1486 1527 </reg32> 1487 1487 - <reg32 offset="5" name="5"> 1488 1488 - <bitfield name="WRITE_ADDR_LO" low="0" high="31" type="hex"/> 1489 1489 - </reg32> 1490 1490 - <reg32 offset="6" name="6"> 1491 1491 - <bitfield name="WRITE_ADDR_HI" low="0" high="31" type="hex"/> 1492 1492 - </reg32> 1528 1528 + <reg64 offset="5" name="WRITE_ADDR" type="waddress"/> 1493 1529 <reg32 offset="7" name="7"> 1494 1530 <bitfield name="WRITE_DATA" low="0" high="31"/> 1495 1531 </reg32> ··· 1494 1550 <!-- Reserved for flags, presumably? Unused in FW --> 1495 1551 <bitfield name="RESERVED" low="0" high="31" type="hex"/> 1496 1552 </reg32> 1497 1497 - <reg32 offset="1" name="1"> 1498 1498 - <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/> 1499 1499 - </reg32> 1500 1500 - <reg32 offset="2" name="2"> 1501 1501 - <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/> 1502 1502 - </reg32> 1553 1553 + <reg64 offset="1" name="POLL_ADDR" type="address"/> 1503 1554 <reg32 offset="3" name="3"> 1504 1555 <bitfield name="REF" low="0" high="31"/> 1505 1556 </reg32> ··· 1512 1573 <bitfield name="POLL" low="4" high="5" type="poll_memory_type"/> 1513 1574 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/> 1514 1575 </reg32> 1515 1515 - <reg32 offset="1" name="1"> 1516 1516 - <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/> 1517 1517 - </reg32> 1518 1518 - <reg32 offset="2" name="2"> 1519 1519 - <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/> 1520 1520 - </reg32> 1576 1576 + <reg64 offset="1" name="POLL_ADDR" type="address"/> 1521 1577 <reg32 offset="3" name="3"> 1522 1578 <bitfield name="REF" low="0" high="31"/> 1523 1579 </reg32> ··· 1646 1712 TODO what is gpuaddr for, seems to be all 0's.. maybe needed for 1647 1713 context switch? 1648 1714 --> 1649 1649 - <reg32 offset="1" name="1"> 1650 1650 - <bitfield name="ADDR_0_LO" low="0" high="31"/> 1651 1651 - </reg32> 1652 1652 - <reg32 offset="2" name="2"> 1653 1653 - <bitfield name="ADDR_0_HI" low="0" high="31"/> 1654 1654 - </reg32> 1715 1715 + <reg64 offset="1" name="ADDR" type="waddress"/> 1655 1716 <reg32 offset="3" name="3"> 1656 1717 <!-- ??? --> 1657 1718 </reg32> ··· 1761 1832 <reg32 offset="0" name="0"> 1762 1833 </reg32> 1763 1834 <stripe varset="chip" variants="A4XX"> 1764 1764 - <reg32 offset="1" name="1"> 1765 1765 - <bitfield name="ADDR" low="0" high="31"/> 1766 1766 - </reg32> 1835 1835 + <reg32 offset="1" name="ADDR" type="address"/> 1767 1836 <reg32 offset="2" name="2"> 1768 1837 <!-- localsize is value minus one: --> 1769 1838 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> ··· 1770 1843 </reg32> 1771 1844 </stripe> 1772 1845 <stripe varset="chip" variants="A5XX-"> 1773 1773 - <reg32 offset="1" name="1"> 1774 1774 - <bitfield name="ADDR_LO" low="0" high="31"/> 1775 1775 - </reg32> 1776 1776 - <reg32 offset="2" name="2"> 1777 1777 - <bitfield name="ADDR_HI" low="0" high="31"/> 1778 1778 - </reg32> 1846 1846 + <reg64 offset="1" name="ADDR" type="address"/> 1779 1847 <reg32 offset="3" name="3"> 1780 1848 <!-- localsize is value minus one: --> 1781 1849 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> ··· 2083 2161 </doc> 2084 2162 </value> 2085 2163 </enum> 2086 2086 - <reg32 offset="0" name="0"> 2087 2087 - <bitfield name="ADDR_LO" low="0" high="31"/> 2088 2088 - </reg32> 2089 2089 - <reg32 offset="1" name="1"> 2090 2090 - <bitfield name="ADDR_HI" low="0" high="31"/> 2091 2091 - </reg32> 2164 2164 + <reg64 offset="0" name="ADDR" type="address"/> 2092 2165 <reg32 offset="2" name="2"> 2093 2166 <bitfield name="DWORDS" low="0" high="19" type="uint"/> 2094 2167 <bitfield name="TYPE" low="20" high="21" type="amble_type"/>

+10 -1

drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml

reviewed

··· 22 22 <reg32 offset="0x00018" name="GLBL_CTRL"/> 23 23 <reg32 offset="0x0001c" name="RBUF_CTRL"/> 24 24 <reg32 offset="0x00020" name="VREG_CTRL_0"/> 25 25 - <reg32 offset="0x00024" name="CTRL_0"/> 25 25 + <reg32 offset="0x00024" name="CTRL_0"> 26 26 + <bitfield name="CLKSL_SHUTDOWNB" pos="7" type="boolean"/> 27 27 + <bitfield name="DIGTOP_PWRDN_B" pos="6" type="boolean"/> 28 28 + <bitfield name="PLL_SHUTDOWNB" pos="5" type="boolean"/> 29 29 + <bitfield name="DLN3_SHUTDOWNB" pos="4" type="boolean"/> 30 30 + <bitfield name="DLN2_SHUTDOWNB" pos="3" type="boolean"/> 31 31 + <bitfield name="CLK_SHUTDOWNB" pos="2" type="boolean"/> 32 32 + <bitfield name="DLN1_SHUTDOWNB" pos="1" type="boolean"/> 33 33 + <bitfield name="DLN0_SHUTDOWNB" pos="0" type="boolean"/> 34 34 + </reg32> 26 35 <reg32 offset="0x00028" name="CTRL_1"/> 27 36 <reg32 offset="0x0002c" name="CTRL_2"/> 28 37 <reg32 offset="0x00030" name="CTRL_3"/>

+115 -86

drivers/gpu/drm/msm/registers/gen_header.py

reviewed

··· 11 11 import argparse 12 12 import time 13 13 import datetime 14 14 - import re 15 14 16 15 class Error(Exception): 17 16 def __init__(self, message): ··· 30 31 def names(self): 31 32 return [n for (n, value) in self.values] 32 33 33 33 - def dump(self): 34 34 + def dump(self, is_deprecated): 34 35 use_hex = False 35 36 for (name, value) in self.values: 36 37 if value > 0x1000: ··· 44 45 print("\t%s = %d," % (name, value)) 45 46 print("};\n") 46 47 47 47 - def dump_pack_struct(self): 48 48 + def dump_pack_struct(self, is_deprecated): 48 49 pass 49 50 50 51 class Field(object): ··· 69 70 raise parser.error("booleans should be 1 bit fields") 70 71 elif self.type == "float" and not (high - low == 31 or high - low == 15): 71 72 raise parser.error("floats should be 16 or 32 bit fields") 72 72 - elif not self.type in builtin_types and not self.type in parser.enums: 73 73 + elif self.type not in builtin_types and self.type not in parser.enums: 73 74 raise parser.error("unknown type '%s'" % self.type) 74 75 75 76 def ctype(self, var_name): 76 76 - if self.type == None: 77 77 + if self.type is None: 77 78 type = "uint32_t" 78 79 val = var_name 79 80 elif self.type == "boolean": ··· 123 124 name = f.name.lower() 124 125 else: 125 126 # We hit this path when a reg is defined with no bitset fields, ie. 126 126 - # <reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" low="0" high="28" shr="6" type="uint"/> 127 127 + # <reg32 offset="0x88db" name="RB_RESOLVE_SYSTEM_BUFFER_ARRAY_PITCH" low="0" high="28" shr="6" type="uint"/> 127 128 name = reg.name.lower() 128 129 129 130 if (name in [ "double", "float", "int" ]) or not (name[0].isalpha()): ··· 145 146 "%s(i%d)" % (offset, idx) 146 147 for (idx, (ctype, stride, offset)) in enumerate(indices)]) 147 148 149 149 + def is_number(str): 150 150 + try: 151 151 + int(str) 152 152 + return True 153 153 + except ValueError: 154 154 + return False 155 155 + 156 156 + def sanitize_variant(variant): 157 157 + if variant and "-" in variant: 158 158 + return variant[:variant.index("-")] 159 159 + return variant 160 160 + 148 161 class Bitset(object): 149 162 def __init__(self, name, template): 150 163 self.name = name 151 164 self.inline = False 165 165 + self.reg = None 152 166 if template: 153 167 self.fields = template.fields[:] 154 168 else: ··· 187 175 print("#endif\n") 188 176 189 177 print(" return (struct fd_reg_pair) {") 190 190 - if reg.array: 191 191 - print(" .reg = REG_%s(__i)," % reg.full_name) 192 192 - else: 193 193 - print(" .reg = REG_%s," % reg.full_name) 194 194 - 178 178 + print(" .reg = (uint32_t)%s," % reg.reg_offset()) 195 179 print(" .value =") 196 180 for f in self.fields: 197 181 if f.type in [ "address", "waddress" ]: ··· 212 204 213 205 print(" };") 214 206 215 215 - def dump_pack_struct(self, reg=None): 207 207 + def dump_pack_struct(self, is_deprecated, reg=None): 216 208 if not reg: 217 209 return 218 210 ··· 237 229 tab_to(" uint32_t", "dword;") 238 230 print("};\n") 239 231 232 232 + depcrstr = "" 233 233 + if is_deprecated: 234 234 + depcrstr = " FD_DEPRECATED" 240 235 if reg.array: 241 241 - print("static inline struct fd_reg_pair\npack_%s(uint32_t __i, struct %s fields)\n{" % 242 242 - (prefix, prefix)) 236 236 + print("static inline%s struct fd_reg_pair\npack_%s(uint32_t __i, struct %s fields)\n{" % 237 237 + (depcrstr, prefix, prefix)) 243 238 else: 244 244 - print("static inline struct fd_reg_pair\npack_%s(struct %s fields)\n{" % 245 245 - (prefix, prefix)) 239 239 + print("static inline%s struct fd_reg_pair\npack_%s(struct %s fields)\n{" % 240 240 + (depcrstr, prefix, prefix)) 246 241 247 242 self.dump_regpair_builder(reg) 248 243 ··· 264 253 (prefix, prefix, prefix, skip)) 265 254 266 255 267 267 - def dump(self, prefix=None): 268 268 - if prefix == None: 256 256 + def dump(self, is_deprecated, prefix=None): 257 257 + if prefix is None: 269 258 prefix = self.name 259 259 + if self.reg and self.reg.bit_size == 64: 260 260 + print("static inline uint32_t %s_LO(uint32_t val)\n{" % prefix) 261 261 + print("\treturn val;\n}") 262 262 + print("static inline uint32_t %s_HI(uint32_t val)\n{" % prefix) 263 263 + print("\treturn val;\n}") 270 264 for f in self.fields: 271 265 if f.name: 272 266 name = prefix + "_" + f.name 273 267 else: 274 268 name = prefix 275 269 276 276 - if not f.name and f.low == 0 and f.shr == 0 and not f.type in ["float", "fixed", "ufixed"]: 270 270 + if not f.name and f.low == 0 and f.shr == 0 and f.type not in ["float", "fixed", "ufixed"]: 277 271 pass 278 278 - elif f.type == "boolean" or (f.type == None and f.low == f.high): 272 272 + elif f.type == "boolean" or (f.type is None and f.low == f.high): 279 273 tab_to("#define %s" % name, "0x%08x" % (1 << f.low)) 280 274 else: 281 275 tab_to("#define %s__MASK" % name, "0x%08x" % mask(f.low, f.high)) ··· 302 286 self.domain = domain 303 287 self.variant = variant 304 288 self.parent = parent 289 289 + self.children = [] 305 290 if self.parent: 306 291 self.name = self.parent.name + "_" + self.local_name 307 292 else: ··· 354 337 offset += self.parent.total_offset() 355 338 return offset 356 339 357 357 - def dump(self): 340 340 + def dump(self, is_deprecated): 341 341 + depcrstr = "" 342 342 + if is_deprecated: 343 343 + depcrstr = " FD_DEPRECATED" 358 344 proto = indices_varlist(self.indices()) 359 345 strides = indices_strides(self.indices()) 360 346 array_offset = self.total_offset() 361 347 if self.fixed_offsets: 362 362 - print("static inline uint32_t __offset_%s(%s idx)" % (self.local_name, self.index_ctype())) 348 348 + print("static inline%s uint32_t __offset_%s(%s idx)" % (depcrstr, self.local_name, self.index_ctype())) 363 349 print("{\n\tswitch (idx) {") 364 350 if self.index_type: 365 351 for val, offset in zip(self.index_type.names(), self.offsets): ··· 377 357 else: 378 358 tab_to("#define REG_%s_%s(%s)" % (self.domain, self.name, proto), "(0x%08x + %s )\n" % (array_offset, strides)) 379 359 380 380 - def dump_pack_struct(self): 360 360 + def dump_pack_struct(self, is_deprecated): 381 361 pass 382 362 383 363 def dump_regpair_builder(self): ··· 393 373 self.bit_size = bit_size 394 374 if array: 395 375 self.name = array.name + "_" + self.name 376 376 + array.children.append(self) 396 377 self.full_name = self.domain + "_" + self.name 397 378 if "stride" in attrs: 398 379 self.stride = int(attrs["stride"], 0) ··· 418 397 else: 419 398 return self.offset 420 399 421 421 - def dump(self): 400 400 + def reg_offset(self): 401 401 + if self.array: 402 402 + offset = self.array.offset + self.offset 403 403 + return "(0x%08x + 0x%x*__i)" % (offset, self.array.stride) 404 404 + return "0x%08x" % self.offset 405 405 + 406 406 + def dump(self, is_deprecated): 407 407 + depcrstr = "" 408 408 + if is_deprecated: 409 409 + depcrstr = " FD_DEPRECATED " 422 410 proto = indices_prototype(self.indices()) 423 411 strides = indices_strides(self.indices()) 424 412 offset = self.total_offset() 425 413 if proto == '': 426 414 tab_to("#define REG_%s" % self.full_name, "0x%08x" % offset) 427 415 else: 428 428 - print("static inline uint32_t REG_%s(%s) { return 0x%08x + %s; }" % (self.full_name, proto, offset, strides)) 416 416 + print("static inline%s uint32_t REG_%s(%s) { return 0x%08x + %s; }" % (depcrstr, self.full_name, proto, offset, strides)) 429 417 430 418 if self.bitset.inline: 431 431 - self.bitset.dump(self.full_name) 419 419 + self.bitset.dump(is_deprecated, self.full_name) 420 420 + print("") 432 421 433 433 - def dump_pack_struct(self): 422 422 + def dump_pack_struct(self, is_deprecated): 434 423 if self.bitset.inline: 435 435 - self.bitset.dump_pack_struct(self) 424 424 + self.bitset.dump_pack_struct(is_deprecated, self) 436 425 437 426 def dump_regpair_builder(self): 438 438 - if self.bitset.inline: 439 439 - self.bitset.dump_regpair_builder(self) 427 427 + self.bitset.dump_regpair_builder(self) 440 428 441 429 def dump_py(self): 442 430 print("\tREG_%s = 0x%08x" % (self.full_name, self.offset)) ··· 474 444 self.variants = set() 475 445 self.file = [] 476 446 self.xml_files = [] 477 477 - self.copyright_year = None 478 478 - self.authors = [] 479 479 - self.license = None 480 447 481 448 def error(self, message): 482 449 parser, filename = self.stack[-1] ··· 481 454 482 455 def prefix(self, variant=None): 483 456 if self.current_prefix_type == "variant" and variant: 484 484 - return variant 457 457 + return sanitize_variant(variant) 485 458 elif self.current_stripe: 486 459 return self.current_stripe + "_" + self.current_domain 487 460 elif self.current_prefix: ··· 527 500 return varset 528 501 529 502 def parse_variants(self, attrs): 530 530 - if not "variants" in attrs: 503 503 + if "variants" not in attrs: 531 504 return None 532 532 - variant = attrs["variants"].split(",")[0] 533 533 - if "-" in variant: 534 534 - variant = variant[:variant.index("-")] 535 505 506 506 + variant = attrs["variants"].split(",")[0] 536 507 varset = self.parse_varset(attrs) 537 508 538 538 - assert varset.has_name(variant) 509 509 + if "-" in variant: 510 510 + # if we have a range, validate that both the start and end 511 511 + # of the range are valid enums: 512 512 + start = variant[:variant.index("-")] 513 513 + end = variant[variant.index("-") + 1:] 514 514 + assert varset.has_name(start) 515 515 + if end != "": 516 516 + assert varset.has_name(end) 517 517 + else: 518 518 + assert varset.has_name(variant) 539 519 540 520 return variant 541 521 ··· 606 572 error_str = str(xmlschema.error_log.filter_from_errors()[0]) 607 573 raise self.error("Schema validation failed for: " + filename + "\n" + error_str) 608 574 except ImportError as e: 609 609 - if self.validate: 610 610 - raise e 611 611 - 612 575 print("lxml not found, skipping validation", file=sys.stderr) 613 576 614 577 def do_parse(self, filename): ··· 651 620 652 621 self.current_reg = Reg(attrs, self.prefix(variant), self.current_array, bit_size) 653 622 self.current_reg.bitset = self.current_bitset 623 623 + self.current_bitset.reg = self.current_reg 654 624 655 625 if len(self.stack) == 1: 656 626 self.file.append(self.current_reg) ··· 675 643 elif name == "domain": 676 644 self.current_domain = attrs["name"] 677 645 if "prefix" in attrs: 678 678 - self.current_prefix = self.parse_variants(attrs) 646 646 + self.current_prefix = sanitize_variant(self.parse_variants(attrs)) 679 647 self.current_prefix_type = attrs["prefix"] 680 648 else: 681 649 self.current_prefix = None ··· 683 651 if "varset" in attrs: 684 652 self.current_varset = self.enums[attrs["varset"]] 685 653 elif name == "stripe": 686 686 - self.current_stripe = self.parse_variants(attrs) 654 654 + self.current_stripe = sanitize_variant(self.parse_variants(attrs)) 687 655 elif name == "enum": 688 656 self.current_enum_value = 0 689 657 self.current_enum = Enum(attrs["name"]) ··· 718 686 self.parse_field(attrs["name"], attrs) 719 687 elif name == "database": 720 688 self.do_validate(attrs["xsi:schemaLocation"]) 721 721 - elif name == "copyright": 722 722 - self.copyright_year = attrs["year"] 723 723 - elif name == "author": 724 724 - self.authors.append(attrs["name"] + " <" + attrs["email"] + "> " + attrs["name"]) 725 689 726 690 def end_element(self, name): 727 691 if name == "domain": ··· 731 703 elif name == "reg32": 732 704 self.current_reg = None 733 705 elif name == "array": 706 706 + # if the array has no Reg children, push an implicit reg32: 707 707 + if len(self.current_array.children) == 0: 708 708 + attrs = { 709 709 + "name": "REG", 710 710 + "offset": "0", 711 711 + } 712 712 + self.parse_reg(attrs, 32) 734 713 self.current_array = self.current_array.parent 735 714 elif name == "enum": 736 715 self.current_enum = None 737 737 - elif name == "license": 738 738 - self.license = self.cdata 739 716 740 717 def character_data(self, data): 741 718 self.cdata += data ··· 753 720 if variants: 754 721 for variant, vreg in variants.items(): 755 722 if reg == vreg: 756 756 - d[(usage, variant)].append(reg) 723 723 + d[(usage, sanitize_variant(variant))].append(reg) 757 724 else: 758 725 for variant in self.variants: 759 759 - d[(usage, variant)].append(reg) 726 726 + d[(usage, sanitize_variant(variant))].append(reg) 760 727 761 728 print("#ifdef __cplusplus") 762 729 ··· 786 753 787 754 print("#endif") 788 755 756 756 + def has_variants(self, reg): 757 757 + return reg.name in self.variant_regs and not is_number(reg.name) and not is_number(reg.name[1:]) 758 758 + 789 759 def dump(self): 790 760 enums = [] 791 761 bitsets = [] ··· 802 766 regs.append(e) 803 767 804 768 for e in enums + bitsets + regs: 805 805 - e.dump() 769 769 + e.dump(self.has_variants(e)) 806 770 807 771 self.dump_reg_usages() 808 772 ··· 818 782 819 783 820 784 def dump_reg_variants(self, regname, variants): 821 821 - # Don't bother for things that only have a single variant: 822 822 - if len(variants) == 1: 785 785 + if is_number(regname) or is_number(regname[1:]): 823 786 return 824 787 print("#ifdef __cplusplus") 825 788 print("struct __%s {" % regname) ··· 869 834 xtravar = "__i, " 870 835 print("__%s(%sstruct __%s fields) {" % (regname, xtra, regname)) 871 836 for variant in variants.keys(): 872 872 - print(" if (%s == %s) {" % (varenum.upper(), variant)) 837 837 + if "-" in variant: 838 838 + start = variant[:variant.index("-")] 839 839 + end = variant[variant.index("-") + 1:] 840 840 + if end != "": 841 841 + print(" if ((%s >= %s) && (%s <= %s)) {" % (varenum.upper(), start, varenum.upper(), end)) 842 842 + else: 843 843 + print(" if (%s >= %s) {" % (varenum.upper(), start)) 844 844 + else: 845 845 + print(" if (%s == %s) {" % (varenum.upper(), variant)) 873 846 reg = variants[variant] 874 847 reg.dump_regpair_builder() 875 848 print(" } else") 876 849 print(" assert(!\"invalid variant\");") 850 850 + print(" return (struct fd_reg_pair){};") 877 851 print("}") 878 852 879 853 if bit_size == 64: ··· 895 851 896 852 def dump_structs(self): 897 853 for e in self.file: 898 898 - e.dump_pack_struct() 854 854 + e.dump_pack_struct(self.has_variants(e)) 899 855 900 856 for regname in self.variant_regs: 901 857 self.dump_reg_variants(regname, self.variant_regs[regname]) ··· 912 868 913 869 print("#ifndef %s\n#define %s\n" % (guard, guard)) 914 870 915 915 - print("""/* Autogenerated file, DO NOT EDIT manually! 916 916 - 917 917 - This file was generated by the rules-ng-ng gen_header.py tool in this git repository: 918 918 - http://gitlab.freedesktop.org/mesa/mesa/ 919 919 - git clone https://gitlab.freedesktop.org/mesa/mesa.git 920 920 - 921 921 - The rules-ng-ng source files this header was generated from are: 922 922 - """) 923 923 - maxlen = 0 924 924 - for filepath in p.xml_files: 925 925 - new_filepath = re.sub("^.+drivers","drivers",filepath) 926 926 - maxlen = max(maxlen, len(new_filepath)) 927 927 - for filepath in p.xml_files: 928 928 - pad = " " * (maxlen - len(new_filepath)) 929 929 - filesize = str(os.path.getsize(filepath)) 930 930 - filesize = " " * (7 - len(filesize)) + filesize 931 931 - filetime = time.ctime(os.path.getmtime(filepath)) 932 932 - print("- " + new_filepath + pad + " (" + filesize + " bytes, from <stripped>)") 933 933 - if p.copyright_year: 934 934 - current_year = str(datetime.date.today().year) 935 935 - print() 936 936 - print("Copyright (C) %s-%s by the following authors:" % (p.copyright_year, current_year)) 937 937 - for author in p.authors: 938 938 - print("- " + author) 939 939 - if p.license: 940 940 - print(p.license) 941 941 - print("*/") 871 871 + print("/* Autogenerated file, DO NOT EDIT manually! */") 942 872 943 873 print() 944 874 print("#ifdef __KERNEL__") ··· 930 912 print("#endif") 931 913 print() 932 914 915 915 + print("#ifndef FD_NO_DEPRECATED_PACK") 916 916 + print("#define FD_DEPRECATED __attribute__((deprecated))") 917 917 + print("#else") 918 918 + print("#define FD_DEPRECATED") 919 919 + print("#endif") 920 920 + print() 921 921 + 933 922 func(p) 934 923 935 935 - print("\n#endif /* %s */" % guard) 924 924 + print() 925 925 + print("#undef FD_DEPRECATED") 926 926 + print() 927 927 + 928 928 + print("#endif /* %s */" % guard) 936 929 937 930 938 931 def dump_c_defines(args): ··· 960 931 p = Parser() 961 932 962 933 try: 963 963 - p.parse(args.rnn, args.xml) 934 934 + p.parse(args.rnn, args.xml, args.validate) 964 935 except Error as e: 965 936 print(e, file=sys.stderr) 966 937 exit(1)