tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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clk: renesas: r9a09g056-cpg: Add clock and reset entries for OSTM instances

Introduce a new fixed divider .pllcln_div16 which is sourced from PLLCLN
and add PCLK module clocks gtm_0_pclk through gtm_7_pclk for OSTM0-7.
Add corresponding reset lines GTM_0_PRESETZ through GTM_7_PRESETZ to
control the OSTM instances.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250513154635.273664-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Lad Prabhakar and committed by
Geert Uytterhoeven 82a0bc72 bfb0bc6b

+26
+26
drivers/clk/renesas/r9a09g056-cpg.c
··· 34 34 CLK_PLLCM33_DIV16, 35 35 CLK_PLLCLN_DIV2, 36 36 CLK_PLLCLN_DIV8, 37 + CLK_PLLCLN_DIV16, 37 38 CLK_PLLDTY_ACPU, 38 39 CLK_PLLDTY_ACPU_DIV4, 39 40 CLK_PLLDTY_DIV8, ··· 99 98 100 99 DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2), 101 100 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8), 101 + DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16), 102 102 103 103 DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64), 104 104 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4), ··· 136 134 static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = { 137 135 DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19, 138 136 BUS_MSTOP(3, BIT(5))), 137 + DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3, 138 + BUS_MSTOP(5, BIT(10))), 139 + DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4, 140 + BUS_MSTOP(5, BIT(11))), 141 + DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5, 142 + BUS_MSTOP(2, BIT(13))), 143 + DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6, 144 + BUS_MSTOP(2, BIT(14))), 145 + DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7, 146 + BUS_MSTOP(11, BIT(13))), 147 + DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8, 148 + BUS_MSTOP(11, BIT(14))), 149 + DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9, 150 + BUS_MSTOP(11, BIT(15))), 151 + DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10, 152 + BUS_MSTOP(12, BIT(0))), 139 153 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15, 140 154 BUS_MSTOP(3, BIT(14))), 141 155 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3, ··· 208 190 DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */ 209 191 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */ 210 192 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */ 193 + DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */ 194 + DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */ 195 + DEF_RST(6, 15, 3, 0), /* GTM_2_PRESETZ */ 196 + DEF_RST(7, 0, 3, 1), /* GTM_3_PRESETZ */ 197 + DEF_RST(7, 1, 3, 2), /* GTM_4_PRESETZ */ 198 + DEF_RST(7, 2, 3, 3), /* GTM_5_PRESETZ */ 199 + DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */ 200 + DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */ 211 201 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */ 212 202 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */ 213 203 DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */