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KVM: arm64: Fix various comments

Use tab instead of whitespaces, as well as 2 minor typo fixes.

Signed-off-by: Zenghui Yu (Huawei) <zenghui.yu@linux.dev>
Link: https://patch.msgid.link/20260128075208.23024-1-zenghui.yu@linux.dev
Signed-off-by: Marc Zyngier <maz@kernel.org>

authored by

Zenghui Yu (Huawei) and committed by
Marc Zyngier
82a32eac 9d46e83a

+3 -3
+1 -1
arch/arm64/include/asm/kvm_host.h
··· 201 201 * host to parse the guest S2. 202 202 * This either contains: 203 203 * - the virtual VTTBR programmed by the guest hypervisor with 204 - * CnP cleared 204 + * CnP cleared 205 205 * - The value 1 (VMID=0, BADDR=0, CnP=1) if invalid 206 206 * 207 207 * We also cache the full VTCR which gets used for TLB invalidation,
+1 -1
arch/arm64/kvm/hyp/vhe/sysreg-sr.c
··· 205 205 206 206 /* 207 207 * When running a normal EL1 guest, we only load a new vcpu 208 - * after a context switch, which imvolves a DSB, so all 208 + * after a context switch, which involves a DSB, so all 209 209 * speculative EL1&0 walks will have already completed. 210 210 * If running NV, the vcpu may transition between vEL1 and 211 211 * vEL2 without a context switch, so make sure we complete
+1 -1
arch/arm64/kvm/vgic/vgic-v3-nested.c
··· 57 57 * as the L1 guest is in charge of provisioning the interrupts via its own 58 58 * view of the ICH_LR*_EL2 registers, which conveniently live in the VNCR 59 59 * page. This means that the flow described above does work (there is no 60 - * state to rebuild in the L0 hypervisor), and that most things happed on L2 60 + * state to rebuild in the L0 hypervisor), and that most things happen on L2 61 61 * load/put: 62 62 * 63 63 * - on L2 load: move the in-memory L1 vGIC configuration into a shadow,