Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/ltphy: Program the rest of the PORT_CLOCK_CTL steps
Program the rest of the steps with regards to PORT_CLOCK_CTL in
Non-TBT PLL enable sequence.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-15-suraj.kandpal@intel.com
+26
+25
drivers/gpu/drm/i915/display/intel_lt_phy.c
+25
drivers/gpu/drm/i915/display/intel_lt_phy.c
···
1506
1506
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1507
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bool lane_reversal = dig_port->lane_reversal;
1508
1508
u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
1509
+
enum phy phy = intel_encoder_to_phy(encoder);
1510
+
enum port port = encoder->port;
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intel_wakeref_t wakeref = 0;
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wakeref = intel_lt_phy_transaction_begin(encoder);
···
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LT_PHY_PCLKIN_GATE);
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/* 7. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 0. */
1549
+
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
1550
+
XELPDP_LANE_PCLK_PLL_REQUEST(0), 0);
1551
+
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/* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
1553
+
if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
1554
+
XELPDP_LANE_PCLK_PLL_ACK(0), 0,
1555
+
XE3PLPD_MACCLK_TURNOFF_LATENCY_US, 0, NULL))
1556
+
drm_warn(display->drm, "PHY %c PLL MacCLK Ack deassertion Timeout after %dus.\n",
1557
+
phy_name(phy), XE3PLPD_MACCLK_TURNOFF_LATENCY_US);
1558
+
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/*
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* 9. Follow the Display Voltage Frequency Switching - Sequence Before Frequency
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* Change. We handle this step in bxt_set_cdclk().
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*/
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/* 10. Program DDI_CLK_VALFREQ to match intended DDI clock frequency. */
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/* 11. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 1. */
1565
+
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
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+
XELPDP_LANE_PCLK_PLL_REQUEST(0),
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+
XELPDP_LANE_PCLK_PLL_REQUEST(0));
1568
+
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/* 12. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 1. */
1570
+
if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
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+
XELPDP_LANE_PCLK_PLL_ACK(0),
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XELPDP_LANE_PCLK_PLL_ACK(0),
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XE3PLPD_MACCLK_TURNON_LATENCY_US, 2, NULL))
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+
drm_warn(display->drm, "PHY %c PLL MacCLK Ack assertion Timeout after %dus.\n",
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+
phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_US);
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} else {
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intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), crtc_state->port_clock);
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}
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/* 13. Ungate the forward clock by setting PORT_CLOCK_CTL[Forward Clock Ungate] = 1. */
1581
+
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
1582
+
XELPDP_FORWARD_CLOCK_UNGATE,
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+
XELPDP_FORWARD_CLOCK_UNGATE);
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+
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/* 14. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
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/*
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* 15. Clear the PHY VDR register 0xCC4[Rate Control VDR Update] over PHY message bus for
+1
drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
+1
drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
···
9
9
#define XE3PLPD_MSGBUS_TIMEOUT_FAST_US 500
10
10
#define XE3PLPD_MACCLK_TURNON_LATENCY_MS 1
11
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#define XE3PLPD_MACCLK_TURNON_LATENCY_US 21
12
+
#define XE3PLPD_MACCLK_TURNOFF_LATENCY_US 1
12
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#define XE3PLPD_RATE_CALIB_DONE_LATENCY_US 50
13
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#define XE3PLPD_RESET_START_LATENCY_US 10
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#define XE3PLPD_RESET_END_LATENCY_US 200