Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'for-linus' of https://github.com/openrisc/linux
Pull OpenRISC updates from Stafford Horne:
"Just a few documentation updates from the community:
- Device tree documentation conversion from txt to yaml
- Documentation addition to help users getting started with initramfs
on OpenRISC
* tag 'for-linus' of https://github.com/openrisc/linux:
dt-bindings: interrupt-controller: Convert openrisc,ompic to DT schema
dt-bindings: interrupt-controller: Convert opencores,or1k-pic to DT schema
Documentation:openrisc: Add build instructions with initramfs
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+6
Documentation/arch/openrisc/openrisc_port.rst
+6
Documentation/arch/openrisc/openrisc_port.rst
···
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make ARCH=openrisc CROSS_COMPILE="or1k-linux-" defconfig
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make ARCH=openrisc CROSS_COMPILE="or1k-linux-"
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If you want to embed initramfs in the kernel, also pass ``CONFIG_INITRAMFS_SOURCE``. For example::
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make ARCH=openrisc CROSS_COMPILE="or1k-linux-" CONFIG_INITRAMFS_SOURCE="path/to/rootfs path/to/devnodes"
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For more information on this, please check Documentation/filesystems/ramfs-rootfs-initramfs.rst.
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3) Running on FPGA (optional)
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The OpenRISC community typically uses FuseSoC to manage building and programming
-23
Documentation/devicetree/bindings/interrupt-controller/opencores,or1k-pic.txt
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Documentation/devicetree/bindings/interrupt-controller/opencores,or1k-pic.txt
···
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OpenRISC 1000 Programmable Interrupt Controller
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Required properties:
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-
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- compatible : should be "opencores,or1k-pic-level" for variants with
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level triggered interrupt lines, "opencores,or1k-pic-edge" for variants with
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edge triggered interrupt lines or "opencores,or1200-pic" for machines
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with the non-spec compliant or1200 type implementation.
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"opencores,or1k-pic" is also provided as an alias to "opencores,or1200-pic",
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but this is only for backwards compatibility.
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode an
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interrupt source. The value shall be 1.
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Example:
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intc: interrupt-controller {
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compatible = "opencores,or1k-pic-level";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
+38
Documentation/devicetree/bindings/interrupt-controller/opencores,or1k-pic.yaml
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Documentation/devicetree/bindings/interrupt-controller/opencores,or1k-pic.yaml
···
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/opencores,or1k-pic.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: OpenRISC 1000 Programmable Interrupt Controller
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maintainers:
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- Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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properties:
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compatible:
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enum:
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- opencores,or1k-pic-level
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- opencores,or1k-pic-edge
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- opencores,or1200-pic
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- opencores,or1k-pic
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interrupt-controller: true
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'#interrupt-cells':
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const: 1
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required:
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- compatible
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- interrupt-controller
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- '#interrupt-cells'
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additionalProperties: false
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examples:
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- |
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interrupt-controller {
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compatible = "opencores,or1k-pic-level";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
-22
Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt
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Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt
···
1
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Open Multi-Processor Interrupt Controller
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Required properties:
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- compatible : This should be "openrisc,ompic"
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- reg : Specifies base physical address and size of the register space. The
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size is based on the number of cores the controller has been configured
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to handle, this should be set to 8 bytes per cpu core.
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- interrupt-controller : Identifies the node as an interrupt controller.
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- #interrupt-cells : This should be set to 0 as this will not be an irq
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parent.
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- interrupts : Specifies the interrupt line to which the ompic is wired.
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Example:
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ompic: interrupt-controller@98000000 {
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compatible = "openrisc,ompic";
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reg = <0x98000000 16>;
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interrupt-controller;
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#interrupt-cells = <0>;
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interrupts = <1>;
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};
+45
Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.yaml
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Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.yaml
···
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/openrisc,ompic.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Open Multi-Processor Interrupt Controller
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maintainers:
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- Stafford Horne <shorne@gmail.com>
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properties:
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compatible:
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items:
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- const: openrisc,ompic
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reg:
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maxItems: 1
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interrupt-controller: true
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'#interrupt-cells':
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const: 0
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interrupts:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupt-controller
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- '#interrupt-cells'
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- interrupts
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additionalProperties: false
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examples:
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- |
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interrupt-controller@98000000 {
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compatible = "openrisc,ompic";
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reg = <0x98000000 16>;
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interrupt-controller;
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#interrupt-cells = <0>;
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interrupts = <1>;
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};