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drm/i915/fbc: fix the implementation of wa_18038517565

As per the wa_18038517565, we need to disable FBC compressor
clock gating before enabling FBC and enable after disabling
FBC. Placing the enabling of clock gating in the fbc deactivate
function can make the above wa logic go wrong in case of
frontbuffer rendering FBC mechanism. FBC deactivate can get
called during fb invalidate and then the corresponding FBC
activate can get called without properly disabling the clock
gating and can result in compression stalled. So move the
enable clock gating at the end of one FBC session after FBC
is completely disabled for a pipe.

Bspec: 74212, 72197, 69741, 65555
Fixes: 010363c46189 ("drm/i915/display: implement wa_18038517565")
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://lore.kernel.org/r/20250729124648.288497-1-vinod.govindapillai@intel.com

Vinod Govindapillai 82dde040 b116bd3a

+4 -4
+4 -4
drivers/gpu/drm/i915/display/intel_fbc.c
··· 552 552 if (dpfc_ctl & DPFC_CTL_EN) { 553 553 dpfc_ctl &= ~DPFC_CTL_EN; 554 554 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl); 555 - 556 - /* wa_18038517565 Enable DPFC clock gating after FBC disable */ 557 - if (display->platform.dg2 || DISPLAY_VER(display) >= 14) 558 - fbc_compressor_clkgate_disable_wa(fbc, false); 559 555 } 560 556 } 561 557 ··· 1705 1709 intel_fbc_invalidate_dirty_rect(fbc); 1706 1710 1707 1711 __intel_fbc_cleanup_cfb(fbc); 1712 + 1713 + /* wa_18038517565 Enable DPFC clock gating after FBC disable */ 1714 + if (display->platform.dg2 || DISPLAY_VER(display) >= 14) 1715 + fbc_compressor_clkgate_disable_wa(fbc, false); 1708 1716 1709 1717 fbc->state.plane = NULL; 1710 1718 fbc->flip_pending = false;