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clk: qcom: dispcc-sm8250: Add missing EDP clocks for sm8350

SM8350 supports embedded displayport, but the clocks for this
were previously not accounted for.

Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221102090140.965450-5-robert.foss@linaro.org

authored by

Robert Foss and committed by
Bjorn Andersson
8305ff41 c2b6ad72

+21 -1
+21 -1
drivers/clk/qcom/dispcc-sm8250.c
··· 462 462 }, 463 463 }; 464 464 465 + static struct clk_regmap_div disp_cc_mdss_edp_link_div_clk_src = { 466 + .reg = 0x2288, 467 + .shift = 0, 468 + .width = 2, 469 + .clkr.hw.init = &(struct clk_init_data) { 470 + .name = "disp_cc_mdss_edp_link_div_clk_src", 471 + .parent_hws = (const struct clk_hw*[]){ 472 + &disp_cc_mdss_edp_link_clk_src.clkr.hw, 473 + }, 474 + .num_parents = 1, 475 + .ops = &clk_regmap_div_ro_ops, 476 + }, 477 + }; 478 + 465 479 static struct clk_branch disp_cc_mdss_edp_link_intf_clk = { 466 480 .halt_reg = 0x2074, 467 481 .halt_check = BRANCH_HALT, ··· 485 471 .hw.init = &(struct clk_init_data){ 486 472 .name = "disp_cc_mdss_edp_link_intf_clk", 487 473 .parent_hws = (const struct clk_hw*[]){ 488 - &disp_cc_mdss_edp_link_clk_src.clkr.hw, 474 + &disp_cc_mdss_edp_link_div_clk_src.clkr.hw, 489 475 }, 490 476 .num_parents = 1, 491 477 .flags = CLK_GET_RATE_NOCACHE, ··· 1189 1175 [DISP_CC_MDSS_EDP_GTC_CLK_SRC] = &disp_cc_mdss_edp_gtc_clk_src.clkr, 1190 1176 [DISP_CC_MDSS_EDP_LINK_CLK] = &disp_cc_mdss_edp_link_clk.clkr, 1191 1177 [DISP_CC_MDSS_EDP_LINK_CLK_SRC] = &disp_cc_mdss_edp_link_clk_src.clkr, 1178 + [DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] = &disp_cc_mdss_edp_link_div_clk_src.clkr, 1192 1179 [DISP_CC_MDSS_EDP_LINK_INTF_CLK] = &disp_cc_mdss_edp_link_intf_clk.clkr, 1193 1180 [DISP_CC_MDSS_EDP_PIXEL_CLK] = &disp_cc_mdss_edp_pixel_clk.clkr, 1194 1181 [DISP_CC_MDSS_EDP_PIXEL_CLK_SRC] = &disp_cc_mdss_edp_pixel_clk_src.clkr, ··· 1300 1285 &disp_cc_mdss_dp_pixel1_clk_src, 1301 1286 &disp_cc_mdss_dp_pixel2_clk_src, 1302 1287 &disp_cc_mdss_dp_pixel_clk_src, 1288 + &disp_cc_mdss_edp_aux_clk_src, 1289 + &disp_cc_mdss_edp_link_clk_src, 1290 + &disp_cc_mdss_edp_pixel_clk_src, 1303 1291 &disp_cc_mdss_esc0_clk_src, 1292 + &disp_cc_mdss_esc1_clk_src, 1304 1293 &disp_cc_mdss_mdp_clk_src, 1305 1294 &disp_cc_mdss_pclk0_clk_src, 1306 1295 &disp_cc_mdss_pclk1_clk_src, ··· 1316 1297 &disp_cc_mdss_byte1_div_clk_src, 1317 1298 &disp_cc_mdss_dp_link1_div_clk_src, 1318 1299 &disp_cc_mdss_dp_link_div_clk_src, 1300 + &disp_cc_mdss_edp_link_div_clk_src, 1319 1301 }; 1320 1302 unsigned int i; 1321 1303 static bool offset_applied;