dmaengine: idxd: Expose DSA3.0 capabilities through sysfs

Introduce sysfs interfaces for 3 new Data Streaming Accelerator (DSA)
capability registers (dsacap0-2) to enable userspace awareness of hardware
features in DSA version 3 and later devices.

Userspace components (e.g. configure libraries, workload Apps) require this
information to:
1. Select optimal data transfer strategies based on SGL capabilities
2. Enable hardware-specific optimizations for floating-point operations
3. Configure memory operations with proper numerical handling
4. Verify compute operation compatibility before submitting jobs

The output format is <dsacap2>,<dsacap1>,<dsacap0>, where each DSA
capability value is a 64-bit hexadecimal number, separated by commas.
The ordering follows the DSA 3.0 specification layout:
Offset: 0x190 0x188 0x180
Reg: dsacap2 dsacap1 dsacap0

Example:
cat /sys/bus/dsa/devices/dsa0/dsacaps
000000000000f18d,0014000e000007aa,00fa01ff01ff03ff

According to the DSA 3.0 specification, there are 15 fields defined for
the three dsacap registers. However, there's no need to define all
register structures unless a use case requires them. At this point,
support for the Scatter-Gather List (SGL) located in dsacap0 is necessary,
so only dsacap0 is defined accordingly.

For reference, the DSA 3.0 specification is available at:
Link: https://software.intel.com/content/www/us/en/develop/articles/intel-data-streaming-accelerator-architecture-specification.html

Signed-off-by: Yi Sun <yi.sun@intel.com>
Co-developed-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Tested-by: Yi Lai <yi1.lai@intel.com>
Acked-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Link: https://patch.msgid.link/20260107-idxd-yi-sun-dsa3-sgl-size-v2-1-dbef8f559e48@intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Yi Sun and committed by

Vinod Koul 5 months ago 8308510b e0c51fd0

+73

5 changed files

expand all

Documentation

ABI

stable

sysfs-driver-dma-idxd

drivers

dma

idxd

idxd.h

init.c

registers.h

sysfs.c

+15

Documentation/ABI/stable/sysfs-driver-dma-idxd

··· 136 136 Also last configuration error overloaded. 137 137 Writing to it will clear the status. 138 138 139 + What: /sys/bus/dsa/devices/dsa<m>/dsacaps 140 + Date: April 5, 2026 141 + KernelVersion: 6.20.0 142 + Contact: dmaengine@vger.kernel.org 143 + Description: The DSA3 specification introduces three new capability 144 + registers: dsacap[0-2]. User components (e.g., configuration 145 + libraries and workload applications) require this information 146 + to properly utilize the DSA3 features. 147 + This includes SGL capability support, Enabling hardware-specific 148 + optimizations, Configuring memory, etc. 149 + The output format is '<dsacap2>,<dsacap1>,<dsacap0>' where each 150 + DSA cap value is a 64 bit hex value. 151 + This attribute should only be visible on DSA devices of version 152 + 3 or later. 153 + 139 154 What: /sys/bus/dsa/devices/dsa<m>/iaa_cap 140 155 Date: Sept 14, 2022 141 156 KernelVersion: 6.0.0

drivers/dma/idxd/idxd.h

··· 252 252 struct opcap opcap; 253 253 u32 cmd_cap; 254 254 union iaa_cap_reg iaa_cap; 255 + union dsacap0_reg dsacap0; 256 + union dsacap1_reg dsacap1; 257 + union dsacap2_reg dsacap2; 255 258 }; 256 259 257 260 enum idxd_device_state {

drivers/dma/idxd/init.c

··· 585 585 } 586 586 multi_u64_to_bmap(idxd->opcap_bmap, &idxd->hw.opcap.bits[0], 4); 587 587 588 + if (idxd->hw.version >= DEVICE_VERSION_3) { 589 + idxd->hw.dsacap0.bits = ioread64(idxd->reg_base + IDXD_DSACAP0_OFFSET); 590 + idxd->hw.dsacap1.bits = ioread64(idxd->reg_base + IDXD_DSACAP1_OFFSET); 591 + idxd->hw.dsacap2.bits = ioread64(idxd->reg_base + IDXD_DSACAP2_OFFSET); 592 + } 593 + 588 594 /* read iaa cap */ 589 595 if (idxd->data->type == IDXD_TYPE_IAX && idxd->hw.version >= DEVICE_VERSION_2) 590 596 idxd->hw.iaa_cap.bits = ioread64(idxd->reg_base + IDXD_IAACAP_OFFSET);

+25

drivers/dma/idxd/registers.h

··· 18 18 19 19 #define DEVICE_VERSION_1 0x100 20 20 #define DEVICE_VERSION_2 0x200 21 + #define DEVICE_VERSION_3 0x300 21 22 22 23 #define IDXD_MMIO_BAR 0 23 24 #define IDXD_WQ_BAR 2 ··· 585 584 u32 bits_lower32; 586 585 u32 bits_upper32; 587 586 }; 587 + u64 bits; 588 + }; 589 + 590 + #define IDXD_DSACAP0_OFFSET 0x180 591 + union dsacap0_reg { 592 + u64 bits; 593 + struct { 594 + u64 max_sgl_shift:4; 595 + u64 max_gr_block_shift:4; 596 + u64 ops_inter_domain:7; 597 + u64 rsvd1:17; 598 + u64 sgl_formats:16; 599 + u64 max_sg_process:8; 600 + u64 rsvd2:8; 601 + }; 602 + }; 603 + 604 + #define IDXD_DSACAP1_OFFSET 0x188 605 + union dsacap1_reg { 606 + u64 bits; 607 + }; 608 + 609 + #define IDXD_DSACAP2_OFFSET 0x190 610 + union dsacap2_reg { 588 611 u64 bits; 589 612 }; 590 613

+24

drivers/dma/idxd/sysfs.c

··· 1713 1713 } 1714 1714 static DEVICE_ATTR_RW(event_log_size); 1715 1715 1716 + static ssize_t dsacaps_show(struct device *dev, 1717 + struct device_attribute *attr, char *buf) 1718 + { 1719 + struct idxd_device *idxd = confdev_to_idxd(dev); 1720 + 1721 + return sysfs_emit(buf, "%016llx,%016llx,%016llx\n", 1722 + (u64)idxd->hw.dsacap2.bits, 1723 + (u64)idxd->hw.dsacap1.bits, 1724 + (u64)idxd->hw.dsacap0.bits); 1725 + } 1726 + static DEVICE_ATTR_RO(dsacaps); 1727 + 1716 1728 static bool idxd_device_attr_max_batch_size_invisible(struct attribute *attr, 1717 1729 struct idxd_device *idxd) 1718 1730 { ··· 1762 1750 !idxd->hw.gen_cap.evl_support); 1763 1751 } 1764 1752 1753 + static bool idxd_device_attr_dsacaps_invisible(struct attribute *attr, 1754 + struct idxd_device *idxd) 1755 + { 1756 + return attr == &dev_attr_dsacaps.attr && 1757 + (idxd->data->type != IDXD_TYPE_DSA || 1758 + idxd->hw.version < DEVICE_VERSION_3); 1759 + } 1760 + 1765 1761 static umode_t idxd_device_attr_visible(struct kobject *kobj, 1766 1762 struct attribute *attr, int n) 1767 1763 { ··· 1786 1766 return 0; 1787 1767 1788 1768 if (idxd_device_attr_event_log_size_invisible(attr, idxd)) 1769 + return 0; 1770 + 1771 + if (idxd_device_attr_dsacaps_invisible(attr, idxd)) 1789 1772 return 0; 1790 1773 1791 1774 return attr->mode; ··· 1818 1795 &dev_attr_cmd_status.attr, 1819 1796 &dev_attr_iaa_cap.attr, 1820 1797 &dev_attr_event_log_size.attr, 1798 + &dev_attr_dsacaps.attr, 1821 1799 NULL, 1822 1800 }; 1823 1801

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