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clk: samsung: exynos5250: do not define number of clocks in bindings

Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.

Define number of clocks per each clock controller inside the driver
directly.

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

+4 -1
+4 -1
drivers/clk/samsung/clk-exynos5250.c
··· 100 100 #define PWR_CTRL2_CORE2_UP_RATIO (1 << 4) 101 101 #define PWR_CTRL2_CORE1_UP_RATIO (1 << 0) 102 102 103 + /* NOTE: Must be equal to the last clock ID increased by one */ 104 + #define CLKS_NR (CLK_MOUT_VPLLSRC + 1) 105 + 103 106 /* list of PLLs to be registered */ 104 107 enum exynos5250_plls { 105 108 apll, mpll, cpll, epll, vpll, gpll, bpll, ··· 800 797 panic("%s: unable to determine soc\n", __func__); 801 798 } 802 799 803 - ctx = samsung_clk_init(NULL, reg_base, CLK_NR_CLKS); 800 + ctx = samsung_clk_init(NULL, reg_base, CLKS_NR); 804 801 hws = ctx->clk_data.hws; 805 802 806 803 samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks,