tjh.dev / kernel
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drm/amd/display: Disable MPC rate control on ODM pipe update

[Why]
Seamless boot skips MPC init for the active pipe, resulting in stale MPC
rate control state being retained. This will cause issues since other
logic assumes it is disabled (as DCN30 and newer does not need it).

[How]
Disable MPC rate control on ODM pipe update to cover the seamless boot
case.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Signed-off-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

George Shen and committed by
Alex Deucher 83626efd 95265e4b

+49
+12
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
··· 162 162 int opp_inst[MAX_PIPES] = {0}; 163 163 int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false); 164 164 int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true); 165 + struct mpc *mpc = dc->res_pool->mpc; 166 + int i; 165 167 166 168 opp_cnt = get_odm_config(pipe_ctx, opp_inst); 167 169 ··· 175 173 else 176 174 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 177 175 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 176 + 177 + if (mpc->funcs->set_out_rate_control) { 178 + for (i = 0; i < opp_cnt; ++i) { 179 + mpc->funcs->set_out_rate_control( 180 + mpc, opp_inst[i], 181 + false, 182 + 0, 183 + NULL); 184 + } 185 + } 178 186 179 187 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 180 188 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
+12
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
··· 426 426 int opp_inst[MAX_PIPES] = {0}; 427 427 int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false); 428 428 int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true); 429 + struct mpc *mpc = dc->res_pool->mpc; 430 + int i; 429 431 430 432 opp_cnt = get_odm_config(pipe_ctx, opp_inst); 431 433 ··· 439 437 else 440 438 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 441 439 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 440 + 441 + if (mpc->funcs->set_out_rate_control) { 442 + for (i = 0; i < opp_cnt; ++i) { 443 + mpc->funcs->set_out_rate_control( 444 + mpc, opp_inst[i], 445 + false, 446 + 0, 447 + NULL); 448 + } 449 + } 442 450 443 451 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 444 452 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
+18
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
··· 110 110 MPC_DWB0_MUX, 0xf); 111 111 } 112 112 113 + void mpc3_set_out_rate_control( 114 + struct mpc *mpc, 115 + int opp_id, 116 + bool enable, 117 + bool rate_2x_mode, 118 + struct mpc_dwb_flow_control *flow_control) 119 + { 120 + struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 121 + 122 + /* Always disable mpc out rate and flow control. 123 + * MPC flow rate control is not needed for DCN30 and above. 124 + */ 125 + REG_UPDATE_2(MUX[opp_id], 126 + MPC_OUT_RATE_CONTROL_DISABLE, 1, 127 + MPC_OUT_RATE_CONTROL, 0); 128 + } 129 + 113 130 enum dc_lut_mode mpc3_get_ogam_current(struct mpc *mpc, int mpcc_id) 114 131 { 115 132 /*Contrary to DCN2 and DCN1 wherein a single status register field holds this info; ··· 1536 1519 .set_dwb_mux = mpc3_set_dwb_mux, 1537 1520 .disable_dwb_mux = mpc3_disable_dwb_mux, 1538 1521 .is_dwb_idle = mpc3_is_dwb_idle, 1522 + .set_out_rate_control = mpc3_set_out_rate_control, 1539 1523 .set_gamut_remap = mpc3_set_gamut_remap, 1540 1524 .program_shaper = mpc3_program_shaper, 1541 1525 .acquire_rmu = mpcc3_acquire_rmu,
+7
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
··· 1085 1085 struct mpc *mpc, 1086 1086 int dwb_id); 1087 1087 1088 + void mpc3_set_out_rate_control( 1089 + struct mpc *mpc, 1090 + int opp_id, 1091 + bool enable, 1092 + bool rate_2x_mode, 1093 + struct mpc_dwb_flow_control *flow_control); 1094 + 1088 1095 void mpc3_power_on_ogam_lut( 1089 1096 struct mpc *mpc, int mpcc_id, 1090 1097 bool power_on);