Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'devicetree-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
"DT core:
- Add node lifecycle unit tests
- Add of_property_present() helper aligned with fwnode API
- Print more information on reserved regions on boot
- Update dtc to upstream v1.6.1-66-gabbd523bae6e
- Use strscpy() to instead of strncpy() in DT core
- Add option for schema validation on %.dtb targets
Bindings:
- Add/fix support for listing multiple patterns in DT_SCHEMA_FILES
- Rework external memory controller/bus bindings to properly support
controller specific child node properties
- Convert loongson,ls1x-intc, fcs,fusb302, sil,sii8620, Rockchip
RK3399 PCIe, Synquacer I2C, and Synquacer EXIU bindings to DT
schema format
- Add RiscV SBI PMU event mapping binding
- Add missing contraints on Arm SCMI child node allowed properties
- Add a bunch of missing Socionext UniPhier glue block bindings and
example fixes
- Various fixes for duplicate or conflicting type definitions on DT
properties"
* tag 'devicetree-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (66 commits)
dt-bindings: regulator: Add mps,mpq7932 power-management IC
of: dynamic: Fix spelling mistake "kojbect" -> "kobject"
dt-bindings: drop Sagar Kadam from SiFive binding maintainership
dt-bindings: sram: qcom,imem: document sm8450
dt-bindings: interrupt-controller: convert loongson,ls1x-intc.txt to json-schema
dt-bindings: arm: Add Cortex-A715 and X3
of: dynamic: add lifecycle docbook info to node creation functions
of: add consistency check to of_node_release()
of: do not use "%pOF" printk format on node with refcount of zero
of: unittest: add node lifecycle tests
of: update kconfig unittest help
of: add processing of EXPECT_NOT to of_unittest_expect
of: prepare to add processing of EXPECT_NOT to of_unittest_expect
of: Use preferred of_property_read_* functions
of: Use of_property_present() helper
of: Add of_property_present() helper
of: reserved_mem: Use proper binary prefix
dt-bindings: Fix multi pattern support in DT_SCHEMA_FILES
of: reserved-mem: print out reserved-mem details during boot
dt-bindings: serial: restrict possible child node names
...
+2333
-822
+1
-1
Documentation/devicetree/bindings/Makefile
+1
-1
Documentation/devicetree/bindings/Makefile
···
28
28
find_all_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \
29
29
-name 'processed-schema*' \)
30
30
31
-
find_cmd = $(find_all_cmd) | grep -F "$(DT_SCHEMA_FILES)"
31
+
find_cmd = $(find_all_cmd) | grep -F -e "$(subst :," -e ",$(DT_SCHEMA_FILES))"
32
32
CHK_DT_DOCS := $(shell $(find_cmd))
33
33
34
34
quiet_cmd_yamllint = LINT $(src)
+2
Documentation/devicetree/bindings/arm/cpus.yaml
+2
Documentation/devicetree/bindings/arm/cpus.yaml
···
141
141
- arm,cortex-a78ae
142
142
- arm,cortex-a510
143
143
- arm,cortex-a710
144
+
- arm,cortex-a715
144
145
- arm,cortex-m0
145
146
- arm,cortex-m0+
146
147
- arm,cortex-m1
···
152
151
- arm,cortex-r7
153
152
- arm,cortex-x1
154
153
- arm,cortex-x2
154
+
- arm,cortex-x3
155
155
- arm,neoverse-e1
156
156
- arm,neoverse-n1
157
157
- arm,neoverse-n2
+1
Documentation/devicetree/bindings/ata/intel,ixp4xx-compact-flash.yaml
+1
Documentation/devicetree/bindings/ata/intel,ixp4xx-compact-flash.yaml
+2
-64
Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml
Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml
+2
-64
Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml
Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: http://devicetree.org/schemas/bus/intel,ixp4xx-expansion-bus-controller.yaml#
4
+
$id: http://devicetree.org/schemas/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: Intel IXP4xx Expansion Bus Controller
···
56
56
description: Devices attached to chip selects are represented as
57
57
subnodes.
58
58
type: object
59
-
60
-
properties:
61
-
intel,ixp4xx-eb-t1:
62
-
description: Address timing, extend address phase with n cycles.
63
-
$ref: /schemas/types.yaml#/definitions/uint32
64
-
maximum: 3
65
-
66
-
intel,ixp4xx-eb-t2:
67
-
description: Setup chip select timing, extend setup phase with n cycles.
68
-
$ref: /schemas/types.yaml#/definitions/uint32
69
-
maximum: 3
70
-
71
-
intel,ixp4xx-eb-t3:
72
-
description: Strobe timing, extend strobe phase with n cycles.
73
-
$ref: /schemas/types.yaml#/definitions/uint32
74
-
maximum: 15
75
-
76
-
intel,ixp4xx-eb-t4:
77
-
description: Hold timing, extend hold phase with n cycles.
78
-
$ref: /schemas/types.yaml#/definitions/uint32
79
-
maximum: 3
80
-
81
-
intel,ixp4xx-eb-t5:
82
-
description: Recovery timing, extend recovery phase with n cycles.
83
-
$ref: /schemas/types.yaml#/definitions/uint32
84
-
maximum: 15
85
-
86
-
intel,ixp4xx-eb-cycle-type:
87
-
description: The type of cycles to use on the expansion bus for this
88
-
chip select. 0 = Intel cycles, 1 = Motorola cycles, 2 = HPI cycles.
89
-
$ref: /schemas/types.yaml#/definitions/uint32
90
-
enum: [0, 1, 2]
91
-
92
-
intel,ixp4xx-eb-byte-access-on-halfword:
93
-
description: Allow byte read access on half word devices.
94
-
$ref: /schemas/types.yaml#/definitions/uint32
95
-
enum: [0, 1]
96
-
97
-
intel,ixp4xx-eb-hpi-hrdy-pol-high:
98
-
description: Set HPI HRDY polarity to active high when using HPI.
99
-
$ref: /schemas/types.yaml#/definitions/uint32
100
-
enum: [0, 1]
101
-
102
-
intel,ixp4xx-eb-mux-address-and-data:
103
-
description: Multiplex address and data on the data bus.
104
-
$ref: /schemas/types.yaml#/definitions/uint32
105
-
enum: [0, 1]
106
-
107
-
intel,ixp4xx-eb-ahb-split-transfers:
108
-
description: Enable AHB split transfers.
109
-
$ref: /schemas/types.yaml#/definitions/uint32
110
-
enum: [0, 1]
111
-
112
-
intel,ixp4xx-eb-write-enable:
113
-
description: Enable write cycles.
114
-
$ref: /schemas/types.yaml#/definitions/uint32
115
-
enum: [0, 1]
116
-
117
-
intel,ixp4xx-eb-byte-access:
118
-
description: Expansion bus uses only 8 bits. The default is to use
119
-
16 bits.
120
-
$ref: /schemas/types.yaml#/definitions/uint32
121
-
enum: [0, 1]
59
+
$ref: /schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml#
122
60
123
61
required:
124
62
- compatible
+55
-4
Documentation/devicetree/bindings/clock/qcom,videocc.yaml
+55
-4
Documentation/devicetree/bindings/clock/qcom,videocc.yaml
···
30
30
- qcom,sm8250-videocc
31
31
32
32
clocks:
33
-
items:
34
-
- description: Board XO source
33
+
minItems: 1
34
+
maxItems: 3
35
35
36
36
clock-names:
37
-
items:
38
-
- const: bi_tcxo
37
+
minItems: 1
38
+
maxItems: 3
39
39
40
40
'#clock-cells':
41
41
const: 1
···
67
67
- '#clock-cells'
68
68
- '#reset-cells'
69
69
- '#power-domain-cells'
70
+
71
+
allOf:
72
+
- if:
73
+
properties:
74
+
compatible:
75
+
enum:
76
+
- qcom,sc7180-videocc
77
+
- qcom,sdm845-videocc
78
+
- qcom,sm8150-videocc
79
+
then:
80
+
properties:
81
+
clocks:
82
+
items:
83
+
- description: Board XO source
84
+
clock-names:
85
+
items:
86
+
- const: bi_tcxo
87
+
88
+
- if:
89
+
properties:
90
+
compatible:
91
+
enum:
92
+
- qcom,sc7280-videocc
93
+
then:
94
+
properties:
95
+
clocks:
96
+
items:
97
+
- description: Board XO source
98
+
- description: Board active XO source
99
+
clock-names:
100
+
items:
101
+
- const: bi_tcxo
102
+
- const: bi_tcxo_ao
103
+
104
+
- if:
105
+
properties:
106
+
compatible:
107
+
enum:
108
+
- qcom,sm8250-videocc
109
+
then:
110
+
properties:
111
+
clocks:
112
+
items:
113
+
- description: AHB
114
+
- description: Board XO source
115
+
- description: Board active XO source
116
+
clock-names:
117
+
items:
118
+
- const: iface
119
+
- const: bi_tcxo
120
+
- const: bi_tcxo_ao
70
121
71
122
additionalProperties: false
72
123
-1
Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml
-1
Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml
+3
-36
Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml
+3
-36
Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml
···
61
61
62
62
examples:
63
63
- |
64
-
sysctrl@61840000 {
65
-
compatible = "socionext,uniphier-sysctrl", "simple-mfd", "syscon";
66
-
reg = <0x61840000 0x4000>;
67
-
68
-
clock {
69
-
compatible = "socionext,uniphier-ld11-clock";
70
-
#clock-cells = <1>;
71
-
};
72
-
73
-
// other nodes ...
74
-
};
75
-
76
-
- |
77
-
mioctrl@59810000 {
78
-
compatible = "socionext,uniphier-mioctrl", "simple-mfd", "syscon";
79
-
reg = <0x59810000 0x800>;
80
-
81
-
clock {
82
-
compatible = "socionext,uniphier-ld11-mio-clock";
83
-
#clock-cells = <1>;
84
-
};
85
-
86
-
// other nodes ...
87
-
};
88
-
89
-
- |
90
-
perictrl@59820000 {
91
-
compatible = "socionext,uniphier-perictrl", "simple-mfd", "syscon";
92
-
reg = <0x59820000 0x200>;
93
-
94
-
clock {
95
-
compatible = "socionext,uniphier-ld11-peri-clock";
96
-
#clock-cells = <1>;
97
-
};
98
-
99
-
// other nodes ...
64
+
clock-controller {
65
+
compatible = "socionext,uniphier-ld11-clock";
66
+
#clock-cells = <1>;
100
67
};
+108
Documentation/devicetree/bindings/display/bridge/sil,sii8620.yaml
+108
Documentation/devicetree/bindings/display/bridge/sil,sii8620.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/bridge/sil,sii8620.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Silicon Image SiI8620 HDMI/MHL bridge
8
+
9
+
maintainers:
10
+
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11
+
12
+
properties:
13
+
compatible:
14
+
const: sil,sii8620
15
+
16
+
reg:
17
+
maxItems: 1
18
+
19
+
clocks:
20
+
maxItems: 1
21
+
22
+
clock-names:
23
+
items:
24
+
- const: xtal
25
+
26
+
cvcc10-supply:
27
+
description: Digital Core Supply Voltage (1.0V)
28
+
29
+
interrupts:
30
+
maxItems: 1
31
+
32
+
iovcc18-supply:
33
+
description: I/O Supply Voltage (1.8V)
34
+
35
+
reset-gpios:
36
+
maxItems: 1
37
+
38
+
ports:
39
+
$ref: /schemas/graph.yaml#/properties/ports
40
+
unevaluatedProperties: false
41
+
42
+
properties:
43
+
port@0:
44
+
$ref: /schemas/graph.yaml#/properties/port
45
+
description:
46
+
Video port for HDMI (encoder) input
47
+
48
+
port@1:
49
+
$ref: /schemas/graph.yaml#/properties/port
50
+
description:
51
+
MHL to connector port
52
+
53
+
required:
54
+
- port@0
55
+
- port@1
56
+
57
+
required:
58
+
- compatible
59
+
- reg
60
+
- clocks
61
+
- cvcc10-supply
62
+
- interrupts
63
+
- iovcc18-supply
64
+
- reset-gpios
65
+
- ports
66
+
67
+
additionalProperties: false
68
+
69
+
examples:
70
+
- |
71
+
#include <dt-bindings/gpio/gpio.h>
72
+
#include <dt-bindings/interrupt-controller/irq.h>
73
+
74
+
i2c {
75
+
#address-cells = <1>;
76
+
#size-cells = <0>;
77
+
78
+
bridge@39 {
79
+
reg = <0x39>;
80
+
compatible = "sil,sii8620";
81
+
cvcc10-supply = <&ldo36_reg>;
82
+
iovcc18-supply = <&ldo34_reg>;
83
+
interrupt-parent = <&gpf0>;
84
+
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
85
+
reset-gpios = <&gpv7 0 GPIO_ACTIVE_LOW>;
86
+
clocks = <&pmu_system_controller 0>;
87
+
clock-names = "xtal";
88
+
89
+
ports {
90
+
#address-cells = <1>;
91
+
#size-cells = <0>;
92
+
93
+
port@0 {
94
+
reg = <0>;
95
+
mhl_to_hdmi: endpoint {
96
+
remote-endpoint = <&hdmi_to_mhl>;
97
+
};
98
+
};
99
+
100
+
port@1 {
101
+
reg = <1>;
102
+
mhl_to_musb_con: endpoint {
103
+
remote-endpoint = <&musb_con_to_mhl>;
104
+
};
105
+
};
106
+
};
107
+
};
108
+
};
-33
Documentation/devicetree/bindings/display/bridge/sil-sii8620.txt
-33
Documentation/devicetree/bindings/display/bridge/sil-sii8620.txt
···
1
-
Silicon Image SiI8620 HDMI/MHL bridge bindings
2
-
3
-
Required properties:
4
-
- compatible: "sil,sii8620"
5
-
- reg: i2c address of the bridge
6
-
- cvcc10-supply: Digital Core Supply Voltage (1.0V)
7
-
- iovcc18-supply: I/O Supply Voltage (1.8V)
8
-
- interrupts: interrupt specifier of INT pin
9
-
- reset-gpios: gpio specifier of RESET pin
10
-
- clocks, clock-names: specification and name of "xtal" clock
11
-
- video interfaces: Device node can contain video interface port
12
-
node for HDMI encoder according to [1].
13
-
14
-
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
15
-
16
-
Example:
17
-
sii8620@39 {
18
-
reg = <0x39>;
19
-
compatible = "sil,sii8620";
20
-
cvcc10-supply = <&ldo36_reg>;
21
-
iovcc18-supply = <&ldo34_reg>;
22
-
interrupt-parent = <&gpf0>;
23
-
interrupts = <2 0>;
24
-
reset-gpio = <&gpv7 0 0>;
25
-
clocks = <&pmu_system_controller 0>;
26
-
clock-names = "xtal";
27
-
28
-
port {
29
-
mhl_to_hdmi: endpoint {
30
-
remote-endpoint = <&hdmi_to_mhl>;
31
-
};
32
-
};
33
-
};
+1
-2
Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+1
-2
Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+1
-1
Documentation/devicetree/bindings/display/msm/gpu.yaml
+1
-1
Documentation/devicetree/bindings/display/msm/gpu.yaml
+1
-2
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml
+1
-2
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml
+1
-2
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml
+1
-2
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml
+1
-2
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml
+1
-2
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml
+1
-2
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml
+1
-2
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml
+1
-2
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml
+1
-2
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml
+1
-2
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml
+1
-2
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml
+1
-2
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
+1
-2
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
+1
-2
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml
+1
-2
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml
+1
-2
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-tvo.yaml
+1
-2
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-tvo.yaml
+1
-2
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml
+1
-2
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml
+1
-8
Documentation/devicetree/bindings/dma/ti/k3-udma.yaml
+1
-8
Documentation/devicetree/bindings/dma/ti/k3-udma.yaml
···
44
44
45
45
allOf:
46
46
- $ref: "../dma-controller.yaml#"
47
+
- $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
47
48
48
49
properties:
49
50
"#dma-cells":
···
78
77
- const: tchanrt
79
78
80
79
msi-parent: true
81
-
82
-
ti,sci:
83
-
description: phandle to TI-SCI compatible System controller node
84
-
$ref: /schemas/types.yaml#/definitions/phandle
85
-
86
-
ti,sci-dev-id:
87
-
description: TI-SCI device id of UDMAP
88
-
$ref: /schemas/types.yaml#/definitions/uint32
89
80
90
81
ti,ringacc:
91
82
description: phandle to the ring accelerator node
+33
-10
Documentation/devicetree/bindings/firmware/arm,scmi.yaml
+33
-10
Documentation/devicetree/bindings/firmware/arm,scmi.yaml
···
100
100
Channel specifier required when using OP-TEE transport.
101
101
102
102
protocol@11:
103
-
type: object
103
+
$ref: '#/$defs/protocol-node'
104
+
unevaluatedProperties: false
105
+
104
106
properties:
105
107
reg:
106
108
const: 0x11
···
114
112
- '#power-domain-cells'
115
113
116
114
protocol@13:
117
-
type: object
115
+
$ref: '#/$defs/protocol-node'
116
+
unevaluatedProperties: false
117
+
118
118
properties:
119
119
reg:
120
120
const: 0x13
···
128
124
- '#clock-cells'
129
125
130
126
protocol@14:
131
-
type: object
127
+
$ref: '#/$defs/protocol-node'
128
+
unevaluatedProperties: false
129
+
132
130
properties:
133
131
reg:
134
132
const: 0x14
···
142
136
- '#clock-cells'
143
137
144
138
protocol@15:
145
-
type: object
139
+
$ref: '#/$defs/protocol-node'
140
+
unevaluatedProperties: false
141
+
146
142
properties:
147
143
reg:
148
144
const: 0x15
···
156
148
- '#thermal-sensor-cells'
157
149
158
150
protocol@16:
159
-
type: object
151
+
$ref: '#/$defs/protocol-node'
152
+
unevaluatedProperties: false
153
+
160
154
properties:
161
155
reg:
162
156
const: 0x16
···
170
160
- '#reset-cells'
171
161
172
162
protocol@17:
173
-
type: object
163
+
$ref: '#/$defs/protocol-node'
164
+
unevaluatedProperties: false
165
+
174
166
properties:
175
167
reg:
176
168
const: 0x17
177
169
178
170
regulators:
179
171
type: object
172
+
additionalProperties: false
180
173
description:
181
174
The list of all regulators provided by this SCMI controller.
182
175
176
+
properties:
177
+
'#address-cells':
178
+
const: 1
179
+
180
+
'#size-cells':
181
+
const: 0
182
+
183
183
patternProperties:
184
-
'^regulators@[0-9a-f]+$':
184
+
'^regulator@[0-9a-f]+$':
185
185
type: object
186
186
$ref: "../regulator/regulator.yaml#"
187
+
unevaluatedProperties: false
187
188
188
189
properties:
189
190
reg:
···
205
184
- reg
206
185
207
186
protocol@18:
208
-
type: object
187
+
$ref: '#/$defs/protocol-node'
188
+
unevaluatedProperties: false
189
+
209
190
properties:
210
191
reg:
211
192
const: 0x18
212
193
213
194
additionalProperties: false
214
195
215
-
patternProperties:
216
-
'^protocol@[0-9a-f]+$':
196
+
$defs:
197
+
protocol-node:
217
198
type: object
218
199
description:
219
200
Each sub-node represents a protocol supported. If the platform
+1
-2
Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml
+1
-2
Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml
-29
Documentation/devicetree/bindings/i2c/i2c-synquacer.txt
-29
Documentation/devicetree/bindings/i2c/i2c-synquacer.txt
···
1
-
Socionext SynQuacer I2C
2
-
3
-
Required properties:
4
-
- compatible : Must be "socionext,synquacer-i2c"
5
-
- reg : Offset and length of the register set for the device
6
-
- interrupts : A single interrupt specifier
7
-
- #address-cells : Must be <1>;
8
-
- #size-cells : Must be <0>;
9
-
- clock-names : Must contain "pclk".
10
-
- clocks : Must contain an entry for each name in clock-names.
11
-
(See the common clock bindings.)
12
-
13
-
Optional properties:
14
-
- clock-frequency : Desired I2C bus clock frequency in Hz. As only Normal and
15
-
Fast modes are supported, possible values are 100000 and
16
-
400000.
17
-
18
-
Example :
19
-
20
-
i2c@51210000 {
21
-
compatible = "socionext,synquacer-i2c";
22
-
reg = <0x51210000 0x1000>;
23
-
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
24
-
#address-cells = <1>;
25
-
#size-cells = <0>;
26
-
clock-names = "pclk";
27
-
clocks = <&clk_i2c>;
28
-
clock-frequency = <400000>;
29
-
};
+2
Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
+2
Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
+58
Documentation/devicetree/bindings/i2c/socionext,synquacer-i2c.yaml
+58
Documentation/devicetree/bindings/i2c/socionext,synquacer-i2c.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/i2c/socionext,synquacer-i2c.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Socionext SynQuacer I2C Controller
8
+
9
+
maintainers:
10
+
- Ard Biesheuvel <ardb@kernel.org>
11
+
12
+
allOf:
13
+
- $ref: /schemas/i2c/i2c-controller.yaml#
14
+
15
+
properties:
16
+
compatible:
17
+
const: socionext,synquacer-i2c
18
+
19
+
reg:
20
+
maxItems: 1
21
+
22
+
clocks:
23
+
maxItems: 1
24
+
25
+
clock-names:
26
+
const: pclk
27
+
28
+
clock-frequency:
29
+
minimum: 100000
30
+
maximum: 400000
31
+
32
+
interrupts:
33
+
maxItems: 1
34
+
35
+
required:
36
+
- compatible
37
+
- reg
38
+
- interrupts
39
+
- clocks
40
+
- clock-names
41
+
42
+
unevaluatedProperties: false
43
+
44
+
examples:
45
+
- |
46
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
47
+
48
+
i2c@51210000 {
49
+
compatible = "socionext,synquacer-i2c";
50
+
reg = <0x51210000 0x1000>;
51
+
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
52
+
#address-cells = <1>;
53
+
#size-cells = <0>;
54
+
clock-names = "pclk";
55
+
clocks = <&clk_i2c>;
56
+
clock-frequency = <400000>;
57
+
};
58
+
...
+2
-1
Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
+2
-1
Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
···
109
109
for system suspend/resume.
110
110
111
111
brcm,int-fwd-mask:
112
-
$ref: /schemas/types.yaml#/definitions/uint32
112
+
$ref: /schemas/types.yaml#/definitions/uint32-array
113
+
maxItems: 1
113
114
description: >
114
115
if present, a bit mask to configure the interrupts which have a mux gate,
115
116
typically UARTs. Setting these bits will make their respective interrupt
-24
Documentation/devicetree/bindings/interrupt-controller/loongson,ls1x-intc.txt
-24
Documentation/devicetree/bindings/interrupt-controller/loongson,ls1x-intc.txt
···
1
-
Loongson ls1x Interrupt Controller
2
-
3
-
Required properties:
4
-
5
-
- compatible : should be "loongson,ls1x-intc". Valid strings are:
6
-
7
-
- reg : Specifies base physical address and size of the registers.
8
-
- interrupt-controller : Identifies the node as an interrupt controller
9
-
- #interrupt-cells : Specifies the number of cells needed to encode an
10
-
interrupt source. The value shall be 2.
11
-
- interrupts : Specifies the CPU interrupt the controller is connected to.
12
-
13
-
Example:
14
-
15
-
intc: interrupt-controller@1fd01040 {
16
-
compatible = "loongson,ls1x-intc";
17
-
reg = <0x1fd01040 0x18>;
18
-
19
-
interrupt-controller;
20
-
#interrupt-cells = <2>;
21
-
22
-
interrupt-parent = <&cpu_intc>;
23
-
interrupts = <2>;
24
-
};
+51
Documentation/devicetree/bindings/interrupt-controller/loongson,ls1x-intc.yaml
+51
Documentation/devicetree/bindings/interrupt-controller/loongson,ls1x-intc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/interrupt-controller/loongson,ls1x-intc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Loongson-1 Interrupt Controller
8
+
9
+
maintainers:
10
+
- Keguang Zhang <keguang.zhang@gmail.com>
11
+
12
+
description:
13
+
Loongson-1 interrupt controller is connected to the MIPS core interrupt
14
+
controller, which controls several groups of interrupts.
15
+
16
+
properties:
17
+
compatible:
18
+
const: loongson,ls1x-intc
19
+
20
+
reg:
21
+
maxItems: 1
22
+
23
+
interrupt-controller: true
24
+
25
+
'#interrupt-cells':
26
+
const: 2
27
+
28
+
interrupts:
29
+
maxItems: 1
30
+
31
+
required:
32
+
- compatible
33
+
- reg
34
+
- interrupt-controller
35
+
- '#interrupt-cells'
36
+
- interrupts
37
+
38
+
additionalProperties: false
39
+
40
+
examples:
41
+
- |
42
+
intc0: interrupt-controller@1fd01040 {
43
+
compatible = "loongson,ls1x-intc";
44
+
reg = <0x1fd01040 0x18>;
45
+
46
+
interrupt-controller;
47
+
#interrupt-cells = <2>;
48
+
49
+
interrupt-parent = <&cpu_intc>;
50
+
interrupts = <2>;
51
+
};
-1
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
-1
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
-31
Documentation/devicetree/bindings/interrupt-controller/socionext,synquacer-exiu.txt
-31
Documentation/devicetree/bindings/interrupt-controller/socionext,synquacer-exiu.txt
···
1
-
Socionext SynQuacer External Interrupt Unit (EXIU)
2
-
3
-
The Socionext Synquacer SoC has an external interrupt unit (EXIU)
4
-
that forwards a block of 32 configurable input lines to 32 adjacent
5
-
level-high type GICv3 SPIs.
6
-
7
-
Required properties:
8
-
9
-
- compatible : Should be "socionext,synquacer-exiu".
10
-
- reg : Specifies base physical address and size of the
11
-
control registers.
12
-
- interrupt-controller : Identifies the node as an interrupt controller.
13
-
- #interrupt-cells : Specifies the number of cells needed to encode an
14
-
interrupt source. The value must be 3.
15
-
- socionext,spi-base : The SPI number of the first SPI of the 32 adjacent
16
-
ones the EXIU forwards its interrups to.
17
-
18
-
Notes:
19
-
20
-
- Only SPIs can use the EXIU as an interrupt parent.
21
-
22
-
Example:
23
-
24
-
exiu: interrupt-controller@510c0000 {
25
-
compatible = "socionext,synquacer-exiu";
26
-
reg = <0x0 0x510c0000 0x0 0x20>;
27
-
interrupt-controller;
28
-
interrupt-parent = <&gic>;
29
-
#interrupt-cells = <3>;
30
-
socionext,spi-base = <112>;
31
-
};
+53
Documentation/devicetree/bindings/interrupt-controller/socionext,synquacer-exiu.yaml
+53
Documentation/devicetree/bindings/interrupt-controller/socionext,synquacer-exiu.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/interrupt-controller/socionext,synquacer-exiu.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Socionext SynQuacer External Interrupt Unit (EXIU)
8
+
9
+
maintainers:
10
+
- Ard Biesheuvel <ardb@kernel.org>
11
+
12
+
description: |+
13
+
The Socionext SynQuacer SoC has an external interrupt unit (EXIU)
14
+
that forwards a block of 32 configurable input lines to 32 adjacent
15
+
level-high type GICv3 SPIs.
16
+
17
+
properties:
18
+
compatible:
19
+
const: socionext,synquacer-exiu
20
+
21
+
reg:
22
+
maxItems: 1
23
+
24
+
'#interrupt-cells':
25
+
const: 3
26
+
27
+
interrupt-controller: true
28
+
29
+
socionext,spi-base:
30
+
$ref: /schemas/types.yaml#/definitions/uint32
31
+
description: The SPI number of the first SPI of the 32 adjacent ones the
32
+
EXIU forwards its interrupts to.
33
+
34
+
required:
35
+
- compatible
36
+
- reg
37
+
- '#interrupt-cells'
38
+
- interrupt-controller
39
+
- socionext,spi-base
40
+
41
+
unevaluatedProperties: false
42
+
43
+
examples:
44
+
- |
45
+
interrupt-controller@510c0000 {
46
+
compatible = "socionext,synquacer-exiu";
47
+
reg = <0x510c0000 0x20>;
48
+
interrupt-controller;
49
+
interrupt-parent = <&gic>;
50
+
#interrupt-cells = <3>;
51
+
socionext,spi-base = <112>;
52
+
};
53
+
...
+80
Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml
+80
Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Peripheral properties for Intel IXP4xx Expansion Bus
8
+
9
+
description:
10
+
The IXP4xx expansion bus controller handles access to devices on the
11
+
memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
12
+
including IXP42x, IXP43x, IXP45x and IXP46x.
13
+
14
+
maintainers:
15
+
- Linus Walleij <linus.walleij@linaro.org>
16
+
17
+
properties:
18
+
intel,ixp4xx-eb-t1:
19
+
description: Address timing, extend address phase with n cycles.
20
+
$ref: /schemas/types.yaml#/definitions/uint32
21
+
maximum: 3
22
+
23
+
intel,ixp4xx-eb-t2:
24
+
description: Setup chip select timing, extend setup phase with n cycles.
25
+
$ref: /schemas/types.yaml#/definitions/uint32
26
+
maximum: 3
27
+
28
+
intel,ixp4xx-eb-t3:
29
+
description: Strobe timing, extend strobe phase with n cycles.
30
+
$ref: /schemas/types.yaml#/definitions/uint32
31
+
maximum: 15
32
+
33
+
intel,ixp4xx-eb-t4:
34
+
description: Hold timing, extend hold phase with n cycles.
35
+
$ref: /schemas/types.yaml#/definitions/uint32
36
+
maximum: 3
37
+
38
+
intel,ixp4xx-eb-t5:
39
+
description: Recovery timing, extend recovery phase with n cycles.
40
+
$ref: /schemas/types.yaml#/definitions/uint32
41
+
maximum: 15
42
+
43
+
intel,ixp4xx-eb-cycle-type:
44
+
description: The type of cycles to use on the expansion bus for this
45
+
chip select. 0 = Intel cycles, 1 = Motorola cycles, 2 = HPI cycles.
46
+
$ref: /schemas/types.yaml#/definitions/uint32
47
+
enum: [0, 1, 2]
48
+
49
+
intel,ixp4xx-eb-byte-access-on-halfword:
50
+
description: Allow byte read access on half word devices.
51
+
$ref: /schemas/types.yaml#/definitions/uint32
52
+
enum: [0, 1]
53
+
54
+
intel,ixp4xx-eb-hpi-hrdy-pol-high:
55
+
description: Set HPI HRDY polarity to active high when using HPI.
56
+
$ref: /schemas/types.yaml#/definitions/uint32
57
+
enum: [0, 1]
58
+
59
+
intel,ixp4xx-eb-mux-address-and-data:
60
+
description: Multiplex address and data on the data bus.
61
+
$ref: /schemas/types.yaml#/definitions/uint32
62
+
enum: [0, 1]
63
+
64
+
intel,ixp4xx-eb-ahb-split-transfers:
65
+
description: Enable AHB split transfers.
66
+
$ref: /schemas/types.yaml#/definitions/uint32
67
+
enum: [0, 1]
68
+
69
+
intel,ixp4xx-eb-write-enable:
70
+
description: Enable write cycles.
71
+
$ref: /schemas/types.yaml#/definitions/uint32
72
+
enum: [0, 1]
73
+
74
+
intel,ixp4xx-eb-byte-access:
75
+
description: Expansion bus uses only 8 bits. The default is to use
76
+
16 bits.
77
+
$ref: /schemas/types.yaml#/definitions/uint32
78
+
enum: [0, 1]
79
+
80
+
additionalProperties: true
+1
Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml
+1
Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml
+1
-1
Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml
+1
-1
Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml
···
90
90
91
91
interrupt-controller:
92
92
description: |
93
-
The GPMC driver implements and interrupt controller for
93
+
The GPMC driver implements an interrupt controller for
94
94
the NAND events "fifoevent" and "termcount" plus the
95
95
rising/falling edges on the GPMC_WAIT pins.
96
96
The interrupt number mapping is as follows
+1
-2
Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
+1
-2
Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
+1
Documentation/devicetree/bindings/mtd/mtd-physmap.yaml
+1
Documentation/devicetree/bindings/mtd/mtd-physmap.yaml
+46
-55
Documentation/devicetree/bindings/nvmem/socionext,uniphier-efuse.yaml
+46
-55
Documentation/devicetree/bindings/nvmem/socionext,uniphier-efuse.yaml
···
31
31
32
32
examples:
33
33
- |
34
-
// The UniPhier eFuse should be a subnode of a "soc-glue" node.
34
+
efuse@100 {
35
+
compatible = "socionext,uniphier-efuse";
36
+
reg = <0x100 0x28>;
37
+
};
35
38
36
-
soc-glue@5f900000 {
37
-
compatible = "simple-mfd";
39
+
efuse@200 {
40
+
compatible = "socionext,uniphier-efuse";
41
+
reg = <0x200 0x68>;
38
42
#address-cells = <1>;
39
43
#size-cells = <1>;
40
-
ranges = <0x0 0x5f900000 0x2000>;
41
44
42
-
efuse@100 {
43
-
compatible = "socionext,uniphier-efuse";
44
-
reg = <0x100 0x28>;
45
+
/* Data cells */
46
+
usb_rterm0: trim@54,4 {
47
+
reg = <0x54 1>;
48
+
bits = <4 2>;
45
49
};
46
-
47
-
efuse@200 {
48
-
compatible = "socionext,uniphier-efuse";
49
-
reg = <0x200 0x68>;
50
-
#address-cells = <1>;
51
-
#size-cells = <1>;
52
-
53
-
/* Data cells */
54
-
usb_rterm0: trim@54,4 {
55
-
reg = <0x54 1>;
56
-
bits = <4 2>;
57
-
};
58
-
usb_rterm1: trim@55,4 {
59
-
reg = <0x55 1>;
60
-
bits = <4 2>;
61
-
};
62
-
usb_rterm2: trim@58,4 {
63
-
reg = <0x58 1>;
64
-
bits = <4 2>;
65
-
};
66
-
usb_rterm3: trim@59,4 {
67
-
reg = <0x59 1>;
68
-
bits = <4 2>;
69
-
};
70
-
usb_sel_t0: trim@54,0 {
71
-
reg = <0x54 1>;
72
-
bits = <0 4>;
73
-
};
74
-
usb_sel_t1: trim@55,0 {
75
-
reg = <0x55 1>;
76
-
bits = <0 4>;
77
-
};
78
-
usb_sel_t2: trim@58,0 {
79
-
reg = <0x58 1>;
80
-
bits = <0 4>;
81
-
};
82
-
usb_sel_t3: trim@59,0 {
83
-
reg = <0x59 1>;
84
-
bits = <0 4>;
85
-
};
86
-
usb_hs_i0: trim@56,0 {
87
-
reg = <0x56 1>;
88
-
bits = <0 4>;
89
-
};
90
-
usb_hs_i2: trim@5a,0 {
91
-
reg = <0x5a 1>;
92
-
bits = <0 4>;
93
-
};
50
+
usb_rterm1: trim@55,4 {
51
+
reg = <0x55 1>;
52
+
bits = <4 2>;
53
+
};
54
+
usb_rterm2: trim@58,4 {
55
+
reg = <0x58 1>;
56
+
bits = <4 2>;
57
+
};
58
+
usb_rterm3: trim@59,4 {
59
+
reg = <0x59 1>;
60
+
bits = <4 2>;
61
+
};
62
+
usb_sel_t0: trim@54,0 {
63
+
reg = <0x54 1>;
64
+
bits = <0 4>;
65
+
};
66
+
usb_sel_t1: trim@55,0 {
67
+
reg = <0x55 1>;
68
+
bits = <0 4>;
69
+
};
70
+
usb_sel_t2: trim@58,0 {
71
+
reg = <0x58 1>;
72
+
bits = <0 4>;
73
+
};
74
+
usb_sel_t3: trim@59,0 {
75
+
reg = <0x59 1>;
76
+
bits = <0 4>;
77
+
};
78
+
usb_hs_i0: trim@56,0 {
79
+
reg = <0x56 1>;
80
+
bits = <0 4>;
81
+
};
82
+
usb_hs_i2: trim@5a,0 {
83
+
reg = <0x5a 1>;
84
+
bits = <0 4>;
94
85
};
95
86
};
+69
Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-common.yaml
+69
Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-common.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-common.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Rockchip AXI PCIe Bridge Common Properties
8
+
9
+
maintainers:
10
+
- Shawn Lin <shawn.lin@rock-chips.com>
11
+
12
+
properties:
13
+
reg:
14
+
maxItems: 2
15
+
16
+
clocks:
17
+
maxItems: 4
18
+
19
+
clock-names:
20
+
items:
21
+
- const: aclk
22
+
- const: aclk-perf
23
+
- const: hclk
24
+
- const: pm
25
+
26
+
num-lanes:
27
+
maximum: 4
28
+
29
+
phys:
30
+
oneOf:
31
+
- maxItems: 1
32
+
- maxItems: 4
33
+
34
+
phy-names:
35
+
oneOf:
36
+
- const: pcie-phy
37
+
- items:
38
+
- const: pcie-phy-0
39
+
- const: pcie-phy-1
40
+
- const: pcie-phy-2
41
+
- const: pcie-phy-3
42
+
43
+
resets:
44
+
maxItems: 7
45
+
46
+
reset-names:
47
+
items:
48
+
- const: core
49
+
- const: mgmt
50
+
- const: mgmt-sticky
51
+
- const: pipe
52
+
- const: pm
53
+
- const: pclk
54
+
- const: aclk
55
+
56
+
required:
57
+
- compatible
58
+
- reg
59
+
- reg-names
60
+
- clocks
61
+
- clock-names
62
+
- phys
63
+
- phy-names
64
+
- resets
65
+
- reset-names
66
+
67
+
additionalProperties: true
68
+
69
+
...
+68
Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml
+68
Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-ep.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Rockchip AXI PCIe Endpoint
8
+
9
+
maintainers:
10
+
- Shawn Lin <shawn.lin@rock-chips.com>
11
+
12
+
allOf:
13
+
- $ref: /schemas/pci/pci-ep.yaml#
14
+
- $ref: rockchip,rk3399-pcie-common.yaml#
15
+
16
+
properties:
17
+
compatible:
18
+
const: rockchip,rk3399-pcie-ep
19
+
20
+
reg: true
21
+
22
+
reg-names:
23
+
items:
24
+
- const: apb-base
25
+
- const: mem-base
26
+
27
+
rockchip,max-outbound-regions:
28
+
description: Maximum number of outbound regions
29
+
$ref: /schemas/types.yaml#/definitions/uint32
30
+
maximum: 32
31
+
default: 32
32
+
33
+
required:
34
+
- rockchip,max-outbound-regions
35
+
36
+
unevaluatedProperties: false
37
+
38
+
examples:
39
+
- |
40
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
41
+
#include <dt-bindings/gpio/gpio.h>
42
+
#include <dt-bindings/clock/rk3399-cru.h>
43
+
44
+
bus {
45
+
#address-cells = <2>;
46
+
#size-cells = <2>;
47
+
48
+
pcie-ep@f8000000 {
49
+
compatible = "rockchip,rk3399-pcie-ep";
50
+
reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>;
51
+
reg-names = "apb-base", "mem-base";
52
+
clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
53
+
<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
54
+
clock-names = "aclk", "aclk-perf",
55
+
"hclk", "pm";
56
+
max-functions = /bits/ 8 <8>;
57
+
num-lanes = <4>;
58
+
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
59
+
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
60
+
<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
61
+
reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
62
+
"pm", "pclk", "aclk";
63
+
phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
64
+
phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
65
+
rockchip,max-outbound-regions = <16>;
66
+
};
67
+
};
68
+
...
+132
Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml
+132
Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Rockchip AXI PCIe Root Port Bridge Host
8
+
9
+
maintainers:
10
+
- Shawn Lin <shawn.lin@rock-chips.com>
11
+
12
+
allOf:
13
+
- $ref: /schemas/pci/pci-bus.yaml#
14
+
- $ref: rockchip,rk3399-pcie-common.yaml#
15
+
16
+
properties:
17
+
compatible:
18
+
const: rockchip,rk3399-pcie
19
+
20
+
reg: true
21
+
22
+
reg-names:
23
+
items:
24
+
- const: axi-base
25
+
- const: apb-base
26
+
27
+
interrupts:
28
+
maxItems: 3
29
+
30
+
interrupt-names:
31
+
items:
32
+
- const: sys
33
+
- const: legacy
34
+
- const: client
35
+
36
+
aspm-no-l0s:
37
+
description: This property is needed if using 24MHz OSC for RC's PHY.
38
+
39
+
ep-gpios:
40
+
description: pre-reset GPIO
41
+
42
+
vpcie12v-supply:
43
+
description: The 12v regulator to use for PCIe.
44
+
45
+
vpcie3v3-supply:
46
+
description: The 3.3v regulator to use for PCIe.
47
+
48
+
vpcie1v8-supply:
49
+
description: The 1.8v regulator to use for PCIe.
50
+
51
+
vpcie0v9-supply:
52
+
description: The 0.9v regulator to use for PCIe.
53
+
54
+
interrupt-controller:
55
+
type: object
56
+
additionalProperties: false
57
+
58
+
properties:
59
+
'#address-cells':
60
+
const: 0
61
+
62
+
'#interrupt-cells':
63
+
const: 1
64
+
65
+
interrupt-controller: true
66
+
67
+
required:
68
+
- ranges
69
+
- "#interrupt-cells"
70
+
- interrupts
71
+
- interrupt-controller
72
+
- interrupt-map
73
+
- interrupt-map-mask
74
+
- msi-map
75
+
76
+
unevaluatedProperties: false
77
+
78
+
examples:
79
+
- |
80
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
81
+
#include <dt-bindings/gpio/gpio.h>
82
+
#include <dt-bindings/clock/rk3399-cru.h>
83
+
84
+
bus {
85
+
#address-cells = <2>;
86
+
#size-cells = <2>;
87
+
88
+
pcie@f8000000 {
89
+
compatible = "rockchip,rk3399-pcie";
90
+
device_type = "pci";
91
+
#address-cells = <3>;
92
+
#size-cells = <2>;
93
+
clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
94
+
<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
95
+
clock-names = "aclk", "aclk-perf",
96
+
"hclk", "pm";
97
+
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
98
+
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
99
+
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
100
+
interrupt-names = "sys", "legacy", "client";
101
+
ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
102
+
ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
103
+
0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
104
+
num-lanes = <4>;
105
+
msi-map = <0x0 &its 0x0 0x1000>;
106
+
reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
107
+
reg-names = "axi-base", "apb-base";
108
+
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
109
+
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
110
+
<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
111
+
reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
112
+
"pm", "pclk", "aclk";
113
+
/* deprecated legacy PHY model */
114
+
phys = <&pcie_phy>;
115
+
phy-names = "pcie-phy";
116
+
pinctrl-names = "default";
117
+
pinctrl-0 = <&pcie_clkreq>;
118
+
#interrupt-cells = <1>;
119
+
interrupt-map-mask = <0 0 0 7>;
120
+
interrupt-map = <0 0 0 1 &pcie0_intc 0>,
121
+
<0 0 0 2 &pcie0_intc 1>,
122
+
<0 0 0 3 &pcie0_intc 2>,
123
+
<0 0 0 4 &pcie0_intc 3>;
124
+
125
+
pcie0_intc: interrupt-controller {
126
+
interrupt-controller;
127
+
#address-cells = <0>;
128
+
#interrupt-cells = <1>;
129
+
};
130
+
};
131
+
};
132
+
...
-62
Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt
-62
Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt
···
1
-
* Rockchip AXI PCIe Endpoint Controller DT description
2
-
3
-
Required properties:
4
-
- compatible: Should contain "rockchip,rk3399-pcie-ep"
5
-
- reg: Two register ranges as listed in the reg-names property
6
-
- reg-names: Must include the following names
7
-
- "apb-base"
8
-
- "mem-base"
9
-
- clocks: Must contain an entry for each entry in clock-names.
10
-
See ../clocks/clock-bindings.txt for details.
11
-
- clock-names: Must include the following entries:
12
-
- "aclk"
13
-
- "aclk-perf"
14
-
- "hclk"
15
-
- "pm"
16
-
- resets: Must contain seven entries for each entry in reset-names.
17
-
See ../reset/reset.txt for details.
18
-
- reset-names: Must include the following names
19
-
- "core"
20
-
- "mgmt"
21
-
- "mgmt-sticky"
22
-
- "pipe"
23
-
- "pm"
24
-
- "aclk"
25
-
- "pclk"
26
-
- pinctrl-names : The pin control state names
27
-
- pinctrl-0: The "default" pinctrl state
28
-
- phys: Must contain an phandle to a PHY for each entry in phy-names.
29
-
- phy-names: Must include 4 entries for all 4 lanes even if some of
30
-
them won't be used for your cases. Entries are of the form "pcie-phy-N":
31
-
where N ranges from 0 to 3.
32
-
(see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
33
-
for changing the #phy-cells of phy node to support it)
34
-
- rockchip,max-outbound-regions: Maximum number of outbound regions
35
-
36
-
Optional Property:
37
-
- num-lanes: number of lanes to use
38
-
- max-functions: Maximum number of functions that can be configured (default 1).
39
-
40
-
pcie0-ep: pcie@f8000000 {
41
-
compatible = "rockchip,rk3399-pcie-ep";
42
-
#address-cells = <3>;
43
-
#size-cells = <2>;
44
-
rockchip,max-outbound-regions = <16>;
45
-
clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
46
-
<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
47
-
clock-names = "aclk", "aclk-perf",
48
-
"hclk", "pm";
49
-
max-functions = /bits/ 8 <8>;
50
-
num-lanes = <4>;
51
-
reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>;
52
-
reg-names = "apb-base", "mem-base";
53
-
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
54
-
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
55
-
<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
56
-
reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
57
-
"pm", "pclk", "aclk";
58
-
phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
59
-
phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
60
-
pinctrl-names = "default";
61
-
pinctrl-0 = <&pcie_clkreq>;
62
-
};
-135
Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt
-135
Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt
···
1
-
* Rockchip AXI PCIe Root Port Bridge DT description
2
-
3
-
Required properties:
4
-
- #address-cells: Address representation for root ports, set to <3>
5
-
- #size-cells: Size representation for root ports, set to <2>
6
-
- #interrupt-cells: specifies the number of cells needed to encode an
7
-
interrupt source. The value must be 1.
8
-
- compatible: Should contain "rockchip,rk3399-pcie"
9
-
- reg: Two register ranges as listed in the reg-names property
10
-
- reg-names: Must include the following names
11
-
- "axi-base"
12
-
- "apb-base"
13
-
- clocks: Must contain an entry for each entry in clock-names.
14
-
See ../clocks/clock-bindings.txt for details.
15
-
- clock-names: Must include the following entries:
16
-
- "aclk"
17
-
- "aclk-perf"
18
-
- "hclk"
19
-
- "pm"
20
-
- msi-map: Maps a Requester ID to an MSI controller and associated
21
-
msi-specifier data. See ./pci-msi.txt
22
-
- interrupts: Three interrupt entries must be specified.
23
-
- interrupt-names: Must include the following names
24
-
- "sys"
25
-
- "legacy"
26
-
- "client"
27
-
- resets: Must contain seven entries for each entry in reset-names.
28
-
See ../reset/reset.txt for details.
29
-
- reset-names: Must include the following names
30
-
- "core"
31
-
- "mgmt"
32
-
- "mgmt-sticky"
33
-
- "pipe"
34
-
- "pm"
35
-
- "aclk"
36
-
- "pclk"
37
-
- pinctrl-names : The pin control state names
38
-
- pinctrl-0: The "default" pinctrl state
39
-
- #interrupt-cells: specifies the number of cells needed to encode an
40
-
interrupt source. The value must be 1.
41
-
- interrupt-map-mask and interrupt-map: standard PCI properties
42
-
43
-
Required properties for legacy PHY model (deprecated):
44
-
- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
45
-
- phy-names: MUST be "pcie-phy".
46
-
47
-
Required properties for per-lane PHY model (preferred):
48
-
- phys: Must contain an phandle to a PHY for each entry in phy-names.
49
-
- phy-names: Must include 4 entries for all 4 lanes even if some of
50
-
them won't be used for your cases. Entries are of the form "pcie-phy-N":
51
-
where N ranges from 0 to 3.
52
-
(see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
53
-
for changing the #phy-cells of phy node to support it)
54
-
55
-
Optional Property:
56
-
- aspm-no-l0s: RC won't support ASPM L0s. This property is needed if
57
-
using 24MHz OSC for RC's PHY.
58
-
- ep-gpios: contain the entry for pre-reset GPIO
59
-
- num-lanes: number of lanes to use
60
-
- vpcie12v-supply: The phandle to the 12v regulator to use for PCIe.
61
-
- vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
62
-
- vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.
63
-
- vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe.
64
-
65
-
*Interrupt controller child node*
66
-
The core controller provides a single interrupt for legacy INTx. The PCIe node
67
-
should contain an interrupt controller node as a target for the PCI
68
-
'interrupt-map' property. This node represents the domain at which the four
69
-
INTx interrupts are decoded and routed.
70
-
71
-
72
-
Required properties for Interrupt controller child node:
73
-
- interrupt-controller: identifies the node as an interrupt controller
74
-
- #address-cells: specifies the number of cells needed to encode an
75
-
address. The value must be 0.
76
-
- #interrupt-cells: specifies the number of cells needed to encode an
77
-
interrupt source. The value must be 1.
78
-
79
-
Example:
80
-
81
-
pcie0: pcie@f8000000 {
82
-
compatible = "rockchip,rk3399-pcie";
83
-
#address-cells = <3>;
84
-
#size-cells = <2>;
85
-
clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
86
-
<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
87
-
clock-names = "aclk", "aclk-perf",
88
-
"hclk", "pm";
89
-
bus-range = <0x0 0x1>;
90
-
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
91
-
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
92
-
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
93
-
interrupt-names = "sys", "legacy", "client";
94
-
assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
95
-
assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
96
-
assigned-clock-rates = <100000000>;
97
-
ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
98
-
ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
99
-
0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
100
-
num-lanes = <4>;
101
-
msi-map = <0x0 &its 0x0 0x1000>;
102
-
reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
103
-
reg-names = "axi-base", "apb-base";
104
-
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
105
-
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
106
-
<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
107
-
reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
108
-
"pm", "pclk", "aclk";
109
-
/* deprecated legacy PHY model */
110
-
phys = <&pcie_phy>;
111
-
phy-names = "pcie-phy";
112
-
pinctrl-names = "default";
113
-
pinctrl-0 = <&pcie_clkreq>;
114
-
#interrupt-cells = <1>;
115
-
interrupt-map-mask = <0 0 0 7>;
116
-
interrupt-map = <0 0 0 1 &pcie0_intc 0>,
117
-
<0 0 0 2 &pcie0_intc 1>,
118
-
<0 0 0 3 &pcie0_intc 2>,
119
-
<0 0 0 4 &pcie0_intc 3>;
120
-
pcie0_intc: interrupt-controller {
121
-
interrupt-controller;
122
-
#address-cells = <0>;
123
-
#interrupt-cells = <1>;
124
-
};
125
-
};
126
-
127
-
pcie0: pcie@f8000000 {
128
-
...
129
-
130
-
/* preferred per-lane PHY model */
131
-
phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
132
-
phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
133
-
134
-
...
135
-
};
+5
-9
Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
+5
-9
Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
+161
Documentation/devicetree/bindings/perf/riscv,pmu.yaml
+161
Documentation/devicetree/bindings/perf/riscv,pmu.yaml
···
1
+
# SPDX-License-Identifier: BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/perf/riscv,pmu.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: RISC-V SBI PMU events
8
+
9
+
maintainers:
10
+
- Atish Patra <atishp@rivosinc.com>
11
+
12
+
description: |
13
+
The SBI PMU extension allows supervisor software to configure, start and
14
+
stop any performance counter at anytime. Thus, a user can leverage all
15
+
capabilities of performance analysis tools, such as perf, if the SBI PMU
16
+
extension is enabled. The following constraints apply:
17
+
18
+
The platform must provide information about PMU event to counter mappings
19
+
either via device tree or another way, specific to the platform.
20
+
Without the event to counter mappings, the SBI PMU extension cannot be used.
21
+
22
+
Platforms should provide information about the PMU event selector values
23
+
that should be encoded in the expected value of MHPMEVENTx while configuring
24
+
MHPMCOUNTERx for that specific event. The can either be done via device tree
25
+
or another way, specific to the platform.
26
+
The exact value to be written to MHPMEVENTx is completely dependent on the
27
+
platform.
28
+
29
+
For information on the SBI specification see the section "Performance
30
+
Monitoring Unit Extension" of:
31
+
https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc
32
+
33
+
properties:
34
+
compatible:
35
+
const: riscv,pmu
36
+
37
+
riscv,event-to-mhpmevent:
38
+
$ref: /schemas/types.yaml#/definitions/uint32-matrix
39
+
description:
40
+
Represents an ONE-to-ONE mapping between a PMU event and the event
41
+
selector value that the platform expects to be written to the MHPMEVENTx
42
+
CSR for that event.
43
+
The mapping is encoded in an matrix format where each element represents
44
+
an event.
45
+
This property shouldn't encode any raw hardware event.
46
+
items:
47
+
items:
48
+
- description: event_idx, a 20-bit wide encoding of the event type and
49
+
code. Refer to the SBI specification for a complete description of
50
+
the event types and codes.
51
+
- description: upper 32 bits of the event selector value for MHPMEVENTx
52
+
- description: lower 32 bits of the event selector value for MHPMEVENTx
53
+
54
+
riscv,event-to-mhpmcounters:
55
+
$ref: /schemas/types.yaml#/definitions/uint32-matrix
56
+
description:
57
+
Represents a MANY-to-MANY mapping between a range of events and all the
58
+
MHPMCOUNTERx in a bitmap format that can be used to monitor these range
59
+
of events. The information is encoded in an matrix format where each
60
+
element represents a certain range of events and corresponding counters.
61
+
This property shouldn't encode any raw event.
62
+
items:
63
+
items:
64
+
- description: first event_idx of the range of events
65
+
- description: last event_idx of the range of events
66
+
- description: bitmap of MHPMCOUNTERx for this event
67
+
68
+
riscv,raw-event-to-mhpmcounters:
69
+
$ref: /schemas/types.yaml#/definitions/uint32-matrix
70
+
description:
71
+
Represents an ONE-to-MANY or MANY-to-MANY mapping between the rawevent(s)
72
+
and all the MHPMCOUNTERx in a bitmap format that can be used to monitor
73
+
that raw event.
74
+
The encoding of the raw events are platform specific. The information is
75
+
encoded in a matrix format where each element represents the specific raw
76
+
event(s).
77
+
If a platform directly encodes each raw PMU event as a unique ID, the
78
+
value of variant must be 0xffffffff_ffffffff.
79
+
items:
80
+
items:
81
+
- description:
82
+
upper 32 invariant bits for the range of events
83
+
- description:
84
+
lower 32 invariant bits for the range of events
85
+
- description:
86
+
upper 32 bits of the variant bit mask for the range of events
87
+
- description:
88
+
lower 32 bits of the variant bit mask for the range of events
89
+
- description:
90
+
bitmap of all MHPMCOUNTERx that can monitor the range of events
91
+
92
+
dependencies:
93
+
"riscv,event-to-mhpmevent": [ "riscv,event-to-mhpmcounters" ]
94
+
"riscv,event-to-mhpmcounters": [ "riscv,event-to-mhpmevent" ]
95
+
96
+
required:
97
+
- compatible
98
+
99
+
additionalProperties: false
100
+
101
+
examples:
102
+
- |
103
+
pmu {
104
+
compatible = "riscv,pmu";
105
+
riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
106
+
riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
107
+
<0x00002 0x00002 0x00000004>,
108
+
<0x00003 0x0000A 0x00000ff8>,
109
+
<0x10000 0x10033 0x000ff000>;
110
+
riscv,raw-event-to-mhpmcounters =
111
+
/* For event ID 0x0002 */
112
+
<0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
113
+
/* For event ID 0-4 */
114
+
<0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
115
+
/* For event ID 0xffffffff0000000f - 0xffffffff000000ff */
116
+
<0xffffffff 0x0 0xffffffff 0xffffff0f 0x00000ff0>;
117
+
};
118
+
119
+
- |
120
+
/*
121
+
* For HiFive Unmatched board the encodings can be found here
122
+
* https://sifive.cdn.prismic.io/sifive/1a82e600-1f93-4f41-b2d8-86ed8b16acba_fu740-c000-manual-v1p6.pdf
123
+
*
124
+
* This example also binds standard SBI PMU hardware IDs to U74 PMU event
125
+
* codes, U74 uses a bitfield for events encoding, so several U74 events
126
+
* can be bound to a single perf ID.
127
+
* See SBI PMU hardware IDs in arch/riscv/include/asm/sbi.h
128
+
*/
129
+
pmu {
130
+
compatible = "riscv,pmu";
131
+
riscv,event-to-mhpmevent =
132
+
/* SBI_PMU_HW_CACHE_REFERENCES -> Instruction or Data cache/ITIM busy */
133
+
<0x00003 0x00000000 0x1801>,
134
+
/* SBI_PMU_HW_CACHE_MISSES -> Instruction or Data cache miss or MMIO access */
135
+
<0x00004 0x00000000 0x0302>,
136
+
/* SBI_PMU_HW_BRANCH_INSTRUCTIONS -> Conditional branch retired */
137
+
<0x00005 0x00000000 0x4000>,
138
+
/* SBI_PMU_HW_BRANCH_MISSES -> Branch or jump misprediction */
139
+
<0x00006 0x00000000 0x6001>,
140
+
/* L1D_READ_MISS -> Data cache miss or MMIO access */
141
+
<0x10001 0x00000000 0x0202>,
142
+
/* L1D_WRITE_ACCESS -> Data cache write-back */
143
+
<0x10002 0x00000000 0x0402>,
144
+
/* L1I_READ_ACCESS -> Instruction cache miss */
145
+
<0x10009 0x00000000 0x0102>,
146
+
/* LL_READ_MISS -> UTLB miss */
147
+
<0x10011 0x00000000 0x2002>,
148
+
/* DTLB_READ_MISS -> Data TLB miss */
149
+
<0x10019 0x00000000 0x1002>,
150
+
/* ITLB_READ_MISS-> Instruction TLB miss */
151
+
<0x10021 0x00000000 0x0802>;
152
+
riscv,event-to-mhpmcounters = <0x00003 0x00006 0x18>,
153
+
<0x10001 0x10002 0x18>,
154
+
<0x10009 0x10009 0x18>,
155
+
<0x10011 0x10011 0x18>,
156
+
<0x10019 0x10019 0x18>,
157
+
<0x10021 0x10021 0x18>;
158
+
riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xfc0000ff 0x18>,
159
+
<0x0 0x1 0xffffffff 0xfff800ff 0x18>,
160
+
<0x0 0x2 0xffffffff 0xffffe0ff 0x18>;
161
+
};
+2
-1
Documentation/devicetree/bindings/phy/hisilicon,hi3660-usb3.yaml
+2
-1
Documentation/devicetree/bindings/phy/hisilicon,hi3660-usb3.yaml
+2
-1
Documentation/devicetree/bindings/phy/hisilicon,hi3670-usb3.yaml
+2
-1
Documentation/devicetree/bindings/phy/hisilicon,hi3670-usb3.yaml
···
32
32
description: phandle of syscon used to control phy deep sleep.
33
33
34
34
hisilicon,eye-diagram-param:
35
-
$ref: /schemas/types.yaml#/definitions/uint32
35
+
$ref: /schemas/types.yaml#/definitions/uint32-array
36
+
maxItems: 1
36
37
description: Eye diagram for phy.
37
38
38
39
hisilicon,tx-vboost-lvl:
+8
-16
Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml
+8
-16
Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml
···
117
117
118
118
examples:
119
119
- |
120
-
ahci-glue@65700000 {
121
-
compatible = "socionext,uniphier-pxs3-ahci-glue",
122
-
"simple-mfd";
123
-
#address-cells = <1>;
124
-
#size-cells = <1>;
125
-
ranges = <0 0x65700000 0x100>;
126
-
127
-
ahci_phy: phy@10 {
128
-
compatible = "socionext,uniphier-pxs3-ahci-phy";
129
-
reg = <0x10 0x10>;
130
-
#phy-cells = <0>;
131
-
clock-names = "link", "phy";
132
-
clocks = <&sys_clk 28>, <&sys_clk 30>;
133
-
reset-names = "link", "phy";
134
-
resets = <&sys_rst 28>, <&sys_rst 30>;
135
-
};
120
+
ahci_phy: phy@10 {
121
+
compatible = "socionext,uniphier-pxs3-ahci-phy";
122
+
reg = <0x10 0x10>;
123
+
#phy-cells = <0>;
124
+
clock-names = "link", "phy";
125
+
clocks = <&sys_clk 28>, <&sys_clk 30>;
126
+
reset-names = "link", "phy";
127
+
resets = <&sys_rst 28>, <&sys_rst 30>;
136
128
};
+15
-20
Documentation/devicetree/bindings/phy/socionext,uniphier-usb2-phy.yaml
+15
-20
Documentation/devicetree/bindings/phy/socionext,uniphier-usb2-phy.yaml
···
61
61
- |
62
62
// The UniPhier usb2-phy should be a subnode of a "syscon" compatible node.
63
63
64
-
soc-glue@5f800000 {
65
-
compatible = "socionext,uniphier-ld11-soc-glue", "simple-mfd", "syscon";
66
-
reg = <0x5f800000 0x2000>;
64
+
usb-hub {
65
+
compatible = "socionext,uniphier-ld11-usb2-phy";
66
+
#address-cells = <1>;
67
+
#size-cells = <0>;
67
68
68
-
usb-controller {
69
-
compatible = "socionext,uniphier-ld11-usb2-phy";
70
-
#address-cells = <1>;
71
-
#size-cells = <0>;
69
+
usb_phy0: phy@0 {
70
+
reg = <0>;
71
+
#phy-cells = <0>;
72
+
};
72
73
73
-
usb_phy0: phy@0 {
74
-
reg = <0>;
75
-
#phy-cells = <0>;
76
-
};
74
+
usb_phy1: phy@1 {
75
+
reg = <1>;
76
+
#phy-cells = <0>;
77
+
};
77
78
78
-
usb_phy1: phy@1 {
79
-
reg = <1>;
80
-
#phy-cells = <0>;
81
-
};
82
-
83
-
usb_phy2: phy@2 {
84
-
reg = <2>;
85
-
#phy-cells = <0>;
86
-
};
79
+
usb_phy2: phy@2 {
80
+
reg = <2>;
81
+
#phy-cells = <0>;
87
82
};
88
83
};
+11
-18
Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml
+11
-18
Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml
···
146
146
147
147
examples:
148
148
- |
149
-
usb-glue@65b00000 {
150
-
compatible = "socionext,uniphier-ld20-dwc3-glue", "simple-mfd";
151
-
#address-cells = <1>;
152
-
#size-cells = <1>;
153
-
ranges = <0 0x65b00000 0x400>;
154
-
155
-
usb_hsphy0: hs-phy@200 {
156
-
compatible = "socionext,uniphier-ld20-usb3-hsphy";
157
-
reg = <0x200 0x10>;
158
-
#phy-cells = <0>;
159
-
clock-names = "link", "phy";
160
-
clocks = <&sys_clk 14>, <&sys_clk 16>;
161
-
reset-names = "link", "phy";
162
-
resets = <&sys_rst 14>, <&sys_rst 16>;
163
-
vbus-supply = <&usb_vbus0>;
164
-
nvmem-cell-names = "rterm", "sel_t", "hs_i";
165
-
nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, <&usb_hs_i0>;
166
-
};
149
+
usb_hsphy0: phy@200 {
150
+
compatible = "socionext,uniphier-ld20-usb3-hsphy";
151
+
reg = <0x200 0x10>;
152
+
#phy-cells = <0>;
153
+
clock-names = "link", "phy";
154
+
clocks = <&sys_clk 14>, <&sys_clk 16>;
155
+
reset-names = "link", "phy";
156
+
resets = <&sys_rst 14>, <&sys_rst 16>;
157
+
vbus-supply = <&usb_vbus0>;
158
+
nvmem-cell-names = "rterm", "sel_t", "hs_i";
159
+
nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, <&usb_hs_i0>;
167
160
};
+9
-17
Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml
+9
-17
Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml
···
131
131
132
132
examples:
133
133
- |
134
-
usb-glue@65b00000 {
135
-
compatible = "socionext,uniphier-ld20-dwc3-glue",
136
-
"simple-mfd";
137
-
#address-cells = <1>;
138
-
#size-cells = <1>;
139
-
ranges = <0 0x65b00000 0x400>;
140
-
141
-
usb_ssphy0: ss-phy@300 {
142
-
compatible = "socionext,uniphier-ld20-usb3-ssphy";
143
-
reg = <0x300 0x10>;
144
-
#phy-cells = <0>;
145
-
clock-names = "link", "phy";
146
-
clocks = <&sys_clk 14>, <&sys_clk 16>;
147
-
reset-names = "link", "phy";
148
-
resets = <&sys_rst 14>, <&sys_rst 16>;
149
-
vbus-supply = <&usb_vbus0>;
150
-
};
134
+
usb_ssphy0: phy@300 {
135
+
compatible = "socionext,uniphier-ld20-usb3-ssphy";
136
+
reg = <0x300 0x10>;
137
+
#phy-cells = <0>;
138
+
clock-names = "link", "phy";
139
+
clocks = <&sys_clk 14>, <&sys_clk 16>;
140
+
reset-names = "link", "phy";
141
+
resets = <&sys_rst 14>, <&sys_rst 16>;
142
+
vbus-supply = <&usb_vbus0>;
151
143
};
+12
-5
Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml
+12
-5
Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml
···
1
1
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
2
3
%YAML 1.2
3
4
---
4
5
$id: http://devicetree.org/schemas/pinctrl/socionext,uniphier-pinctrl.yaml#
···
70
69
- |
71
70
// The UniPhier pinctrl should be a subnode of a "syscon" compatible node.
72
71
73
-
soc-glue@5f800000 {
74
-
compatible = "socionext,uniphier-pro4-soc-glue", "simple-mfd", "syscon";
75
-
reg = <0x5f800000 0x2000>;
72
+
pinctrl {
73
+
compatible = "socionext,uniphier-ld20-pinctrl";
76
74
77
-
pinctrl: pinctrl {
78
-
compatible = "socionext,uniphier-pro4-pinctrl";
75
+
pinctrl_ether_rgmii: ether-rgmii {
76
+
groups = "ether_rgmii";
77
+
function = "ether_rgmii";
78
+
79
+
tx {
80
+
pins = "RGMII_TXCLK", "RGMII_TXD0", "RGMII_TXD1",
81
+
"RGMII_TXD2", "RGMII_TXD3", "RGMII_TXCTL";
82
+
drive-strength = <9>;
83
+
};
79
84
};
80
85
};
-3
Documentation/devicetree/bindings/power/power-domain.yaml
-3
Documentation/devicetree/bindings/power/power-domain.yaml
···
43
43
domain would be considered as capable of being powered-on or powered-off.
44
44
45
45
operating-points-v2:
46
-
$ref: /schemas/types.yaml#/definitions/phandle-array
47
-
items:
48
-
maxItems: 1
49
46
description:
50
47
Phandles to the OPP tables of power domains provided by a power domain
51
48
provider. If the provider provides a single power domain only or all
+1
-2
Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.yaml
+1
-2
Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.yaml
-1
Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
-1
Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
+68
Documentation/devicetree/bindings/regulator/mps,mpq7932.yaml
+68
Documentation/devicetree/bindings/regulator/mps,mpq7932.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/regulator/mps,mpq7932.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Monolithic Power System MPQ7932 PMIC
8
+
9
+
maintainers:
10
+
- Saravanan Sekar <saravanan@linumiz.com>
11
+
12
+
properties:
13
+
compatible:
14
+
enum:
15
+
- mps,mpq7932
16
+
17
+
reg:
18
+
maxItems: 1
19
+
20
+
regulators:
21
+
type: object
22
+
description: |
23
+
list of regulators provided by this controller, must be named
24
+
after their hardware counterparts BUCK[1-6]
25
+
26
+
patternProperties:
27
+
"^buck[1-6]$":
28
+
type: object
29
+
$ref: regulator.yaml#
30
+
unevaluatedProperties: false
31
+
32
+
additionalProperties: false
33
+
34
+
required:
35
+
- compatible
36
+
- reg
37
+
- regulators
38
+
39
+
additionalProperties: false
40
+
41
+
examples:
42
+
- |
43
+
i2c {
44
+
#address-cells = <1>;
45
+
#size-cells = <0>;
46
+
47
+
pmic@3 {
48
+
compatible = "mps,mpq7932";
49
+
reg = <0x3>;
50
+
51
+
regulators {
52
+
buck1 {
53
+
regulator-name = "buck1";
54
+
regulator-min-microvolt = <1600000>;
55
+
regulator-max-microvolt = <1800000>;
56
+
regulator-boot-on;
57
+
};
58
+
59
+
buck2 {
60
+
regulator-name = "buck2";
61
+
regulator-min-microvolt = <1700000>;
62
+
regulator-max-microvolt = <1800000>;
63
+
regulator-boot-on;
64
+
};
65
+
};
66
+
};
67
+
};
68
+
...
+7
-14
Documentation/devicetree/bindings/regulator/socionext,uniphier-regulator.yaml
+7
-14
Documentation/devicetree/bindings/regulator/socionext,uniphier-regulator.yaml
···
89
89
90
90
examples:
91
91
- |
92
-
usb-glue@65b00000 {
93
-
compatible = "simple-mfd";
94
-
#address-cells = <1>;
95
-
#size-cells = <1>;
96
-
ranges = <0 0x65b00000 0x400>;
97
-
98
-
usb_vbus0: regulators@100 {
99
-
compatible = "socionext,uniphier-ld20-usb3-regulator";
100
-
reg = <0x100 0x10>;
101
-
clock-names = "link";
102
-
clocks = <&sys_clk 14>;
103
-
reset-names = "link";
104
-
resets = <&sys_rst 14>;
105
-
};
92
+
usb_vbus0: regulators@100 {
93
+
compatible = "socionext,uniphier-ld20-usb3-regulator";
94
+
reg = <0x100 0x10>;
95
+
clock-names = "link";
96
+
clocks = <&sys_clk 14>;
97
+
reset-names = "link";
98
+
resets = <&sys_rst 14>;
106
99
};
+6
-6
Documentation/devicetree/bindings/reserved-memory/reserved-memory.yaml
+6
-6
Documentation/devicetree/bindings/reserved-memory/reserved-memory.yaml
···
31
31
reg: true
32
32
33
33
size:
34
-
$ref: /schemas/types.yaml#/definitions/uint32-array
35
-
minItems: 1
36
-
maxItems: 2
34
+
oneOf:
35
+
- $ref: /schemas/types.yaml#/definitions/uint32
36
+
- $ref: /schemas/types.yaml#/definitions/uint64
37
37
description: >
38
38
Length based on parent's \#size-cells. Size in bytes of memory to
39
39
reserve.
40
40
41
41
alignment:
42
-
$ref: /schemas/types.yaml#/definitions/uint32-array
43
-
minItems: 1
44
-
maxItems: 2
42
+
oneOf:
43
+
- $ref: /schemas/types.yaml#/definitions/uint32
44
+
- $ref: /schemas/types.yaml#/definitions/uint64
45
45
description: >
46
46
Length based on parent's \#size-cells. Address boundary for
47
47
alignment of allocation.
+8
-15
Documentation/devicetree/bindings/reset/socionext,uniphier-glue-reset.yaml
+8
-15
Documentation/devicetree/bindings/reset/socionext,uniphier-glue-reset.yaml
···
95
95
96
96
examples:
97
97
- |
98
-
usb-glue@65b00000 {
99
-
compatible = "simple-mfd";
100
-
#address-cells = <1>;
101
-
#size-cells = <1>;
102
-
ranges = <0 0x65b00000 0x400>;
103
-
104
-
usb_rst: reset@0 {
105
-
compatible = "socionext,uniphier-ld20-usb3-reset";
106
-
reg = <0x0 0x4>;
107
-
#reset-cells = <1>;
108
-
clock-names = "link";
109
-
clocks = <&sys_clk 14>;
110
-
reset-names = "link";
111
-
resets = <&sys_rst 14>;
112
-
};
98
+
usb_rst: reset-controller@0 {
99
+
compatible = "socionext,uniphier-ld20-usb3-reset";
100
+
reg = <0x0 0x4>;
101
+
#reset-cells = <1>;
102
+
clock-names = "link";
103
+
clocks = <&sys_clk 14>;
104
+
reset-names = "link";
105
+
resets = <&sys_rst 14>;
113
106
};
+3
-49
Documentation/devicetree/bindings/reset/socionext,uniphier-reset.yaml
+3
-49
Documentation/devicetree/bindings/reset/socionext,uniphier-reset.yaml
···
66
66
67
67
examples:
68
68
- |
69
-
sysctrl@61840000 {
70
-
compatible = "socionext,uniphier-sysctrl", "simple-mfd", "syscon";
71
-
reg = <0x61840000 0x4000>;
72
-
73
-
reset {
74
-
compatible = "socionext,uniphier-ld11-reset";
75
-
#reset-cells = <1>;
76
-
};
77
-
78
-
// other nodes ...
79
-
};
80
-
81
-
- |
82
-
mioctrl@59810000 {
83
-
compatible = "socionext,uniphier-mioctrl", "simple-mfd", "syscon";
84
-
reg = <0x59810000 0x800>;
85
-
86
-
reset {
87
-
compatible = "socionext,uniphier-ld11-mio-reset";
88
-
#reset-cells = <1>;
89
-
};
90
-
91
-
// other nodes ...
92
-
};
93
-
94
-
- |
95
-
perictrl@59820000 {
96
-
compatible = "socionext,uniphier-perictrl", "simple-mfd", "syscon";
97
-
reg = <0x59820000 0x200>;
98
-
99
-
reset {
100
-
compatible = "socionext,uniphier-ld11-peri-reset";
101
-
#reset-cells = <1>;
102
-
};
103
-
104
-
// other nodes ...
105
-
};
106
-
107
-
- |
108
-
adamv@57920000 {
109
-
compatible = "socionext,uniphier-ld11-adamv", "simple-mfd", "syscon";
110
-
reg = <0x57920000 0x1000>;
111
-
112
-
reset {
113
-
compatible = "socionext,uniphier-ld11-adamv-reset";
114
-
#reset-cells = <1>;
115
-
};
116
-
117
-
// other nodes ...
69
+
reset-controller {
70
+
compatible = "socionext,uniphier-ld11-reset";
71
+
#reset-cells = <1>;
118
72
};
+1
-2
Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
+1
-2
Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
···
8
8
title: SiFive Composable Cache Controller
9
9
10
10
maintainers:
11
-
- Sagar Kadam <sagar.kadam@sifive.com>
12
-
- Paul Walmsley <paul.walmsley@sifive.com>
11
+
- Paul Walmsley <paul.walmsley@sifive.com>
13
12
14
13
description:
15
14
The SiFive Composable Cache Controller is used to provide access to fast copies
+1
Documentation/devicetree/bindings/serial/8250.yaml
+1
Documentation/devicetree/bindings/serial/8250.yaml
+1
-1
Documentation/devicetree/bindings/serial/serial.yaml
+1
-1
Documentation/devicetree/bindings/serial/serial.yaml
+50
Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-adamv.yaml
+50
Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-adamv.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-adamv.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Socionext UniPhier ADAMV block
8
+
9
+
maintainers:
10
+
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
11
+
12
+
description: |+
13
+
ADAMV block implemented on Socionext UniPhier SoCs is an analog signal
14
+
amplifier that is a part of the external video and audio I/O system.
15
+
16
+
This block is defined for controlling audio I/O reset only.
17
+
18
+
properties:
19
+
compatible:
20
+
items:
21
+
- enum:
22
+
- socionext,uniphier-ld11-adamv
23
+
- socionext,uniphier-ld20-adamv
24
+
- const: simple-mfd
25
+
- const: syscon
26
+
27
+
reg:
28
+
maxItems: 1
29
+
30
+
reset-controller:
31
+
$ref: /schemas/reset/socionext,uniphier-reset.yaml#
32
+
33
+
required:
34
+
- compatible
35
+
- reg
36
+
37
+
additionalProperties: false
38
+
39
+
examples:
40
+
- |
41
+
syscon@57920000 {
42
+
compatible = "socionext,uniphier-ld20-adamv",
43
+
"simple-mfd", "syscon";
44
+
reg = <0x57920000 0x1000>;
45
+
46
+
reset-controller {
47
+
compatible = "socionext,uniphier-ld20-adamv-reset";
48
+
#reset-cells = <1>;
49
+
};
50
+
};
+77
Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-ahci-glue.yaml
+77
Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-ahci-glue.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-ahci-glue.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Socionext UniPhier SoC AHCI glue layer
8
+
9
+
maintainers:
10
+
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
11
+
12
+
description: |+
13
+
AHCI glue layer implemented on Socionext UniPhier SoCs is a sideband
14
+
logic handling signals to AHCI host controller inside AHCI component.
15
+
16
+
properties:
17
+
compatible:
18
+
items:
19
+
- enum:
20
+
- socionext,uniphier-pro4-ahci-glue
21
+
- socionext,uniphier-pxs2-ahci-glue
22
+
- socionext,uniphier-pxs3-ahci-glue
23
+
- const: simple-mfd
24
+
25
+
reg:
26
+
maxItems: 1
27
+
28
+
"#address-cells":
29
+
const: 1
30
+
31
+
"#size-cells":
32
+
const: 1
33
+
34
+
ranges: true
35
+
36
+
patternProperties:
37
+
"^reset-controller@[0-9a-f]+$":
38
+
$ref: /schemas/reset/socionext,uniphier-glue-reset.yaml#
39
+
40
+
"phy@[0-9a-f]+$":
41
+
$ref: /schemas/phy/socionext,uniphier-ahci-phy.yaml#
42
+
43
+
required:
44
+
- compatible
45
+
- reg
46
+
47
+
additionalProperties: false
48
+
49
+
examples:
50
+
- |
51
+
sata-controller@65700000 {
52
+
compatible = "socionext,uniphier-pxs3-ahci-glue", "simple-mfd";
53
+
reg = <0x65b00000 0x400>;
54
+
#address-cells = <1>;
55
+
#size-cells = <1>;
56
+
ranges = <0 0x65700000 0x100>;
57
+
58
+
reset-controller@0 {
59
+
compatible = "socionext,uniphier-pxs3-ahci-reset";
60
+
reg = <0x0 0x4>;
61
+
clock-names = "link";
62
+
clocks = <&sys_clk 28>;
63
+
reset-names = "link";
64
+
resets = <&sys_rst 28>;
65
+
#reset-cells = <1>;
66
+
};
67
+
68
+
phy@10 {
69
+
compatible = "socionext,uniphier-pxs3-ahci-phy";
70
+
reg = <0x10 0x10>;
71
+
clock-names = "link", "phy";
72
+
clocks = <&sys_clk 28>, <&sys_clk 30>;
73
+
reset-names = "link", "phy";
74
+
resets = <&sys_rst 28>, <&sys_rst 30>;
75
+
#phy-cells = <0>;
76
+
};
77
+
};
+106
Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml
+106
Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-dwc3-glue.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Socionext UniPhier SoC DWC3 USB3.0 glue layer
8
+
9
+
maintainers:
10
+
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
11
+
12
+
description: |+
13
+
DWC3 USB3.0 glue layer implemented on Socionext UniPhier SoCs is
14
+
a sideband logic handling signals to DWC3 host controller inside
15
+
USB3.0 component.
16
+
17
+
properties:
18
+
compatible:
19
+
items:
20
+
- enum:
21
+
- socionext,uniphier-pro4-dwc3-glue
22
+
- socionext,uniphier-pro5-dwc3-glue
23
+
- socionext,uniphier-pxs2-dwc3-glue
24
+
- socionext,uniphier-ld20-dwc3-glue
25
+
- socionext,uniphier-pxs3-dwc3-glue
26
+
- socionext,uniphier-nx1-dwc3-glue
27
+
- const: simple-mfd
28
+
29
+
reg:
30
+
maxItems: 1
31
+
32
+
"#address-cells":
33
+
const: 1
34
+
35
+
"#size-cells":
36
+
const: 1
37
+
38
+
ranges: true
39
+
40
+
patternProperties:
41
+
"^reset-controller@[0-9a-f]+$":
42
+
$ref: /schemas/reset/socionext,uniphier-glue-reset.yaml#
43
+
44
+
"^regulator@[0-9a-f]+$":
45
+
$ref: /schemas/regulator/socionext,uniphier-regulator.yaml#
46
+
47
+
"^phy@[0-9a-f]+$":
48
+
oneOf:
49
+
- $ref: /schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
50
+
- $ref: /schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
51
+
52
+
required:
53
+
- compatible
54
+
- reg
55
+
56
+
additionalProperties: false
57
+
58
+
examples:
59
+
- |
60
+
usb@65b00000 {
61
+
compatible = "socionext,uniphier-ld20-dwc3-glue", "simple-mfd";
62
+
reg = <0x65b00000 0x400>;
63
+
#address-cells = <1>;
64
+
#size-cells = <1>;
65
+
ranges = <0 0x65b00000 0x400>;
66
+
67
+
reset-controller@0 {
68
+
compatible = "socionext,uniphier-ld20-usb3-reset";
69
+
reg = <0x0 0x4>;
70
+
#reset-cells = <1>;
71
+
clock-names = "link";
72
+
clocks = <&sys_clk 14>;
73
+
reset-names = "link";
74
+
resets = <&sys_rst 14>;
75
+
};
76
+
77
+
regulator@100 {
78
+
compatible = "socionext,uniphier-ld20-usb3-regulator";
79
+
reg = <0x100 0x10>;
80
+
clock-names = "link";
81
+
clocks = <&sys_clk 14>;
82
+
reset-names = "link";
83
+
resets = <&sys_rst 14>;
84
+
};
85
+
86
+
phy@200 {
87
+
compatible = "socionext,uniphier-ld20-usb3-hsphy";
88
+
reg = <0x200 0x10>;
89
+
#phy-cells = <0>;
90
+
clock-names = "link", "phy";
91
+
clocks = <&sys_clk 14>, <&sys_clk 16>;
92
+
reset-names = "link", "phy";
93
+
resets = <&sys_rst 14>, <&sys_rst 16>;
94
+
};
95
+
96
+
phy@300 {
97
+
compatible = "socionext,uniphier-ld20-usb3-ssphy";
98
+
reg = <0x300 0x10>;
99
+
#phy-cells = <0>;
100
+
clock-names = "link", "phy";
101
+
clocks = <&sys_clk 14>, <&sys_clk 18>;
102
+
reset-names = "link", "phy";
103
+
resets = <&sys_rst 14>, <&sys_rst 18>;
104
+
};
105
+
};
106
+
+65
Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-mioctrl.yaml
+65
Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-mioctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-mioctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Socionext UniPhier media I/O block (MIO) controller
8
+
9
+
maintainers:
10
+
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
11
+
12
+
description: |+
13
+
Media I/O block implemented on Socionext UniPhier SoCs is a legacy
14
+
integrated component of the stream type peripherals including USB2.0,
15
+
SD/eMMC, and MIO-DMAC.
16
+
Media I/O block has a common logic to control the component.
17
+
18
+
Recent SoCs have SD interface logic specialized only for SD functions
19
+
as a subset of media I/O block. See socionext,uniphier-sdctrl.yaml.
20
+
21
+
properties:
22
+
compatible:
23
+
items:
24
+
- enum:
25
+
- socionext,uniphier-ld4-mioctrl
26
+
- socionext,uniphier-pro4-mioctrl
27
+
- socionext,uniphier-sld8-mioctrl
28
+
- socionext,uniphier-ld11-mioctrl
29
+
- const: simple-mfd
30
+
- const: syscon
31
+
32
+
reg:
33
+
maxItems: 1
34
+
35
+
clock-controller:
36
+
$ref: /schemas/clock/socionext,uniphier-clock.yaml#
37
+
38
+
reset-controller:
39
+
$ref: /schemas/reset/socionext,uniphier-reset.yaml#
40
+
41
+
required:
42
+
- compatible
43
+
- reg
44
+
45
+
additionalProperties: false
46
+
47
+
examples:
48
+
- |
49
+
syscon@5b3e0000 {
50
+
compatible = "socionext,uniphier-ld11-mioctrl",
51
+
"simple-mfd", "syscon";
52
+
reg = <0x5b3e0000 0x800>;
53
+
54
+
clock-controller {
55
+
compatible = "socionext,uniphier-ld11-mio-clock";
56
+
#clock-cells = <1>;
57
+
};
58
+
59
+
reset-controller {
60
+
compatible = "socionext,uniphier-ld11-mio-reset";
61
+
#reset-cells = <1>;
62
+
resets = <&sys_rst 7>;
63
+
};
64
+
};
65
+
+64
Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml
+64
Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-perictrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Socionext UniPhier peripheral block controller
8
+
9
+
maintainers:
10
+
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
11
+
12
+
description: |+
13
+
Peripheral block implemented on Socionext UniPhier SoCs is an integrated
14
+
component of the peripherals including UART, I2C/FI2C, and SCSSI.
15
+
Peripheral block controller is a logic to control the component.
16
+
17
+
properties:
18
+
compatible:
19
+
items:
20
+
- enum:
21
+
- socionext,uniphier-ld4-perictrl
22
+
- socionext,uniphier-pro4-perictrl
23
+
- socionext,uniphier-pro5-perictrl
24
+
- socionext,uniphier-pxs2-perictrl
25
+
- socionext,uniphier-sld8-perictrl
26
+
- socionext,uniphier-ld11-perictrl
27
+
- socionext,uniphier-ld20-perictrl
28
+
- socionext,uniphier-pxs3-perictrl
29
+
- socionext,uniphier-nx1-perictrl
30
+
- const: simple-mfd
31
+
- const: syscon
32
+
33
+
reg:
34
+
maxItems: 1
35
+
36
+
clock-controller:
37
+
$ref: /schemas/clock/socionext,uniphier-clock.yaml#
38
+
39
+
reset-controller:
40
+
$ref: /schemas/reset/socionext,uniphier-reset.yaml#
41
+
42
+
required:
43
+
- compatible
44
+
- reg
45
+
46
+
additionalProperties: false
47
+
48
+
examples:
49
+
- |
50
+
syscon@59820000 {
51
+
compatible = "socionext,uniphier-ld20-perictrl",
52
+
"simple-mfd", "syscon";
53
+
reg = <0x59820000 0x200>;
54
+
55
+
clock-controller {
56
+
compatible = "socionext,uniphier-ld20-peri-clock";
57
+
#clock-cells = <1>;
58
+
};
59
+
60
+
reset-controller {
61
+
compatible = "socionext,uniphier-ld20-peri-reset";
62
+
#reset-cells = <1>;
63
+
};
64
+
};
+61
Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-sdctrl.yaml
+61
Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-sdctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-sdctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Socionext UniPhier SD interface logic
8
+
9
+
maintainers:
10
+
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
11
+
12
+
description: |+
13
+
SD interface logic implemented on Socionext UniPhier SoCs is
14
+
attached outside SDHC, and has some SD related functions such as
15
+
clock control, reset control, mode switch, and so on.
16
+
17
+
properties:
18
+
compatible:
19
+
items:
20
+
- enum:
21
+
- socionext,uniphier-pro5-sdctrl
22
+
- socionext,uniphier-pxs2-sdctrl
23
+
- socionext,uniphier-ld11-sdctrl
24
+
- socionext,uniphier-ld20-sdctrl
25
+
- socionext,uniphier-pxs3-sdctrl
26
+
- socionext,uniphier-nx1-sdctrl
27
+
- const: simple-mfd
28
+
- const: syscon
29
+
30
+
reg:
31
+
maxItems: 1
32
+
33
+
clock-controller:
34
+
$ref: /schemas/clock/socionext,uniphier-clock.yaml#
35
+
36
+
reset-controller:
37
+
$ref: /schemas/reset/socionext,uniphier-reset.yaml#
38
+
39
+
required:
40
+
- compatible
41
+
- reg
42
+
43
+
additionalProperties: false
44
+
45
+
examples:
46
+
- |
47
+
syscon@59810000 {
48
+
compatible = "socionext,uniphier-ld20-sdctrl",
49
+
"simple-mfd", "syscon";
50
+
reg = <0x59810000 0x400>;
51
+
52
+
clock-controller {
53
+
compatible = "socionext,uniphier-ld20-sd-clock";
54
+
#clock-cells = <1>;
55
+
};
56
+
57
+
reset-controller {
58
+
compatible = "socionext,uniphier-ld20-sd-reset";
59
+
#reset-cells = <1>;
60
+
};
61
+
};
+68
Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue-debug.yaml
+68
Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue-debug.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-soc-glue-debug.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Socionext UniPhier SoC-glue logic debug part
8
+
9
+
maintainers:
10
+
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
11
+
12
+
description: |+
13
+
SoC-glue logic debug part implemented on Socionext UniPhier SoCs is
14
+
a collection of miscellaneous function registers handling signals outside
15
+
system components for debug and monitor use.
16
+
17
+
properties:
18
+
compatible:
19
+
items:
20
+
- enum:
21
+
- socionext,uniphier-ld4-soc-glue-debug
22
+
- socionext,uniphier-pro4-soc-glue-debug
23
+
- socionext,uniphier-pro5-soc-glue-debug
24
+
- socionext,uniphier-pxs2-soc-glue-debug
25
+
- socionext,uniphier-sld8-soc-glue-debug
26
+
- socionext,uniphier-ld11-soc-glue-debug
27
+
- socionext,uniphier-ld20-soc-glue-debug
28
+
- socionext,uniphier-pxs3-soc-glue-debug
29
+
- socionext,uniphier-nx1-soc-glue-debug
30
+
- const: simple-mfd
31
+
- const: syscon
32
+
33
+
reg:
34
+
maxItems: 1
35
+
36
+
"#address-cells":
37
+
const: 1
38
+
39
+
"#size-cells":
40
+
const: 1
41
+
42
+
ranges: true
43
+
44
+
patternProperties:
45
+
"^efuse@[0-9a-f]+$":
46
+
$ref: /schemas/nvmem/socionext,uniphier-efuse.yaml#
47
+
48
+
required:
49
+
- compatible
50
+
- reg
51
+
52
+
additionalProperties: false
53
+
54
+
examples:
55
+
- |
56
+
syscon@5f900000 {
57
+
compatible = "socionext,uniphier-pxs2-soc-glue-debug",
58
+
"simple-mfd", "syscon";
59
+
reg = <0x5f900000 0x2000>;
60
+
#address-cells = <1>;
61
+
#size-cells = <1>;
62
+
ranges = <0 0x5f900000 0x2000>;
63
+
64
+
efuse@100 {
65
+
compatible = "socionext,uniphier-efuse";
66
+
reg = <0x100 0x28>;
67
+
};
68
+
};
+114
Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue.yaml
+114
Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-soc-glue.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Socionext UniPhier SoC-glue logic
8
+
9
+
maintainers:
10
+
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
11
+
12
+
description: |+
13
+
SoC-glue logic implemented on Socionext UniPhier SoCs is a collection of
14
+
miscellaneous function registers handling signals outside system components.
15
+
16
+
properties:
17
+
compatible:
18
+
items:
19
+
- enum:
20
+
- socionext,uniphier-ld4-soc-glue
21
+
- socionext,uniphier-pro4-soc-glue
22
+
- socionext,uniphier-pro5-soc-glue
23
+
- socionext,uniphier-pxs2-soc-glue
24
+
- socionext,uniphier-sld8-soc-glue
25
+
- socionext,uniphier-ld11-soc-glue
26
+
- socionext,uniphier-ld20-soc-glue
27
+
- socionext,uniphier-pxs3-soc-glue
28
+
- socionext,uniphier-nx1-soc-glue
29
+
- const: simple-mfd
30
+
- const: syscon
31
+
32
+
reg:
33
+
maxItems: 1
34
+
35
+
pinctrl:
36
+
$ref: /schemas/pinctrl/socionext,uniphier-pinctrl.yaml#
37
+
38
+
usb-hub:
39
+
$ref: /schemas/phy/socionext,uniphier-usb2-phy.yaml#
40
+
41
+
clock-controller:
42
+
$ref: /schemas/clock/socionext,uniphier-clock.yaml#
43
+
44
+
allOf:
45
+
- if:
46
+
not:
47
+
properties:
48
+
compatible:
49
+
contains:
50
+
enum:
51
+
- socionext,uniphier-pro4-soc-glue
52
+
- socionext,uniphier-ld11-soc-glue
53
+
then:
54
+
properties:
55
+
usb-hub: false
56
+
57
+
- if:
58
+
not:
59
+
properties:
60
+
compatible:
61
+
contains:
62
+
const: socionext,uniphier-pro4-soc-glue
63
+
then:
64
+
properties:
65
+
clock-controller: false
66
+
67
+
required:
68
+
- compatible
69
+
- reg
70
+
71
+
additionalProperties: false
72
+
73
+
examples:
74
+
- |
75
+
syscon@5f800000 {
76
+
compatible = "socionext,uniphier-pro4-soc-glue",
77
+
"simple-mfd", "syscon";
78
+
reg = <0x5f800000 0x2000>;
79
+
80
+
pinctrl {
81
+
compatible = "socionext,uniphier-pro4-pinctrl";
82
+
};
83
+
84
+
usb-hub {
85
+
compatible = "socionext,uniphier-pro4-usb2-phy";
86
+
#address-cells = <1>;
87
+
#size-cells = <0>;
88
+
89
+
phy@0 {
90
+
reg = <0>;
91
+
#phy-cells = <0>;
92
+
};
93
+
94
+
phy@1 {
95
+
reg = <1>;
96
+
#phy-cells = <0>;
97
+
};
98
+
99
+
phy@2 {
100
+
reg = <2>;
101
+
#phy-cells = <0>;
102
+
};
103
+
104
+
phy@3 {
105
+
reg = <3>;
106
+
#phy-cells = <0>;
107
+
};
108
+
};
109
+
110
+
clock-controller {
111
+
compatible = "socionext,uniphier-pro4-sg-clock";
112
+
#clock-cells = <1>;
113
+
};
114
+
};
+104
Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-sysctrl.yaml
+104
Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-sysctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-sysctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Socionext UniPhier system controller
8
+
9
+
maintainers:
10
+
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
11
+
12
+
description: |+
13
+
System controller implemented on Socionext UniPhier SoCs has multiple
14
+
functions such as clock control, reset control, internal watchdog timer,
15
+
thermal management, and so on.
16
+
17
+
properties:
18
+
compatible:
19
+
items:
20
+
- enum:
21
+
- socionext,uniphier-ld4-sysctrl
22
+
- socionext,uniphier-pro4-sysctrl
23
+
- socionext,uniphier-pro5-sysctrl
24
+
- socionext,uniphier-pxs2-sysctrl
25
+
- socionext,uniphier-sld8-sysctrl
26
+
- socionext,uniphier-ld11-sysctrl
27
+
- socionext,uniphier-ld20-sysctrl
28
+
- socionext,uniphier-pxs3-sysctrl
29
+
- socionext,uniphier-nx1-sysctrl
30
+
- const: simple-mfd
31
+
- const: syscon
32
+
33
+
reg:
34
+
maxItems: 1
35
+
36
+
clock-controller:
37
+
$ref: /schemas/clock/socionext,uniphier-clock.yaml#
38
+
39
+
reset-controller:
40
+
$ref: /schemas/reset/socionext,uniphier-reset.yaml#
41
+
42
+
watchdog:
43
+
$ref: /schemas/watchdog/socionext,uniphier-wdt.yaml#
44
+
45
+
thermal-sensor:
46
+
$ref: /schemas/thermal/socionext,uniphier-thermal.yaml#
47
+
48
+
allOf:
49
+
- if:
50
+
properties:
51
+
compatible:
52
+
contains:
53
+
const: socionext,uniphier-ld4-sysctrl
54
+
then:
55
+
properties:
56
+
watchdog: false
57
+
58
+
- if:
59
+
properties:
60
+
compatible:
61
+
contains:
62
+
enum:
63
+
- socionext,uniphier-ld4-sysctrl
64
+
- socionext,uniphier-pro4-sysctrl
65
+
- socionext,uniphier-sld8-sysctrl
66
+
- socionext,uniphier-ld11-sysctrl
67
+
then:
68
+
properties:
69
+
thermal-sensor: false
70
+
71
+
additionalProperties: false
72
+
73
+
required:
74
+
- compatible
75
+
- reg
76
+
77
+
examples:
78
+
- |
79
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
80
+
syscon@61840000 {
81
+
compatible = "socionext,uniphier-ld20-sysctrl",
82
+
"simple-mfd", "syscon";
83
+
reg = <0x61840000 0x4000>;
84
+
85
+
clock-controller {
86
+
compatible = "socionext,uniphier-ld20-clock";
87
+
#clock-cells = <1>;
88
+
};
89
+
90
+
reset-controller {
91
+
compatible = "socionext,uniphier-ld20-reset";
92
+
#reset-cells = <1>;
93
+
};
94
+
95
+
watchdog {
96
+
compatible = "socionext,uniphier-wdt";
97
+
};
98
+
99
+
thermal-sensor {
100
+
compatible = "socionext,uniphier-ld20-thermal";
101
+
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
102
+
#thermal-sensor-cells = <0>;
103
+
};
104
+
};
+4
-9
Documentation/devicetree/bindings/soc/ti/k3-ringacc.yaml
+4
-9
Documentation/devicetree/bindings/soc/ti/k3-ringacc.yaml
···
25
25
The Ring Accelerator is a hardware module that is responsible for accelerating
26
26
management of the packet queues. The K3 SoCs can have more than one RA instances
27
27
28
+
allOf:
29
+
- $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
30
+
28
31
properties:
29
32
compatible:
30
33
items:
···
57
54
$ref: /schemas/types.yaml#/definitions/uint32
58
55
description: TI-SCI RM subtype for GP ring range
59
56
60
-
ti,sci:
61
-
$ref: /schemas/types.yaml#/definitions/phandle-array
62
-
description: phandle on TI-SCI compatible System controller node
63
-
64
-
ti,sci-dev-id:
65
-
$ref: /schemas/types.yaml#/definitions/uint32
66
-
description: TI-SCI device id of the ring accelerator
67
-
68
57
required:
69
58
- compatible
70
59
- reg
···
67
72
- ti,sci
68
73
- ti,sci-dev-id
69
74
70
-
additionalProperties: false
75
+
unevaluatedProperties: false
71
76
72
77
examples:
73
78
- |
+1
Documentation/devicetree/bindings/sram/qcom,imem.yaml
+1
Documentation/devicetree/bindings/sram/qcom,imem.yaml
+5
-10
Documentation/devicetree/bindings/thermal/socionext,uniphier-thermal.yaml
+5
-10
Documentation/devicetree/bindings/thermal/socionext,uniphier-thermal.yaml
···
46
46
- |
47
47
// The UniPhier thermal should be a subnode of a "syscon" compatible node.
48
48
49
-
sysctrl@61840000 {
50
-
compatible = "socionext,uniphier-ld20-sysctrl",
51
-
"simple-mfd", "syscon";
52
-
reg = <0x61840000 0x10000>;
53
-
54
-
pvtctl: thermal {
55
-
compatible = "socionext,uniphier-ld20-thermal";
56
-
interrupts = <0 3 1>;
57
-
#thermal-sensor-cells = <0>;
58
-
};
49
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
50
+
pvtctl: thermal-sensor {
51
+
compatible = "socionext,uniphier-ld20-thermal";
52
+
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
53
+
#thermal-sensor-cells = <0>;
59
54
};
+3
Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
+3
Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
-34
Documentation/devicetree/bindings/usb/fcs,fusb302.txt
-34
Documentation/devicetree/bindings/usb/fcs,fusb302.txt
···
1
-
Fairchild FUSB302 Type-C Port controllers
2
-
3
-
Required properties :
4
-
- compatible : "fcs,fusb302"
5
-
- reg : I2C slave address
6
-
- interrupts : Interrupt specifier
7
-
8
-
Required sub-node:
9
-
- connector : The "usb-c-connector" attached to the FUSB302 IC. The bindings
10
-
of the connector node are specified in:
11
-
12
-
Documentation/devicetree/bindings/connector/usb-connector.yaml
13
-
14
-
15
-
Example:
16
-
17
-
fusb302: typec-portc@54 {
18
-
compatible = "fcs,fusb302";
19
-
reg = <0x54>;
20
-
interrupt-parent = <&nmi_intc>;
21
-
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
22
-
23
-
usb_con: connector {
24
-
compatible = "usb-c-connector";
25
-
label = "USB-C";
26
-
power-role = "dual";
27
-
try-power-role = "sink";
28
-
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
29
-
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
30
-
PDO_VAR(3000, 12000, 3000)
31
-
PDO_PPS_APDO(3000, 11000, 3000)>;
32
-
op-sink-microwatt = <10000000>;
33
-
};
34
-
};
+67
Documentation/devicetree/bindings/usb/fcs,fusb302.yaml
+67
Documentation/devicetree/bindings/usb/fcs,fusb302.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/usb/fcs,fusb302.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Fairchild FUSB302 Type-C Port controller
8
+
9
+
maintainers:
10
+
- Rob Herring <robh@kernel.org>
11
+
12
+
properties:
13
+
compatible:
14
+
const: fcs,fusb302
15
+
16
+
reg:
17
+
maxItems: 1
18
+
19
+
interrupts:
20
+
maxItems: 1
21
+
22
+
vbus-supply:
23
+
description: VBUS power supply
24
+
25
+
connector:
26
+
type: object
27
+
$ref: /schemas/connector/usb-connector.yaml#
28
+
unevaluatedProperties: false
29
+
30
+
required:
31
+
- compatible
32
+
- reg
33
+
- interrupts
34
+
- vbus-supply
35
+
- connector
36
+
37
+
additionalProperties: false
38
+
39
+
examples:
40
+
- |
41
+
#include <dt-bindings/interrupt-controller/irq.h>
42
+
#include <dt-bindings/usb/pd.h>
43
+
44
+
i2c {
45
+
#address-cells = <1>;
46
+
#size-cells = <0>;
47
+
48
+
typec-portc@54 {
49
+
compatible = "fcs,fusb302";
50
+
reg = <0x54>;
51
+
interrupt-parent = <&nmi_intc>;
52
+
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
53
+
vbus-supply = <&vbus_typec>;
54
+
55
+
connector {
56
+
compatible = "usb-c-connector";
57
+
label = "USB-C";
58
+
power-role = "dual";
59
+
try-power-role = "sink";
60
+
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
61
+
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
62
+
PDO_VAR(3000, 12000, 3000)
63
+
PDO_PPS_APDO(3000, 11000, 3000)>;
64
+
op-sink-microwatt = <10000000>;
65
+
};
66
+
};
67
+
};
+2
Documentation/devicetree/bindings/vendor-prefixes.yaml
+2
Documentation/devicetree/bindings/vendor-prefixes.yaml
+1
Documentation/devicetree/bindings/watchdog/maxim,max63xx.yaml
+1
Documentation/devicetree/bindings/watchdog/maxim,max63xx.yaml
+2
-8
Documentation/devicetree/bindings/watchdog/socionext,uniphier-wdt.yaml
+2
-8
Documentation/devicetree/bindings/watchdog/socionext,uniphier-wdt.yaml
···
25
25
- |
26
26
// The UniPhier watchdog should be a subnode of a "syscon" compatible node.
27
27
28
-
sysctrl@61840000 {
29
-
compatible = "socionext,uniphier-ld11-sysctrl",
30
-
"simple-mfd", "syscon";
31
-
reg = <0x61840000 0x10000>;
32
-
33
-
watchdog {
34
-
compatible = "socionext,uniphier-wdt";
35
-
};
28
+
watchdog {
29
+
compatible = "socionext,uniphier-wdt";
36
30
};
+4
-3
MAINTAINERS
+4
-3
MAINTAINERS
···
2265
2265
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
2266
2266
S: Maintained
2267
2267
F: Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml
2268
-
F: Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml
2268
+
F: Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion*
2269
2269
F: Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt
2270
2270
F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml
2271
2271
F: Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml
···
2963
2963
F: Documentation/devicetree/bindings/arm/socionext/uniphier.yaml
2964
2964
F: Documentation/devicetree/bindings/gpio/socionext,uniphier-gpio.yaml
2965
2965
F: Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml
2966
+
F: Documentation/devicetree/bindings/soc/socionext/socionext,uniphier*.yaml
2966
2967
F: arch/arm/boot/dts/uniphier*
2967
2968
F: arch/arm/include/asm/hardware/cache-uniphier.h
2968
2969
F: arch/arm/mach-uniphier/
···
16271
16270
L: linux-pci@vger.kernel.org
16272
16271
L: linux-rockchip@lists.infradead.org
16273
16272
S: Maintained
16274
-
F: Documentation/devicetree/bindings/pci/rockchip-pcie*
16273
+
F: Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie*
16275
16274
F: drivers/pci/controller/pcie-rockchip*
16276
16275
16277
16276
PCIE DRIVER FOR SOCIONEXT UNIPHIER
···
19298
19297
M: Ard Biesheuvel <ardb@kernel.org>
19299
19298
L: linux-i2c@vger.kernel.org
19300
19299
S: Maintained
19301
-
F: Documentation/devicetree/bindings/i2c/i2c-synquacer.txt
19300
+
F: Documentation/devicetree/bindings/i2c/socionext,synquacer-i2c.yaml
19302
19301
F: drivers/i2c/busses/i2c-synquacer.c
19303
19302
19304
19303
SOCIONEXT UNIPHIER SOUND DRIVER
+8
-1
Makefile
+8
-1
Makefile
···
1493
1493
1494
1494
ifneq ($(filter dtbs_check, $(MAKECMDGOALS)),)
1495
1495
export CHECK_DTBS=y
1496
-
dtbs: dt_binding_check
1496
+
endif
1497
+
1498
+
ifneq ($(CHECK_DTBS),)
1499
+
dtbs_prepare: dt_binding_check
1497
1500
endif
1498
1501
1499
1502
dtbs_check: dtbs
···
1795
1792
@echo ' 3: more obscure warnings, can most likely be ignored'
1796
1793
@echo ' e: warnings are being treated as errors'
1797
1794
@echo ' Multiple levels can be combined with W=12 or W=123'
1795
+
@$(if $(dtstree), \
1796
+
echo ' make CHECK_DTBS=1 [targets] Check all generated dtb files against schema'; \
1797
+
echo ' This can be applied both to "dtbs" and to individual "foo.dtb" targets' ; \
1798
+
)
1798
1799
@echo ''
1799
1800
@echo 'Execute "make" or "make all" to build all targets marked with [*] '
1800
1801
@echo 'For further info see the ./README file'
+13
-1
drivers/of/Kconfig
+13
-1
drivers/of/Kconfig
···
23
23
that are executed once at boot time, and the results dumped to the
24
24
console.
25
25
26
-
If unsure, say N here, but this option is safe to enable.
26
+
This option should only be enabled for a development kernel. The tests
27
+
will taint the kernel with TAINT_TEST. The tests will cause ERROR and
28
+
WARNING messages to print on the console. The tests will cause stack
29
+
traces to print on the console. It is possible that the tests will
30
+
leave the devicetree in a corrupted state.
31
+
32
+
The unittest output will be verbose. Copy the output to a file
33
+
via capturing the console output or via the dmesg command. Process
34
+
this file with scripts/dtc/of_unittest_expect to reduce the
35
+
verbosity, test whether expected output is present, and to
36
+
summarize the results.
37
+
38
+
If unsure, say N here. This option is not safe to enable.
27
39
28
40
config OF_ALL_DTBS
29
41
bool "Build all Device Tree Blobs"
+1
-2
drivers/of/base.c
+1
-2
drivers/of/base.c
···
1884
1884
{
1885
1885
ap->np = np;
1886
1886
ap->id = id;
1887
-
strncpy(ap->stem, stem, stem_len);
1888
-
ap->stem[stem_len] = 0;
1887
+
strscpy(ap->stem, stem, stem_len + 1);
1889
1888
list_add_tail(&ap->link, &aliases_lookup);
1890
1889
pr_debug("adding DT alias:%s: stem=%s id=%i node=%pOF\n",
1891
1890
ap->alias, ap->stem, ap->id, np);
+28
-3
drivers/of/dynamic.c
+28
-3
drivers/of/dynamic.c
···
329
329
{
330
330
struct device_node *node = kobj_to_device_node(kobj);
331
331
332
+
/*
333
+
* can not use '"%pOF", node' in pr_err() calls from this function
334
+
* because an of_node_get(node) when refcount is already zero
335
+
* will result in an error and a stack dump
336
+
*/
337
+
332
338
/* We should never be releasing nodes that haven't been detached. */
333
339
if (!of_node_check_flag(node, OF_DETACHED)) {
334
-
pr_err("ERROR: Bad of_node_put() on %pOF\n", node);
335
-
dump_stack();
340
+
341
+
pr_err("ERROR: %s() detected bad of_node_put() on %pOF/%s\n",
342
+
__func__, node->parent, node->full_name);
343
+
344
+
/*
345
+
* of unittests will test this path. Do not print the stack
346
+
* trace when the error is caused by unittest so that we do
347
+
* not display what a normal developer might reasonably
348
+
* consider a real bug.
349
+
*/
350
+
if (!IS_ENABLED(CONFIG_OF_UNITTEST) ||
351
+
strcmp(node->parent->full_name, "testcase-data")) {
352
+
dump_stack();
353
+
pr_err("ERROR: next of_node_put() on this node will result in a kobject warning 'refcount_t: underflow; use-after-free.'\n");
354
+
}
355
+
336
356
return;
337
357
}
338
358
if (!of_node_check_flag(node, OF_DYNAMIC))
···
376
356
pr_err("ERROR: %s(), unexpected properties in %pOF\n",
377
357
__func__, node);
378
358
}
359
+
360
+
if (node->child)
361
+
pr_err("ERROR: %s() unexpected children for %pOF/%s\n",
362
+
__func__, node->parent, node->full_name);
379
363
380
364
property_list_free(node->properties);
381
365
property_list_free(node->deadprops);
···
443
419
* another node. The node data are dynamically allocated and all the node
444
420
* flags have the OF_DYNAMIC & OF_DETACHED bits set.
445
421
*
446
-
* Return: The newly allocated node or NULL on out of memory error.
422
+
* Return: The newly allocated node or NULL on out of memory error. Use
423
+
* of_node_put() on it when done to free the memory allocated for it.
447
424
*/
448
425
struct device_node *__of_node_dup(const struct device_node *np,
449
426
const char *full_name)
+9
-3
drivers/of/irq.c
+9
-3
drivers/of/irq.c
···
438
438
return rc;
439
439
440
440
domain = irq_find_host(oirq.np);
441
-
if (!domain)
442
-
return -EPROBE_DEFER;
441
+
if (!domain) {
442
+
rc = -EPROBE_DEFER;
443
+
goto out;
444
+
}
443
445
444
-
return irq_create_of_mapping(&oirq);
446
+
rc = irq_create_of_mapping(&oirq);
447
+
out:
448
+
of_node_put(oirq.np);
449
+
450
+
return rc;
445
451
}
446
452
EXPORT_SYMBOL_GPL(of_irq_get);
447
453
+1
-1
drivers/of/kobj.c
+1
-1
drivers/of/kobj.c
+10
drivers/of/of_reserved_mem.c
+10
drivers/of/of_reserved_mem.c
···
285
285
else
286
286
memblock_phys_free(rmem->base,
287
287
rmem->size);
288
+
} else {
289
+
phys_addr_t end = rmem->base + rmem->size - 1;
290
+
bool reusable =
291
+
(of_get_flat_dt_prop(node, "reusable", NULL)) != NULL;
292
+
293
+
pr_info("%pa..%pa (%lu KiB) %s %s %s\n",
294
+
&rmem->base, &end, (unsigned long)(rmem->size / SZ_1K),
295
+
nomap ? "nomap" : "map",
296
+
reusable ? "reusable" : "non-reusable",
297
+
rmem->name ? rmem->name : "unknown");
288
298
}
289
299
}
290
300
}
+1
-1
drivers/of/overlay.c
+1
-1
drivers/of/overlay.c
···
1121
1121
* The topmost check is done by exploiting this property. For each
1122
1122
* affected device node in the log list we check if this overlay is
1123
1123
* the one closest to the tail. If another overlay has affected this
1124
-
* device node and is closest to the tail, then removal is not permited.
1124
+
* device node and is closest to the tail, then removal is not permitted.
1125
1125
*/
1126
1126
static int overlay_removal_is_ok(struct overlay_changeset *remove_ovcs)
1127
1127
{
+2
-5
drivers/of/platform.c
+2
-5
drivers/of/platform.c
···
222
222
struct device *parent)
223
223
{
224
224
struct amba_device *dev;
225
-
const void *prop;
226
225
int ret;
227
226
228
227
pr_debug("Creating amba device %pOF\n", node);
···
249
250
of_device_make_bus_id(&dev->dev);
250
251
251
252
/* Allow the HW Peripheral ID to be overridden */
252
-
prop = of_get_property(node, "arm,primecell-periphid", NULL);
253
-
if (prop)
254
-
dev->periphid = of_read_ulong(prop, 1);
253
+
of_property_read_u32(node, "arm,primecell-periphid", &dev->periphid);
255
254
256
255
ret = of_address_to_resource(node, 0, &dev->res);
257
256
if (ret) {
···
526
529
int ret;
527
530
528
531
/* Check if we have a MacOS display without a node spec */
529
-
if (of_get_property(of_chosen, "linux,bootx-noscreen", NULL)) {
532
+
if (of_property_present(of_chosen, "linux,bootx-noscreen")) {
530
533
/*
531
534
* The old code tried to work out which node was the MacOS
532
535
* display based on the address. I'm dropping that since the
+2
-2
drivers/of/property.c
+2
-2
drivers/of/property.c
···
1072
1072
np = NULL;
1073
1073
}
1074
1074
1075
-
if (of_find_property(np, "compatible", NULL))
1075
+
if (of_property_present(np, "compatible"))
1076
1076
break;
1077
1077
1078
1078
np = of_get_next_parent(np);
···
1300
1300
* Ignore node with gpio-hog property since its gpios are all provided
1301
1301
* by its parent.
1302
1302
*/
1303
-
if (of_find_property(np, "gpio-hog", NULL))
1303
+
if (of_property_read_bool(np, "gpio-hog"))
1304
1304
return NULL;
1305
1305
1306
1306
if (of_parse_phandle_with_args(np, prop_name, "#gpio-cells", index,
+1
drivers/of/unittest-data/testcases_common.dtsi
+1
drivers/of/unittest-data/testcases_common.dtsi
+8
drivers/of/unittest-data/tests-lifecycle.dtsi
+8
drivers/of/unittest-data/tests-lifecycle.dtsi
+148
-2
drivers/of/unittest.c
+148
-2
drivers/of/unittest.c
···
54
54
* Print the expected message only if the current loglevel will allow
55
55
* the actual message to print.
56
56
*
57
-
* Do not use EXPECT_BEGIN() or EXPECT_END() for messages generated by
58
-
* pr_debug().
57
+
* Do not use EXPECT_BEGIN(), EXPECT_END(), EXPECT_NOT_BEGIN(), or
58
+
* EXPECT_NOT_END() to report messages expected to be reported or not
59
+
* reported by pr_debug().
59
60
*/
60
61
#define EXPECT_BEGIN(level, fmt, ...) \
61
62
printk(level pr_fmt("EXPECT \\ : ") fmt, ##__VA_ARGS__)
62
63
63
64
#define EXPECT_END(level, fmt, ...) \
64
65
printk(level pr_fmt("EXPECT / : ") fmt, ##__VA_ARGS__)
66
+
67
+
#define EXPECT_NOT_BEGIN(level, fmt, ...) \
68
+
printk(level pr_fmt("EXPECT_NOT \\ : ") fmt, ##__VA_ARGS__)
69
+
70
+
#define EXPECT_NOT_END(level, fmt, ...) \
71
+
printk(level pr_fmt("EXPECT_NOT / : ") fmt, ##__VA_ARGS__)
65
72
66
73
static void __init of_unittest_find_node_by_name(void)
67
74
{
···
1495
1488
struct device_node *next = np->sibling;
1496
1489
1497
1490
np->parent = of_root;
1491
+
/* this will clear OF_DETACHED in np and children */
1498
1492
attach_node_and_children(np);
1499
1493
np = next;
1500
1494
}
···
3006
2998
static inline void __init of_unittest_overlay(void) { }
3007
2999
#endif
3008
3000
3001
+
static void __init of_unittest_lifecycle(void)
3002
+
{
3003
+
#ifdef CONFIG_OF_DYNAMIC
3004
+
unsigned int refcount;
3005
+
int found_refcount_one = 0;
3006
+
int put_count = 0;
3007
+
struct device_node *np;
3008
+
struct device_node *prev_sibling, *next_sibling;
3009
+
const char *refcount_path = "/testcase-data/refcount-node";
3010
+
const char *refcount_parent_path = "/testcase-data";
3011
+
3012
+
/*
3013
+
* Node lifecycle tests, non-dynamic node:
3014
+
*
3015
+
* - Decrementing refcount to zero via of_node_put() should cause the
3016
+
* attempt to free the node memory by of_node_release() to fail
3017
+
* because the node is not a dynamic node.
3018
+
*
3019
+
* - Decrementing refcount past zero should result in additional
3020
+
* errors reported.
3021
+
*/
3022
+
3023
+
np = of_find_node_by_path(refcount_path);
3024
+
unittest(np, "find refcount_path \"%s\"\n", refcount_path);
3025
+
if (np == NULL)
3026
+
goto out_skip_tests;
3027
+
3028
+
while (!found_refcount_one) {
3029
+
3030
+
if (put_count++ > 10) {
3031
+
unittest(0, "guardrail to avoid infinite loop\n");
3032
+
goto out_skip_tests;
3033
+
}
3034
+
3035
+
refcount = kref_read(&np->kobj.kref);
3036
+
if (refcount == 1)
3037
+
found_refcount_one = 1;
3038
+
else
3039
+
of_node_put(np);
3040
+
}
3041
+
3042
+
EXPECT_BEGIN(KERN_INFO, "OF: ERROR: of_node_release() detected bad of_node_put() on /testcase-data/refcount-node");
3043
+
3044
+
/*
3045
+
* refcount is now one, decrementing to zero will result in a call to
3046
+
* of_node_release() to free the node's memory, which should result
3047
+
* in an error
3048
+
*/
3049
+
unittest(1, "/testcase-data/refcount-node is one");
3050
+
of_node_put(np);
3051
+
3052
+
EXPECT_END(KERN_INFO, "OF: ERROR: of_node_release() detected bad of_node_put() on /testcase-data/refcount-node");
3053
+
3054
+
3055
+
/*
3056
+
* expect stack trace for subsequent of_node_put():
3057
+
* __refcount_sub_and_test() calls:
3058
+
* refcount_warn_saturate(r, REFCOUNT_SUB_UAF)
3059
+
*
3060
+
* Not capturing entire WARN_ONCE() trace with EXPECT_*(), just
3061
+
* the first three lines, and the last line.
3062
+
*/
3063
+
EXPECT_BEGIN(KERN_INFO, "------------[ cut here ]------------");
3064
+
EXPECT_BEGIN(KERN_INFO, "WARNING: <<all>>");
3065
+
EXPECT_BEGIN(KERN_INFO, "refcount_t: underflow; use-after-free.");
3066
+
EXPECT_BEGIN(KERN_INFO, "---[ end trace <<int>> ]---");
3067
+
3068
+
/* refcount is now zero, this should fail */
3069
+
unittest(1, "/testcase-data/refcount-node is zero");
3070
+
of_node_put(np);
3071
+
3072
+
EXPECT_END(KERN_INFO, "---[ end trace <<int>> ]---");
3073
+
EXPECT_END(KERN_INFO, "refcount_t: underflow; use-after-free.");
3074
+
EXPECT_END(KERN_INFO, "WARNING: <<all>>");
3075
+
EXPECT_END(KERN_INFO, "------------[ cut here ]------------");
3076
+
3077
+
/*
3078
+
* Q. do we expect to get yet another warning?
3079
+
* A. no, the WARNING is from WARN_ONCE()
3080
+
*/
3081
+
EXPECT_NOT_BEGIN(KERN_INFO, "------------[ cut here ]------------");
3082
+
EXPECT_NOT_BEGIN(KERN_INFO, "WARNING: <<all>>");
3083
+
EXPECT_NOT_BEGIN(KERN_INFO, "refcount_t: underflow; use-after-free.");
3084
+
EXPECT_NOT_BEGIN(KERN_INFO, "---[ end trace <<int>> ]---");
3085
+
3086
+
unittest(1, "/testcase-data/refcount-node is zero, second time");
3087
+
of_node_put(np);
3088
+
3089
+
EXPECT_NOT_END(KERN_INFO, "---[ end trace <<int>> ]---");
3090
+
EXPECT_NOT_END(KERN_INFO, "refcount_t: underflow; use-after-free.");
3091
+
EXPECT_NOT_END(KERN_INFO, "WARNING: <<all>>");
3092
+
EXPECT_NOT_END(KERN_INFO, "------------[ cut here ]------------");
3093
+
3094
+
/*
3095
+
* refcount of zero will trigger stack traces from any further
3096
+
* attempt to of_node_get() node "refcount-node". One example of
3097
+
* this is where of_unittest_check_node_linkage() will recursively
3098
+
* scan the tree, with 'for_each_child_of_node()' doing an
3099
+
* of_node_get() of the children of a node.
3100
+
*
3101
+
* Prevent the stack trace by removing node "refcount-node" from
3102
+
* its parent's child list.
3103
+
*
3104
+
* WARNING: EVIL, EVIL, EVIL:
3105
+
*
3106
+
* Directly manipulate the child list of node /testcase-data to
3107
+
* remove child refcount-node. This is ignoring all proper methods
3108
+
* of removing a child and will leak a small amount of memory.
3109
+
*/
3110
+
3111
+
np = of_find_node_by_path(refcount_parent_path);
3112
+
unittest(np, "find refcount_parent_path \"%s\"\n", refcount_parent_path);
3113
+
unittest(np, "ERROR: devicetree live tree left in a 'bad state' if test fail\n");
3114
+
if (np == NULL)
3115
+
return;
3116
+
3117
+
prev_sibling = np->child;
3118
+
next_sibling = prev_sibling->sibling;
3119
+
if (!strcmp(prev_sibling->full_name, "refcount-node")) {
3120
+
np->child = next_sibling;
3121
+
next_sibling = next_sibling->sibling;
3122
+
}
3123
+
while (next_sibling) {
3124
+
if (!strcmp(next_sibling->full_name, "refcount-node"))
3125
+
prev_sibling->sibling = next_sibling->sibling;
3126
+
prev_sibling = next_sibling;
3127
+
next_sibling = next_sibling->sibling;
3128
+
}
3129
+
of_node_put(np);
3130
+
3131
+
return;
3132
+
3133
+
out_skip_tests:
3134
+
#endif
3135
+
unittest(0, "One or more lifecycle tests skipped\n");
3136
+
}
3137
+
3009
3138
#ifdef CONFIG_OF_OVERLAY
3010
3139
3011
3140
/*
···
3647
3502
of_unittest_match_node();
3648
3503
of_unittest_platform_populate();
3649
3504
of_unittest_overlay();
3505
+
of_unittest_lifecycle();
3650
3506
3651
3507
/* Double check linkage after removing testcase data */
3652
3508
of_unittest_check_tree_linkage();
+1
-1
include/dt-bindings/gpio/gpio.h
+1
-1
include/dt-bindings/gpio/gpio.h
+28
-2
include/linux/of.h
+28
-2
include/linux/of.h
···
100
100
struct property *old_prop;
101
101
};
102
102
103
+
/**
104
+
* of_node_init - initialize a devicetree node
105
+
* @node: Pointer to device node that has been created by kzalloc()
106
+
* @phandle_name: Name of property holding a phandle value
107
+
*
108
+
* On return the device_node refcount is set to one. Use of_node_put()
109
+
* on @node when done to free the memory allocated for it. If the node
110
+
* is NOT a dynamic node the memory will not be freed. The decision of
111
+
* whether to free the memory will be done by node->release(), which is
112
+
* of_node_release().
113
+
*/
103
114
/* initialize a node */
104
-
extern struct kobj_type of_node_ktype;
115
+
extern const struct kobj_type of_node_ktype;
105
116
extern const struct fwnode_operations of_fwnode_ops;
106
117
static inline void of_node_init(struct device_node *node)
107
118
{
···
1191
1180
* @np: device node from which the property value is to be read.
1192
1181
* @propname: name of the property to be searched.
1193
1182
*
1194
-
* Search for a property in a device node.
1183
+
* Search for a boolean property in a device node. Usage on non-boolean
1184
+
* property types is deprecated.
1195
1185
*
1196
1186
* Return: true if the property exists false otherwise.
1197
1187
*/
···
1202
1190
struct property *prop = of_find_property(np, propname, NULL);
1203
1191
1204
1192
return prop ? true : false;
1193
+
}
1194
+
1195
+
/**
1196
+
* of_property_present - Test if a property is present in a node
1197
+
* @np: device node to search for the property.
1198
+
* @propname: name of the property to be searched.
1199
+
*
1200
+
* Test for a property present in a device node.
1201
+
*
1202
+
* Return: true if the property exists false otherwise.
1203
+
*/
1204
+
static inline bool of_property_present(const struct device_node *np, const char *propname)
1205
+
{
1206
+
return of_property_read_bool(np, propname);
1205
1207
}
1206
1208
1207
1209
/**
+8
-3
scripts/dtc/dtc-parser.y
+8
-3
scripts/dtc/dtc-parser.y
···
404
404
* within the mask to one (i.e. | in the
405
405
* mask), all bits are one.
406
406
*/
407
-
if (($2 > mask) && (($2 | mask) != -1ULL))
408
-
ERROR(&@2, "Value out of range for"
409
-
" %d-bit array element", $1.bits);
407
+
if (($2 > mask) && (($2 | mask) != -1ULL)) {
408
+
char *loc = srcpos_string(&@2);
409
+
fprintf(stderr,
410
+
"WARNING: %s: Value 0x%016" PRIx64
411
+
" truncated to 0x%0*" PRIx64 "\n",
412
+
loc, $2, $1.bits / 4, ($2 & mask));
413
+
free(loc);
414
+
}
410
415
}
411
416
412
417
$$.data = data_append_integer($1.data, $2, $1.bits);
+2
-2
scripts/dtc/libfdt/fdt.h
+2
-2
scripts/dtc/libfdt/fdt.h
+158
-25
scripts/dtc/of_unittest_expect
+158
-25
scripts/dtc/of_unittest_expect
···
9
9
# on the console log that results from executing the Linux kernel
10
10
# devicetree unittest (drivers/of/unitest.c).
11
11
12
-
$VUFX = "220201a";
12
+
$VUFX = "230211a";
13
13
14
14
use strict 'refs';
15
15
use strict subs;
···
62
62
} else {
63
63
return 0;
64
64
}
65
+
} elsif ($type eq "all") {
66
+
return 1;
65
67
} elsif ($type eq "") {
66
68
if ($expect_next ne $got_next) {
67
69
return 0;
···
132
130
133
131
<<int>> matches: [+-]*[0-9]+
134
132
<<hex>> matches: (0x)*[0-9a-f]+
133
+
<<all>> matches: anything to end of line
135
134
136
135
'EXPECT \\' (begin) and 'EXPECT /' (end) lines are suppressed.
137
136
···
243
240
$pr_fmt = "### dt-test ### ";
244
241
$exp_begin = "${pr_fmt}EXPECT \\\\ : ";
245
242
$exp_end = "${pr_fmt}EXPECT / : ";
243
+
$expnot_begin = "${pr_fmt}EXPECT_NOT \\\\ : ";
244
+
$expnot_end = "${pr_fmt}EXPECT_NOT / : ";
246
245
247
246
248
247
$line_num = "";
···
254
249
while ($line = <ARGV>) {
255
250
256
251
chomp $line;
252
+
253
+
$suppress_line = 0;
257
254
258
255
$prefix = " "; ## 2 characters
259
256
···
281
274
if ($line =~ /^\s*$exp_begin/) {
282
275
$data = $line;
283
276
$data =~ s/^\s*$exp_begin//;
284
-
push @begin, $data;
277
+
push @exp_begin_stack, $data;
285
278
286
279
if ($verbose) {
287
280
if ($print_line_num) {
···
309
302
310
303
$found = 0;
311
304
$no_begin = 0;
312
-
if (@found_or_begin > 0) {
313
-
$begin = pop @found_or_begin;
305
+
if (@exp_found_or_begin > 0) {
306
+
$begin = pop @exp_found_or_begin;
314
307
if (compare($data, $begin)) {
315
308
$found = 1;
309
+
$exp_found++;
316
310
}
317
311
} elsif (@begin > 0) {
318
-
$begin = pop @begin;
312
+
$begin = pop @exp_begin_stack;
319
313
} else {
320
314
$no_begin = 1;
321
315
}
322
316
323
317
if ($no_begin) {
324
318
325
-
$expect_missing_begin++;
326
-
print "** ERROR: EXPECT end without any EXPECT begin:\n";
319
+
$exp_missing_begin++;
320
+
print "** ERROR: EXPECT end without matching EXPECT begin:\n";
327
321
print " end ---> $line\n";
328
322
329
323
} elsif (! $found) {
···
333
325
$line_num = sprintf("%4s ", $.);
334
326
}
335
327
336
-
$expect_not_found++;
328
+
$exp_missing++;
337
329
printf "** %s%s$script_name WARNING - not found ---> %s\n",
338
330
$line_num, $timestamp, $data;
339
331
340
-
} elsif (! compare($data, $begin)) {
332
+
} elsif (! compare($data, $begin) and ($data ne $begin)) {
341
333
342
-
$expect_missing_end++;
334
+
$exp_missing_end++;
343
335
print "** ERROR: EXPECT end does not match EXPECT begin:\n";
344
336
print " begin -> $begin\n";
345
337
print " end ---> $line\n";
346
338
339
+
}
340
+
341
+
next LINE;
342
+
}
343
+
344
+
345
+
# ----- find EXPECT_NOT begin
346
+
347
+
if ($line =~ /^\s*$expnot_begin/) {
348
+
$data = $line;
349
+
$data =~ s/^\s*$expnot_begin//;
350
+
push @expnot_begin_stack, $data;
351
+
352
+
if ($verbose) {
353
+
if ($print_line_num) {
354
+
$line_num = sprintf("%4s ", $.);
355
+
}
356
+
printf "%s %s%s%s\n", $prefix, $line_num, $timestamp, $line;
357
+
}
358
+
359
+
next LINE;
360
+
}
361
+
362
+
363
+
# ----- find EXPECT_NOT end
364
+
365
+
if ($line =~ /^\s*$expnot_end/) {
366
+
$data = $line;
367
+
$data =~ s/^\s*$expnot_end//;
368
+
369
+
if ($verbose) {
370
+
if ($print_line_num) {
371
+
$line_num = sprintf("%4s ", $.);
372
+
}
373
+
printf "%s %s%s%s\n", $prefix, $line_num, $timestamp, $line;
374
+
}
375
+
376
+
$found = 0;
377
+
$no_begin = 0;
378
+
if (@expnot_found_or_begin > 0) {
379
+
$begin = pop @expnot_found_or_begin;
380
+
if (compare($data, $begin)) {
381
+
$found = 1;
382
+
$expnot_found++;
383
+
}
384
+
} elsif (@expnot_begin_stack <= 0) {
385
+
$no_begin = 1;
386
+
}
387
+
388
+
if ($no_begin) {
389
+
390
+
$expnot_missing_begin++;
391
+
print "** ERROR: EXPECT_NOT end without matching EXPECT_NOT begin:\n";
392
+
print " end ---> $line\n";
393
+
394
+
}
395
+
396
+
if ($found) {
397
+
398
+
if ($print_line_num) {
399
+
$line_num = sprintf("%4s ", $.);
400
+
}
401
+
402
+
printf "** %s%s$script_name WARNING - next line matches EXPECT_NOT\n",
403
+
$line_num, $timestamp;
404
+
printf "** %s%s%s\n", $line_num, $timestamp, $line;
405
+
347
406
} else {
348
407
349
-
$expect_found++;
408
+
$expnot_missing++;
350
409
410
+
}
411
+
412
+
if (@expnot_begin_stack > 0) {
413
+
$begin = pop @expnot_begin_stack;
414
+
415
+
if (! compare($data, $begin) and ($data ne $begin)) {
416
+
417
+
$expnot_missing_end++;
418
+
print "** ERROR: EXPECT_NOT end does not match EXPECT_NOT begin:\n";
419
+
print " begin -> $begin\n";
420
+
print " end ---> $line\n";
421
+
422
+
}
351
423
}
352
424
353
425
next LINE;
···
445
357
}
446
358
447
359
$found = 0;
448
-
foreach $begin (@begin) {
360
+
foreach $begin (@exp_begin_stack) {
361
+
if (compare($begin, $line)) {
362
+
$found = 1;
363
+
last;
364
+
}
365
+
}
366
+
367
+
if ($found) {
368
+
$begin = shift @exp_begin_stack;
369
+
while (! compare($begin, $line)) {
370
+
push @exp_found_or_begin, $begin;
371
+
$begin = shift @exp_begin_stack;
372
+
}
373
+
push @exp_found_or_begin, $line;
374
+
375
+
if ($hide_expect) {
376
+
$suppress_line = 1;
377
+
}
378
+
$prefix = "ok"; # 2 characters
379
+
}
380
+
381
+
382
+
$found = 0;
383
+
foreach $begin (@expnot_begin_stack) {
449
384
if (compare($begin, $line)) {
450
385
$found = 1;
451
386
last;
···
478
367
if ($found) {
479
368
$begin = shift @begin;
480
369
while (! compare($begin, $line)) {
481
-
push @found_or_begin, $begin;
370
+
push @expnot_found_or_begin, $begin;
482
371
$begin = shift @begin;
483
372
}
484
-
push @found_or_begin, $line;
373
+
push @expnot_found_or_begin, $line;
485
374
486
375
if ($hide_expect) {
487
376
$suppress_line = 1;
488
-
next LINE;
489
377
}
490
-
$prefix = "ok"; # 2 characters
378
+
$prefix = "**"; # 2 characters
491
379
}
492
380
381
+
382
+
if ($suppress_line) {
383
+
next LINE;
384
+
}
493
385
494
386
if ($print_line_num) {
495
387
$line_num = sprintf("%4s ", $.);
···
505
391
print "\n";
506
392
print "** EXPECT statistics:\n";
507
393
print "**\n";
508
-
printf "** EXPECT found : %4i\n", $expect_found;
509
-
printf "** EXPECT not found : %4i\n", $expect_not_found;
510
-
printf "** missing EXPECT begin : %4i\n", $expect_missing_begin;
511
-
printf "** missing EXPECT end : %4i\n", $expect_missing_end;
512
-
printf "** unittest FAIL : %4i\n", $unittest_fail;
513
-
printf "** internal error : %4i\n", $internal_err;
394
+
printf "** non-zero values expected:\n";
395
+
print "**\n";
396
+
printf "** EXPECT found : %4i\n", $exp_found;
397
+
printf "** EXPECT_NOT not found : %4i\n", $expnot_missing;
398
+
print "**\n";
399
+
printf "** zero values expected:\n";
400
+
print "**\n";
401
+
printf "** EXPECT not found : %4i\n", $exp_missing;
402
+
printf "** missing EXPECT begin : %4i\n", $exp_missing_begin;
403
+
printf "** missing EXPECT end : %4i\n", $exp_missing_end;
404
+
print "**\n";
405
+
printf "** EXPECT_NOT found : %4i\n", $expnot_found;
406
+
printf "** missing EXPECT_NOT begin : %4i\n", $expnot_missing_begin;
407
+
printf "** missing EXPECT_NOT end : %4i\n", $expnot_missing_end;
408
+
print "**\n";
409
+
printf "** unittest FAIL : %4i\n", $unittest_fail;
410
+
printf "** internal error : %4i\n", $internal_err;
514
411
}
515
412
516
-
if (@begin) {
517
-
print "** ERROR: EXPECT begin without any EXPECT end:\n";
413
+
if (@exp_begin_stack) {
414
+
print "** ERROR: EXPECT begin without matching EXPECT end:\n";
518
415
print " This list may be misleading.\n";
519
-
foreach $begin (@begin) {
416
+
foreach $begin (@exp_begin_stack) {
417
+
print " begin ---> $begin\n";
418
+
}
419
+
}
420
+
421
+
if (@expnot_begin_stack) {
422
+
print "** ERROR: EXPECT_NOT begin without matching EXPECT_NOT end:\n";
423
+
print " This list may be misleading.\n";
424
+
foreach $begin (@expnot_begin_stack) {
520
425
print " begin ---> $begin\n";
521
426
}
522
427
}