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dt-bindings: firmware: google,gs101-acpm-ipc: add ACPM clocks

The firmware exposes clocks that can be controlled via the
Alive Clock and Power Manager (ACPM) interface.

Make the ACPM node a clock provider by adding the mandatory
"#clock-cells" property, which allows devices to reference its
clock outputs.

Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Tested-by: Peter Griffin <peter.griffin@linaro.org> # on gs101-oriole
Link: https://patch.msgid.link/20251010-acpm-clk-v6-1-321ee8826fd4@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

authored by

Tudor Ambarus and committed by
Krzysztof Kozlowski 83c4e3c3 3a866087

+37
+11
Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml
··· 24 24 compatible: 25 25 const: google,gs101-acpm-ipc 26 26 27 + "#clock-cells": 28 + const: 1 29 + description: 30 + Clocks that are variable and index based. These clocks don't provide 31 + an entire range of values between the limits but only discrete points 32 + within the range. The firmware also manages the voltage scaling 33 + appropriately with the clock scaling. The argument is the ID of the 34 + clock contained by the firmware messages. 35 + 27 36 mboxes: 28 37 maxItems: 1 29 38 ··· 54 45 55 46 required: 56 47 - compatible 48 + - "#clock-cells" 57 49 - mboxes 58 50 - shmem 59 51 ··· 66 56 67 57 power-management { 68 58 compatible = "google,gs101-acpm-ipc"; 59 + #clock-cells = <1>; 69 60 mboxes = <&ap2apm_mailbox>; 70 61 shmem = <&apm_sram>; 71 62
+26
include/dt-bindings/clock/google,gs101-acpm.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright 2025 Linaro Ltd. 4 + * 5 + * Device Tree binding constants for Google gs101 ACPM clock controller. 6 + */ 7 + 8 + #ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_ACPM_H 9 + #define _DT_BINDINGS_CLOCK_GOOGLE_GS101_ACPM_H 10 + 11 + #define GS101_CLK_ACPM_DVFS_MIF 0 12 + #define GS101_CLK_ACPM_DVFS_INT 1 13 + #define GS101_CLK_ACPM_DVFS_CPUCL0 2 14 + #define GS101_CLK_ACPM_DVFS_CPUCL1 3 15 + #define GS101_CLK_ACPM_DVFS_CPUCL2 4 16 + #define GS101_CLK_ACPM_DVFS_G3D 5 17 + #define GS101_CLK_ACPM_DVFS_G3DL2 6 18 + #define GS101_CLK_ACPM_DVFS_TPU 7 19 + #define GS101_CLK_ACPM_DVFS_INTCAM 8 20 + #define GS101_CLK_ACPM_DVFS_TNR 9 21 + #define GS101_CLK_ACPM_DVFS_CAM 10 22 + #define GS101_CLK_ACPM_DVFS_MFC 11 23 + #define GS101_CLK_ACPM_DVFS_DISP 12 24 + #define GS101_CLK_ACPM_DVFS_BO 13 25 + 26 + #endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_ACPM_H */