Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (40 commits)
vmwgfx: Snoop DMA transfers with non-covering sizes
vmwgfx: Move the prefered mode first in the list
vmwgfx: Unreference surface on cursor error path
vmwgfx: Free prefered mode on error path
vmwgfx: Use pointer return error codes
vmwgfx: Fix hw cursor position
vmwgfx: Infrastructure for explicit placement
vmwgfx: Make the preferred autofit mode have a 60Hz vrefresh
vmwgfx: Remove screen object active list
vmwgfx: Screen object cleanups
drm/radeon/kms: consolidate GART code, fix segfault after GPU lockup V2
drm/radeon/kms: don't poll forever if MC GDDR link training fails
drm/radeon/kms: fix DP setup on TRAVIS bridges
drm/radeon/kms: set HPD polarity in hpd_init()
drm/radeon/kms: add MSI module parameter
drm/radeon/kms: Add MSI quirk for Dell RS690
drm/radeon/kms: Add MSI quirk for HP RS690
drm/radeon/kms: split MSI check into a separate function
vmwgfx: Reinstate the update_layout ioctl
drm/radeon/kms: always do extended edid probe
...
+2950
-2659
+6
-2
drivers/gpu/drm/drm_crtc.c
+6
-2
drivers/gpu/drm/drm_crtc.c
···
163
163
{ DRM_MODE_CONNECTOR_HDMIB, "HDMI-B", 0 },
164
164
{ DRM_MODE_CONNECTOR_TV, "TV", 0 },
165
165
{ DRM_MODE_CONNECTOR_eDP, "eDP", 0 },
166
+
{ DRM_MODE_CONNECTOR_VIRTUAL, "Virtual", 0},
166
167
};
167
168
168
169
static struct drm_prop_enum_list drm_encoder_enum_list[] =
···
172
171
{ DRM_MODE_ENCODER_TMDS, "TMDS" },
173
172
{ DRM_MODE_ENCODER_LVDS, "LVDS" },
174
173
{ DRM_MODE_ENCODER_TVDAC, "TV" },
174
+
{ DRM_MODE_ENCODER_VIRTUAL, "Virtual" },
175
175
};
176
176
177
177
char *drm_get_encoder_name(struct drm_encoder *encoder)
···
466
464
list_add_tail(&connector->head, &dev->mode_config.connector_list);
467
465
dev->mode_config.num_connector++;
468
466
469
-
drm_connector_attach_property(connector,
470
-
dev->mode_config.edid_property, 0);
467
+
if (connector_type != DRM_MODE_CONNECTOR_VIRTUAL)
468
+
drm_connector_attach_property(connector,
469
+
dev->mode_config.edid_property,
470
+
0);
471
471
472
472
drm_connector_attach_property(connector,
473
473
dev->mode_config.dpms_property, 0);
+1
-1
drivers/gpu/drm/radeon/Makefile
+1
-1
drivers/gpu/drm/radeon/Makefile
···
70
70
r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \
71
71
r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \
72
72
evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \
73
-
radeon_trace_points.o ni.o cayman_blit_shaders.o
73
+
radeon_trace_points.o ni.o cayman_blit_shaders.o atombios_encoders.o
74
74
75
75
radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
76
76
radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
+21
-35
drivers/gpu/drm/radeon/atombios_crtc.c
+21
-35
drivers/gpu/drm/radeon/atombios_crtc.c
···
558
558
bpc = connector->display_info.bpc;
559
559
encoder_mode = atombios_get_encoder_mode(encoder);
560
560
if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
561
-
radeon_encoder_is_dp_bridge(encoder)) {
561
+
(radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
562
562
if (connector) {
563
563
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
564
564
struct radeon_connector_atom_dig *dig_connector =
···
638
638
if (ss_enabled && ss->percentage)
639
639
args.v3.sInput.ucDispPllConfig |=
640
640
DISPPLL_CONFIG_SS_ENABLE;
641
-
if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT) ||
642
-
radeon_encoder_is_dp_bridge(encoder)) {
641
+
if (ENCODER_MODE_IS_DP(encoder_mode)) {
642
+
args.v3.sInput.ucDispPllConfig |=
643
+
DISPPLL_CONFIG_COHERENT_MODE;
644
+
/* 16200 or 27000 */
645
+
args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
646
+
} else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
643
647
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
644
-
if (encoder_mode == ATOM_ENCODER_MODE_DP) {
648
+
if (encoder_mode == ATOM_ENCODER_MODE_HDMI)
649
+
/* deep color support */
650
+
args.v3.sInput.usPixelClock =
651
+
cpu_to_le16((mode->clock * bpc / 8) / 10);
652
+
if (dig->coherent_mode)
645
653
args.v3.sInput.ucDispPllConfig |=
646
654
DISPPLL_CONFIG_COHERENT_MODE;
647
-
/* 16200 or 27000 */
648
-
args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
649
-
} else {
650
-
if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
651
-
/* deep color support */
652
-
args.v3.sInput.usPixelClock =
653
-
cpu_to_le16((mode->clock * bpc / 8) / 10);
654
-
}
655
-
if (dig->coherent_mode)
656
-
args.v3.sInput.ucDispPllConfig |=
657
-
DISPPLL_CONFIG_COHERENT_MODE;
658
-
if (mode->clock > 165000)
659
-
args.v3.sInput.ucDispPllConfig |=
660
-
DISPPLL_CONFIG_DUAL_LINK;
661
-
}
662
-
} else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
663
-
if (encoder_mode == ATOM_ENCODER_MODE_DP) {
655
+
if (mode->clock > 165000)
664
656
args.v3.sInput.ucDispPllConfig |=
665
-
DISPPLL_CONFIG_COHERENT_MODE;
666
-
/* 16200 or 27000 */
667
-
args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
668
-
} else if (encoder_mode != ATOM_ENCODER_MODE_LVDS) {
669
-
if (mode->clock > 165000)
670
-
args.v3.sInput.ucDispPllConfig |=
671
-
DISPPLL_CONFIG_DUAL_LINK;
672
-
}
657
+
DISPPLL_CONFIG_DUAL_LINK;
673
658
}
674
-
if (radeon_encoder_is_dp_bridge(encoder)) {
675
-
struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
676
-
struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
677
-
args.v3.sInput.ucExtTransmitterID = ext_radeon_encoder->encoder_id;
678
-
} else
659
+
if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
660
+
ENCODER_OBJECT_ID_NONE)
661
+
args.v3.sInput.ucExtTransmitterID =
662
+
radeon_encoder_get_dp_bridge_encoder_id(encoder);
663
+
else
679
664
args.v3.sInput.ucExtTransmitterID = 0;
680
665
681
666
atom_execute_table(rdev->mode_info.atom_context,
···
930
945
bpc = connector->display_info.bpc;
931
946
932
947
switch (encoder_mode) {
948
+
case ATOM_ENCODER_MODE_DP_MST:
933
949
case ATOM_ENCODER_MODE_DP:
934
950
/* DP/eDP */
935
951
dp_clock = dig_connector->dp_clock / 10;
···
1436
1450
* PPLL/DCPLL programming and only program the DP DTO for the
1437
1451
* crtc virtual pixel clock.
1438
1452
*/
1439
-
if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1453
+
if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
1440
1454
if (ASIC_IS_DCE5(rdev) || rdev->clock.dp_extclk)
1441
1455
return ATOM_PPLL_INVALID;
1442
1456
}
+18
-2
drivers/gpu/drm/radeon/atombios_dp.c
+18
-2
drivers/gpu/drm/radeon/atombios_dp.c
···
482
482
int bpp = convert_bpc_to_bpp(connector->display_info.bpc);
483
483
int lane_num, max_pix_clock;
484
484
485
-
if (radeon_connector_encoder_is_dp_bridge(connector))
485
+
if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
486
+
ENCODER_OBJECT_ID_NUTMEG)
486
487
return 270000;
487
488
488
489
lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
···
554
553
{
555
554
struct drm_device *dev = encoder->dev;
556
555
struct radeon_device *rdev = dev->dev_private;
556
+
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
557
557
int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
558
558
559
559
if (!ASIC_IS_DCE4(rdev))
560
560
return;
561
561
562
-
if (radeon_connector_encoder_is_dp_bridge(connector))
562
+
if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
563
+
ENCODER_OBJECT_ID_NUTMEG)
563
564
panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
565
+
else if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
566
+
ENCODER_OBJECT_ID_TRAVIS)
567
+
panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
568
+
else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
569
+
u8 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
570
+
if (tmp & 1)
571
+
panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
572
+
}
564
573
565
574
atombios_dig_encoder_setup(encoder,
566
575
ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
567
576
panel_mode);
577
+
578
+
if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
579
+
(panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
580
+
radeon_write_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_SET, 1);
581
+
}
568
582
}
569
583
570
584
void radeon_dp_set_link_config(struct drm_connector *connector,
+2369
drivers/gpu/drm/radeon/atombios_encoders.c
+2369
drivers/gpu/drm/radeon/atombios_encoders.c
···
1
+
/*
2
+
* Copyright 2007-11 Advanced Micro Devices, Inc.
3
+
* Copyright 2008 Red Hat Inc.
4
+
*
5
+
* Permission is hereby granted, free of charge, to any person obtaining a
6
+
* copy of this software and associated documentation files (the "Software"),
7
+
* to deal in the Software without restriction, including without limitation
8
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
9
+
* and/or sell copies of the Software, and to permit persons to whom the
10
+
* Software is furnished to do so, subject to the following conditions:
11
+
*
12
+
* The above copyright notice and this permission notice shall be included in
13
+
* all copies or substantial portions of the Software.
14
+
*
15
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21
+
* OTHER DEALINGS IN THE SOFTWARE.
22
+
*
23
+
* Authors: Dave Airlie
24
+
* Alex Deucher
25
+
*/
26
+
#include "drmP.h"
27
+
#include "drm_crtc_helper.h"
28
+
#include "radeon_drm.h"
29
+
#include "radeon.h"
30
+
#include "atom.h"
31
+
32
+
extern int atom_debug;
33
+
34
+
/* evil but including atombios.h is much worse */
35
+
bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36
+
struct drm_display_mode *mode);
37
+
38
+
39
+
static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
40
+
{
41
+
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
42
+
switch (radeon_encoder->encoder_id) {
43
+
case ENCODER_OBJECT_ID_INTERNAL_LVDS:
44
+
case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
45
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
46
+
case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
47
+
case ENCODER_OBJECT_ID_INTERNAL_DVO1:
48
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
49
+
case ENCODER_OBJECT_ID_INTERNAL_DDI:
50
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
51
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
52
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
53
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
54
+
return true;
55
+
default:
56
+
return false;
57
+
}
58
+
}
59
+
60
+
static struct drm_connector *
61
+
radeon_get_connector_for_encoder_init(struct drm_encoder *encoder)
62
+
{
63
+
struct drm_device *dev = encoder->dev;
64
+
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
65
+
struct drm_connector *connector;
66
+
struct radeon_connector *radeon_connector;
67
+
68
+
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
69
+
radeon_connector = to_radeon_connector(connector);
70
+
if (radeon_encoder->devices & radeon_connector->devices)
71
+
return connector;
72
+
}
73
+
return NULL;
74
+
}
75
+
76
+
static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
77
+
struct drm_display_mode *mode,
78
+
struct drm_display_mode *adjusted_mode)
79
+
{
80
+
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
81
+
struct drm_device *dev = encoder->dev;
82
+
struct radeon_device *rdev = dev->dev_private;
83
+
84
+
/* set the active encoder to connector routing */
85
+
radeon_encoder_set_active_device(encoder);
86
+
drm_mode_set_crtcinfo(adjusted_mode, 0);
87
+
88
+
/* hw bug */
89
+
if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
90
+
&& (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
91
+
adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
92
+
93
+
/* get the native mode for LVDS */
94
+
if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
95
+
radeon_panel_mode_fixup(encoder, adjusted_mode);
96
+
97
+
/* get the native mode for TV */
98
+
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
99
+
struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
100
+
if (tv_dac) {
101
+
if (tv_dac->tv_std == TV_STD_NTSC ||
102
+
tv_dac->tv_std == TV_STD_NTSC_J ||
103
+
tv_dac->tv_std == TV_STD_PAL_M)
104
+
radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
105
+
else
106
+
radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
107
+
}
108
+
}
109
+
110
+
if (ASIC_IS_DCE3(rdev) &&
111
+
((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
112
+
(radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
113
+
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
114
+
radeon_dp_set_link_config(connector, mode);
115
+
}
116
+
117
+
return true;
118
+
}
119
+
120
+
static void
121
+
atombios_dac_setup(struct drm_encoder *encoder, int action)
122
+
{
123
+
struct drm_device *dev = encoder->dev;
124
+
struct radeon_device *rdev = dev->dev_private;
125
+
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
126
+
DAC_ENCODER_CONTROL_PS_ALLOCATION args;
127
+
int index = 0;
128
+
struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
129
+
130
+
memset(&args, 0, sizeof(args));
131
+
132
+
switch (radeon_encoder->encoder_id) {
133
+
case ENCODER_OBJECT_ID_INTERNAL_DAC1:
134
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
135
+
index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
136
+
break;
137
+
case ENCODER_OBJECT_ID_INTERNAL_DAC2:
138
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
139
+
index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
140
+
break;
141
+
}
142
+
143
+
args.ucAction = action;
144
+
145
+
if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
146
+
args.ucDacStandard = ATOM_DAC1_PS2;
147
+
else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
148
+
args.ucDacStandard = ATOM_DAC1_CV;
149
+
else {
150
+
switch (dac_info->tv_std) {
151
+
case TV_STD_PAL:
152
+
case TV_STD_PAL_M:
153
+
case TV_STD_SCART_PAL:
154
+
case TV_STD_SECAM:
155
+
case TV_STD_PAL_CN:
156
+
args.ucDacStandard = ATOM_DAC1_PAL;
157
+
break;
158
+
case TV_STD_NTSC:
159
+
case TV_STD_NTSC_J:
160
+
case TV_STD_PAL_60:
161
+
default:
162
+
args.ucDacStandard = ATOM_DAC1_NTSC;
163
+
break;
164
+
}
165
+
}
166
+
args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
167
+
168
+
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
169
+
170
+
}
171
+
172
+
static void
173
+
atombios_tv_setup(struct drm_encoder *encoder, int action)
174
+
{
175
+
struct drm_device *dev = encoder->dev;
176
+
struct radeon_device *rdev = dev->dev_private;
177
+
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
178
+
TV_ENCODER_CONTROL_PS_ALLOCATION args;
179
+
int index = 0;
180
+
struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
181
+
182
+
memset(&args, 0, sizeof(args));
183
+
184
+
index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
185
+
186
+
args.sTVEncoder.ucAction = action;
187
+
188
+
if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
189
+
args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
190
+
else {
191
+
switch (dac_info->tv_std) {
192
+
case TV_STD_NTSC:
193
+
args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
194
+
break;
195
+
case TV_STD_PAL:
196
+
args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
197
+
break;
198
+
case TV_STD_PAL_M:
199
+
args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
200
+
break;
201
+
case TV_STD_PAL_60:
202
+
args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
203
+
break;
204
+
case TV_STD_NTSC_J:
205
+
args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
206
+
break;
207
+
case TV_STD_SCART_PAL:
208
+
args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
209
+
break;
210
+
case TV_STD_SECAM:
211
+
args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
212
+
break;
213
+
case TV_STD_PAL_CN:
214
+
args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
215
+
break;
216
+
default:
217
+
args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
218
+
break;
219
+
}
220
+
}
221
+
222
+
args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
223
+
224
+
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
225
+
226
+
}
227
+
228
+
union dvo_encoder_control {
229
+
ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
230
+
DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
231
+
DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
232
+
};
233
+
234
+
void
235
+
atombios_dvo_setup(struct drm_encoder *encoder, int action)
236
+
{
237
+
struct drm_device *dev = encoder->dev;
238
+
struct radeon_device *rdev = dev->dev_private;
239
+
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
240
+
union dvo_encoder_control args;
241
+
int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
242
+
uint8_t frev, crev;
243
+
244
+
memset(&args, 0, sizeof(args));
245
+
246
+
if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
247
+
return;
248
+
249
+
switch (frev) {
250
+
case 1:
251
+
switch (crev) {
252
+
case 1:
253
+
/* R4xx, R5xx */
254
+
args.ext_tmds.sXTmdsEncoder.ucEnable = action;
255
+
256
+
if (radeon_encoder->pixel_clock > 165000)
257
+
args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
258
+
259
+
args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
260
+
break;
261
+
case 2:
262
+
/* RS600/690/740 */
263
+
args.dvo.sDVOEncoder.ucAction = action;
264
+
args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
265
+
/* DFP1, CRT1, TV1 depending on the type of port */
266
+
args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
267
+
268
+
if (radeon_encoder->pixel_clock > 165000)
269
+
args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
270
+
break;
271
+
case 3:
272
+
/* R6xx */
273
+
args.dvo_v3.ucAction = action;
274
+
args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
275
+
args.dvo_v3.ucDVOConfig = 0; /* XXX */
276
+
break;
277
+
default:
278
+
DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
279
+
break;
280
+
}
281
+
break;
282
+
default:
283
+
DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
284
+
break;
285
+
}
286
+
287
+
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
288
+
}
289
+
290
+
union lvds_encoder_control {
291
+
LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
292
+
LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
293
+
};
294
+
295
+
void
296
+
atombios_digital_setup(struct drm_encoder *encoder, int action)
297
+
{
298
+
struct drm_device *dev = encoder->dev;
299
+
struct radeon_device *rdev = dev->dev_private;
300
+
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
301
+
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
302
+
union lvds_encoder_control args;
303
+
int index = 0;
304
+
int hdmi_detected = 0;
305
+
uint8_t frev, crev;
306
+
307
+
if (!dig)
308
+
return;
309
+
310
+
if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
311
+
hdmi_detected = 1;
312
+
313
+
memset(&args, 0, sizeof(args));
314
+
315
+
switch (radeon_encoder->encoder_id) {
316
+
case ENCODER_OBJECT_ID_INTERNAL_LVDS:
317
+
index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
318
+
break;
319
+
case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
320
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
321
+
index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
322
+
break;
323
+
case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
324
+
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
325
+
index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
326
+
else
327
+
index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
328
+
break;
329
+
}
330
+
331
+
if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
332
+
return;
333
+
334
+
switch (frev) {
335
+
case 1:
336
+
case 2:
337
+
switch (crev) {
338
+
case 1:
339
+
args.v1.ucMisc = 0;
340
+
args.v1.ucAction = action;
341
+
if (hdmi_detected)
342
+
args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
343
+
args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
344
+
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
345
+
if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
346
+
args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
347
+
if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
348
+
args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
349
+
} else {
350
+
if (dig->linkb)
351
+
args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
352
+
if (radeon_encoder->pixel_clock > 165000)
353
+
args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
354
+
/*if (pScrn->rgbBits == 8) */
355
+
args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
356
+
}
357
+
break;
358
+
case 2:
359
+
case 3:
360
+
args.v2.ucMisc = 0;
361
+
args.v2.ucAction = action;
362
+
if (crev == 3) {
363
+
if (dig->coherent_mode)
364
+
args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
365
+
}
366
+
if (hdmi_detected)
367
+
args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
368
+
args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
369
+
args.v2.ucTruncate = 0;
370
+
args.v2.ucSpatial = 0;
371
+
args.v2.ucTemporal = 0;
372
+
args.v2.ucFRC = 0;
373
+
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
374
+
if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
375
+
args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
376
+
if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
377
+
args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
378
+
if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
379
+
args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
380
+
}
381
+
if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
382
+
args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
383
+
if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
384
+
args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
385
+
if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
386
+
args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
387
+
}
388
+
} else {
389
+
if (dig->linkb)
390
+
args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
391
+
if (radeon_encoder->pixel_clock > 165000)
392
+
args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
393
+
}
394
+
break;
395
+
default:
396
+
DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
397
+
break;
398
+
}
399
+
break;
400
+
default:
401
+
DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
402
+
break;
403
+
}
404
+
405
+
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
406
+
}
407
+
408
+
int
409
+
atombios_get_encoder_mode(struct drm_encoder *encoder)
410
+
{
411
+
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
412
+
struct drm_device *dev = encoder->dev;
413
+
struct radeon_device *rdev = dev->dev_private;
414
+
struct drm_connector *connector;
415
+
struct radeon_connector *radeon_connector;
416
+
struct radeon_connector_atom_dig *dig_connector;
417
+
418
+
/* dp bridges are always DP */
419
+
if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
420
+
return ATOM_ENCODER_MODE_DP;
421
+
422
+
/* DVO is always DVO */
423
+
if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO)
424
+
return ATOM_ENCODER_MODE_DVO;
425
+
426
+
connector = radeon_get_connector_for_encoder(encoder);
427
+
/* if we don't have an active device yet, just use one of
428
+
* the connectors tied to the encoder.
429
+
*/
430
+
if (!connector)
431
+
connector = radeon_get_connector_for_encoder_init(encoder);
432
+
radeon_connector = to_radeon_connector(connector);
433
+
434
+
switch (connector->connector_type) {
435
+
case DRM_MODE_CONNECTOR_DVII:
436
+
case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
437
+
if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
438
+
/* fix me */
439
+
if (ASIC_IS_DCE4(rdev))
440
+
return ATOM_ENCODER_MODE_DVI;
441
+
else
442
+
return ATOM_ENCODER_MODE_HDMI;
443
+
} else if (radeon_connector->use_digital)
444
+
return ATOM_ENCODER_MODE_DVI;
445
+
else
446
+
return ATOM_ENCODER_MODE_CRT;
447
+
break;
448
+
case DRM_MODE_CONNECTOR_DVID:
449
+
case DRM_MODE_CONNECTOR_HDMIA:
450
+
default:
451
+
if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
452
+
/* fix me */
453
+
if (ASIC_IS_DCE4(rdev))
454
+
return ATOM_ENCODER_MODE_DVI;
455
+
else
456
+
return ATOM_ENCODER_MODE_HDMI;
457
+
} else
458
+
return ATOM_ENCODER_MODE_DVI;
459
+
break;
460
+
case DRM_MODE_CONNECTOR_LVDS:
461
+
return ATOM_ENCODER_MODE_LVDS;
462
+
break;
463
+
case DRM_MODE_CONNECTOR_DisplayPort:
464
+
dig_connector = radeon_connector->con_priv;
465
+
if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
466
+
(dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
467
+
return ATOM_ENCODER_MODE_DP;
468
+
else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
469
+
/* fix me */
470
+
if (ASIC_IS_DCE4(rdev))
471
+
return ATOM_ENCODER_MODE_DVI;
472
+
else
473
+
return ATOM_ENCODER_MODE_HDMI;
474
+
} else
475
+
return ATOM_ENCODER_MODE_DVI;
476
+
break;
477
+
case DRM_MODE_CONNECTOR_eDP:
478
+
return ATOM_ENCODER_MODE_DP;
479
+
case DRM_MODE_CONNECTOR_DVIA:
480
+
case DRM_MODE_CONNECTOR_VGA:
481
+
return ATOM_ENCODER_MODE_CRT;
482
+
break;
483
+
case DRM_MODE_CONNECTOR_Composite:
484
+
case DRM_MODE_CONNECTOR_SVIDEO:
485
+
case DRM_MODE_CONNECTOR_9PinDIN:
486
+
/* fix me */
487
+
return ATOM_ENCODER_MODE_TV;
488
+
/*return ATOM_ENCODER_MODE_CV;*/
489
+
break;
490
+
}
491
+
}
492
+
493
+
/*
494
+
* DIG Encoder/Transmitter Setup
495
+
*
496
+
* DCE 3.0/3.1
497
+
* - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
498
+
* Supports up to 3 digital outputs
499
+
* - 2 DIG encoder blocks.
500
+
* DIG1 can drive UNIPHY link A or link B
501
+
* DIG2 can drive UNIPHY link B or LVTMA
502
+
*
503
+
* DCE 3.2
504
+
* - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
505
+
* Supports up to 5 digital outputs
506
+
* - 2 DIG encoder blocks.
507
+
* DIG1/2 can drive UNIPHY0/1/2 link A or link B
508
+
*
509
+
* DCE 4.0/5.0
510
+
* - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
511
+
* Supports up to 6 digital outputs
512
+
* - 6 DIG encoder blocks.
513
+
* - DIG to PHY mapping is hardcoded
514
+
* DIG1 drives UNIPHY0 link A, A+B
515
+
* DIG2 drives UNIPHY0 link B
516
+
* DIG3 drives UNIPHY1 link A, A+B
517
+
* DIG4 drives UNIPHY1 link B
518
+
* DIG5 drives UNIPHY2 link A, A+B
519
+
* DIG6 drives UNIPHY2 link B
520
+
*
521
+
* DCE 4.1
522
+
* - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
523
+
* Supports up to 6 digital outputs
524
+
* - 2 DIG encoder blocks.
525
+
* DIG1/2 can drive UNIPHY0/1/2 link A or link B
526
+
*
527
+
* Routing
528
+
* crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
529
+
* Examples:
530
+
* crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
531
+
* crtc1 -> dig1 -> UNIPHY0 link B -> DP
532
+
* crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
533
+
* crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
534
+
*/
535
+
536
+
union dig_encoder_control {
537
+
DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
538
+
DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
539
+
DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
540
+
DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
541
+
};
542
+
543
+
void
544
+
atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
545
+
{
546
+
struct drm_device *dev = encoder->dev;
547
+
struct radeon_device *rdev = dev->dev_private;
548
+
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
549
+
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
550
+
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
551
+
union dig_encoder_control args;
552
+
int index = 0;
553
+
uint8_t frev, crev;
554
+
int dp_clock = 0;
555
+
int dp_lane_count = 0;
556
+
int hpd_id = RADEON_HPD_NONE;
557
+
int bpc = 8;
558
+
559
+
if (connector) {
560
+
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
561
+
struct radeon_connector_atom_dig *dig_connector =
562
+
radeon_connector->con_priv;
563
+
564
+
dp_clock = dig_connector->dp_clock;
565
+
dp_lane_count = dig_connector->dp_lane_count;
566
+
hpd_id = radeon_connector->hpd.hpd;
567
+
bpc = connector->display_info.bpc;
568
+
}
569
+
570
+
/* no dig encoder assigned */
571
+
if (dig->dig_encoder == -1)
572
+
return;
573
+
574
+
memset(&args, 0, sizeof(args));
575
+
576
+
if (ASIC_IS_DCE4(rdev))
577
+
index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
578
+
else {
579
+
if (dig->dig_encoder)
580
+
index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
581
+
else
582
+
index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
583
+
}
584
+
585
+
if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
586
+
return;
587
+
588
+
switch (frev) {
589
+
case 1:
590
+
switch (crev) {
591
+
case 1:
592
+
args.v1.ucAction = action;
593
+
args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
594
+
if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
595
+
args.v3.ucPanelMode = panel_mode;
596
+
else
597
+
args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
598
+
599
+
if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
600
+
args.v1.ucLaneNum = dp_lane_count;
601
+
else if (radeon_encoder->pixel_clock > 165000)
602
+
args.v1.ucLaneNum = 8;
603
+
else
604
+
args.v1.ucLaneNum = 4;
605
+
606
+
if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
607
+
args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
608
+
switch (radeon_encoder->encoder_id) {
609
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
610
+
args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
611
+
break;
612
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
613
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
614
+
args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
615
+
break;
616
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
617
+
args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
618
+
break;
619
+
}
620
+
if (dig->linkb)
621
+
args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
622
+
else
623
+
args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
624
+
break;
625
+
case 2:
626
+
case 3:
627
+
args.v3.ucAction = action;
628
+
args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
629
+
if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
630
+
args.v3.ucPanelMode = panel_mode;
631
+
else
632
+
args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
633
+
634
+
if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
635
+
args.v3.ucLaneNum = dp_lane_count;
636
+
else if (radeon_encoder->pixel_clock > 165000)
637
+
args.v3.ucLaneNum = 8;
638
+
else
639
+
args.v3.ucLaneNum = 4;
640
+
641
+
if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
642
+
args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
643
+
args.v3.acConfig.ucDigSel = dig->dig_encoder;
644
+
switch (bpc) {
645
+
case 0:
646
+
args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
647
+
break;
648
+
case 6:
649
+
args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
650
+
break;
651
+
case 8:
652
+
default:
653
+
args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
654
+
break;
655
+
case 10:
656
+
args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
657
+
break;
658
+
case 12:
659
+
args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
660
+
break;
661
+
case 16:
662
+
args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
663
+
break;
664
+
}
665
+
break;
666
+
case 4:
667
+
args.v4.ucAction = action;
668
+
args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
669
+
if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
670
+
args.v4.ucPanelMode = panel_mode;
671
+
else
672
+
args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
673
+
674
+
if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
675
+
args.v4.ucLaneNum = dp_lane_count;
676
+
else if (radeon_encoder->pixel_clock > 165000)
677
+
args.v4.ucLaneNum = 8;
678
+
else
679
+
args.v4.ucLaneNum = 4;
680
+
681
+
if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) {
682
+
if (dp_clock == 270000)
683
+
args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
684
+
else if (dp_clock == 540000)
685
+
args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
686
+
}
687
+
args.v4.acConfig.ucDigSel = dig->dig_encoder;
688
+
switch (bpc) {
689
+
case 0:
690
+
args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
691
+
break;
692
+
case 6:
693
+
args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
694
+
break;
695
+
case 8:
696
+
default:
697
+
args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
698
+
break;
699
+
case 10:
700
+
args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
701
+
break;
702
+
case 12:
703
+
args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
704
+
break;
705
+
case 16:
706
+
args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
707
+
break;
708
+
}
709
+
if (hpd_id == RADEON_HPD_NONE)
710
+
args.v4.ucHPD_ID = 0;
711
+
else
712
+
args.v4.ucHPD_ID = hpd_id + 1;
713
+
break;
714
+
default:
715
+
DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
716
+
break;
717
+
}
718
+
break;
719
+
default:
720
+
DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
721
+
break;
722
+
}
723
+
724
+
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
725
+
726
+
}
727
+
728
+
union dig_transmitter_control {
729
+
DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
730
+
DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
731
+
DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
732
+
DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
733
+
};
734
+
735
+
void
736
+
atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
737
+
{
738
+
struct drm_device *dev = encoder->dev;
739
+
struct radeon_device *rdev = dev->dev_private;
740
+
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
741
+
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
742
+
struct drm_connector *connector;
743
+
union dig_transmitter_control args;
744
+
int index = 0;
745
+
uint8_t frev, crev;
746
+
bool is_dp = false;
747
+
int pll_id = 0;
748
+
int dp_clock = 0;
749
+
int dp_lane_count = 0;
750
+
int connector_object_id = 0;
751
+
int igp_lane_info = 0;
752
+
int dig_encoder = dig->dig_encoder;
753
+
754
+
if (action == ATOM_TRANSMITTER_ACTION_INIT) {
755
+
connector = radeon_get_connector_for_encoder_init(encoder);
756
+
/* just needed to avoid bailing in the encoder check. the encoder
757
+
* isn't used for init
758
+
*/
759
+
dig_encoder = 0;
760
+
} else
761
+
connector = radeon_get_connector_for_encoder(encoder);
762
+
763
+
if (connector) {
764
+
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
765
+
struct radeon_connector_atom_dig *dig_connector =
766
+
radeon_connector->con_priv;
767
+
768
+
dp_clock = dig_connector->dp_clock;
769
+
dp_lane_count = dig_connector->dp_lane_count;
770
+
connector_object_id =
771
+
(radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
772
+
igp_lane_info = dig_connector->igp_lane_info;
773
+
}
774
+
775
+
if (encoder->crtc) {
776
+
struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
777
+
pll_id = radeon_crtc->pll_id;
778
+
}
779
+
780
+
/* no dig encoder assigned */
781
+
if (dig_encoder == -1)
782
+
return;
783
+
784
+
if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
785
+
is_dp = true;
786
+
787
+
memset(&args, 0, sizeof(args));
788
+
789
+
switch (radeon_encoder->encoder_id) {
790
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
791
+
index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
792
+
break;
793
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
794
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
795
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
796
+
index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
797
+
break;
798
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
799
+
index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
800
+
break;
801
+
}
802
+
803
+
if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
804
+
return;
805
+
806
+
switch (frev) {
807
+
case 1:
808
+
switch (crev) {
809
+
case 1:
810
+
args.v1.ucAction = action;
811
+
if (action == ATOM_TRANSMITTER_ACTION_INIT) {
812
+
args.v1.usInitInfo = cpu_to_le16(connector_object_id);
813
+
} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
814
+
args.v1.asMode.ucLaneSel = lane_num;
815
+
args.v1.asMode.ucLaneSet = lane_set;
816
+
} else {
817
+
if (is_dp)
818
+
args.v1.usPixelClock =
819
+
cpu_to_le16(dp_clock / 10);
820
+
else if (radeon_encoder->pixel_clock > 165000)
821
+
args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
822
+
else
823
+
args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
824
+
}
825
+
826
+
args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
827
+
828
+
if (dig_encoder)
829
+
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
830
+
else
831
+
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
832
+
833
+
if ((rdev->flags & RADEON_IS_IGP) &&
834
+
(radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
835
+
if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
836
+
if (igp_lane_info & 0x1)
837
+
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
838
+
else if (igp_lane_info & 0x2)
839
+
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
840
+
else if (igp_lane_info & 0x4)
841
+
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
842
+
else if (igp_lane_info & 0x8)
843
+
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
844
+
} else {
845
+
if (igp_lane_info & 0x3)
846
+
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
847
+
else if (igp_lane_info & 0xc)
848
+
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
849
+
}
850
+
}
851
+
852
+
if (dig->linkb)
853
+
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
854
+
else
855
+
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
856
+
857
+
if (is_dp)
858
+
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
859
+
else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
860
+
if (dig->coherent_mode)
861
+
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
862
+
if (radeon_encoder->pixel_clock > 165000)
863
+
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
864
+
}
865
+
break;
866
+
case 2:
867
+
args.v2.ucAction = action;
868
+
if (action == ATOM_TRANSMITTER_ACTION_INIT) {
869
+
args.v2.usInitInfo = cpu_to_le16(connector_object_id);
870
+
} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
871
+
args.v2.asMode.ucLaneSel = lane_num;
872
+
args.v2.asMode.ucLaneSet = lane_set;
873
+
} else {
874
+
if (is_dp)
875
+
args.v2.usPixelClock =
876
+
cpu_to_le16(dp_clock / 10);
877
+
else if (radeon_encoder->pixel_clock > 165000)
878
+
args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
879
+
else
880
+
args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
881
+
}
882
+
883
+
args.v2.acConfig.ucEncoderSel = dig_encoder;
884
+
if (dig->linkb)
885
+
args.v2.acConfig.ucLinkSel = 1;
886
+
887
+
switch (radeon_encoder->encoder_id) {
888
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
889
+
args.v2.acConfig.ucTransmitterSel = 0;
890
+
break;
891
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
892
+
args.v2.acConfig.ucTransmitterSel = 1;
893
+
break;
894
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
895
+
args.v2.acConfig.ucTransmitterSel = 2;
896
+
break;
897
+
}
898
+
899
+
if (is_dp) {
900
+
args.v2.acConfig.fCoherentMode = 1;
901
+
args.v2.acConfig.fDPConnector = 1;
902
+
} else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
903
+
if (dig->coherent_mode)
904
+
args.v2.acConfig.fCoherentMode = 1;
905
+
if (radeon_encoder->pixel_clock > 165000)
906
+
args.v2.acConfig.fDualLinkConnector = 1;
907
+
}
908
+
break;
909
+
case 3:
910
+
args.v3.ucAction = action;
911
+
if (action == ATOM_TRANSMITTER_ACTION_INIT) {
912
+
args.v3.usInitInfo = cpu_to_le16(connector_object_id);
913
+
} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
914
+
args.v3.asMode.ucLaneSel = lane_num;
915
+
args.v3.asMode.ucLaneSet = lane_set;
916
+
} else {
917
+
if (is_dp)
918
+
args.v3.usPixelClock =
919
+
cpu_to_le16(dp_clock / 10);
920
+
else if (radeon_encoder->pixel_clock > 165000)
921
+
args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
922
+
else
923
+
args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
924
+
}
925
+
926
+
if (is_dp)
927
+
args.v3.ucLaneNum = dp_lane_count;
928
+
else if (radeon_encoder->pixel_clock > 165000)
929
+
args.v3.ucLaneNum = 8;
930
+
else
931
+
args.v3.ucLaneNum = 4;
932
+
933
+
if (dig->linkb)
934
+
args.v3.acConfig.ucLinkSel = 1;
935
+
if (dig_encoder & 1)
936
+
args.v3.acConfig.ucEncoderSel = 1;
937
+
938
+
/* Select the PLL for the PHY
939
+
* DP PHY should be clocked from external src if there is
940
+
* one.
941
+
*/
942
+
/* On DCE4, if there is an external clock, it generates the DP ref clock */
943
+
if (is_dp && rdev->clock.dp_extclk)
944
+
args.v3.acConfig.ucRefClkSource = 2; /* external src */
945
+
else
946
+
args.v3.acConfig.ucRefClkSource = pll_id;
947
+
948
+
switch (radeon_encoder->encoder_id) {
949
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
950
+
args.v3.acConfig.ucTransmitterSel = 0;
951
+
break;
952
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
953
+
args.v3.acConfig.ucTransmitterSel = 1;
954
+
break;
955
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
956
+
args.v3.acConfig.ucTransmitterSel = 2;
957
+
break;
958
+
}
959
+
960
+
if (is_dp)
961
+
args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
962
+
else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
963
+
if (dig->coherent_mode)
964
+
args.v3.acConfig.fCoherentMode = 1;
965
+
if (radeon_encoder->pixel_clock > 165000)
966
+
args.v3.acConfig.fDualLinkConnector = 1;
967
+
}
968
+
break;
969
+
case 4:
970
+
args.v4.ucAction = action;
971
+
if (action == ATOM_TRANSMITTER_ACTION_INIT) {
972
+
args.v4.usInitInfo = cpu_to_le16(connector_object_id);
973
+
} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
974
+
args.v4.asMode.ucLaneSel = lane_num;
975
+
args.v4.asMode.ucLaneSet = lane_set;
976
+
} else {
977
+
if (is_dp)
978
+
args.v4.usPixelClock =
979
+
cpu_to_le16(dp_clock / 10);
980
+
else if (radeon_encoder->pixel_clock > 165000)
981
+
args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
982
+
else
983
+
args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
984
+
}
985
+
986
+
if (is_dp)
987
+
args.v4.ucLaneNum = dp_lane_count;
988
+
else if (radeon_encoder->pixel_clock > 165000)
989
+
args.v4.ucLaneNum = 8;
990
+
else
991
+
args.v4.ucLaneNum = 4;
992
+
993
+
if (dig->linkb)
994
+
args.v4.acConfig.ucLinkSel = 1;
995
+
if (dig_encoder & 1)
996
+
args.v4.acConfig.ucEncoderSel = 1;
997
+
998
+
/* Select the PLL for the PHY
999
+
* DP PHY should be clocked from external src if there is
1000
+
* one.
1001
+
*/
1002
+
/* On DCE5 DCPLL usually generates the DP ref clock */
1003
+
if (is_dp) {
1004
+
if (rdev->clock.dp_extclk)
1005
+
args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1006
+
else
1007
+
args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1008
+
} else
1009
+
args.v4.acConfig.ucRefClkSource = pll_id;
1010
+
1011
+
switch (radeon_encoder->encoder_id) {
1012
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1013
+
args.v4.acConfig.ucTransmitterSel = 0;
1014
+
break;
1015
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1016
+
args.v4.acConfig.ucTransmitterSel = 1;
1017
+
break;
1018
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1019
+
args.v4.acConfig.ucTransmitterSel = 2;
1020
+
break;
1021
+
}
1022
+
1023
+
if (is_dp)
1024
+
args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1025
+
else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1026
+
if (dig->coherent_mode)
1027
+
args.v4.acConfig.fCoherentMode = 1;
1028
+
if (radeon_encoder->pixel_clock > 165000)
1029
+
args.v4.acConfig.fDualLinkConnector = 1;
1030
+
}
1031
+
break;
1032
+
default:
1033
+
DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1034
+
break;
1035
+
}
1036
+
break;
1037
+
default:
1038
+
DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1039
+
break;
1040
+
}
1041
+
1042
+
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1043
+
}
1044
+
1045
+
bool
1046
+
atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1047
+
{
1048
+
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1049
+
struct drm_device *dev = radeon_connector->base.dev;
1050
+
struct radeon_device *rdev = dev->dev_private;
1051
+
union dig_transmitter_control args;
1052
+
int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1053
+
uint8_t frev, crev;
1054
+
1055
+
if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1056
+
goto done;
1057
+
1058
+
if (!ASIC_IS_DCE4(rdev))
1059
+
goto done;
1060
+
1061
+
if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1062
+
(action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1063
+
goto done;
1064
+
1065
+
if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1066
+
goto done;
1067
+
1068
+
memset(&args, 0, sizeof(args));
1069
+
1070
+
args.v1.ucAction = action;
1071
+
1072
+
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1073
+
1074
+
/* wait for the panel to power up */
1075
+
if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1076
+
int i;
1077
+
1078
+
for (i = 0; i < 300; i++) {
1079
+
if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1080
+
return true;
1081
+
mdelay(1);
1082
+
}
1083
+
return false;
1084
+
}
1085
+
done:
1086
+
return true;
1087
+
}
1088
+
1089
+
union external_encoder_control {
1090
+
EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1091
+
EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1092
+
};
1093
+
1094
+
static void
1095
+
atombios_external_encoder_setup(struct drm_encoder *encoder,
1096
+
struct drm_encoder *ext_encoder,
1097
+
int action)
1098
+
{
1099
+
struct drm_device *dev = encoder->dev;
1100
+
struct radeon_device *rdev = dev->dev_private;
1101
+
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1102
+
struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1103
+
union external_encoder_control args;
1104
+
struct drm_connector *connector;
1105
+
int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1106
+
u8 frev, crev;
1107
+
int dp_clock = 0;
1108
+
int dp_lane_count = 0;
1109
+
int connector_object_id = 0;
1110
+
u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1111
+
int bpc = 8;
1112
+
1113
+
if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1114
+
connector = radeon_get_connector_for_encoder_init(encoder);
1115
+
else
1116
+
connector = radeon_get_connector_for_encoder(encoder);
1117
+
1118
+
if (connector) {
1119
+
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1120
+
struct radeon_connector_atom_dig *dig_connector =
1121
+
radeon_connector->con_priv;
1122
+
1123
+
dp_clock = dig_connector->dp_clock;
1124
+
dp_lane_count = dig_connector->dp_lane_count;
1125
+
connector_object_id =
1126
+
(radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1127
+
bpc = connector->display_info.bpc;
1128
+
}
1129
+
1130
+
memset(&args, 0, sizeof(args));
1131
+
1132
+
if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1133
+
return;
1134
+
1135
+
switch (frev) {
1136
+
case 1:
1137
+
/* no params on frev 1 */
1138
+
break;
1139
+
case 2:
1140
+
switch (crev) {
1141
+
case 1:
1142
+
case 2:
1143
+
args.v1.sDigEncoder.ucAction = action;
1144
+
args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1145
+
args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1146
+
1147
+
if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1148
+
if (dp_clock == 270000)
1149
+
args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1150
+
args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1151
+
} else if (radeon_encoder->pixel_clock > 165000)
1152
+
args.v1.sDigEncoder.ucLaneNum = 8;
1153
+
else
1154
+
args.v1.sDigEncoder.ucLaneNum = 4;
1155
+
break;
1156
+
case 3:
1157
+
args.v3.sExtEncoder.ucAction = action;
1158
+
if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1159
+
args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1160
+
else
1161
+
args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1162
+
args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1163
+
1164
+
if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1165
+
if (dp_clock == 270000)
1166
+
args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1167
+
else if (dp_clock == 540000)
1168
+
args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1169
+
args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1170
+
} else if (radeon_encoder->pixel_clock > 165000)
1171
+
args.v3.sExtEncoder.ucLaneNum = 8;
1172
+
else
1173
+
args.v3.sExtEncoder.ucLaneNum = 4;
1174
+
switch (ext_enum) {
1175
+
case GRAPH_OBJECT_ENUM_ID1:
1176
+
args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1177
+
break;
1178
+
case GRAPH_OBJECT_ENUM_ID2:
1179
+
args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1180
+
break;
1181
+
case GRAPH_OBJECT_ENUM_ID3:
1182
+
args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1183
+
break;
1184
+
}
1185
+
switch (bpc) {
1186
+
case 0:
1187
+
args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1188
+
break;
1189
+
case 6:
1190
+
args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1191
+
break;
1192
+
case 8:
1193
+
default:
1194
+
args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1195
+
break;
1196
+
case 10:
1197
+
args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1198
+
break;
1199
+
case 12:
1200
+
args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1201
+
break;
1202
+
case 16:
1203
+
args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1204
+
break;
1205
+
}
1206
+
break;
1207
+
default:
1208
+
DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1209
+
return;
1210
+
}
1211
+
break;
1212
+
default:
1213
+
DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1214
+
return;
1215
+
}
1216
+
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1217
+
}
1218
+
1219
+
static void
1220
+
atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1221
+
{
1222
+
struct drm_device *dev = encoder->dev;
1223
+
struct radeon_device *rdev = dev->dev_private;
1224
+
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1225
+
struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1226
+
ENABLE_YUV_PS_ALLOCATION args;
1227
+
int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1228
+
uint32_t temp, reg;
1229
+
1230
+
memset(&args, 0, sizeof(args));
1231
+
1232
+
if (rdev->family >= CHIP_R600)
1233
+
reg = R600_BIOS_3_SCRATCH;
1234
+
else
1235
+
reg = RADEON_BIOS_3_SCRATCH;
1236
+
1237
+
/* XXX: fix up scratch reg handling */
1238
+
temp = RREG32(reg);
1239
+
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1240
+
WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1241
+
(radeon_crtc->crtc_id << 18)));
1242
+
else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1243
+
WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1244
+
else
1245
+
WREG32(reg, 0);
1246
+
1247
+
if (enable)
1248
+
args.ucEnable = ATOM_ENABLE;
1249
+
args.ucCRTC = radeon_crtc->crtc_id;
1250
+
1251
+
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1252
+
1253
+
WREG32(reg, temp);
1254
+
}
1255
+
1256
+
static void
1257
+
radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1258
+
{
1259
+
struct drm_device *dev = encoder->dev;
1260
+
struct radeon_device *rdev = dev->dev_private;
1261
+
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1262
+
DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1263
+
int index = 0;
1264
+
1265
+
memset(&args, 0, sizeof(args));
1266
+
1267
+
switch (radeon_encoder->encoder_id) {
1268
+
case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1269
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1270
+
index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1271
+
break;
1272
+
case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1273
+
case ENCODER_OBJECT_ID_INTERNAL_DDI:
1274
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1275
+
index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1276
+
break;
1277
+
case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1278
+
index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1279
+
break;
1280
+
case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1281
+
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1282
+
index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1283
+
else
1284
+
index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1285
+
break;
1286
+
case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1287
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1288
+
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1289
+
index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1290
+
else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1291
+
index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1292
+
else
1293
+
index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1294
+
break;
1295
+
case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1296
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1297
+
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1298
+
index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1299
+
else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1300
+
index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1301
+
else
1302
+
index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1303
+
break;
1304
+
default:
1305
+
return;
1306
+
}
1307
+
1308
+
switch (mode) {
1309
+
case DRM_MODE_DPMS_ON:
1310
+
args.ucAction = ATOM_ENABLE;
1311
+
/* workaround for DVOOutputControl on some RS690 systems */
1312
+
if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1313
+
u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1314
+
WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1315
+
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1316
+
WREG32(RADEON_BIOS_3_SCRATCH, reg);
1317
+
} else
1318
+
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1319
+
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1320
+
args.ucAction = ATOM_LCD_BLON;
1321
+
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1322
+
}
1323
+
break;
1324
+
case DRM_MODE_DPMS_STANDBY:
1325
+
case DRM_MODE_DPMS_SUSPEND:
1326
+
case DRM_MODE_DPMS_OFF:
1327
+
args.ucAction = ATOM_DISABLE;
1328
+
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1329
+
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1330
+
args.ucAction = ATOM_LCD_BLOFF;
1331
+
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1332
+
}
1333
+
break;
1334
+
}
1335
+
}
1336
+
1337
+
static void
1338
+
radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1339
+
{
1340
+
struct drm_device *dev = encoder->dev;
1341
+
struct radeon_device *rdev = dev->dev_private;
1342
+
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1343
+
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1344
+
struct radeon_connector *radeon_connector = NULL;
1345
+
struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1346
+
1347
+
if (connector) {
1348
+
radeon_connector = to_radeon_connector(connector);
1349
+
radeon_dig_connector = radeon_connector->con_priv;
1350
+
}
1351
+
1352
+
switch (mode) {
1353
+
case DRM_MODE_DPMS_ON:
1354
+
/* some early dce3.2 boards have a bug in their transmitter control table */
1355
+
if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730))
1356
+
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1357
+
else
1358
+
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1359
+
if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1360
+
if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1361
+
atombios_set_edp_panel_power(connector,
1362
+
ATOM_TRANSMITTER_ACTION_POWER_ON);
1363
+
radeon_dig_connector->edp_on = true;
1364
+
}
1365
+
if (ASIC_IS_DCE4(rdev))
1366
+
atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1367
+
radeon_dp_link_train(encoder, connector);
1368
+
if (ASIC_IS_DCE4(rdev))
1369
+
atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1370
+
}
1371
+
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1372
+
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1373
+
break;
1374
+
case DRM_MODE_DPMS_STANDBY:
1375
+
case DRM_MODE_DPMS_SUSPEND:
1376
+
case DRM_MODE_DPMS_OFF:
1377
+
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1378
+
if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1379
+
if (ASIC_IS_DCE4(rdev))
1380
+
atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1381
+
if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1382
+
atombios_set_edp_panel_power(connector,
1383
+
ATOM_TRANSMITTER_ACTION_POWER_OFF);
1384
+
radeon_dig_connector->edp_on = false;
1385
+
}
1386
+
}
1387
+
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1388
+
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1389
+
break;
1390
+
}
1391
+
}
1392
+
1393
+
static void
1394
+
radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1395
+
struct drm_encoder *ext_encoder,
1396
+
int mode)
1397
+
{
1398
+
struct drm_device *dev = encoder->dev;
1399
+
struct radeon_device *rdev = dev->dev_private;
1400
+
1401
+
switch (mode) {
1402
+
case DRM_MODE_DPMS_ON:
1403
+
default:
1404
+
if (ASIC_IS_DCE41(rdev)) {
1405
+
atombios_external_encoder_setup(encoder, ext_encoder,
1406
+
EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1407
+
atombios_external_encoder_setup(encoder, ext_encoder,
1408
+
EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1409
+
} else
1410
+
atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1411
+
break;
1412
+
case DRM_MODE_DPMS_STANDBY:
1413
+
case DRM_MODE_DPMS_SUSPEND:
1414
+
case DRM_MODE_DPMS_OFF:
1415
+
if (ASIC_IS_DCE41(rdev)) {
1416
+
atombios_external_encoder_setup(encoder, ext_encoder,
1417
+
EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1418
+
atombios_external_encoder_setup(encoder, ext_encoder,
1419
+
EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1420
+
} else
1421
+
atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1422
+
break;
1423
+
}
1424
+
}
1425
+
1426
+
static void
1427
+
radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1428
+
{
1429
+
struct drm_device *dev = encoder->dev;
1430
+
struct radeon_device *rdev = dev->dev_private;
1431
+
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1432
+
struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1433
+
1434
+
DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1435
+
radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1436
+
radeon_encoder->active_device);
1437
+
switch (radeon_encoder->encoder_id) {
1438
+
case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1439
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1440
+
case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1441
+
case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1442
+
case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1443
+
case ENCODER_OBJECT_ID_INTERNAL_DDI:
1444
+
case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1445
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1446
+
radeon_atom_encoder_dpms_avivo(encoder, mode);
1447
+
break;
1448
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1449
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1450
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1451
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1452
+
radeon_atom_encoder_dpms_dig(encoder, mode);
1453
+
break;
1454
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1455
+
if (ASIC_IS_DCE5(rdev)) {
1456
+
switch (mode) {
1457
+
case DRM_MODE_DPMS_ON:
1458
+
atombios_dvo_setup(encoder, ATOM_ENABLE);
1459
+
break;
1460
+
case DRM_MODE_DPMS_STANDBY:
1461
+
case DRM_MODE_DPMS_SUSPEND:
1462
+
case DRM_MODE_DPMS_OFF:
1463
+
atombios_dvo_setup(encoder, ATOM_DISABLE);
1464
+
break;
1465
+
}
1466
+
} else if (ASIC_IS_DCE3(rdev))
1467
+
radeon_atom_encoder_dpms_dig(encoder, mode);
1468
+
else
1469
+
radeon_atom_encoder_dpms_avivo(encoder, mode);
1470
+
break;
1471
+
case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1472
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1473
+
if (ASIC_IS_DCE5(rdev)) {
1474
+
switch (mode) {
1475
+
case DRM_MODE_DPMS_ON:
1476
+
atombios_dac_setup(encoder, ATOM_ENABLE);
1477
+
break;
1478
+
case DRM_MODE_DPMS_STANDBY:
1479
+
case DRM_MODE_DPMS_SUSPEND:
1480
+
case DRM_MODE_DPMS_OFF:
1481
+
atombios_dac_setup(encoder, ATOM_DISABLE);
1482
+
break;
1483
+
}
1484
+
} else
1485
+
radeon_atom_encoder_dpms_avivo(encoder, mode);
1486
+
break;
1487
+
default:
1488
+
return;
1489
+
}
1490
+
1491
+
if (ext_encoder)
1492
+
radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1493
+
1494
+
radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1495
+
1496
+
}
1497
+
1498
+
union crtc_source_param {
1499
+
SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1500
+
SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1501
+
};
1502
+
1503
+
static void
1504
+
atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1505
+
{
1506
+
struct drm_device *dev = encoder->dev;
1507
+
struct radeon_device *rdev = dev->dev_private;
1508
+
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1509
+
struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1510
+
union crtc_source_param args;
1511
+
int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1512
+
uint8_t frev, crev;
1513
+
struct radeon_encoder_atom_dig *dig;
1514
+
1515
+
memset(&args, 0, sizeof(args));
1516
+
1517
+
if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1518
+
return;
1519
+
1520
+
switch (frev) {
1521
+
case 1:
1522
+
switch (crev) {
1523
+
case 1:
1524
+
default:
1525
+
if (ASIC_IS_AVIVO(rdev))
1526
+
args.v1.ucCRTC = radeon_crtc->crtc_id;
1527
+
else {
1528
+
if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1529
+
args.v1.ucCRTC = radeon_crtc->crtc_id;
1530
+
} else {
1531
+
args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1532
+
}
1533
+
}
1534
+
switch (radeon_encoder->encoder_id) {
1535
+
case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1536
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1537
+
args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1538
+
break;
1539
+
case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1540
+
case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1541
+
if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1542
+
args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1543
+
else
1544
+
args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1545
+
break;
1546
+
case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1547
+
case ENCODER_OBJECT_ID_INTERNAL_DDI:
1548
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1549
+
args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1550
+
break;
1551
+
case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1552
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1553
+
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1554
+
args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1555
+
else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1556
+
args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1557
+
else
1558
+
args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1559
+
break;
1560
+
case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1561
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1562
+
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1563
+
args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1564
+
else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1565
+
args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1566
+
else
1567
+
args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1568
+
break;
1569
+
}
1570
+
break;
1571
+
case 2:
1572
+
args.v2.ucCRTC = radeon_crtc->crtc_id;
1573
+
if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1574
+
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1575
+
1576
+
if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1577
+
args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1578
+
else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1579
+
args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1580
+
else
1581
+
args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1582
+
} else
1583
+
args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1584
+
switch (radeon_encoder->encoder_id) {
1585
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1586
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1587
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1588
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1589
+
dig = radeon_encoder->enc_priv;
1590
+
switch (dig->dig_encoder) {
1591
+
case 0:
1592
+
args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1593
+
break;
1594
+
case 1:
1595
+
args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1596
+
break;
1597
+
case 2:
1598
+
args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1599
+
break;
1600
+
case 3:
1601
+
args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1602
+
break;
1603
+
case 4:
1604
+
args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1605
+
break;
1606
+
case 5:
1607
+
args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1608
+
break;
1609
+
}
1610
+
break;
1611
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1612
+
args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1613
+
break;
1614
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1615
+
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1616
+
args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1617
+
else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1618
+
args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1619
+
else
1620
+
args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1621
+
break;
1622
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1623
+
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1624
+
args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1625
+
else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1626
+
args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1627
+
else
1628
+
args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1629
+
break;
1630
+
}
1631
+
break;
1632
+
}
1633
+
break;
1634
+
default:
1635
+
DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1636
+
return;
1637
+
}
1638
+
1639
+
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1640
+
1641
+
/* update scratch regs with new routing */
1642
+
radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1643
+
}
1644
+
1645
+
static void
1646
+
atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1647
+
struct drm_display_mode *mode)
1648
+
{
1649
+
struct drm_device *dev = encoder->dev;
1650
+
struct radeon_device *rdev = dev->dev_private;
1651
+
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1652
+
struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1653
+
1654
+
/* Funky macbooks */
1655
+
if ((dev->pdev->device == 0x71C5) &&
1656
+
(dev->pdev->subsystem_vendor == 0x106b) &&
1657
+
(dev->pdev->subsystem_device == 0x0080)) {
1658
+
if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1659
+
uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1660
+
1661
+
lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1662
+
lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1663
+
1664
+
WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1665
+
}
1666
+
}
1667
+
1668
+
/* set scaler clears this on some chips */
1669
+
if (ASIC_IS_AVIVO(rdev) &&
1670
+
(!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1671
+
if (ASIC_IS_DCE4(rdev)) {
1672
+
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1673
+
WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1674
+
EVERGREEN_INTERLEAVE_EN);
1675
+
else
1676
+
WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1677
+
} else {
1678
+
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1679
+
WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1680
+
AVIVO_D1MODE_INTERLEAVE_EN);
1681
+
else
1682
+
WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1683
+
}
1684
+
}
1685
+
}
1686
+
1687
+
static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1688
+
{
1689
+
struct drm_device *dev = encoder->dev;
1690
+
struct radeon_device *rdev = dev->dev_private;
1691
+
struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1692
+
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1693
+
struct drm_encoder *test_encoder;
1694
+
struct radeon_encoder_atom_dig *dig;
1695
+
uint32_t dig_enc_in_use = 0;
1696
+
1697
+
/* DCE4/5 */
1698
+
if (ASIC_IS_DCE4(rdev)) {
1699
+
dig = radeon_encoder->enc_priv;
1700
+
if (ASIC_IS_DCE41(rdev)) {
1701
+
/* ontario follows DCE4 */
1702
+
if (rdev->family == CHIP_PALM) {
1703
+
if (dig->linkb)
1704
+
return 1;
1705
+
else
1706
+
return 0;
1707
+
} else
1708
+
/* llano follows DCE3.2 */
1709
+
return radeon_crtc->crtc_id;
1710
+
} else {
1711
+
switch (radeon_encoder->encoder_id) {
1712
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1713
+
if (dig->linkb)
1714
+
return 1;
1715
+
else
1716
+
return 0;
1717
+
break;
1718
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1719
+
if (dig->linkb)
1720
+
return 3;
1721
+
else
1722
+
return 2;
1723
+
break;
1724
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1725
+
if (dig->linkb)
1726
+
return 5;
1727
+
else
1728
+
return 4;
1729
+
break;
1730
+
}
1731
+
}
1732
+
}
1733
+
1734
+
/* on DCE32 and encoder can driver any block so just crtc id */
1735
+
if (ASIC_IS_DCE32(rdev)) {
1736
+
return radeon_crtc->crtc_id;
1737
+
}
1738
+
1739
+
/* on DCE3 - LVTMA can only be driven by DIGB */
1740
+
list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1741
+
struct radeon_encoder *radeon_test_encoder;
1742
+
1743
+
if (encoder == test_encoder)
1744
+
continue;
1745
+
1746
+
if (!radeon_encoder_is_digital(test_encoder))
1747
+
continue;
1748
+
1749
+
radeon_test_encoder = to_radeon_encoder(test_encoder);
1750
+
dig = radeon_test_encoder->enc_priv;
1751
+
1752
+
if (dig->dig_encoder >= 0)
1753
+
dig_enc_in_use |= (1 << dig->dig_encoder);
1754
+
}
1755
+
1756
+
if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1757
+
if (dig_enc_in_use & 0x2)
1758
+
DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1759
+
return 1;
1760
+
}
1761
+
if (!(dig_enc_in_use & 1))
1762
+
return 0;
1763
+
return 1;
1764
+
}
1765
+
1766
+
/* This only needs to be called once at startup */
1767
+
void
1768
+
radeon_atom_encoder_init(struct radeon_device *rdev)
1769
+
{
1770
+
struct drm_device *dev = rdev->ddev;
1771
+
struct drm_encoder *encoder;
1772
+
1773
+
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1774
+
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1775
+
struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1776
+
1777
+
switch (radeon_encoder->encoder_id) {
1778
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1779
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1780
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1781
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1782
+
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1783
+
break;
1784
+
default:
1785
+
break;
1786
+
}
1787
+
1788
+
if (ext_encoder && ASIC_IS_DCE41(rdev))
1789
+
atombios_external_encoder_setup(encoder, ext_encoder,
1790
+
EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1791
+
}
1792
+
}
1793
+
1794
+
static void
1795
+
radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1796
+
struct drm_display_mode *mode,
1797
+
struct drm_display_mode *adjusted_mode)
1798
+
{
1799
+
struct drm_device *dev = encoder->dev;
1800
+
struct radeon_device *rdev = dev->dev_private;
1801
+
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1802
+
struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1803
+
1804
+
radeon_encoder->pixel_clock = adjusted_mode->clock;
1805
+
1806
+
if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1807
+
if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1808
+
atombios_yuv_setup(encoder, true);
1809
+
else
1810
+
atombios_yuv_setup(encoder, false);
1811
+
}
1812
+
1813
+
switch (radeon_encoder->encoder_id) {
1814
+
case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1815
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1816
+
case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1817
+
case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1818
+
atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1819
+
break;
1820
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1821
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1822
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1823
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1824
+
if (ASIC_IS_DCE4(rdev)) {
1825
+
/* disable the transmitter */
1826
+
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1827
+
/* setup and enable the encoder */
1828
+
atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1829
+
1830
+
/* enable the transmitter */
1831
+
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1832
+
} else {
1833
+
/* disable the encoder and transmitter */
1834
+
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1835
+
atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1836
+
1837
+
/* setup and enable the encoder and transmitter */
1838
+
atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1839
+
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1840
+
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1841
+
}
1842
+
break;
1843
+
case ENCODER_OBJECT_ID_INTERNAL_DDI:
1844
+
case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1845
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1846
+
atombios_dvo_setup(encoder, ATOM_ENABLE);
1847
+
break;
1848
+
case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1849
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1850
+
case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1851
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1852
+
atombios_dac_setup(encoder, ATOM_ENABLE);
1853
+
if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1854
+
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1855
+
atombios_tv_setup(encoder, ATOM_ENABLE);
1856
+
else
1857
+
atombios_tv_setup(encoder, ATOM_DISABLE);
1858
+
}
1859
+
break;
1860
+
}
1861
+
1862
+
if (ext_encoder) {
1863
+
if (ASIC_IS_DCE41(rdev))
1864
+
atombios_external_encoder_setup(encoder, ext_encoder,
1865
+
EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1866
+
else
1867
+
atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1868
+
}
1869
+
1870
+
atombios_apply_encoder_quirks(encoder, adjusted_mode);
1871
+
1872
+
if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1873
+
r600_hdmi_enable(encoder);
1874
+
r600_hdmi_setmode(encoder, adjusted_mode);
1875
+
}
1876
+
}
1877
+
1878
+
static bool
1879
+
atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1880
+
{
1881
+
struct drm_device *dev = encoder->dev;
1882
+
struct radeon_device *rdev = dev->dev_private;
1883
+
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1884
+
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1885
+
1886
+
if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1887
+
ATOM_DEVICE_CV_SUPPORT |
1888
+
ATOM_DEVICE_CRT_SUPPORT)) {
1889
+
DAC_LOAD_DETECTION_PS_ALLOCATION args;
1890
+
int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1891
+
uint8_t frev, crev;
1892
+
1893
+
memset(&args, 0, sizeof(args));
1894
+
1895
+
if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1896
+
return false;
1897
+
1898
+
args.sDacload.ucMisc = 0;
1899
+
1900
+
if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1901
+
(radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1902
+
args.sDacload.ucDacType = ATOM_DAC_A;
1903
+
else
1904
+
args.sDacload.ucDacType = ATOM_DAC_B;
1905
+
1906
+
if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1907
+
args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1908
+
else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1909
+
args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1910
+
else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1911
+
args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1912
+
if (crev >= 3)
1913
+
args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1914
+
} else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1915
+
args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1916
+
if (crev >= 3)
1917
+
args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1918
+
}
1919
+
1920
+
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1921
+
1922
+
return true;
1923
+
} else
1924
+
return false;
1925
+
}
1926
+
1927
+
static enum drm_connector_status
1928
+
radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1929
+
{
1930
+
struct drm_device *dev = encoder->dev;
1931
+
struct radeon_device *rdev = dev->dev_private;
1932
+
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1933
+
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1934
+
uint32_t bios_0_scratch;
1935
+
1936
+
if (!atombios_dac_load_detect(encoder, connector)) {
1937
+
DRM_DEBUG_KMS("detect returned false \n");
1938
+
return connector_status_unknown;
1939
+
}
1940
+
1941
+
if (rdev->family >= CHIP_R600)
1942
+
bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1943
+
else
1944
+
bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1945
+
1946
+
DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1947
+
if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1948
+
if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1949
+
return connector_status_connected;
1950
+
}
1951
+
if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1952
+
if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1953
+
return connector_status_connected;
1954
+
}
1955
+
if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1956
+
if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1957
+
return connector_status_connected;
1958
+
}
1959
+
if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1960
+
if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1961
+
return connector_status_connected; /* CTV */
1962
+
else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1963
+
return connector_status_connected; /* STV */
1964
+
}
1965
+
return connector_status_disconnected;
1966
+
}
1967
+
1968
+
static enum drm_connector_status
1969
+
radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1970
+
{
1971
+
struct drm_device *dev = encoder->dev;
1972
+
struct radeon_device *rdev = dev->dev_private;
1973
+
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1974
+
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1975
+
struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1976
+
u32 bios_0_scratch;
1977
+
1978
+
if (!ASIC_IS_DCE4(rdev))
1979
+
return connector_status_unknown;
1980
+
1981
+
if (!ext_encoder)
1982
+
return connector_status_unknown;
1983
+
1984
+
if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
1985
+
return connector_status_unknown;
1986
+
1987
+
/* load detect on the dp bridge */
1988
+
atombios_external_encoder_setup(encoder, ext_encoder,
1989
+
EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
1990
+
1991
+
bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1992
+
1993
+
DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1994
+
if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1995
+
if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1996
+
return connector_status_connected;
1997
+
}
1998
+
if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1999
+
if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2000
+
return connector_status_connected;
2001
+
}
2002
+
if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2003
+
if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2004
+
return connector_status_connected;
2005
+
}
2006
+
if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2007
+
if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2008
+
return connector_status_connected; /* CTV */
2009
+
else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2010
+
return connector_status_connected; /* STV */
2011
+
}
2012
+
return connector_status_disconnected;
2013
+
}
2014
+
2015
+
void
2016
+
radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2017
+
{
2018
+
struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2019
+
2020
+
if (ext_encoder)
2021
+
/* ddc_setup on the dp bridge */
2022
+
atombios_external_encoder_setup(encoder, ext_encoder,
2023
+
EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2024
+
2025
+
}
2026
+
2027
+
static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2028
+
{
2029
+
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2030
+
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2031
+
2032
+
if ((radeon_encoder->active_device &
2033
+
(ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2034
+
(radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2035
+
ENCODER_OBJECT_ID_NONE)) {
2036
+
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2037
+
if (dig)
2038
+
dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2039
+
}
2040
+
2041
+
radeon_atom_output_lock(encoder, true);
2042
+
radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2043
+
2044
+
if (connector) {
2045
+
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2046
+
2047
+
/* select the clock/data port if it uses a router */
2048
+
if (radeon_connector->router.cd_valid)
2049
+
radeon_router_select_cd_port(radeon_connector);
2050
+
2051
+
/* turn eDP panel on for mode set */
2052
+
if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2053
+
atombios_set_edp_panel_power(connector,
2054
+
ATOM_TRANSMITTER_ACTION_POWER_ON);
2055
+
}
2056
+
2057
+
/* this is needed for the pll/ss setup to work correctly in some cases */
2058
+
atombios_set_encoder_crtc_source(encoder);
2059
+
}
2060
+
2061
+
static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2062
+
{
2063
+
radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2064
+
radeon_atom_output_lock(encoder, false);
2065
+
}
2066
+
2067
+
static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2068
+
{
2069
+
struct drm_device *dev = encoder->dev;
2070
+
struct radeon_device *rdev = dev->dev_private;
2071
+
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2072
+
struct radeon_encoder_atom_dig *dig;
2073
+
2074
+
/* check for pre-DCE3 cards with shared encoders;
2075
+
* can't really use the links individually, so don't disable
2076
+
* the encoder if it's in use by another connector
2077
+
*/
2078
+
if (!ASIC_IS_DCE3(rdev)) {
2079
+
struct drm_encoder *other_encoder;
2080
+
struct radeon_encoder *other_radeon_encoder;
2081
+
2082
+
list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2083
+
other_radeon_encoder = to_radeon_encoder(other_encoder);
2084
+
if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2085
+
drm_helper_encoder_in_use(other_encoder))
2086
+
goto disable_done;
2087
+
}
2088
+
}
2089
+
2090
+
radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2091
+
2092
+
switch (radeon_encoder->encoder_id) {
2093
+
case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2094
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2095
+
case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2096
+
case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2097
+
atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2098
+
break;
2099
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2100
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2101
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2102
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2103
+
if (ASIC_IS_DCE4(rdev))
2104
+
/* disable the transmitter */
2105
+
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2106
+
else {
2107
+
/* disable the encoder and transmitter */
2108
+
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2109
+
atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
2110
+
}
2111
+
break;
2112
+
case ENCODER_OBJECT_ID_INTERNAL_DDI:
2113
+
case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2114
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2115
+
atombios_dvo_setup(encoder, ATOM_DISABLE);
2116
+
break;
2117
+
case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2118
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2119
+
case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2120
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2121
+
atombios_dac_setup(encoder, ATOM_DISABLE);
2122
+
if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2123
+
atombios_tv_setup(encoder, ATOM_DISABLE);
2124
+
break;
2125
+
}
2126
+
2127
+
disable_done:
2128
+
if (radeon_encoder_is_digital(encoder)) {
2129
+
if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2130
+
r600_hdmi_disable(encoder);
2131
+
dig = radeon_encoder->enc_priv;
2132
+
dig->dig_encoder = -1;
2133
+
}
2134
+
radeon_encoder->active_device = 0;
2135
+
}
2136
+
2137
+
/* these are handled by the primary encoders */
2138
+
static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2139
+
{
2140
+
2141
+
}
2142
+
2143
+
static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2144
+
{
2145
+
2146
+
}
2147
+
2148
+
static void
2149
+
radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2150
+
struct drm_display_mode *mode,
2151
+
struct drm_display_mode *adjusted_mode)
2152
+
{
2153
+
2154
+
}
2155
+
2156
+
static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2157
+
{
2158
+
2159
+
}
2160
+
2161
+
static void
2162
+
radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2163
+
{
2164
+
2165
+
}
2166
+
2167
+
static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2168
+
struct drm_display_mode *mode,
2169
+
struct drm_display_mode *adjusted_mode)
2170
+
{
2171
+
return true;
2172
+
}
2173
+
2174
+
static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2175
+
.dpms = radeon_atom_ext_dpms,
2176
+
.mode_fixup = radeon_atom_ext_mode_fixup,
2177
+
.prepare = radeon_atom_ext_prepare,
2178
+
.mode_set = radeon_atom_ext_mode_set,
2179
+
.commit = radeon_atom_ext_commit,
2180
+
.disable = radeon_atom_ext_disable,
2181
+
/* no detect for TMDS/LVDS yet */
2182
+
};
2183
+
2184
+
static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2185
+
.dpms = radeon_atom_encoder_dpms,
2186
+
.mode_fixup = radeon_atom_mode_fixup,
2187
+
.prepare = radeon_atom_encoder_prepare,
2188
+
.mode_set = radeon_atom_encoder_mode_set,
2189
+
.commit = radeon_atom_encoder_commit,
2190
+
.disable = radeon_atom_encoder_disable,
2191
+
.detect = radeon_atom_dig_detect,
2192
+
};
2193
+
2194
+
static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2195
+
.dpms = radeon_atom_encoder_dpms,
2196
+
.mode_fixup = radeon_atom_mode_fixup,
2197
+
.prepare = radeon_atom_encoder_prepare,
2198
+
.mode_set = radeon_atom_encoder_mode_set,
2199
+
.commit = radeon_atom_encoder_commit,
2200
+
.detect = radeon_atom_dac_detect,
2201
+
};
2202
+
2203
+
void radeon_enc_destroy(struct drm_encoder *encoder)
2204
+
{
2205
+
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2206
+
kfree(radeon_encoder->enc_priv);
2207
+
drm_encoder_cleanup(encoder);
2208
+
kfree(radeon_encoder);
2209
+
}
2210
+
2211
+
static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2212
+
.destroy = radeon_enc_destroy,
2213
+
};
2214
+
2215
+
struct radeon_encoder_atom_dac *
2216
+
radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2217
+
{
2218
+
struct drm_device *dev = radeon_encoder->base.dev;
2219
+
struct radeon_device *rdev = dev->dev_private;
2220
+
struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2221
+
2222
+
if (!dac)
2223
+
return NULL;
2224
+
2225
+
dac->tv_std = radeon_atombios_get_tv_info(rdev);
2226
+
return dac;
2227
+
}
2228
+
2229
+
struct radeon_encoder_atom_dig *
2230
+
radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2231
+
{
2232
+
int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2233
+
struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2234
+
2235
+
if (!dig)
2236
+
return NULL;
2237
+
2238
+
/* coherent mode by default */
2239
+
dig->coherent_mode = true;
2240
+
dig->dig_encoder = -1;
2241
+
2242
+
if (encoder_enum == 2)
2243
+
dig->linkb = true;
2244
+
else
2245
+
dig->linkb = false;
2246
+
2247
+
return dig;
2248
+
}
2249
+
2250
+
void
2251
+
radeon_add_atom_encoder(struct drm_device *dev,
2252
+
uint32_t encoder_enum,
2253
+
uint32_t supported_device,
2254
+
u16 caps)
2255
+
{
2256
+
struct radeon_device *rdev = dev->dev_private;
2257
+
struct drm_encoder *encoder;
2258
+
struct radeon_encoder *radeon_encoder;
2259
+
2260
+
/* see if we already added it */
2261
+
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2262
+
radeon_encoder = to_radeon_encoder(encoder);
2263
+
if (radeon_encoder->encoder_enum == encoder_enum) {
2264
+
radeon_encoder->devices |= supported_device;
2265
+
return;
2266
+
}
2267
+
2268
+
}
2269
+
2270
+
/* add a new one */
2271
+
radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2272
+
if (!radeon_encoder)
2273
+
return;
2274
+
2275
+
encoder = &radeon_encoder->base;
2276
+
switch (rdev->num_crtc) {
2277
+
case 1:
2278
+
encoder->possible_crtcs = 0x1;
2279
+
break;
2280
+
case 2:
2281
+
default:
2282
+
encoder->possible_crtcs = 0x3;
2283
+
break;
2284
+
case 4:
2285
+
encoder->possible_crtcs = 0xf;
2286
+
break;
2287
+
case 6:
2288
+
encoder->possible_crtcs = 0x3f;
2289
+
break;
2290
+
}
2291
+
2292
+
radeon_encoder->enc_priv = NULL;
2293
+
2294
+
radeon_encoder->encoder_enum = encoder_enum;
2295
+
radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2296
+
radeon_encoder->devices = supported_device;
2297
+
radeon_encoder->rmx_type = RMX_OFF;
2298
+
radeon_encoder->underscan_type = UNDERSCAN_OFF;
2299
+
radeon_encoder->is_ext_encoder = false;
2300
+
radeon_encoder->caps = caps;
2301
+
2302
+
switch (radeon_encoder->encoder_id) {
2303
+
case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2304
+
case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2305
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2306
+
case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2307
+
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2308
+
radeon_encoder->rmx_type = RMX_FULL;
2309
+
drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2310
+
radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2311
+
} else {
2312
+
drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2313
+
radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2314
+
}
2315
+
drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2316
+
break;
2317
+
case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2318
+
drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2319
+
radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2320
+
drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2321
+
break;
2322
+
case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2323
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2324
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2325
+
drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2326
+
radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2327
+
drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2328
+
break;
2329
+
case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2330
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2331
+
case ENCODER_OBJECT_ID_INTERNAL_DDI:
2332
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2333
+
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2334
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2335
+
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2336
+
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2337
+
radeon_encoder->rmx_type = RMX_FULL;
2338
+
drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2339
+
radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2340
+
} else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2341
+
drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2342
+
radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2343
+
} else {
2344
+
drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2345
+
radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2346
+
}
2347
+
drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2348
+
break;
2349
+
case ENCODER_OBJECT_ID_SI170B:
2350
+
case ENCODER_OBJECT_ID_CH7303:
2351
+
case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2352
+
case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2353
+
case ENCODER_OBJECT_ID_TITFP513:
2354
+
case ENCODER_OBJECT_ID_VT1623:
2355
+
case ENCODER_OBJECT_ID_HDMI_SI1930:
2356
+
case ENCODER_OBJECT_ID_TRAVIS:
2357
+
case ENCODER_OBJECT_ID_NUTMEG:
2358
+
/* these are handled by the primary encoders */
2359
+
radeon_encoder->is_ext_encoder = true;
2360
+
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2361
+
drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2362
+
else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2363
+
drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2364
+
else
2365
+
drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2366
+
drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2367
+
break;
2368
+
}
2369
+
}
+8
-10
drivers/gpu/drm/radeon/evergreen.c
+8
-10
drivers/gpu/drm/radeon/evergreen.c
···
353
353
default:
354
354
break;
355
355
}
356
+
radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
356
357
}
357
358
if (rdev->irq.installed)
358
359
evergreen_irq_set(rdev);
···
894
893
u32 tmp;
895
894
int r;
896
895
897
-
if (rdev->gart.table.vram.robj == NULL) {
896
+
if (rdev->gart.robj == NULL) {
898
897
dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
899
898
return -EINVAL;
900
899
}
···
946
945
void evergreen_pcie_gart_disable(struct radeon_device *rdev)
947
946
{
948
947
u32 tmp;
949
-
int r;
950
948
951
949
/* Disable all tables */
952
950
WREG32(VM_CONTEXT0_CNTL, 0);
···
965
965
WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
966
966
WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
967
967
WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
968
-
if (rdev->gart.table.vram.robj) {
969
-
r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
970
-
if (likely(r == 0)) {
971
-
radeon_bo_kunmap(rdev->gart.table.vram.robj);
972
-
radeon_bo_unpin(rdev->gart.table.vram.robj);
973
-
radeon_bo_unreserve(rdev->gart.table.vram.robj);
974
-
}
975
-
}
968
+
radeon_gart_table_vram_unpin(rdev);
976
969
}
977
970
978
971
void evergreen_pcie_gart_fini(struct radeon_device *rdev)
···
3024
3031
}
3025
3032
}
3026
3033
3034
+
r = r600_vram_scratch_init(rdev);
3035
+
if (r)
3036
+
return r;
3037
+
3027
3038
evergreen_mc_program(rdev);
3028
3039
if (rdev->flags & RADEON_IS_AGP) {
3029
3040
evergreen_agp_enable(rdev);
···
3232
3235
radeon_ib_pool_fini(rdev);
3233
3236
radeon_irq_kms_fini(rdev);
3234
3237
evergreen_pcie_gart_fini(rdev);
3238
+
r600_vram_scratch_fini(rdev);
3235
3239
radeon_gem_fini(rdev);
3236
3240
radeon_fence_driver_fini(rdev);
3237
3241
radeon_agp_fini(rdev);
+17
-3
drivers/gpu/drm/radeon/evergreen_blit_kms.c
+17
-3
drivers/gpu/drm/radeon/evergreen_blit_kms.c
···
94
94
else
95
95
cp_coher_size = ((size + 255) >> 8);
96
96
97
+
if (rdev->family >= CHIP_CAYMAN) {
98
+
/* CP_COHER_CNTL2 has to be set manually when submitting a surface_sync
99
+
* to the RB directly. For IBs, the CP programs this as part of the
100
+
* surface_sync packet.
101
+
*/
102
+
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
103
+
radeon_ring_write(rdev, (0x85e8 - PACKET3_SET_CONFIG_REG_START) >> 2);
104
+
radeon_ring_write(rdev, 0); /* CP_COHER_CNTL2 */
105
+
}
97
106
radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
98
107
radeon_ring_write(rdev, sync_type);
99
108
radeon_ring_write(rdev, cp_coher_size);
···
183
174
static void
184
175
set_tex_resource(struct radeon_device *rdev,
185
176
int format, int w, int h, int pitch,
186
-
u64 gpu_addr)
177
+
u64 gpu_addr, u32 size)
187
178
{
188
179
u32 sq_tex_resource_word0, sq_tex_resource_word1;
189
180
u32 sq_tex_resource_word4, sq_tex_resource_word7;
···
204
195
205
196
sq_tex_resource_word7 = format |
206
197
S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_TEXTURE);
198
+
199
+
cp_set_surface_sync(rdev,
200
+
PACKET3_TC_ACTION_ENA, size, gpu_addr);
207
201
208
202
radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8));
209
203
radeon_ring_write(rdev, 0);
···
625
613
rdev->r600_blit.primitives.set_default_state = set_default_state;
626
614
627
615
rdev->r600_blit.ring_size_common = 55; /* shaders + def state */
628
-
rdev->r600_blit.ring_size_common += 10; /* fence emit for VB IB */
616
+
rdev->r600_blit.ring_size_common += 16; /* fence emit for VB IB */
629
617
rdev->r600_blit.ring_size_common += 5; /* done copy */
630
-
rdev->r600_blit.ring_size_common += 10; /* fence emit for done copy */
618
+
rdev->r600_blit.ring_size_common += 16; /* fence emit for done copy */
631
619
632
620
rdev->r600_blit.ring_size_per_loop = 74;
621
+
if (rdev->family >= CHIP_CAYMAN)
622
+
rdev->r600_blit.ring_size_per_loop += 9; /* additional DWs for surface sync */
633
623
634
624
rdev->r600_blit.max_dim = 16384;
635
625
+12
-13
drivers/gpu/drm/radeon/ni.c
+12
-13
drivers/gpu/drm/radeon/ni.c
···
262
262
WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
263
263
264
264
/* wait for training to complete */
265
-
while (!(RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD))
266
-
udelay(10);
265
+
for (i = 0; i < rdev->usec_timeout; i++) {
266
+
if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
267
+
break;
268
+
udelay(1);
269
+
}
267
270
268
271
if (running)
269
272
WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
···
936
933
{
937
934
int r;
938
935
939
-
if (rdev->gart.table.vram.robj == NULL) {
936
+
if (rdev->gart.robj == NULL) {
940
937
dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
941
938
return -EINVAL;
942
939
}
···
981
978
982
979
void cayman_pcie_gart_disable(struct radeon_device *rdev)
983
980
{
984
-
int r;
985
-
986
981
/* Disable all tables */
987
982
WREG32(VM_CONTEXT0_CNTL, 0);
988
983
WREG32(VM_CONTEXT1_CNTL, 0);
···
996
995
WREG32(VM_L2_CNTL2, 0);
997
996
WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
998
997
L2_CACHE_BIGK_FRAGMENT_SIZE(6));
999
-
if (rdev->gart.table.vram.robj) {
1000
-
r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
1001
-
if (likely(r == 0)) {
1002
-
radeon_bo_kunmap(rdev->gart.table.vram.robj);
1003
-
radeon_bo_unpin(rdev->gart.table.vram.robj);
1004
-
radeon_bo_unreserve(rdev->gart.table.vram.robj);
1005
-
}
1006
-
}
998
+
radeon_gart_table_vram_unpin(rdev);
1007
999
}
1008
1000
1009
1001
void cayman_pcie_gart_fini(struct radeon_device *rdev)
···
1356
1362
return r;
1357
1363
}
1358
1364
1365
+
r = r600_vram_scratch_init(rdev);
1366
+
if (r)
1367
+
return r;
1368
+
1359
1369
evergreen_mc_program(rdev);
1360
1370
r = cayman_pcie_gart_enable(rdev);
1361
1371
if (r)
···
1555
1557
radeon_ib_pool_fini(rdev);
1556
1558
radeon_irq_kms_fini(rdev);
1557
1559
cayman_pcie_gart_fini(rdev);
1560
+
r600_vram_scratch_fini(rdev);
1558
1561
radeon_gem_fini(rdev);
1559
1562
radeon_fence_driver_fini(rdev);
1560
1563
radeon_bo_fini(rdev);
+5
-2
drivers/gpu/drm/radeon/r100.c
+5
-2
drivers/gpu/drm/radeon/r100.c
···
537
537
default:
538
538
break;
539
539
}
540
+
radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
540
541
}
541
542
if (rdev->irq.installed)
542
543
r100_irq_set(rdev);
···
578
577
{
579
578
int r;
580
579
581
-
if (rdev->gart.table.ram.ptr) {
580
+
if (rdev->gart.ptr) {
582
581
WARN(1, "R100 PCI GART already initialized\n");
583
582
return 0;
584
583
}
···
637
636
638
637
int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
639
638
{
639
+
u32 *gtt = rdev->gart.ptr;
640
+
640
641
if (i < 0 || i > rdev->gart.num_gpu_pages) {
641
642
return -EINVAL;
642
643
}
643
-
rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
644
+
gtt[i] = cpu_to_le32(lower_32_bits(addr));
644
645
return 0;
645
646
}
646
647
+4
-12
drivers/gpu/drm/radeon/r300.c
+4
-12
drivers/gpu/drm/radeon/r300.c
···
74
74
75
75
int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
76
76
{
77
-
void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
77
+
void __iomem *ptr = rdev->gart.ptr;
78
78
79
79
if (i < 0 || i > rdev->gart.num_gpu_pages) {
80
80
return -EINVAL;
···
93
93
{
94
94
int r;
95
95
96
-
if (rdev->gart.table.vram.robj) {
96
+
if (rdev->gart.robj) {
97
97
WARN(1, "RV370 PCIE GART already initialized\n");
98
98
return 0;
99
99
}
···
116
116
uint32_t tmp;
117
117
int r;
118
118
119
-
if (rdev->gart.table.vram.robj == NULL) {
119
+
if (rdev->gart.robj == NULL) {
120
120
dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
121
121
return -EINVAL;
122
122
}
···
154
154
void rv370_pcie_gart_disable(struct radeon_device *rdev)
155
155
{
156
156
u32 tmp;
157
-
int r;
158
157
159
158
WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0);
160
159
WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0);
···
162
163
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
163
164
tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
164
165
WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
165
-
if (rdev->gart.table.vram.robj) {
166
-
r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
167
-
if (likely(r == 0)) {
168
-
radeon_bo_kunmap(rdev->gart.table.vram.robj);
169
-
radeon_bo_unpin(rdev->gart.table.vram.robj);
170
-
radeon_bo_unreserve(rdev->gart.table.vram.robj);
171
-
}
172
-
}
166
+
radeon_gart_table_vram_unpin(rdev);
173
167
}
174
168
175
169
void rv370_pcie_gart_fini(struct radeon_device *rdev)
+83
-23
drivers/gpu/drm/radeon/r600.c
+83
-23
drivers/gpu/drm/radeon/r600.c
···
763
763
struct drm_device *dev = rdev->ddev;
764
764
struct drm_connector *connector;
765
765
766
-
if (ASIC_IS_DCE3(rdev)) {
767
-
u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
768
-
if (ASIC_IS_DCE32(rdev))
769
-
tmp |= DC_HPDx_EN;
766
+
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
767
+
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
770
768
771
-
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
772
-
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
769
+
if (ASIC_IS_DCE3(rdev)) {
770
+
u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
771
+
if (ASIC_IS_DCE32(rdev))
772
+
tmp |= DC_HPDx_EN;
773
+
773
774
switch (radeon_connector->hpd.hpd) {
774
775
case RADEON_HPD_1:
775
776
WREG32(DC_HPD1_CONTROL, tmp);
···
800
799
default:
801
800
break;
802
801
}
803
-
}
804
-
} else {
805
-
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
806
-
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
802
+
} else {
807
803
switch (radeon_connector->hpd.hpd) {
808
804
case RADEON_HPD_1:
809
805
WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
···
818
820
break;
819
821
}
820
822
}
823
+
radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
821
824
}
822
825
if (rdev->irq.installed)
823
826
r600_irq_set(rdev);
···
896
897
/* flush hdp cache so updates hit vram */
897
898
if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
898
899
!(rdev->flags & RADEON_IS_AGP)) {
899
-
void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
900
+
void __iomem *ptr = (void *)rdev->gart.ptr;
900
901
u32 tmp;
901
902
902
903
/* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
···
931
932
{
932
933
int r;
933
934
934
-
if (rdev->gart.table.vram.robj) {
935
+
if (rdev->gart.robj) {
935
936
WARN(1, "R600 PCIE GART already initialized\n");
936
937
return 0;
937
938
}
···
948
949
u32 tmp;
949
950
int r, i;
950
951
951
-
if (rdev->gart.table.vram.robj == NULL) {
952
+
if (rdev->gart.robj == NULL) {
952
953
dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
953
954
return -EINVAL;
954
955
}
···
1003
1004
void r600_pcie_gart_disable(struct radeon_device *rdev)
1004
1005
{
1005
1006
u32 tmp;
1006
-
int i, r;
1007
+
int i;
1007
1008
1008
1009
/* Disable all tables */
1009
1010
for (i = 0; i < 7; i++)
···
1030
1031
WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1031
1032
WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1032
1033
WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1033
-
if (rdev->gart.table.vram.robj) {
1034
-
r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
1035
-
if (likely(r == 0)) {
1036
-
radeon_bo_kunmap(rdev->gart.table.vram.robj);
1037
-
radeon_bo_unpin(rdev->gart.table.vram.robj);
1038
-
radeon_bo_unreserve(rdev->gart.table.vram.robj);
1039
-
}
1040
-
}
1034
+
radeon_gart_table_vram_unpin(rdev);
1041
1035
}
1042
1036
1043
1037
void r600_pcie_gart_fini(struct radeon_device *rdev)
···
1130
1138
WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1131
1139
WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1132
1140
}
1133
-
WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1141
+
WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1134
1142
tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1135
1143
tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1136
1144
WREG32(MC_VM_FB_LOCATION, tmp);
···
1267
1275
}
1268
1276
radeon_update_bandwidth_info(rdev);
1269
1277
return 0;
1278
+
}
1279
+
1280
+
int r600_vram_scratch_init(struct radeon_device *rdev)
1281
+
{
1282
+
int r;
1283
+
1284
+
if (rdev->vram_scratch.robj == NULL) {
1285
+
r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1286
+
PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1287
+
&rdev->vram_scratch.robj);
1288
+
if (r) {
1289
+
return r;
1290
+
}
1291
+
}
1292
+
1293
+
r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1294
+
if (unlikely(r != 0))
1295
+
return r;
1296
+
r = radeon_bo_pin(rdev->vram_scratch.robj,
1297
+
RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1298
+
if (r) {
1299
+
radeon_bo_unreserve(rdev->vram_scratch.robj);
1300
+
return r;
1301
+
}
1302
+
r = radeon_bo_kmap(rdev->vram_scratch.robj,
1303
+
(void **)&rdev->vram_scratch.ptr);
1304
+
if (r)
1305
+
radeon_bo_unpin(rdev->vram_scratch.robj);
1306
+
radeon_bo_unreserve(rdev->vram_scratch.robj);
1307
+
1308
+
return r;
1309
+
}
1310
+
1311
+
void r600_vram_scratch_fini(struct radeon_device *rdev)
1312
+
{
1313
+
int r;
1314
+
1315
+
if (rdev->vram_scratch.robj == NULL) {
1316
+
return;
1317
+
}
1318
+
r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1319
+
if (likely(r == 0)) {
1320
+
radeon_bo_kunmap(rdev->vram_scratch.robj);
1321
+
radeon_bo_unpin(rdev->vram_scratch.robj);
1322
+
radeon_bo_unreserve(rdev->vram_scratch.robj);
1323
+
}
1324
+
radeon_bo_unref(&rdev->vram_scratch.robj);
1270
1325
}
1271
1326
1272
1327
/* We doesn't check that the GPU really needs a reset we simply do the
···
2371
2332
if (rdev->wb.use_event) {
2372
2333
u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET +
2373
2334
(u64)(rdev->fence_drv.scratch_reg - rdev->scratch.reg_base);
2335
+
/* flush read cache over gart */
2336
+
radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
2337
+
radeon_ring_write(rdev, PACKET3_TC_ACTION_ENA |
2338
+
PACKET3_VC_ACTION_ENA |
2339
+
PACKET3_SH_ACTION_ENA);
2340
+
radeon_ring_write(rdev, 0xFFFFFFFF);
2341
+
radeon_ring_write(rdev, 0);
2342
+
radeon_ring_write(rdev, 10); /* poll interval */
2374
2343
/* EVENT_WRITE_EOP - flush caches, send int */
2375
2344
radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2376
2345
radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
···
2387
2340
radeon_ring_write(rdev, fence->seq);
2388
2341
radeon_ring_write(rdev, 0);
2389
2342
} else {
2343
+
/* flush read cache over gart */
2344
+
radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
2345
+
radeon_ring_write(rdev, PACKET3_TC_ACTION_ENA |
2346
+
PACKET3_VC_ACTION_ENA |
2347
+
PACKET3_SH_ACTION_ENA);
2348
+
radeon_ring_write(rdev, 0xFFFFFFFF);
2349
+
radeon_ring_write(rdev, 0);
2350
+
radeon_ring_write(rdev, 10); /* poll interval */
2390
2351
radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2391
2352
radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2392
2353
/* wait for 3D idle clean */
···
2475
2420
return r;
2476
2421
}
2477
2422
}
2423
+
2424
+
r = r600_vram_scratch_init(rdev);
2425
+
if (r)
2426
+
return r;
2478
2427
2479
2428
r600_mc_program(rdev);
2480
2429
if (rdev->flags & RADEON_IS_AGP) {
···
2700
2641
radeon_ib_pool_fini(rdev);
2701
2642
radeon_irq_kms_fini(rdev);
2702
2643
r600_pcie_gart_fini(rdev);
2644
+
r600_vram_scratch_fini(rdev);
2703
2645
radeon_agp_fini(rdev);
2704
2646
radeon_gem_fini(rdev);
2705
2647
radeon_fence_driver_fini(rdev);
+7
-7
drivers/gpu/drm/radeon/r600_blit_kms.c
+7
-7
drivers/gpu/drm/radeon/r600_blit_kms.c
···
201
201
static void
202
202
set_tex_resource(struct radeon_device *rdev,
203
203
int format, int w, int h, int pitch,
204
-
u64 gpu_addr)
204
+
u64 gpu_addr, u32 size)
205
205
{
206
206
uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
207
207
···
221
221
S_038010_DST_SEL_Y(SQ_SEL_Y) |
222
222
S_038010_DST_SEL_Z(SQ_SEL_Z) |
223
223
S_038010_DST_SEL_W(SQ_SEL_W);
224
+
225
+
cp_set_surface_sync(rdev,
226
+
PACKET3_TC_ACTION_ENA, size, gpu_addr);
224
227
225
228
radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
226
229
radeon_ring_write(rdev, 0);
···
503
500
rdev->r600_blit.primitives.set_default_state = set_default_state;
504
501
505
502
rdev->r600_blit.ring_size_common = 40; /* shaders + def state */
506
-
rdev->r600_blit.ring_size_common += 10; /* fence emit for VB IB */
503
+
rdev->r600_blit.ring_size_common += 16; /* fence emit for VB IB */
507
504
rdev->r600_blit.ring_size_common += 5; /* done copy */
508
-
rdev->r600_blit.ring_size_common += 10; /* fence emit for done copy */
505
+
rdev->r600_blit.ring_size_common += 16; /* fence emit for done copy */
509
506
510
507
rdev->r600_blit.ring_size_per_loop = 76;
511
508
/* set_render_target emits 2 extra dwords on rv6xx */
···
763
760
vb[11] = i2f(h);
764
761
765
762
rdev->r600_blit.primitives.set_tex_resource(rdev, FMT_8_8_8_8,
766
-
w, h, w, src_gpu_addr);
767
-
rdev->r600_blit.primitives.cp_set_surface_sync(rdev,
768
-
PACKET3_TC_ACTION_ENA,
769
-
size_in_bytes, src_gpu_addr);
763
+
w, h, w, src_gpu_addr, size_in_bytes);
770
764
rdev->r600_blit.primitives.set_render_target(rdev, COLOR_8_8_8_8,
771
765
w, h, dst_gpu_addr);
772
766
rdev->r600_blit.primitives.set_scissors(rdev, 0, 0, w, h);
+27
-30
drivers/gpu/drm/radeon/radeon.h
+27
-30
drivers/gpu/drm/radeon/radeon.h
···
93
93
extern int radeon_disp_priority;
94
94
extern int radeon_hw_i2c;
95
95
extern int radeon_pcie_gen2;
96
+
extern int radeon_msi;
96
97
97
98
/*
98
99
* Copy from radeon_drv.h so we don't have to include both and have conflicting
···
307
306
*/
308
307
struct radeon_mc;
309
308
310
-
struct radeon_gart_table_ram {
311
-
volatile uint32_t *ptr;
312
-
};
313
-
314
-
struct radeon_gart_table_vram {
315
-
struct radeon_bo *robj;
316
-
volatile uint32_t *ptr;
317
-
};
318
-
319
-
union radeon_gart_table {
320
-
struct radeon_gart_table_ram ram;
321
-
struct radeon_gart_table_vram vram;
322
-
};
323
-
324
309
#define RADEON_GPU_PAGE_SIZE 4096
325
310
#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
326
311
#define RADEON_GPU_PAGE_SHIFT 12
327
312
328
313
struct radeon_gart {
329
314
dma_addr_t table_addr;
315
+
struct radeon_bo *robj;
316
+
void *ptr;
330
317
unsigned num_gpu_pages;
331
318
unsigned num_cpu_pages;
332
319
unsigned table_size;
333
-
union radeon_gart_table table;
334
320
struct page **pages;
335
321
dma_addr_t *pages_addr;
336
322
bool *ttm_alloced;
···
328
340
void radeon_gart_table_ram_free(struct radeon_device *rdev);
329
341
int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
330
342
void radeon_gart_table_vram_free(struct radeon_device *rdev);
343
+
int radeon_gart_table_vram_pin(struct radeon_device *rdev);
344
+
void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
331
345
int radeon_gart_init(struct radeon_device *rdev);
332
346
void radeon_gart_fini(struct radeon_device *rdev);
333
347
void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
···
337
347
int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
338
348
int pages, struct page **pagelist,
339
349
dma_addr_t *dma_addr);
350
+
void radeon_gart_restore(struct radeon_device *rdev);
340
351
341
352
342
353
/*
···
428
437
struct evergreen_irq_stat_regs evergreen;
429
438
};
430
439
440
+
#define RADEON_MAX_HPD_PINS 6
441
+
#define RADEON_MAX_CRTCS 6
442
+
#define RADEON_MAX_HDMI_BLOCKS 2
443
+
431
444
struct radeon_irq {
432
445
bool installed;
433
446
bool sw_int;
434
-
/* FIXME: use a define max crtc rather than hardcode it */
435
-
bool crtc_vblank_int[6];
436
-
bool pflip[6];
447
+
bool crtc_vblank_int[RADEON_MAX_CRTCS];
448
+
bool pflip[RADEON_MAX_CRTCS];
437
449
wait_queue_head_t vblank_queue;
438
-
/* FIXME: use defines for max hpd/dacs */
439
-
bool hpd[6];
450
+
bool hpd[RADEON_MAX_HPD_PINS];
440
451
bool gui_idle;
441
452
bool gui_idle_acked;
442
453
wait_queue_head_t idle_queue;
443
-
/* FIXME: use defines for max HDMI blocks */
444
-
bool hdmi[2];
454
+
bool hdmi[RADEON_MAX_HDMI_BLOCKS];
445
455
spinlock_t sw_lock;
446
456
int sw_refcount;
447
457
union radeon_irq_stat_regs stat_regs;
448
-
spinlock_t pflip_lock[6];
449
-
int pflip_refcount[6];
458
+
spinlock_t pflip_lock[RADEON_MAX_CRTCS];
459
+
int pflip_refcount[RADEON_MAX_CRTCS];
450
460
};
451
461
452
462
int radeon_irq_kms_init(struct radeon_device *rdev);
···
525
533
void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
526
534
void (*set_tex_resource)(struct radeon_device *rdev,
527
535
int format, int w, int h, int pitch,
528
-
u64 gpu_addr);
536
+
u64 gpu_addr, u32 size);
529
537
void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
530
538
int x2, int y2);
531
539
void (*draw_auto)(struct radeon_device *rdev);
···
1135
1143
int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1136
1144
struct drm_file *filp);
1137
1145
1138
-
/* VRAM scratch page for HDP bug */
1139
-
struct r700_vram_scratch {
1146
+
/* VRAM scratch page for HDP bug, default vram page */
1147
+
struct r600_vram_scratch {
1140
1148
struct radeon_bo *robj;
1141
1149
volatile uint32_t *ptr;
1150
+
u64 gpu_addr;
1142
1151
};
1143
1152
1144
1153
/*
···
1211
1218
const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1212
1219
const struct firmware *mc_fw; /* NI MC firmware */
1213
1220
struct r600_blit r600_blit;
1214
-
struct r700_vram_scratch vram_scratch;
1221
+
struct r600_vram_scratch vram_scratch;
1215
1222
int msi_enabled; /* msi enabled */
1216
1223
struct r600_ih ih; /* r6/700 interrupt ring */
1217
1224
struct work_struct hotplug_work;
···
1435
1442
/* AGP */
1436
1443
extern int radeon_gpu_reset(struct radeon_device *rdev);
1437
1444
extern void radeon_agp_disable(struct radeon_device *rdev);
1438
-
extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1439
-
extern void radeon_gart_restore(struct radeon_device *rdev);
1440
1445
extern int radeon_modeset_init(struct radeon_device *rdev);
1441
1446
extern void radeon_modeset_fini(struct radeon_device *rdev);
1442
1447
extern bool radeon_card_posted(struct radeon_device *rdev);
···
1456
1465
extern int radeon_resume_kms(struct drm_device *dev);
1457
1466
extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1458
1467
extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1468
+
1469
+
/*
1470
+
* R600 vram scratch functions
1471
+
*/
1472
+
int r600_vram_scratch_init(struct radeon_device *rdev);
1473
+
void r600_vram_scratch_fini(struct radeon_device *rdev);
1459
1474
1460
1475
/*
1461
1476
* r600 functions used by radeon_encoder.c
+16
-74
drivers/gpu/drm/radeon/radeon_connectors.c
+16
-74
drivers/gpu/drm/radeon/radeon_connectors.c
···
44
44
radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder,
45
45
struct drm_connector *drm_connector);
46
46
47
-
bool radeon_connector_encoder_is_dp_bridge(struct drm_connector *connector);
48
-
49
47
void radeon_connector_hotplug(struct drm_connector *connector)
50
48
{
51
49
struct drm_device *dev = connector->dev;
···
430
432
return 0;
431
433
}
432
434
433
-
/*
434
-
* Some integrated ATI Radeon chipset implementations (e. g.
435
-
* Asus M2A-VM HDMI) may indicate the availability of a DDC,
436
-
* even when there's no monitor connected. For these connectors
437
-
* following DDC probe extension will be applied: check also for the
438
-
* availability of EDID with at least a correct EDID header. Only then,
439
-
* DDC is assumed to be available. This prevents drm_get_edid() and
440
-
* drm_edid_block_valid() from periodically dumping data and kernel
441
-
* errors into the logs and onto the terminal.
442
-
*/
443
-
static bool radeon_connector_needs_extended_probe(struct radeon_device *dev,
444
-
uint32_t supported_device,
445
-
int connector_type)
446
-
{
447
-
/* Asus M2A-VM HDMI board sends data to i2c bus even,
448
-
* if HDMI add-on card is not plugged in or HDMI is disabled in
449
-
* BIOS. Valid DDC can only be assumed, if also a valid EDID header
450
-
* can be retrieved via i2c bus during DDC probe */
451
-
if ((dev->pdev->device == 0x791e) &&
452
-
(dev->pdev->subsystem_vendor == 0x1043) &&
453
-
(dev->pdev->subsystem_device == 0x826d)) {
454
-
if ((connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
455
-
(supported_device == ATOM_DEVICE_DFP2_SUPPORT))
456
-
return true;
457
-
}
458
-
/* ECS A740GM-M with ATI RADEON 2100 sends data to i2c bus
459
-
* for a DVI connector that is not implemented */
460
-
if ((dev->pdev->device == 0x796e) &&
461
-
(dev->pdev->subsystem_vendor == 0x1019) &&
462
-
(dev->pdev->subsystem_device == 0x2615)) {
463
-
if ((connector_type == DRM_MODE_CONNECTOR_DVID) &&
464
-
(supported_device == ATOM_DEVICE_DFP2_SUPPORT))
465
-
return true;
466
-
}
467
-
/* TOSHIBA Satellite L300D with ATI Mobility Radeon x1100
468
-
* (RS690M) sends data to i2c bus for a HDMI connector that
469
-
* is not implemented */
470
-
if ((dev->pdev->device == 0x791f) &&
471
-
(dev->pdev->subsystem_vendor == 0x1179) &&
472
-
(dev->pdev->subsystem_device == 0xff68)) {
473
-
if ((connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
474
-
(supported_device == ATOM_DEVICE_DFP2_SUPPORT))
475
-
return true;
476
-
}
477
-
478
-
/* Default: no EDID header probe required for DDC probing */
479
-
return false;
480
-
}
481
-
482
435
static void radeon_fixup_lvds_native_mode(struct drm_encoder *encoder,
483
436
struct drm_connector *connector)
484
437
{
···
670
721
ret = connector_status_disconnected;
671
722
672
723
if (radeon_connector->ddc_bus)
673
-
dret = radeon_ddc_probe(radeon_connector,
674
-
radeon_connector->requires_extended_probe);
724
+
dret = radeon_ddc_probe(radeon_connector);
675
725
if (dret) {
676
726
radeon_connector->detected_by_load = false;
677
727
if (radeon_connector->edid) {
···
712
764
if (radeon_connector->dac_load_detect && encoder) {
713
765
encoder_funcs = encoder->helper_private;
714
766
ret = encoder_funcs->detect(encoder, connector);
715
-
if (ret == connector_status_connected)
767
+
if (ret != connector_status_disconnected)
716
768
radeon_connector->detected_by_load = true;
717
769
}
718
770
}
···
852
904
bool dret = false;
853
905
854
906
if (radeon_connector->ddc_bus)
855
-
dret = radeon_ddc_probe(radeon_connector,
856
-
radeon_connector->requires_extended_probe);
907
+
dret = radeon_ddc_probe(radeon_connector);
857
908
if (dret) {
858
909
radeon_connector->detected_by_load = false;
859
910
if (radeon_connector->edid) {
···
952
1005
ret = encoder_funcs->detect(encoder, connector);
953
1006
if (ret == connector_status_connected) {
954
1007
radeon_connector->use_digital = false;
955
-
radeon_connector->detected_by_load = true;
956
1008
}
1009
+
if (ret != connector_status_disconnected)
1010
+
radeon_connector->detected_by_load = true;
957
1011
}
958
1012
break;
959
1013
}
···
1151
1203
}
1152
1204
} else {
1153
1205
/* need to setup ddc on the bridge */
1154
-
if (radeon_connector_encoder_is_dp_bridge(connector)) {
1206
+
if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1207
+
ENCODER_OBJECT_ID_NONE) {
1155
1208
if (encoder)
1156
1209
radeon_atom_ext_encoder_setup_ddc(encoder);
1157
1210
}
···
1162
1213
return ret;
1163
1214
}
1164
1215
1165
-
bool radeon_connector_encoder_is_dp_bridge(struct drm_connector *connector)
1216
+
u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
1166
1217
{
1167
1218
struct drm_mode_object *obj;
1168
1219
struct drm_encoder *encoder;
1169
1220
struct radeon_encoder *radeon_encoder;
1170
1221
int i;
1171
-
bool found = false;
1172
1222
1173
1223
for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1174
1224
if (connector->encoder_ids[i] == 0)
···
1183
1235
switch (radeon_encoder->encoder_id) {
1184
1236
case ENCODER_OBJECT_ID_TRAVIS:
1185
1237
case ENCODER_OBJECT_ID_NUTMEG:
1186
-
found = true;
1187
-
break;
1238
+
return radeon_encoder->encoder_id;
1188
1239
default:
1189
1240
break;
1190
1241
}
1191
1242
}
1192
1243
1193
-
return found;
1244
+
return ENCODER_OBJECT_ID_NONE;
1194
1245
}
1195
1246
1196
1247
bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector)
···
1266
1319
if (!radeon_dig_connector->edp_on)
1267
1320
atombios_set_edp_panel_power(connector,
1268
1321
ATOM_TRANSMITTER_ACTION_POWER_OFF);
1269
-
} else if (radeon_connector_encoder_is_dp_bridge(connector)) {
1322
+
} else if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1323
+
ENCODER_OBJECT_ID_NONE) {
1270
1324
/* DP bridges are always DP */
1271
1325
radeon_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1272
1326
/* get the DPCD from the bridge */
···
1276
1328
if (encoder) {
1277
1329
/* setup ddc on the bridge */
1278
1330
radeon_atom_ext_encoder_setup_ddc(encoder);
1279
-
if (radeon_ddc_probe(radeon_connector,
1280
-
radeon_connector->requires_extended_probe)) /* try DDC */
1331
+
if (radeon_ddc_probe(radeon_connector)) /* try DDC */
1281
1332
ret = connector_status_connected;
1282
1333
else if (radeon_connector->dac_load_detect) { /* try load detection */
1283
1334
struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
···
1294
1347
if (radeon_dp_getdpcd(radeon_connector))
1295
1348
ret = connector_status_connected;
1296
1349
} else {
1297
-
if (radeon_ddc_probe(radeon_connector,
1298
-
radeon_connector->requires_extended_probe))
1350
+
if (radeon_ddc_probe(radeon_connector))
1299
1351
ret = connector_status_connected;
1300
1352
}
1301
1353
}
···
1439
1493
radeon_connector->shared_ddc = shared_ddc;
1440
1494
radeon_connector->connector_object_id = connector_object_id;
1441
1495
radeon_connector->hpd = *hpd;
1442
-
radeon_connector->requires_extended_probe =
1443
-
radeon_connector_needs_extended_probe(rdev, supported_device,
1444
-
connector_type);
1496
+
1445
1497
radeon_connector->router = *router;
1446
1498
if (router->ddc_valid || router->cd_valid) {
1447
1499
radeon_connector->router_bus = radeon_i2c_lookup(rdev, &router->i2c_info);
···
1786
1842
radeon_connector->devices = supported_device;
1787
1843
radeon_connector->connector_object_id = connector_object_id;
1788
1844
radeon_connector->hpd = *hpd;
1789
-
radeon_connector->requires_extended_probe =
1790
-
radeon_connector_needs_extended_probe(rdev, supported_device,
1791
-
connector_type);
1845
+
1792
1846
switch (connector_type) {
1793
1847
case DRM_MODE_CONNECTOR_VGA:
1794
1848
drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
+2
-34
drivers/gpu/drm/radeon/radeon_display.c
+2
-34
drivers/gpu/drm/radeon/radeon_display.c
···
33
33
#include "drm_crtc_helper.h"
34
34
#include "drm_edid.h"
35
35
36
-
static int radeon_ddc_dump(struct drm_connector *connector);
37
-
38
36
static void avivo_crtc_load_lut(struct drm_crtc *crtc)
39
37
{
40
38
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
···
667
669
static bool radeon_setup_enc_conn(struct drm_device *dev)
668
670
{
669
671
struct radeon_device *rdev = dev->dev_private;
670
-
struct drm_connector *drm_connector;
671
672
bool ret = false;
672
673
673
674
if (rdev->bios) {
···
686
689
if (ret) {
687
690
radeon_setup_encoder_clones(dev);
688
691
radeon_print_display_setup(dev);
689
-
list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
690
-
radeon_ddc_dump(drm_connector);
691
692
}
692
693
693
694
return ret;
···
703
708
704
709
if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
705
710
(radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) ||
706
-
radeon_connector_encoder_is_dp_bridge(&radeon_connector->base)) {
711
+
(radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
712
+
ENCODER_OBJECT_ID_NONE)) {
707
713
struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
708
714
709
715
if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
···
737
741
}
738
742
drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
739
743
return 0;
740
-
}
741
-
742
-
static int radeon_ddc_dump(struct drm_connector *connector)
743
-
{
744
-
struct edid *edid;
745
-
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
746
-
int ret = 0;
747
-
748
-
/* on hw with routers, select right port */
749
-
if (radeon_connector->router.ddc_valid)
750
-
radeon_router_select_ddc_port(radeon_connector);
751
-
752
-
if (!radeon_connector->ddc_bus)
753
-
return -1;
754
-
edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
755
-
/* Log EDID retrieval status here. In particular with regard to
756
-
* connectors with requires_extended_probe flag set, that will prevent
757
-
* function radeon_dvi_detect() to fetch EDID on this connector,
758
-
* as long as there is no valid EDID header found */
759
-
if (edid) {
760
-
DRM_INFO("Radeon display connector %s: Found valid EDID",
761
-
drm_get_connector_name(connector));
762
-
kfree(edid);
763
-
} else {
764
-
DRM_INFO("Radeon display connector %s: No monitor connected or invalid EDID",
765
-
drm_get_connector_name(connector));
766
-
}
767
-
return ret;
768
744
}
769
745
770
746
/* avivo */
+4
drivers/gpu/drm/radeon/radeon_drv.c
+4
drivers/gpu/drm/radeon/radeon_drv.c
···
119
119
int radeon_disp_priority = 0;
120
120
int radeon_hw_i2c = 0;
121
121
int radeon_pcie_gen2 = 0;
122
+
int radeon_msi = -1;
122
123
123
124
MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
124
125
module_param_named(no_wb, radeon_no_wb, int, 0444);
···
165
164
166
165
MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (1 = enable)");
167
166
module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
167
+
168
+
MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
169
+
module_param_named(msi, radeon_msi, int, 0444);
168
170
169
171
static int radeon_suspend(struct drm_device *dev, pm_message_t state)
170
172
{
+3
-2148
drivers/gpu/drm/radeon/radeon_encoders.c
+3
-2148
drivers/gpu/drm/radeon/radeon_encoders.c
···
29
29
#include "radeon.h"
30
30
#include "atom.h"
31
31
32
-
extern int atom_debug;
33
-
34
-
/* evil but including atombios.h is much worse */
35
-
bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36
-
struct drm_display_mode *mode);
37
-
38
32
static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
39
33
{
40
34
struct drm_device *dev = encoder->dev;
···
150
156
return ret;
151
157
}
152
158
153
-
static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
154
-
{
155
-
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
156
-
switch (radeon_encoder->encoder_id) {
157
-
case ENCODER_OBJECT_ID_INTERNAL_LVDS:
158
-
case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
159
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
160
-
case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
161
-
case ENCODER_OBJECT_ID_INTERNAL_DVO1:
162
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
163
-
case ENCODER_OBJECT_ID_INTERNAL_DDI:
164
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
165
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
166
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
167
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
168
-
return true;
169
-
default:
170
-
return false;
171
-
}
172
-
}
173
-
174
159
void
175
160
radeon_link_encoder_connector(struct drm_device *dev)
176
161
{
···
202
229
return NULL;
203
230
}
204
231
205
-
static struct drm_connector *
206
-
radeon_get_connector_for_encoder_init(struct drm_encoder *encoder)
207
-
{
208
-
struct drm_device *dev = encoder->dev;
209
-
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
210
-
struct drm_connector *connector;
211
-
struct radeon_connector *radeon_connector;
212
-
213
-
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
214
-
radeon_connector = to_radeon_connector(connector);
215
-
if (radeon_encoder->devices & radeon_connector->devices)
216
-
return connector;
217
-
}
218
-
return NULL;
219
-
}
220
-
221
-
struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder)
232
+
struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder)
222
233
{
223
234
struct drm_device *dev = encoder->dev;
224
235
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
···
223
266
return NULL;
224
267
}
225
268
226
-
bool radeon_encoder_is_dp_bridge(struct drm_encoder *encoder)
269
+
u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder)
227
270
{
228
-
struct drm_encoder *other_encoder = radeon_atom_get_external_encoder(encoder);
271
+
struct drm_encoder *other_encoder = radeon_get_external_encoder(encoder);
229
272
230
273
if (other_encoder) {
231
274
struct radeon_encoder *radeon_encoder = to_radeon_encoder(other_encoder);
···
289
332
290
333
}
291
334
292
-
static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
293
-
struct drm_display_mode *mode,
294
-
struct drm_display_mode *adjusted_mode)
295
-
{
296
-
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
297
-
struct drm_device *dev = encoder->dev;
298
-
struct radeon_device *rdev = dev->dev_private;
299
-
300
-
/* set the active encoder to connector routing */
301
-
radeon_encoder_set_active_device(encoder);
302
-
drm_mode_set_crtcinfo(adjusted_mode, 0);
303
-
304
-
/* hw bug */
305
-
if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
306
-
&& (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
307
-
adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
308
-
309
-
/* get the native mode for LVDS */
310
-
if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
311
-
radeon_panel_mode_fixup(encoder, adjusted_mode);
312
-
313
-
/* get the native mode for TV */
314
-
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
315
-
struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
316
-
if (tv_dac) {
317
-
if (tv_dac->tv_std == TV_STD_NTSC ||
318
-
tv_dac->tv_std == TV_STD_NTSC_J ||
319
-
tv_dac->tv_std == TV_STD_PAL_M)
320
-
radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
321
-
else
322
-
radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
323
-
}
324
-
}
325
-
326
-
if (ASIC_IS_DCE3(rdev) &&
327
-
((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
328
-
radeon_encoder_is_dp_bridge(encoder))) {
329
-
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
330
-
radeon_dp_set_link_config(connector, mode);
331
-
}
332
-
333
-
return true;
334
-
}
335
-
336
-
static void
337
-
atombios_dac_setup(struct drm_encoder *encoder, int action)
338
-
{
339
-
struct drm_device *dev = encoder->dev;
340
-
struct radeon_device *rdev = dev->dev_private;
341
-
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
342
-
DAC_ENCODER_CONTROL_PS_ALLOCATION args;
343
-
int index = 0;
344
-
struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
345
-
346
-
memset(&args, 0, sizeof(args));
347
-
348
-
switch (radeon_encoder->encoder_id) {
349
-
case ENCODER_OBJECT_ID_INTERNAL_DAC1:
350
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
351
-
index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
352
-
break;
353
-
case ENCODER_OBJECT_ID_INTERNAL_DAC2:
354
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
355
-
index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
356
-
break;
357
-
}
358
-
359
-
args.ucAction = action;
360
-
361
-
if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
362
-
args.ucDacStandard = ATOM_DAC1_PS2;
363
-
else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
364
-
args.ucDacStandard = ATOM_DAC1_CV;
365
-
else {
366
-
switch (dac_info->tv_std) {
367
-
case TV_STD_PAL:
368
-
case TV_STD_PAL_M:
369
-
case TV_STD_SCART_PAL:
370
-
case TV_STD_SECAM:
371
-
case TV_STD_PAL_CN:
372
-
args.ucDacStandard = ATOM_DAC1_PAL;
373
-
break;
374
-
case TV_STD_NTSC:
375
-
case TV_STD_NTSC_J:
376
-
case TV_STD_PAL_60:
377
-
default:
378
-
args.ucDacStandard = ATOM_DAC1_NTSC;
379
-
break;
380
-
}
381
-
}
382
-
args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
383
-
384
-
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
385
-
386
-
}
387
-
388
-
static void
389
-
atombios_tv_setup(struct drm_encoder *encoder, int action)
390
-
{
391
-
struct drm_device *dev = encoder->dev;
392
-
struct radeon_device *rdev = dev->dev_private;
393
-
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
394
-
TV_ENCODER_CONTROL_PS_ALLOCATION args;
395
-
int index = 0;
396
-
struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
397
-
398
-
memset(&args, 0, sizeof(args));
399
-
400
-
index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
401
-
402
-
args.sTVEncoder.ucAction = action;
403
-
404
-
if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
405
-
args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
406
-
else {
407
-
switch (dac_info->tv_std) {
408
-
case TV_STD_NTSC:
409
-
args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
410
-
break;
411
-
case TV_STD_PAL:
412
-
args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
413
-
break;
414
-
case TV_STD_PAL_M:
415
-
args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
416
-
break;
417
-
case TV_STD_PAL_60:
418
-
args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
419
-
break;
420
-
case TV_STD_NTSC_J:
421
-
args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
422
-
break;
423
-
case TV_STD_SCART_PAL:
424
-
args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
425
-
break;
426
-
case TV_STD_SECAM:
427
-
args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
428
-
break;
429
-
case TV_STD_PAL_CN:
430
-
args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
431
-
break;
432
-
default:
433
-
args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
434
-
break;
435
-
}
436
-
}
437
-
438
-
args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
439
-
440
-
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
441
-
442
-
}
443
-
444
-
union dvo_encoder_control {
445
-
ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
446
-
DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
447
-
DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
448
-
};
449
-
450
-
void
451
-
atombios_dvo_setup(struct drm_encoder *encoder, int action)
452
-
{
453
-
struct drm_device *dev = encoder->dev;
454
-
struct radeon_device *rdev = dev->dev_private;
455
-
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
456
-
union dvo_encoder_control args;
457
-
int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
458
-
459
-
memset(&args, 0, sizeof(args));
460
-
461
-
if (ASIC_IS_DCE3(rdev)) {
462
-
/* DCE3+ */
463
-
args.dvo_v3.ucAction = action;
464
-
args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
465
-
args.dvo_v3.ucDVOConfig = 0; /* XXX */
466
-
} else if (ASIC_IS_DCE2(rdev)) {
467
-
/* DCE2 (pre-DCE3 R6xx, RS600/690/740 */
468
-
args.dvo.sDVOEncoder.ucAction = action;
469
-
args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
470
-
/* DFP1, CRT1, TV1 depending on the type of port */
471
-
args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
472
-
473
-
if (radeon_encoder->pixel_clock > 165000)
474
-
args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
475
-
} else {
476
-
/* R4xx, R5xx */
477
-
args.ext_tmds.sXTmdsEncoder.ucEnable = action;
478
-
479
-
if (radeon_encoder->pixel_clock > 165000)
480
-
args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
481
-
482
-
/*if (pScrn->rgbBits == 8)*/
483
-
args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
484
-
}
485
-
486
-
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
487
-
}
488
-
489
-
union lvds_encoder_control {
490
-
LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
491
-
LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
492
-
};
493
-
494
-
void
495
-
atombios_digital_setup(struct drm_encoder *encoder, int action)
496
-
{
497
-
struct drm_device *dev = encoder->dev;
498
-
struct radeon_device *rdev = dev->dev_private;
499
-
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
500
-
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
501
-
union lvds_encoder_control args;
502
-
int index = 0;
503
-
int hdmi_detected = 0;
504
-
uint8_t frev, crev;
505
-
506
-
if (!dig)
507
-
return;
508
-
509
-
if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
510
-
hdmi_detected = 1;
511
-
512
-
memset(&args, 0, sizeof(args));
513
-
514
-
switch (radeon_encoder->encoder_id) {
515
-
case ENCODER_OBJECT_ID_INTERNAL_LVDS:
516
-
index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
517
-
break;
518
-
case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
519
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
520
-
index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
521
-
break;
522
-
case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
523
-
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
524
-
index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
525
-
else
526
-
index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
527
-
break;
528
-
}
529
-
530
-
if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
531
-
return;
532
-
533
-
switch (frev) {
534
-
case 1:
535
-
case 2:
536
-
switch (crev) {
537
-
case 1:
538
-
args.v1.ucMisc = 0;
539
-
args.v1.ucAction = action;
540
-
if (hdmi_detected)
541
-
args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
542
-
args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
543
-
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
544
-
if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
545
-
args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
546
-
if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
547
-
args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
548
-
} else {
549
-
if (dig->linkb)
550
-
args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
551
-
if (radeon_encoder->pixel_clock > 165000)
552
-
args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
553
-
/*if (pScrn->rgbBits == 8) */
554
-
args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
555
-
}
556
-
break;
557
-
case 2:
558
-
case 3:
559
-
args.v2.ucMisc = 0;
560
-
args.v2.ucAction = action;
561
-
if (crev == 3) {
562
-
if (dig->coherent_mode)
563
-
args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
564
-
}
565
-
if (hdmi_detected)
566
-
args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
567
-
args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
568
-
args.v2.ucTruncate = 0;
569
-
args.v2.ucSpatial = 0;
570
-
args.v2.ucTemporal = 0;
571
-
args.v2.ucFRC = 0;
572
-
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
573
-
if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
574
-
args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
575
-
if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
576
-
args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
577
-
if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
578
-
args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
579
-
}
580
-
if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
581
-
args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
582
-
if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
583
-
args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
584
-
if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
585
-
args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
586
-
}
587
-
} else {
588
-
if (dig->linkb)
589
-
args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
590
-
if (radeon_encoder->pixel_clock > 165000)
591
-
args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
592
-
}
593
-
break;
594
-
default:
595
-
DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
596
-
break;
597
-
}
598
-
break;
599
-
default:
600
-
DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
601
-
break;
602
-
}
603
-
604
-
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
605
-
}
606
-
607
-
int
608
-
atombios_get_encoder_mode(struct drm_encoder *encoder)
609
-
{
610
-
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
611
-
struct drm_device *dev = encoder->dev;
612
-
struct radeon_device *rdev = dev->dev_private;
613
-
struct drm_connector *connector;
614
-
struct radeon_connector *radeon_connector;
615
-
struct radeon_connector_atom_dig *dig_connector;
616
-
617
-
/* dp bridges are always DP */
618
-
if (radeon_encoder_is_dp_bridge(encoder))
619
-
return ATOM_ENCODER_MODE_DP;
620
-
621
-
/* DVO is always DVO */
622
-
if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO)
623
-
return ATOM_ENCODER_MODE_DVO;
624
-
625
-
connector = radeon_get_connector_for_encoder(encoder);
626
-
/* if we don't have an active device yet, just use one of
627
-
* the connectors tied to the encoder.
628
-
*/
629
-
if (!connector)
630
-
connector = radeon_get_connector_for_encoder_init(encoder);
631
-
radeon_connector = to_radeon_connector(connector);
632
-
633
-
switch (connector->connector_type) {
634
-
case DRM_MODE_CONNECTOR_DVII:
635
-
case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
636
-
if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
637
-
/* fix me */
638
-
if (ASIC_IS_DCE4(rdev))
639
-
return ATOM_ENCODER_MODE_DVI;
640
-
else
641
-
return ATOM_ENCODER_MODE_HDMI;
642
-
} else if (radeon_connector->use_digital)
643
-
return ATOM_ENCODER_MODE_DVI;
644
-
else
645
-
return ATOM_ENCODER_MODE_CRT;
646
-
break;
647
-
case DRM_MODE_CONNECTOR_DVID:
648
-
case DRM_MODE_CONNECTOR_HDMIA:
649
-
default:
650
-
if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
651
-
/* fix me */
652
-
if (ASIC_IS_DCE4(rdev))
653
-
return ATOM_ENCODER_MODE_DVI;
654
-
else
655
-
return ATOM_ENCODER_MODE_HDMI;
656
-
} else
657
-
return ATOM_ENCODER_MODE_DVI;
658
-
break;
659
-
case DRM_MODE_CONNECTOR_LVDS:
660
-
return ATOM_ENCODER_MODE_LVDS;
661
-
break;
662
-
case DRM_MODE_CONNECTOR_DisplayPort:
663
-
dig_connector = radeon_connector->con_priv;
664
-
if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
665
-
(dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
666
-
return ATOM_ENCODER_MODE_DP;
667
-
else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
668
-
/* fix me */
669
-
if (ASIC_IS_DCE4(rdev))
670
-
return ATOM_ENCODER_MODE_DVI;
671
-
else
672
-
return ATOM_ENCODER_MODE_HDMI;
673
-
} else
674
-
return ATOM_ENCODER_MODE_DVI;
675
-
break;
676
-
case DRM_MODE_CONNECTOR_eDP:
677
-
return ATOM_ENCODER_MODE_DP;
678
-
case DRM_MODE_CONNECTOR_DVIA:
679
-
case DRM_MODE_CONNECTOR_VGA:
680
-
return ATOM_ENCODER_MODE_CRT;
681
-
break;
682
-
case DRM_MODE_CONNECTOR_Composite:
683
-
case DRM_MODE_CONNECTOR_SVIDEO:
684
-
case DRM_MODE_CONNECTOR_9PinDIN:
685
-
/* fix me */
686
-
return ATOM_ENCODER_MODE_TV;
687
-
/*return ATOM_ENCODER_MODE_CV;*/
688
-
break;
689
-
}
690
-
}
691
-
692
-
/*
693
-
* DIG Encoder/Transmitter Setup
694
-
*
695
-
* DCE 3.0/3.1
696
-
* - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
697
-
* Supports up to 3 digital outputs
698
-
* - 2 DIG encoder blocks.
699
-
* DIG1 can drive UNIPHY link A or link B
700
-
* DIG2 can drive UNIPHY link B or LVTMA
701
-
*
702
-
* DCE 3.2
703
-
* - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
704
-
* Supports up to 5 digital outputs
705
-
* - 2 DIG encoder blocks.
706
-
* DIG1/2 can drive UNIPHY0/1/2 link A or link B
707
-
*
708
-
* DCE 4.0/5.0
709
-
* - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
710
-
* Supports up to 6 digital outputs
711
-
* - 6 DIG encoder blocks.
712
-
* - DIG to PHY mapping is hardcoded
713
-
* DIG1 drives UNIPHY0 link A, A+B
714
-
* DIG2 drives UNIPHY0 link B
715
-
* DIG3 drives UNIPHY1 link A, A+B
716
-
* DIG4 drives UNIPHY1 link B
717
-
* DIG5 drives UNIPHY2 link A, A+B
718
-
* DIG6 drives UNIPHY2 link B
719
-
*
720
-
* DCE 4.1
721
-
* - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
722
-
* Supports up to 6 digital outputs
723
-
* - 2 DIG encoder blocks.
724
-
* DIG1/2 can drive UNIPHY0/1/2 link A or link B
725
-
*
726
-
* Routing
727
-
* crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
728
-
* Examples:
729
-
* crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
730
-
* crtc1 -> dig1 -> UNIPHY0 link B -> DP
731
-
* crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
732
-
* crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
733
-
*/
734
-
735
-
union dig_encoder_control {
736
-
DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
737
-
DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
738
-
DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
739
-
DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
740
-
};
741
-
742
-
void
743
-
atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
744
-
{
745
-
struct drm_device *dev = encoder->dev;
746
-
struct radeon_device *rdev = dev->dev_private;
747
-
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
748
-
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
749
-
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
750
-
union dig_encoder_control args;
751
-
int index = 0;
752
-
uint8_t frev, crev;
753
-
int dp_clock = 0;
754
-
int dp_lane_count = 0;
755
-
int hpd_id = RADEON_HPD_NONE;
756
-
int bpc = 8;
757
-
758
-
if (connector) {
759
-
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
760
-
struct radeon_connector_atom_dig *dig_connector =
761
-
radeon_connector->con_priv;
762
-
763
-
dp_clock = dig_connector->dp_clock;
764
-
dp_lane_count = dig_connector->dp_lane_count;
765
-
hpd_id = radeon_connector->hpd.hpd;
766
-
bpc = connector->display_info.bpc;
767
-
}
768
-
769
-
/* no dig encoder assigned */
770
-
if (dig->dig_encoder == -1)
771
-
return;
772
-
773
-
memset(&args, 0, sizeof(args));
774
-
775
-
if (ASIC_IS_DCE4(rdev))
776
-
index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
777
-
else {
778
-
if (dig->dig_encoder)
779
-
index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
780
-
else
781
-
index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
782
-
}
783
-
784
-
if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
785
-
return;
786
-
787
-
args.v1.ucAction = action;
788
-
args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
789
-
if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
790
-
args.v3.ucPanelMode = panel_mode;
791
-
else
792
-
args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
793
-
794
-
if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
795
-
(args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST))
796
-
args.v1.ucLaneNum = dp_lane_count;
797
-
else if (radeon_encoder->pixel_clock > 165000)
798
-
args.v1.ucLaneNum = 8;
799
-
else
800
-
args.v1.ucLaneNum = 4;
801
-
802
-
if (ASIC_IS_DCE5(rdev)) {
803
-
if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
804
-
(args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) {
805
-
if (dp_clock == 270000)
806
-
args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
807
-
else if (dp_clock == 540000)
808
-
args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
809
-
}
810
-
args.v4.acConfig.ucDigSel = dig->dig_encoder;
811
-
switch (bpc) {
812
-
case 0:
813
-
args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
814
-
break;
815
-
case 6:
816
-
args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
817
-
break;
818
-
case 8:
819
-
default:
820
-
args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
821
-
break;
822
-
case 10:
823
-
args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
824
-
break;
825
-
case 12:
826
-
args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
827
-
break;
828
-
case 16:
829
-
args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
830
-
break;
831
-
}
832
-
if (hpd_id == RADEON_HPD_NONE)
833
-
args.v4.ucHPD_ID = 0;
834
-
else
835
-
args.v4.ucHPD_ID = hpd_id + 1;
836
-
} else if (ASIC_IS_DCE4(rdev)) {
837
-
if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
838
-
args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
839
-
args.v3.acConfig.ucDigSel = dig->dig_encoder;
840
-
switch (bpc) {
841
-
case 0:
842
-
args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
843
-
break;
844
-
case 6:
845
-
args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
846
-
break;
847
-
case 8:
848
-
default:
849
-
args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
850
-
break;
851
-
case 10:
852
-
args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
853
-
break;
854
-
case 12:
855
-
args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
856
-
break;
857
-
case 16:
858
-
args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
859
-
break;
860
-
}
861
-
} else {
862
-
if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
863
-
args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
864
-
switch (radeon_encoder->encoder_id) {
865
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
866
-
args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
867
-
break;
868
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
869
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
870
-
args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
871
-
break;
872
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
873
-
args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
874
-
break;
875
-
}
876
-
if (dig->linkb)
877
-
args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
878
-
else
879
-
args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
880
-
}
881
-
882
-
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
883
-
884
-
}
885
-
886
-
union dig_transmitter_control {
887
-
DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
888
-
DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
889
-
DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
890
-
DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
891
-
};
892
-
893
-
void
894
-
atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
895
-
{
896
-
struct drm_device *dev = encoder->dev;
897
-
struct radeon_device *rdev = dev->dev_private;
898
-
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
899
-
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
900
-
struct drm_connector *connector;
901
-
union dig_transmitter_control args;
902
-
int index = 0;
903
-
uint8_t frev, crev;
904
-
bool is_dp = false;
905
-
int pll_id = 0;
906
-
int dp_clock = 0;
907
-
int dp_lane_count = 0;
908
-
int connector_object_id = 0;
909
-
int igp_lane_info = 0;
910
-
int dig_encoder = dig->dig_encoder;
911
-
912
-
if (action == ATOM_TRANSMITTER_ACTION_INIT) {
913
-
connector = radeon_get_connector_for_encoder_init(encoder);
914
-
/* just needed to avoid bailing in the encoder check. the encoder
915
-
* isn't used for init
916
-
*/
917
-
dig_encoder = 0;
918
-
} else
919
-
connector = radeon_get_connector_for_encoder(encoder);
920
-
921
-
if (connector) {
922
-
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
923
-
struct radeon_connector_atom_dig *dig_connector =
924
-
radeon_connector->con_priv;
925
-
926
-
dp_clock = dig_connector->dp_clock;
927
-
dp_lane_count = dig_connector->dp_lane_count;
928
-
connector_object_id =
929
-
(radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
930
-
igp_lane_info = dig_connector->igp_lane_info;
931
-
}
932
-
933
-
/* no dig encoder assigned */
934
-
if (dig_encoder == -1)
935
-
return;
936
-
937
-
if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
938
-
is_dp = true;
939
-
940
-
memset(&args, 0, sizeof(args));
941
-
942
-
switch (radeon_encoder->encoder_id) {
943
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
944
-
index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
945
-
break;
946
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
947
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
948
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
949
-
index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
950
-
break;
951
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
952
-
index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
953
-
break;
954
-
}
955
-
956
-
if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
957
-
return;
958
-
959
-
args.v1.ucAction = action;
960
-
if (action == ATOM_TRANSMITTER_ACTION_INIT) {
961
-
args.v1.usInitInfo = cpu_to_le16(connector_object_id);
962
-
} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
963
-
args.v1.asMode.ucLaneSel = lane_num;
964
-
args.v1.asMode.ucLaneSet = lane_set;
965
-
} else {
966
-
if (is_dp)
967
-
args.v1.usPixelClock =
968
-
cpu_to_le16(dp_clock / 10);
969
-
else if (radeon_encoder->pixel_clock > 165000)
970
-
args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
971
-
else
972
-
args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
973
-
}
974
-
if (ASIC_IS_DCE4(rdev)) {
975
-
if (is_dp)
976
-
args.v3.ucLaneNum = dp_lane_count;
977
-
else if (radeon_encoder->pixel_clock > 165000)
978
-
args.v3.ucLaneNum = 8;
979
-
else
980
-
args.v3.ucLaneNum = 4;
981
-
982
-
if (dig->linkb)
983
-
args.v3.acConfig.ucLinkSel = 1;
984
-
if (dig_encoder & 1)
985
-
args.v3.acConfig.ucEncoderSel = 1;
986
-
987
-
/* Select the PLL for the PHY
988
-
* DP PHY should be clocked from external src if there is
989
-
* one.
990
-
*/
991
-
if (encoder->crtc) {
992
-
struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
993
-
pll_id = radeon_crtc->pll_id;
994
-
}
995
-
996
-
if (ASIC_IS_DCE5(rdev)) {
997
-
/* On DCE5 DCPLL usually generates the DP ref clock */
998
-
if (is_dp) {
999
-
if (rdev->clock.dp_extclk)
1000
-
args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1001
-
else
1002
-
args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1003
-
} else
1004
-
args.v4.acConfig.ucRefClkSource = pll_id;
1005
-
} else {
1006
-
/* On DCE4, if there is an external clock, it generates the DP ref clock */
1007
-
if (is_dp && rdev->clock.dp_extclk)
1008
-
args.v3.acConfig.ucRefClkSource = 2; /* external src */
1009
-
else
1010
-
args.v3.acConfig.ucRefClkSource = pll_id;
1011
-
}
1012
-
1013
-
switch (radeon_encoder->encoder_id) {
1014
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1015
-
args.v3.acConfig.ucTransmitterSel = 0;
1016
-
break;
1017
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1018
-
args.v3.acConfig.ucTransmitterSel = 1;
1019
-
break;
1020
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1021
-
args.v3.acConfig.ucTransmitterSel = 2;
1022
-
break;
1023
-
}
1024
-
1025
-
if (is_dp)
1026
-
args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1027
-
else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1028
-
if (dig->coherent_mode)
1029
-
args.v3.acConfig.fCoherentMode = 1;
1030
-
if (radeon_encoder->pixel_clock > 165000)
1031
-
args.v3.acConfig.fDualLinkConnector = 1;
1032
-
}
1033
-
} else if (ASIC_IS_DCE32(rdev)) {
1034
-
args.v2.acConfig.ucEncoderSel = dig_encoder;
1035
-
if (dig->linkb)
1036
-
args.v2.acConfig.ucLinkSel = 1;
1037
-
1038
-
switch (radeon_encoder->encoder_id) {
1039
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1040
-
args.v2.acConfig.ucTransmitterSel = 0;
1041
-
break;
1042
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1043
-
args.v2.acConfig.ucTransmitterSel = 1;
1044
-
break;
1045
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1046
-
args.v2.acConfig.ucTransmitterSel = 2;
1047
-
break;
1048
-
}
1049
-
1050
-
if (is_dp) {
1051
-
args.v2.acConfig.fCoherentMode = 1;
1052
-
args.v2.acConfig.fDPConnector = 1;
1053
-
} else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1054
-
if (dig->coherent_mode)
1055
-
args.v2.acConfig.fCoherentMode = 1;
1056
-
if (radeon_encoder->pixel_clock > 165000)
1057
-
args.v2.acConfig.fDualLinkConnector = 1;
1058
-
}
1059
-
} else {
1060
-
args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1061
-
1062
-
if (dig_encoder)
1063
-
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1064
-
else
1065
-
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1066
-
1067
-
if ((rdev->flags & RADEON_IS_IGP) &&
1068
-
(radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1069
-
if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
1070
-
if (igp_lane_info & 0x1)
1071
-
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1072
-
else if (igp_lane_info & 0x2)
1073
-
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1074
-
else if (igp_lane_info & 0x4)
1075
-
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1076
-
else if (igp_lane_info & 0x8)
1077
-
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1078
-
} else {
1079
-
if (igp_lane_info & 0x3)
1080
-
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1081
-
else if (igp_lane_info & 0xc)
1082
-
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1083
-
}
1084
-
}
1085
-
1086
-
if (dig->linkb)
1087
-
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1088
-
else
1089
-
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1090
-
1091
-
if (is_dp)
1092
-
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1093
-
else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1094
-
if (dig->coherent_mode)
1095
-
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1096
-
if (radeon_encoder->pixel_clock > 165000)
1097
-
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1098
-
}
1099
-
}
1100
-
1101
-
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1102
-
}
1103
-
1104
-
bool
1105
-
atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1106
-
{
1107
-
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1108
-
struct drm_device *dev = radeon_connector->base.dev;
1109
-
struct radeon_device *rdev = dev->dev_private;
1110
-
union dig_transmitter_control args;
1111
-
int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1112
-
uint8_t frev, crev;
1113
-
1114
-
if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1115
-
goto done;
1116
-
1117
-
if (!ASIC_IS_DCE4(rdev))
1118
-
goto done;
1119
-
1120
-
if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1121
-
(action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1122
-
goto done;
1123
-
1124
-
if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1125
-
goto done;
1126
-
1127
-
memset(&args, 0, sizeof(args));
1128
-
1129
-
args.v1.ucAction = action;
1130
-
1131
-
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1132
-
1133
-
/* wait for the panel to power up */
1134
-
if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1135
-
int i;
1136
-
1137
-
for (i = 0; i < 300; i++) {
1138
-
if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1139
-
return true;
1140
-
mdelay(1);
1141
-
}
1142
-
return false;
1143
-
}
1144
-
done:
1145
-
return true;
1146
-
}
1147
-
1148
-
union external_encoder_control {
1149
-
EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1150
-
EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1151
-
};
1152
-
1153
-
static void
1154
-
atombios_external_encoder_setup(struct drm_encoder *encoder,
1155
-
struct drm_encoder *ext_encoder,
1156
-
int action)
1157
-
{
1158
-
struct drm_device *dev = encoder->dev;
1159
-
struct radeon_device *rdev = dev->dev_private;
1160
-
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1161
-
struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1162
-
union external_encoder_control args;
1163
-
struct drm_connector *connector;
1164
-
int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1165
-
u8 frev, crev;
1166
-
int dp_clock = 0;
1167
-
int dp_lane_count = 0;
1168
-
int connector_object_id = 0;
1169
-
u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1170
-
int bpc = 8;
1171
-
1172
-
if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1173
-
connector = radeon_get_connector_for_encoder_init(encoder);
1174
-
else
1175
-
connector = radeon_get_connector_for_encoder(encoder);
1176
-
1177
-
if (connector) {
1178
-
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1179
-
struct radeon_connector_atom_dig *dig_connector =
1180
-
radeon_connector->con_priv;
1181
-
1182
-
dp_clock = dig_connector->dp_clock;
1183
-
dp_lane_count = dig_connector->dp_lane_count;
1184
-
connector_object_id =
1185
-
(radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1186
-
bpc = connector->display_info.bpc;
1187
-
}
1188
-
1189
-
memset(&args, 0, sizeof(args));
1190
-
1191
-
if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1192
-
return;
1193
-
1194
-
switch (frev) {
1195
-
case 1:
1196
-
/* no params on frev 1 */
1197
-
break;
1198
-
case 2:
1199
-
switch (crev) {
1200
-
case 1:
1201
-
case 2:
1202
-
args.v1.sDigEncoder.ucAction = action;
1203
-
args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1204
-
args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1205
-
1206
-
if (args.v1.sDigEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1207
-
if (dp_clock == 270000)
1208
-
args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1209
-
args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1210
-
} else if (radeon_encoder->pixel_clock > 165000)
1211
-
args.v1.sDigEncoder.ucLaneNum = 8;
1212
-
else
1213
-
args.v1.sDigEncoder.ucLaneNum = 4;
1214
-
break;
1215
-
case 3:
1216
-
args.v3.sExtEncoder.ucAction = action;
1217
-
if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1218
-
args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1219
-
else
1220
-
args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1221
-
args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1222
-
1223
-
if (args.v3.sExtEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1224
-
if (dp_clock == 270000)
1225
-
args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1226
-
else if (dp_clock == 540000)
1227
-
args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1228
-
args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1229
-
} else if (radeon_encoder->pixel_clock > 165000)
1230
-
args.v3.sExtEncoder.ucLaneNum = 8;
1231
-
else
1232
-
args.v3.sExtEncoder.ucLaneNum = 4;
1233
-
switch (ext_enum) {
1234
-
case GRAPH_OBJECT_ENUM_ID1:
1235
-
args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1236
-
break;
1237
-
case GRAPH_OBJECT_ENUM_ID2:
1238
-
args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1239
-
break;
1240
-
case GRAPH_OBJECT_ENUM_ID3:
1241
-
args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1242
-
break;
1243
-
}
1244
-
switch (bpc) {
1245
-
case 0:
1246
-
args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1247
-
break;
1248
-
case 6:
1249
-
args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1250
-
break;
1251
-
case 8:
1252
-
default:
1253
-
args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1254
-
break;
1255
-
case 10:
1256
-
args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1257
-
break;
1258
-
case 12:
1259
-
args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1260
-
break;
1261
-
case 16:
1262
-
args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1263
-
break;
1264
-
}
1265
-
break;
1266
-
default:
1267
-
DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1268
-
return;
1269
-
}
1270
-
break;
1271
-
default:
1272
-
DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1273
-
return;
1274
-
}
1275
-
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1276
-
}
1277
-
1278
-
static void
1279
-
atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1280
-
{
1281
-
struct drm_device *dev = encoder->dev;
1282
-
struct radeon_device *rdev = dev->dev_private;
1283
-
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1284
-
struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1285
-
ENABLE_YUV_PS_ALLOCATION args;
1286
-
int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1287
-
uint32_t temp, reg;
1288
-
1289
-
memset(&args, 0, sizeof(args));
1290
-
1291
-
if (rdev->family >= CHIP_R600)
1292
-
reg = R600_BIOS_3_SCRATCH;
1293
-
else
1294
-
reg = RADEON_BIOS_3_SCRATCH;
1295
-
1296
-
/* XXX: fix up scratch reg handling */
1297
-
temp = RREG32(reg);
1298
-
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1299
-
WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1300
-
(radeon_crtc->crtc_id << 18)));
1301
-
else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1302
-
WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1303
-
else
1304
-
WREG32(reg, 0);
1305
-
1306
-
if (enable)
1307
-
args.ucEnable = ATOM_ENABLE;
1308
-
args.ucCRTC = radeon_crtc->crtc_id;
1309
-
1310
-
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1311
-
1312
-
WREG32(reg, temp);
1313
-
}
1314
-
1315
-
static void
1316
-
radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1317
-
{
1318
-
struct drm_device *dev = encoder->dev;
1319
-
struct radeon_device *rdev = dev->dev_private;
1320
-
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1321
-
struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1322
-
DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1323
-
int index = 0;
1324
-
bool is_dig = false;
1325
-
bool is_dce5_dac = false;
1326
-
bool is_dce5_dvo = false;
1327
-
1328
-
memset(&args, 0, sizeof(args));
1329
-
1330
-
DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1331
-
radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1332
-
radeon_encoder->active_device);
1333
-
switch (radeon_encoder->encoder_id) {
1334
-
case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1335
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1336
-
index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1337
-
break;
1338
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1339
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1340
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1341
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1342
-
is_dig = true;
1343
-
break;
1344
-
case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1345
-
case ENCODER_OBJECT_ID_INTERNAL_DDI:
1346
-
index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1347
-
break;
1348
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1349
-
if (ASIC_IS_DCE5(rdev))
1350
-
is_dce5_dvo = true;
1351
-
else if (ASIC_IS_DCE3(rdev))
1352
-
is_dig = true;
1353
-
else
1354
-
index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1355
-
break;
1356
-
case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1357
-
index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1358
-
break;
1359
-
case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1360
-
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1361
-
index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1362
-
else
1363
-
index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1364
-
break;
1365
-
case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1366
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1367
-
if (ASIC_IS_DCE5(rdev))
1368
-
is_dce5_dac = true;
1369
-
else {
1370
-
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1371
-
index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1372
-
else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1373
-
index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1374
-
else
1375
-
index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1376
-
}
1377
-
break;
1378
-
case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1379
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1380
-
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1381
-
index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1382
-
else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1383
-
index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1384
-
else
1385
-
index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1386
-
break;
1387
-
}
1388
-
1389
-
if (is_dig) {
1390
-
switch (mode) {
1391
-
case DRM_MODE_DPMS_ON:
1392
-
/* some early dce3.2 boards have a bug in their transmitter control table */
1393
-
if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730))
1394
-
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1395
-
else
1396
-
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1397
-
if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1398
-
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1399
-
1400
-
if (connector &&
1401
-
(connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1402
-
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1403
-
struct radeon_connector_atom_dig *radeon_dig_connector =
1404
-
radeon_connector->con_priv;
1405
-
atombios_set_edp_panel_power(connector,
1406
-
ATOM_TRANSMITTER_ACTION_POWER_ON);
1407
-
radeon_dig_connector->edp_on = true;
1408
-
}
1409
-
if (ASIC_IS_DCE4(rdev))
1410
-
atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1411
-
radeon_dp_link_train(encoder, connector);
1412
-
if (ASIC_IS_DCE4(rdev))
1413
-
atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1414
-
}
1415
-
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1416
-
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1417
-
break;
1418
-
case DRM_MODE_DPMS_STANDBY:
1419
-
case DRM_MODE_DPMS_SUSPEND:
1420
-
case DRM_MODE_DPMS_OFF:
1421
-
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1422
-
if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1423
-
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1424
-
1425
-
if (ASIC_IS_DCE4(rdev))
1426
-
atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1427
-
if (connector &&
1428
-
(connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1429
-
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1430
-
struct radeon_connector_atom_dig *radeon_dig_connector =
1431
-
radeon_connector->con_priv;
1432
-
atombios_set_edp_panel_power(connector,
1433
-
ATOM_TRANSMITTER_ACTION_POWER_OFF);
1434
-
radeon_dig_connector->edp_on = false;
1435
-
}
1436
-
}
1437
-
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1438
-
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1439
-
break;
1440
-
}
1441
-
} else if (is_dce5_dac) {
1442
-
switch (mode) {
1443
-
case DRM_MODE_DPMS_ON:
1444
-
atombios_dac_setup(encoder, ATOM_ENABLE);
1445
-
break;
1446
-
case DRM_MODE_DPMS_STANDBY:
1447
-
case DRM_MODE_DPMS_SUSPEND:
1448
-
case DRM_MODE_DPMS_OFF:
1449
-
atombios_dac_setup(encoder, ATOM_DISABLE);
1450
-
break;
1451
-
}
1452
-
} else if (is_dce5_dvo) {
1453
-
switch (mode) {
1454
-
case DRM_MODE_DPMS_ON:
1455
-
atombios_dvo_setup(encoder, ATOM_ENABLE);
1456
-
break;
1457
-
case DRM_MODE_DPMS_STANDBY:
1458
-
case DRM_MODE_DPMS_SUSPEND:
1459
-
case DRM_MODE_DPMS_OFF:
1460
-
atombios_dvo_setup(encoder, ATOM_DISABLE);
1461
-
break;
1462
-
}
1463
-
} else {
1464
-
switch (mode) {
1465
-
case DRM_MODE_DPMS_ON:
1466
-
args.ucAction = ATOM_ENABLE;
1467
-
/* workaround for DVOOutputControl on some RS690 systems */
1468
-
if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1469
-
u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1470
-
WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1471
-
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1472
-
WREG32(RADEON_BIOS_3_SCRATCH, reg);
1473
-
} else
1474
-
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1475
-
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1476
-
args.ucAction = ATOM_LCD_BLON;
1477
-
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1478
-
}
1479
-
break;
1480
-
case DRM_MODE_DPMS_STANDBY:
1481
-
case DRM_MODE_DPMS_SUSPEND:
1482
-
case DRM_MODE_DPMS_OFF:
1483
-
args.ucAction = ATOM_DISABLE;
1484
-
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1485
-
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1486
-
args.ucAction = ATOM_LCD_BLOFF;
1487
-
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1488
-
}
1489
-
break;
1490
-
}
1491
-
}
1492
-
1493
-
if (ext_encoder) {
1494
-
switch (mode) {
1495
-
case DRM_MODE_DPMS_ON:
1496
-
default:
1497
-
if (ASIC_IS_DCE41(rdev)) {
1498
-
atombios_external_encoder_setup(encoder, ext_encoder,
1499
-
EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1500
-
atombios_external_encoder_setup(encoder, ext_encoder,
1501
-
EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1502
-
} else
1503
-
atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1504
-
break;
1505
-
case DRM_MODE_DPMS_STANDBY:
1506
-
case DRM_MODE_DPMS_SUSPEND:
1507
-
case DRM_MODE_DPMS_OFF:
1508
-
if (ASIC_IS_DCE41(rdev)) {
1509
-
atombios_external_encoder_setup(encoder, ext_encoder,
1510
-
EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1511
-
atombios_external_encoder_setup(encoder, ext_encoder,
1512
-
EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1513
-
} else
1514
-
atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1515
-
break;
1516
-
}
1517
-
}
1518
-
1519
-
radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1520
-
1521
-
}
1522
-
1523
-
union crtc_source_param {
1524
-
SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1525
-
SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1526
-
};
1527
-
1528
-
static void
1529
-
atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1530
-
{
1531
-
struct drm_device *dev = encoder->dev;
1532
-
struct radeon_device *rdev = dev->dev_private;
1533
-
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1534
-
struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1535
-
union crtc_source_param args;
1536
-
int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1537
-
uint8_t frev, crev;
1538
-
struct radeon_encoder_atom_dig *dig;
1539
-
1540
-
memset(&args, 0, sizeof(args));
1541
-
1542
-
if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1543
-
return;
1544
-
1545
-
switch (frev) {
1546
-
case 1:
1547
-
switch (crev) {
1548
-
case 1:
1549
-
default:
1550
-
if (ASIC_IS_AVIVO(rdev))
1551
-
args.v1.ucCRTC = radeon_crtc->crtc_id;
1552
-
else {
1553
-
if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1554
-
args.v1.ucCRTC = radeon_crtc->crtc_id;
1555
-
} else {
1556
-
args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1557
-
}
1558
-
}
1559
-
switch (radeon_encoder->encoder_id) {
1560
-
case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1561
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1562
-
args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1563
-
break;
1564
-
case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1565
-
case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1566
-
if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1567
-
args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1568
-
else
1569
-
args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1570
-
break;
1571
-
case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1572
-
case ENCODER_OBJECT_ID_INTERNAL_DDI:
1573
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1574
-
args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1575
-
break;
1576
-
case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1577
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1578
-
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1579
-
args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1580
-
else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1581
-
args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1582
-
else
1583
-
args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1584
-
break;
1585
-
case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1586
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1587
-
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1588
-
args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1589
-
else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1590
-
args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1591
-
else
1592
-
args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1593
-
break;
1594
-
}
1595
-
break;
1596
-
case 2:
1597
-
args.v2.ucCRTC = radeon_crtc->crtc_id;
1598
-
if (radeon_encoder_is_dp_bridge(encoder)) {
1599
-
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1600
-
1601
-
if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1602
-
args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1603
-
else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1604
-
args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1605
-
else
1606
-
args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1607
-
} else
1608
-
args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1609
-
switch (radeon_encoder->encoder_id) {
1610
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1611
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1612
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1613
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1614
-
dig = radeon_encoder->enc_priv;
1615
-
switch (dig->dig_encoder) {
1616
-
case 0:
1617
-
args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1618
-
break;
1619
-
case 1:
1620
-
args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1621
-
break;
1622
-
case 2:
1623
-
args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1624
-
break;
1625
-
case 3:
1626
-
args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1627
-
break;
1628
-
case 4:
1629
-
args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1630
-
break;
1631
-
case 5:
1632
-
args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1633
-
break;
1634
-
}
1635
-
break;
1636
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1637
-
args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1638
-
break;
1639
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1640
-
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1641
-
args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1642
-
else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1643
-
args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1644
-
else
1645
-
args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1646
-
break;
1647
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1648
-
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1649
-
args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1650
-
else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1651
-
args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1652
-
else
1653
-
args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1654
-
break;
1655
-
}
1656
-
break;
1657
-
}
1658
-
break;
1659
-
default:
1660
-
DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1661
-
return;
1662
-
}
1663
-
1664
-
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1665
-
1666
-
/* update scratch regs with new routing */
1667
-
radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1668
-
}
1669
-
1670
-
static void
1671
-
atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1672
-
struct drm_display_mode *mode)
1673
-
{
1674
-
struct drm_device *dev = encoder->dev;
1675
-
struct radeon_device *rdev = dev->dev_private;
1676
-
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1677
-
struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1678
-
1679
-
/* Funky macbooks */
1680
-
if ((dev->pdev->device == 0x71C5) &&
1681
-
(dev->pdev->subsystem_vendor == 0x106b) &&
1682
-
(dev->pdev->subsystem_device == 0x0080)) {
1683
-
if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1684
-
uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1685
-
1686
-
lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1687
-
lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1688
-
1689
-
WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1690
-
}
1691
-
}
1692
-
1693
-
/* set scaler clears this on some chips */
1694
-
if (ASIC_IS_AVIVO(rdev) &&
1695
-
(!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1696
-
if (ASIC_IS_DCE4(rdev)) {
1697
-
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1698
-
WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1699
-
EVERGREEN_INTERLEAVE_EN);
1700
-
else
1701
-
WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1702
-
} else {
1703
-
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1704
-
WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1705
-
AVIVO_D1MODE_INTERLEAVE_EN);
1706
-
else
1707
-
WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1708
-
}
1709
-
}
1710
-
}
1711
-
1712
-
static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1713
-
{
1714
-
struct drm_device *dev = encoder->dev;
1715
-
struct radeon_device *rdev = dev->dev_private;
1716
-
struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1717
-
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1718
-
struct drm_encoder *test_encoder;
1719
-
struct radeon_encoder_atom_dig *dig;
1720
-
uint32_t dig_enc_in_use = 0;
1721
-
1722
-
/* DCE4/5 */
1723
-
if (ASIC_IS_DCE4(rdev)) {
1724
-
dig = radeon_encoder->enc_priv;
1725
-
if (ASIC_IS_DCE41(rdev)) {
1726
-
/* ontario follows DCE4 */
1727
-
if (rdev->family == CHIP_PALM) {
1728
-
if (dig->linkb)
1729
-
return 1;
1730
-
else
1731
-
return 0;
1732
-
} else
1733
-
/* llano follows DCE3.2 */
1734
-
return radeon_crtc->crtc_id;
1735
-
} else {
1736
-
switch (radeon_encoder->encoder_id) {
1737
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1738
-
if (dig->linkb)
1739
-
return 1;
1740
-
else
1741
-
return 0;
1742
-
break;
1743
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1744
-
if (dig->linkb)
1745
-
return 3;
1746
-
else
1747
-
return 2;
1748
-
break;
1749
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1750
-
if (dig->linkb)
1751
-
return 5;
1752
-
else
1753
-
return 4;
1754
-
break;
1755
-
}
1756
-
}
1757
-
}
1758
-
1759
-
/* on DCE32 and encoder can driver any block so just crtc id */
1760
-
if (ASIC_IS_DCE32(rdev)) {
1761
-
return radeon_crtc->crtc_id;
1762
-
}
1763
-
1764
-
/* on DCE3 - LVTMA can only be driven by DIGB */
1765
-
list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1766
-
struct radeon_encoder *radeon_test_encoder;
1767
-
1768
-
if (encoder == test_encoder)
1769
-
continue;
1770
-
1771
-
if (!radeon_encoder_is_digital(test_encoder))
1772
-
continue;
1773
-
1774
-
radeon_test_encoder = to_radeon_encoder(test_encoder);
1775
-
dig = radeon_test_encoder->enc_priv;
1776
-
1777
-
if (dig->dig_encoder >= 0)
1778
-
dig_enc_in_use |= (1 << dig->dig_encoder);
1779
-
}
1780
-
1781
-
if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1782
-
if (dig_enc_in_use & 0x2)
1783
-
DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1784
-
return 1;
1785
-
}
1786
-
if (!(dig_enc_in_use & 1))
1787
-
return 0;
1788
-
return 1;
1789
-
}
1790
-
1791
-
/* This only needs to be called once at startup */
1792
-
void
1793
-
radeon_atom_encoder_init(struct radeon_device *rdev)
1794
-
{
1795
-
struct drm_device *dev = rdev->ddev;
1796
-
struct drm_encoder *encoder;
1797
-
1798
-
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1799
-
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1800
-
struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1801
-
1802
-
switch (radeon_encoder->encoder_id) {
1803
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1804
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1805
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1806
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1807
-
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1808
-
break;
1809
-
default:
1810
-
break;
1811
-
}
1812
-
1813
-
if (ext_encoder && ASIC_IS_DCE41(rdev))
1814
-
atombios_external_encoder_setup(encoder, ext_encoder,
1815
-
EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1816
-
}
1817
-
}
1818
-
1819
-
static void
1820
-
radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1821
-
struct drm_display_mode *mode,
1822
-
struct drm_display_mode *adjusted_mode)
1823
-
{
1824
-
struct drm_device *dev = encoder->dev;
1825
-
struct radeon_device *rdev = dev->dev_private;
1826
-
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1827
-
struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1828
-
1829
-
radeon_encoder->pixel_clock = adjusted_mode->clock;
1830
-
1831
-
if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1832
-
if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1833
-
atombios_yuv_setup(encoder, true);
1834
-
else
1835
-
atombios_yuv_setup(encoder, false);
1836
-
}
1837
-
1838
-
switch (radeon_encoder->encoder_id) {
1839
-
case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1840
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1841
-
case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1842
-
case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1843
-
atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1844
-
break;
1845
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1846
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1847
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1848
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1849
-
if (ASIC_IS_DCE4(rdev)) {
1850
-
/* disable the transmitter */
1851
-
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1852
-
/* setup and enable the encoder */
1853
-
atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1854
-
1855
-
/* enable the transmitter */
1856
-
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1857
-
} else {
1858
-
/* disable the encoder and transmitter */
1859
-
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1860
-
atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1861
-
1862
-
/* setup and enable the encoder and transmitter */
1863
-
atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1864
-
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1865
-
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1866
-
}
1867
-
break;
1868
-
case ENCODER_OBJECT_ID_INTERNAL_DDI:
1869
-
case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1870
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1871
-
atombios_dvo_setup(encoder, ATOM_ENABLE);
1872
-
break;
1873
-
case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1874
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1875
-
case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1876
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1877
-
atombios_dac_setup(encoder, ATOM_ENABLE);
1878
-
if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1879
-
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1880
-
atombios_tv_setup(encoder, ATOM_ENABLE);
1881
-
else
1882
-
atombios_tv_setup(encoder, ATOM_DISABLE);
1883
-
}
1884
-
break;
1885
-
}
1886
-
1887
-
if (ext_encoder) {
1888
-
if (ASIC_IS_DCE41(rdev))
1889
-
atombios_external_encoder_setup(encoder, ext_encoder,
1890
-
EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1891
-
else
1892
-
atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1893
-
}
1894
-
1895
-
atombios_apply_encoder_quirks(encoder, adjusted_mode);
1896
-
1897
-
if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1898
-
r600_hdmi_enable(encoder);
1899
-
r600_hdmi_setmode(encoder, adjusted_mode);
1900
-
}
1901
-
}
1902
-
1903
-
static bool
1904
-
atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1905
-
{
1906
-
struct drm_device *dev = encoder->dev;
1907
-
struct radeon_device *rdev = dev->dev_private;
1908
-
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1909
-
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1910
-
1911
-
if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1912
-
ATOM_DEVICE_CV_SUPPORT |
1913
-
ATOM_DEVICE_CRT_SUPPORT)) {
1914
-
DAC_LOAD_DETECTION_PS_ALLOCATION args;
1915
-
int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1916
-
uint8_t frev, crev;
1917
-
1918
-
memset(&args, 0, sizeof(args));
1919
-
1920
-
if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1921
-
return false;
1922
-
1923
-
args.sDacload.ucMisc = 0;
1924
-
1925
-
if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1926
-
(radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1927
-
args.sDacload.ucDacType = ATOM_DAC_A;
1928
-
else
1929
-
args.sDacload.ucDacType = ATOM_DAC_B;
1930
-
1931
-
if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1932
-
args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1933
-
else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1934
-
args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1935
-
else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1936
-
args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1937
-
if (crev >= 3)
1938
-
args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1939
-
} else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1940
-
args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1941
-
if (crev >= 3)
1942
-
args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1943
-
}
1944
-
1945
-
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1946
-
1947
-
return true;
1948
-
} else
1949
-
return false;
1950
-
}
1951
-
1952
-
static enum drm_connector_status
1953
-
radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1954
-
{
1955
-
struct drm_device *dev = encoder->dev;
1956
-
struct radeon_device *rdev = dev->dev_private;
1957
-
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1958
-
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1959
-
uint32_t bios_0_scratch;
1960
-
1961
-
if (!atombios_dac_load_detect(encoder, connector)) {
1962
-
DRM_DEBUG_KMS("detect returned false \n");
1963
-
return connector_status_unknown;
1964
-
}
1965
-
1966
-
if (rdev->family >= CHIP_R600)
1967
-
bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1968
-
else
1969
-
bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1970
-
1971
-
DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1972
-
if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1973
-
if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1974
-
return connector_status_connected;
1975
-
}
1976
-
if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1977
-
if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1978
-
return connector_status_connected;
1979
-
}
1980
-
if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1981
-
if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1982
-
return connector_status_connected;
1983
-
}
1984
-
if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1985
-
if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1986
-
return connector_status_connected; /* CTV */
1987
-
else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1988
-
return connector_status_connected; /* STV */
1989
-
}
1990
-
return connector_status_disconnected;
1991
-
}
1992
-
1993
-
static enum drm_connector_status
1994
-
radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1995
-
{
1996
-
struct drm_device *dev = encoder->dev;
1997
-
struct radeon_device *rdev = dev->dev_private;
1998
-
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1999
-
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2000
-
struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
2001
-
u32 bios_0_scratch;
2002
-
2003
-
if (!ASIC_IS_DCE4(rdev))
2004
-
return connector_status_unknown;
2005
-
2006
-
if (!ext_encoder)
2007
-
return connector_status_unknown;
2008
-
2009
-
if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2010
-
return connector_status_unknown;
2011
-
2012
-
/* load detect on the dp bridge */
2013
-
atombios_external_encoder_setup(encoder, ext_encoder,
2014
-
EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2015
-
2016
-
bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2017
-
2018
-
DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2019
-
if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2020
-
if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2021
-
return connector_status_connected;
2022
-
}
2023
-
if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2024
-
if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2025
-
return connector_status_connected;
2026
-
}
2027
-
if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2028
-
if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2029
-
return connector_status_connected;
2030
-
}
2031
-
if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2032
-
if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2033
-
return connector_status_connected; /* CTV */
2034
-
else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2035
-
return connector_status_connected; /* STV */
2036
-
}
2037
-
return connector_status_disconnected;
2038
-
}
2039
-
2040
-
void
2041
-
radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2042
-
{
2043
-
struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
2044
-
2045
-
if (ext_encoder)
2046
-
/* ddc_setup on the dp bridge */
2047
-
atombios_external_encoder_setup(encoder, ext_encoder,
2048
-
EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2049
-
2050
-
}
2051
-
2052
-
static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2053
-
{
2054
-
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2055
-
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2056
-
2057
-
if ((radeon_encoder->active_device &
2058
-
(ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2059
-
radeon_encoder_is_dp_bridge(encoder)) {
2060
-
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2061
-
if (dig)
2062
-
dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2063
-
}
2064
-
2065
-
radeon_atom_output_lock(encoder, true);
2066
-
radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2067
-
2068
-
if (connector) {
2069
-
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2070
-
2071
-
/* select the clock/data port if it uses a router */
2072
-
if (radeon_connector->router.cd_valid)
2073
-
radeon_router_select_cd_port(radeon_connector);
2074
-
2075
-
/* turn eDP panel on for mode set */
2076
-
if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2077
-
atombios_set_edp_panel_power(connector,
2078
-
ATOM_TRANSMITTER_ACTION_POWER_ON);
2079
-
}
2080
-
2081
-
/* this is needed for the pll/ss setup to work correctly in some cases */
2082
-
atombios_set_encoder_crtc_source(encoder);
2083
-
}
2084
-
2085
-
static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2086
-
{
2087
-
radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2088
-
radeon_atom_output_lock(encoder, false);
2089
-
}
2090
-
2091
-
static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2092
-
{
2093
-
struct drm_device *dev = encoder->dev;
2094
-
struct radeon_device *rdev = dev->dev_private;
2095
-
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2096
-
struct radeon_encoder_atom_dig *dig;
2097
-
2098
-
/* check for pre-DCE3 cards with shared encoders;
2099
-
* can't really use the links individually, so don't disable
2100
-
* the encoder if it's in use by another connector
2101
-
*/
2102
-
if (!ASIC_IS_DCE3(rdev)) {
2103
-
struct drm_encoder *other_encoder;
2104
-
struct radeon_encoder *other_radeon_encoder;
2105
-
2106
-
list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2107
-
other_radeon_encoder = to_radeon_encoder(other_encoder);
2108
-
if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2109
-
drm_helper_encoder_in_use(other_encoder))
2110
-
goto disable_done;
2111
-
}
2112
-
}
2113
-
2114
-
radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2115
-
2116
-
switch (radeon_encoder->encoder_id) {
2117
-
case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2118
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2119
-
case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2120
-
case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2121
-
atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2122
-
break;
2123
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2124
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2125
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2126
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2127
-
if (ASIC_IS_DCE4(rdev))
2128
-
/* disable the transmitter */
2129
-
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2130
-
else {
2131
-
/* disable the encoder and transmitter */
2132
-
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2133
-
atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
2134
-
}
2135
-
break;
2136
-
case ENCODER_OBJECT_ID_INTERNAL_DDI:
2137
-
case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2138
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2139
-
atombios_dvo_setup(encoder, ATOM_DISABLE);
2140
-
break;
2141
-
case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2142
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2143
-
case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2144
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2145
-
atombios_dac_setup(encoder, ATOM_DISABLE);
2146
-
if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2147
-
atombios_tv_setup(encoder, ATOM_DISABLE);
2148
-
break;
2149
-
}
2150
-
2151
-
disable_done:
2152
-
if (radeon_encoder_is_digital(encoder)) {
2153
-
if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2154
-
r600_hdmi_disable(encoder);
2155
-
dig = radeon_encoder->enc_priv;
2156
-
dig->dig_encoder = -1;
2157
-
}
2158
-
radeon_encoder->active_device = 0;
2159
-
}
2160
-
2161
-
/* these are handled by the primary encoders */
2162
-
static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2163
-
{
2164
-
2165
-
}
2166
-
2167
-
static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2168
-
{
2169
-
2170
-
}
2171
-
2172
-
static void
2173
-
radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2174
-
struct drm_display_mode *mode,
2175
-
struct drm_display_mode *adjusted_mode)
2176
-
{
2177
-
2178
-
}
2179
-
2180
-
static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2181
-
{
2182
-
2183
-
}
2184
-
2185
-
static void
2186
-
radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2187
-
{
2188
-
2189
-
}
2190
-
2191
-
static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2192
-
struct drm_display_mode *mode,
2193
-
struct drm_display_mode *adjusted_mode)
2194
-
{
2195
-
return true;
2196
-
}
2197
-
2198
-
static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2199
-
.dpms = radeon_atom_ext_dpms,
2200
-
.mode_fixup = radeon_atom_ext_mode_fixup,
2201
-
.prepare = radeon_atom_ext_prepare,
2202
-
.mode_set = radeon_atom_ext_mode_set,
2203
-
.commit = radeon_atom_ext_commit,
2204
-
.disable = radeon_atom_ext_disable,
2205
-
/* no detect for TMDS/LVDS yet */
2206
-
};
2207
-
2208
-
static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2209
-
.dpms = radeon_atom_encoder_dpms,
2210
-
.mode_fixup = radeon_atom_mode_fixup,
2211
-
.prepare = radeon_atom_encoder_prepare,
2212
-
.mode_set = radeon_atom_encoder_mode_set,
2213
-
.commit = radeon_atom_encoder_commit,
2214
-
.disable = radeon_atom_encoder_disable,
2215
-
.detect = radeon_atom_dig_detect,
2216
-
};
2217
-
2218
-
static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2219
-
.dpms = radeon_atom_encoder_dpms,
2220
-
.mode_fixup = radeon_atom_mode_fixup,
2221
-
.prepare = radeon_atom_encoder_prepare,
2222
-
.mode_set = radeon_atom_encoder_mode_set,
2223
-
.commit = radeon_atom_encoder_commit,
2224
-
.detect = radeon_atom_dac_detect,
2225
-
};
2226
-
2227
-
void radeon_enc_destroy(struct drm_encoder *encoder)
2228
-
{
2229
-
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2230
-
kfree(radeon_encoder->enc_priv);
2231
-
drm_encoder_cleanup(encoder);
2232
-
kfree(radeon_encoder);
2233
-
}
2234
-
2235
-
static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2236
-
.destroy = radeon_enc_destroy,
2237
-
};
2238
-
2239
-
struct radeon_encoder_atom_dac *
2240
-
radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2241
-
{
2242
-
struct drm_device *dev = radeon_encoder->base.dev;
2243
-
struct radeon_device *rdev = dev->dev_private;
2244
-
struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2245
-
2246
-
if (!dac)
2247
-
return NULL;
2248
-
2249
-
dac->tv_std = radeon_atombios_get_tv_info(rdev);
2250
-
return dac;
2251
-
}
2252
-
2253
-
struct radeon_encoder_atom_dig *
2254
-
radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2255
-
{
2256
-
int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2257
-
struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2258
-
2259
-
if (!dig)
2260
-
return NULL;
2261
-
2262
-
/* coherent mode by default */
2263
-
dig->coherent_mode = true;
2264
-
dig->dig_encoder = -1;
2265
-
2266
-
if (encoder_enum == 2)
2267
-
dig->linkb = true;
2268
-
else
2269
-
dig->linkb = false;
2270
-
2271
-
return dig;
2272
-
}
2273
-
2274
-
void
2275
-
radeon_add_atom_encoder(struct drm_device *dev,
2276
-
uint32_t encoder_enum,
2277
-
uint32_t supported_device,
2278
-
u16 caps)
2279
-
{
2280
-
struct radeon_device *rdev = dev->dev_private;
2281
-
struct drm_encoder *encoder;
2282
-
struct radeon_encoder *radeon_encoder;
2283
-
2284
-
/* see if we already added it */
2285
-
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2286
-
radeon_encoder = to_radeon_encoder(encoder);
2287
-
if (radeon_encoder->encoder_enum == encoder_enum) {
2288
-
radeon_encoder->devices |= supported_device;
2289
-
return;
2290
-
}
2291
-
2292
-
}
2293
-
2294
-
/* add a new one */
2295
-
radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2296
-
if (!radeon_encoder)
2297
-
return;
2298
-
2299
-
encoder = &radeon_encoder->base;
2300
-
switch (rdev->num_crtc) {
2301
-
case 1:
2302
-
encoder->possible_crtcs = 0x1;
2303
-
break;
2304
-
case 2:
2305
-
default:
2306
-
encoder->possible_crtcs = 0x3;
2307
-
break;
2308
-
case 4:
2309
-
encoder->possible_crtcs = 0xf;
2310
-
break;
2311
-
case 6:
2312
-
encoder->possible_crtcs = 0x3f;
2313
-
break;
2314
-
}
2315
-
2316
-
radeon_encoder->enc_priv = NULL;
2317
-
2318
-
radeon_encoder->encoder_enum = encoder_enum;
2319
-
radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2320
-
radeon_encoder->devices = supported_device;
2321
-
radeon_encoder->rmx_type = RMX_OFF;
2322
-
radeon_encoder->underscan_type = UNDERSCAN_OFF;
2323
-
radeon_encoder->is_ext_encoder = false;
2324
-
radeon_encoder->caps = caps;
2325
-
2326
-
switch (radeon_encoder->encoder_id) {
2327
-
case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2328
-
case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2329
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2330
-
case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2331
-
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2332
-
radeon_encoder->rmx_type = RMX_FULL;
2333
-
drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2334
-
radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2335
-
} else {
2336
-
drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2337
-
radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2338
-
}
2339
-
drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2340
-
break;
2341
-
case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2342
-
drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2343
-
radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2344
-
drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2345
-
break;
2346
-
case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2347
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2348
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2349
-
drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2350
-
radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2351
-
drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2352
-
break;
2353
-
case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2354
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2355
-
case ENCODER_OBJECT_ID_INTERNAL_DDI:
2356
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2357
-
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2358
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2359
-
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2360
-
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2361
-
radeon_encoder->rmx_type = RMX_FULL;
2362
-
drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2363
-
radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2364
-
} else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2365
-
drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2366
-
radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2367
-
} else {
2368
-
drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2369
-
radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2370
-
}
2371
-
drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2372
-
break;
2373
-
case ENCODER_OBJECT_ID_SI170B:
2374
-
case ENCODER_OBJECT_ID_CH7303:
2375
-
case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2376
-
case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2377
-
case ENCODER_OBJECT_ID_TITFP513:
2378
-
case ENCODER_OBJECT_ID_VT1623:
2379
-
case ENCODER_OBJECT_ID_HDMI_SI1930:
2380
-
case ENCODER_OBJECT_ID_TRAVIS:
2381
-
case ENCODER_OBJECT_ID_NUTMEG:
2382
-
/* these are handled by the primary encoders */
2383
-
radeon_encoder->is_ext_encoder = true;
2384
-
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2385
-
drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2386
-
else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2387
-
drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2388
-
else
2389
-
drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2390
-
drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2391
-
break;
2392
-
}
2393
-
}
+43
-28
drivers/gpu/drm/radeon/radeon_gart.c
+43
-28
drivers/gpu/drm/radeon/radeon_gart.c
···
49
49
rdev->gart.table_size >> PAGE_SHIFT);
50
50
}
51
51
#endif
52
-
rdev->gart.table.ram.ptr = ptr;
53
-
memset((void *)rdev->gart.table.ram.ptr, 0, rdev->gart.table_size);
52
+
rdev->gart.ptr = ptr;
53
+
memset((void *)rdev->gart.ptr, 0, rdev->gart.table_size);
54
54
return 0;
55
55
}
56
56
57
57
void radeon_gart_table_ram_free(struct radeon_device *rdev)
58
58
{
59
-
if (rdev->gart.table.ram.ptr == NULL) {
59
+
if (rdev->gart.ptr == NULL) {
60
60
return;
61
61
}
62
62
#ifdef CONFIG_X86
63
63
if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
64
64
rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
65
-
set_memory_wb((unsigned long)rdev->gart.table.ram.ptr,
65
+
set_memory_wb((unsigned long)rdev->gart.ptr,
66
66
rdev->gart.table_size >> PAGE_SHIFT);
67
67
}
68
68
#endif
69
69
pci_free_consistent(rdev->pdev, rdev->gart.table_size,
70
-
(void *)rdev->gart.table.ram.ptr,
70
+
(void *)rdev->gart.ptr,
71
71
rdev->gart.table_addr);
72
-
rdev->gart.table.ram.ptr = NULL;
72
+
rdev->gart.ptr = NULL;
73
73
rdev->gart.table_addr = 0;
74
74
}
75
75
···
77
77
{
78
78
int r;
79
79
80
-
if (rdev->gart.table.vram.robj == NULL) {
80
+
if (rdev->gart.robj == NULL) {
81
81
r = radeon_bo_create(rdev, rdev->gart.table_size,
82
82
PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
83
-
&rdev->gart.table.vram.robj);
83
+
&rdev->gart.robj);
84
84
if (r) {
85
85
return r;
86
86
}
···
93
93
uint64_t gpu_addr;
94
94
int r;
95
95
96
-
r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
96
+
r = radeon_bo_reserve(rdev->gart.robj, false);
97
97
if (unlikely(r != 0))
98
98
return r;
99
-
r = radeon_bo_pin(rdev->gart.table.vram.robj,
99
+
r = radeon_bo_pin(rdev->gart.robj,
100
100
RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
101
101
if (r) {
102
-
radeon_bo_unreserve(rdev->gart.table.vram.robj);
102
+
radeon_bo_unreserve(rdev->gart.robj);
103
103
return r;
104
104
}
105
-
r = radeon_bo_kmap(rdev->gart.table.vram.robj,
106
-
(void **)&rdev->gart.table.vram.ptr);
105
+
r = radeon_bo_kmap(rdev->gart.robj, &rdev->gart.ptr);
107
106
if (r)
108
-
radeon_bo_unpin(rdev->gart.table.vram.robj);
109
-
radeon_bo_unreserve(rdev->gart.table.vram.robj);
107
+
radeon_bo_unpin(rdev->gart.robj);
108
+
radeon_bo_unreserve(rdev->gart.robj);
110
109
rdev->gart.table_addr = gpu_addr;
111
110
return r;
112
111
}
113
112
114
-
void radeon_gart_table_vram_free(struct radeon_device *rdev)
113
+
void radeon_gart_table_vram_unpin(struct radeon_device *rdev)
115
114
{
116
115
int r;
117
116
118
-
if (rdev->gart.table.vram.robj == NULL) {
117
+
if (rdev->gart.robj == NULL) {
119
118
return;
120
119
}
121
-
r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
120
+
r = radeon_bo_reserve(rdev->gart.robj, false);
122
121
if (likely(r == 0)) {
123
-
radeon_bo_kunmap(rdev->gart.table.vram.robj);
124
-
radeon_bo_unpin(rdev->gart.table.vram.robj);
125
-
radeon_bo_unreserve(rdev->gart.table.vram.robj);
122
+
radeon_bo_kunmap(rdev->gart.robj);
123
+
radeon_bo_unpin(rdev->gart.robj);
124
+
radeon_bo_unreserve(rdev->gart.robj);
125
+
rdev->gart.ptr = NULL;
126
126
}
127
-
radeon_bo_unref(&rdev->gart.table.vram.robj);
127
+
}
128
+
129
+
void radeon_gart_table_vram_free(struct radeon_device *rdev)
130
+
{
131
+
if (rdev->gart.robj == NULL) {
132
+
return;
133
+
}
134
+
radeon_gart_table_vram_unpin(rdev);
135
+
radeon_bo_unref(&rdev->gart.robj);
128
136
}
129
137
130
138
···
159
151
if (rdev->gart.pages[p]) {
160
152
if (!rdev->gart.ttm_alloced[p])
161
153
pci_unmap_page(rdev->pdev, rdev->gart.pages_addr[p],
162
-
PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
154
+
PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
163
155
rdev->gart.pages[p] = NULL;
164
156
rdev->gart.pages_addr[p] = rdev->dummy_page.addr;
165
157
page_base = rdev->gart.pages_addr[p];
166
158
for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
167
-
radeon_gart_set_page(rdev, t, page_base);
159
+
if (rdev->gart.ptr) {
160
+
radeon_gart_set_page(rdev, t, page_base);
161
+
}
168
162
page_base += RADEON_GPU_PAGE_SIZE;
169
163
}
170
164
}
···
209
199
}
210
200
}
211
201
rdev->gart.pages[p] = pagelist[i];
212
-
page_base = rdev->gart.pages_addr[p];
213
-
for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
214
-
radeon_gart_set_page(rdev, t, page_base);
215
-
page_base += RADEON_GPU_PAGE_SIZE;
202
+
if (rdev->gart.ptr) {
203
+
page_base = rdev->gart.pages_addr[p];
204
+
for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
205
+
radeon_gart_set_page(rdev, t, page_base);
206
+
page_base += RADEON_GPU_PAGE_SIZE;
207
+
}
216
208
}
217
209
}
218
210
mb();
···
227
215
int i, j, t;
228
216
u64 page_base;
229
217
218
+
if (!rdev->gart.ptr) {
219
+
return;
220
+
}
230
221
for (i = 0, t = 0; i < rdev->gart.num_cpu_pages; i++) {
231
222
page_base = rdev->gart.pages_addr[i];
232
223
for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
+11
-17
drivers/gpu/drm/radeon/radeon_i2c.c
+11
-17
drivers/gpu/drm/radeon/radeon_i2c.c
···
34
34
* radeon_ddc_probe
35
35
*
36
36
*/
37
-
bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool requires_extended_probe)
37
+
bool radeon_ddc_probe(struct radeon_connector *radeon_connector)
38
38
{
39
39
u8 out = 0x0;
40
40
u8 buf[8];
···
49
49
{
50
50
.addr = 0x50,
51
51
.flags = I2C_M_RD,
52
-
.len = 1,
52
+
.len = 8,
53
53
.buf = buf,
54
54
}
55
55
};
56
-
57
-
/* Read 8 bytes from i2c for extended probe of EDID header */
58
-
if (requires_extended_probe)
59
-
msgs[1].len = 8;
60
56
61
57
/* on hw with routers, select right port */
62
58
if (radeon_connector->router.ddc_valid)
···
62
66
if (ret != 2)
63
67
/* Couldn't find an accessible DDC on this connector */
64
68
return false;
65
-
if (requires_extended_probe) {
66
-
/* Probe also for valid EDID header
67
-
* EDID header starts with:
68
-
* 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
69
-
* Only the first 6 bytes must be valid as
70
-
* drm_edid_block_valid() can fix the last 2 bytes */
71
-
if (drm_edid_header_is_valid(buf) < 6) {
72
-
/* Couldn't find an accessible EDID on this
73
-
* connector */
74
-
return false;
75
-
}
69
+
/* Probe also for valid EDID header
70
+
* EDID header starts with:
71
+
* 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
72
+
* Only the first 6 bytes must be valid as
73
+
* drm_edid_block_valid() can fix the last 2 bytes */
74
+
if (drm_edid_header_is_valid(buf) < 6) {
75
+
/* Couldn't find an accessible EDID on this
76
+
* connector */
77
+
return false;
76
78
}
77
79
return true;
78
80
}
+48
-12
drivers/gpu/drm/radeon/radeon_irq_kms.c
+48
-12
drivers/gpu/drm/radeon/radeon_irq_kms.c
···
67
67
/* Disable *all* interrupts */
68
68
rdev->irq.sw_int = false;
69
69
rdev->irq.gui_idle = false;
70
-
for (i = 0; i < rdev->num_crtc; i++)
71
-
rdev->irq.crtc_vblank_int[i] = false;
72
-
for (i = 0; i < 6; i++) {
70
+
for (i = 0; i < RADEON_MAX_HPD_PINS; i++)
73
71
rdev->irq.hpd[i] = false;
72
+
for (i = 0; i < RADEON_MAX_CRTCS; i++) {
73
+
rdev->irq.crtc_vblank_int[i] = false;
74
74
rdev->irq.pflip[i] = false;
75
75
}
76
76
radeon_irq_set(rdev);
···
99
99
/* Disable *all* interrupts */
100
100
rdev->irq.sw_int = false;
101
101
rdev->irq.gui_idle = false;
102
-
for (i = 0; i < rdev->num_crtc; i++)
103
-
rdev->irq.crtc_vblank_int[i] = false;
104
-
for (i = 0; i < 6; i++) {
102
+
for (i = 0; i < RADEON_MAX_HPD_PINS; i++)
105
103
rdev->irq.hpd[i] = false;
104
+
for (i = 0; i < RADEON_MAX_CRTCS; i++) {
105
+
rdev->irq.crtc_vblank_int[i] = false;
106
106
rdev->irq.pflip[i] = false;
107
107
}
108
108
radeon_irq_set(rdev);
109
+
}
110
+
111
+
static bool radeon_msi_ok(struct radeon_device *rdev)
112
+
{
113
+
/* RV370/RV380 was first asic with MSI support */
114
+
if (rdev->family < CHIP_RV380)
115
+
return false;
116
+
117
+
/* MSIs don't work on AGP */
118
+
if (rdev->flags & RADEON_IS_AGP)
119
+
return false;
120
+
121
+
/* force MSI on */
122
+
if (radeon_msi == 1)
123
+
return true;
124
+
else if (radeon_msi == 0)
125
+
return false;
126
+
127
+
/* Quirks */
128
+
/* HP RS690 only seems to work with MSIs. */
129
+
if ((rdev->pdev->device == 0x791f) &&
130
+
(rdev->pdev->subsystem_vendor == 0x103c) &&
131
+
(rdev->pdev->subsystem_device == 0x30c2))
132
+
return true;
133
+
134
+
/* Dell RS690 only seems to work with MSIs. */
135
+
if ((rdev->pdev->device == 0x791f) &&
136
+
(rdev->pdev->subsystem_vendor == 0x1028) &&
137
+
(rdev->pdev->subsystem_device == 0x01fd))
138
+
return true;
139
+
140
+
if (rdev->flags & RADEON_IS_IGP) {
141
+
/* APUs work fine with MSIs */
142
+
if (rdev->family >= CHIP_PALM)
143
+
return true;
144
+
/* lots of IGPs have problems with MSIs */
145
+
return false;
146
+
}
147
+
148
+
return true;
109
149
}
110
150
111
151
int radeon_irq_kms_init(struct radeon_device *rdev)
···
164
124
}
165
125
/* enable msi */
166
126
rdev->msi_enabled = 0;
167
-
/* MSIs don't seem to work reliably on all IGP
168
-
* chips. Disable MSI on them for now.
169
-
*/
170
-
if ((rdev->family >= CHIP_RV380) &&
171
-
((!(rdev->flags & RADEON_IS_IGP)) || (rdev->family >= CHIP_PALM)) &&
172
-
(!(rdev->flags & RADEON_IS_AGP))) {
127
+
128
+
if (radeon_msi_ok(rdev)) {
173
129
int ret = pci_enable_msi(rdev->pdev);
174
130
if (!ret) {
175
131
rdev->msi_enabled = 1;
+6
-8
drivers/gpu/drm/radeon/radeon_mode.h
+6
-8
drivers/gpu/drm/radeon/radeon_mode.h
···
438
438
struct radeon_i2c_chan *ddc_bus;
439
439
/* some systems have an hdmi and vga port with a shared ddc line */
440
440
bool shared_ddc;
441
-
/* for some Radeon chip families we apply an additional EDID header
442
-
check as part of the DDC probe */
443
-
bool requires_extended_probe;
444
441
bool use_digital;
445
442
/* we need to mind the EDID between detect
446
443
and get modes due to analog/digital/tvencoder */
···
456
459
struct drm_gem_object *obj;
457
460
};
458
461
462
+
#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
463
+
((em) == ATOM_ENCODER_MODE_DP_MST))
459
464
460
465
extern enum radeon_tv_std
461
466
radeon_combios_get_tv_info(struct radeon_device *rdev);
···
467
468
extern struct drm_connector *
468
469
radeon_get_connector_for_encoder(struct drm_encoder *encoder);
469
470
470
-
extern bool radeon_encoder_is_dp_bridge(struct drm_encoder *encoder);
471
-
extern bool radeon_connector_encoder_is_dp_bridge(struct drm_connector *connector);
471
+
extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
472
+
extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
472
473
extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector);
473
474
extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
474
475
···
488
489
int action, uint8_t lane_num,
489
490
uint8_t lane_set);
490
491
extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
491
-
extern struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder);
492
+
extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
492
493
extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
493
494
u8 write_byte, u8 *read_byte);
494
495
···
518
519
u8 val);
519
520
extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
520
521
extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
521
-
extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector,
522
-
bool requires_extended_probe);
522
+
extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
523
523
extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
524
524
525
525
extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
+3
-2
drivers/gpu/drm/radeon/rs400.c
+3
-2
drivers/gpu/drm/radeon/rs400.c
···
77
77
{
78
78
int r;
79
79
80
-
if (rdev->gart.table.ram.ptr) {
80
+
if (rdev->gart.ptr) {
81
81
WARN(1, "RS400 GART already initialized\n");
82
82
return 0;
83
83
}
···
212
212
int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
213
213
{
214
214
uint32_t entry;
215
+
u32 *gtt = rdev->gart.ptr;
215
216
216
217
if (i < 0 || i > rdev->gart.num_gpu_pages) {
217
218
return -EINVAL;
···
222
221
((upper_32_bits(addr) & 0xff) << 4) |
223
222
RS400_PTE_WRITEABLE | RS400_PTE_READABLE;
224
223
entry = cpu_to_le32(entry);
225
-
rdev->gart.table.ram.ptr[i] = entry;
224
+
gtt[i] = entry;
226
225
return 0;
227
226
}
228
227
+5
-12
drivers/gpu/drm/radeon/rs600.c
+5
-12
drivers/gpu/drm/radeon/rs600.c
···
287
287
default:
288
288
break;
289
289
}
290
+
radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
290
291
}
291
292
if (rdev->irq.installed)
292
293
rs600_irq_set(rdev);
···
414
413
{
415
414
int r;
416
415
417
-
if (rdev->gart.table.vram.robj) {
416
+
if (rdev->gart.robj) {
418
417
WARN(1, "RS600 GART already initialized\n");
419
418
return 0;
420
419
}
···
432
431
u32 tmp;
433
432
int r, i;
434
433
435
-
if (rdev->gart.table.vram.robj == NULL) {
434
+
if (rdev->gart.robj == NULL) {
436
435
dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
437
436
return -EINVAL;
438
437
}
···
495
494
void rs600_gart_disable(struct radeon_device *rdev)
496
495
{
497
496
u32 tmp;
498
-
int r;
499
497
500
498
/* FIXME: disable out of gart access */
501
499
WREG32_MC(R_000100_MC_PT0_CNTL, 0);
502
500
tmp = RREG32_MC(R_000009_MC_CNTL1);
503
501
WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
504
-
if (rdev->gart.table.vram.robj) {
505
-
r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
506
-
if (r == 0) {
507
-
radeon_bo_kunmap(rdev->gart.table.vram.robj);
508
-
radeon_bo_unpin(rdev->gart.table.vram.robj);
509
-
radeon_bo_unreserve(rdev->gart.table.vram.robj);
510
-
}
511
-
}
502
+
radeon_gart_table_vram_unpin(rdev);
512
503
}
513
504
514
505
void rs600_gart_fini(struct radeon_device *rdev)
···
518
525
519
526
int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
520
527
{
521
-
void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
528
+
void __iomem *ptr = (void *)rdev->gart.ptr;
522
529
523
530
if (i < 0 || i > rdev->gart.num_gpu_pages) {
524
531
return -EINVAL;
+10
-63
drivers/gpu/drm/radeon/rv770.c
+10
-63
drivers/gpu/drm/radeon/rv770.c
···
124
124
u32 tmp;
125
125
int r, i;
126
126
127
-
if (rdev->gart.table.vram.robj == NULL) {
127
+
if (rdev->gart.robj == NULL) {
128
128
dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
129
129
return -EINVAL;
130
130
}
···
171
171
void rv770_pcie_gart_disable(struct radeon_device *rdev)
172
172
{
173
173
u32 tmp;
174
-
int i, r;
174
+
int i;
175
175
176
176
/* Disable all tables */
177
177
for (i = 0; i < 7; i++)
···
191
191
WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
192
192
WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
193
193
WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
194
-
if (rdev->gart.table.vram.robj) {
195
-
r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
196
-
if (likely(r == 0)) {
197
-
radeon_bo_kunmap(rdev->gart.table.vram.robj);
198
-
radeon_bo_unpin(rdev->gart.table.vram.robj);
199
-
radeon_bo_unreserve(rdev->gart.table.vram.robj);
200
-
}
201
-
}
194
+
radeon_gart_table_vram_unpin(rdev);
202
195
}
203
196
204
197
void rv770_pcie_gart_fini(struct radeon_device *rdev)
···
275
282
WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
276
283
rdev->mc.vram_end >> 12);
277
284
}
278
-
WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
285
+
WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
279
286
tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
280
287
tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
281
288
WREG32(MC_VM_FB_LOCATION, tmp);
···
952
959
953
960
}
954
961
955
-
static int rv770_vram_scratch_init(struct radeon_device *rdev)
956
-
{
957
-
int r;
958
-
u64 gpu_addr;
959
-
960
-
if (rdev->vram_scratch.robj == NULL) {
961
-
r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
962
-
PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
963
-
&rdev->vram_scratch.robj);
964
-
if (r) {
965
-
return r;
966
-
}
967
-
}
968
-
969
-
r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
970
-
if (unlikely(r != 0))
971
-
return r;
972
-
r = radeon_bo_pin(rdev->vram_scratch.robj,
973
-
RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
974
-
if (r) {
975
-
radeon_bo_unreserve(rdev->vram_scratch.robj);
976
-
return r;
977
-
}
978
-
r = radeon_bo_kmap(rdev->vram_scratch.robj,
979
-
(void **)&rdev->vram_scratch.ptr);
980
-
if (r)
981
-
radeon_bo_unpin(rdev->vram_scratch.robj);
982
-
radeon_bo_unreserve(rdev->vram_scratch.robj);
983
-
984
-
return r;
985
-
}
986
-
987
-
static void rv770_vram_scratch_fini(struct radeon_device *rdev)
988
-
{
989
-
int r;
990
-
991
-
if (rdev->vram_scratch.robj == NULL) {
992
-
return;
993
-
}
994
-
r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
995
-
if (likely(r == 0)) {
996
-
radeon_bo_kunmap(rdev->vram_scratch.robj);
997
-
radeon_bo_unpin(rdev->vram_scratch.robj);
998
-
radeon_bo_unreserve(rdev->vram_scratch.robj);
999
-
}
1000
-
radeon_bo_unref(&rdev->vram_scratch.robj);
1001
-
}
1002
-
1003
962
void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1004
963
{
1005
964
u64 size_bf, size_af;
···
1051
1106
}
1052
1107
}
1053
1108
1109
+
r = r600_vram_scratch_init(rdev);
1110
+
if (r)
1111
+
return r;
1112
+
1054
1113
rv770_mc_program(rdev);
1055
1114
if (rdev->flags & RADEON_IS_AGP) {
1056
1115
rv770_agp_enable(rdev);
···
1063
1114
if (r)
1064
1115
return r;
1065
1116
}
1066
-
r = rv770_vram_scratch_init(rdev);
1067
-
if (r)
1068
-
return r;
1117
+
1069
1118
rv770_gpu_init(rdev);
1070
1119
r = r600_blit_init(rdev);
1071
1120
if (r) {
···
1263
1316
radeon_ib_pool_fini(rdev);
1264
1317
radeon_irq_kms_fini(rdev);
1265
1318
rv770_pcie_gart_fini(rdev);
1266
-
rv770_vram_scratch_fini(rdev);
1319
+
r600_vram_scratch_fini(rdev);
1267
1320
radeon_gem_fini(rdev);
1268
1321
radeon_fence_driver_fini(rdev);
1269
1322
radeon_agp_fini(rdev);
+6
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
+6
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
···
104
104
#define DRM_IOCTL_VMW_PRESENT_READBACK \
105
105
DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
106
106
struct drm_vmw_present_readback_arg)
107
+
#define DRM_IOCTL_VMW_UPDATE_LAYOUT \
108
+
DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
109
+
struct drm_vmw_update_layout_arg)
107
110
108
111
/**
109
112
* The core DRM version of this macro doesn't account for
···
169
166
VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
170
167
vmw_present_readback_ioctl,
171
168
DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
169
+
VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
170
+
vmw_kms_update_layout_ioctl,
171
+
DRM_MASTER | DRM_UNLOCKED),
172
172
};
173
173
174
174
static struct pci_device_id vmw_pci_id_list[] = {
+4
-2
drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
+4
-2
drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
···
40
40
#include "ttm/ttm_module.h"
41
41
#include "vmwgfx_fence.h"
42
42
43
-
#define VMWGFX_DRIVER_DATE "20111008"
43
+
#define VMWGFX_DRIVER_DATE "20111025"
44
44
#define VMWGFX_DRIVER_MAJOR 2
45
-
#define VMWGFX_DRIVER_MINOR 2
45
+
#define VMWGFX_DRIVER_MINOR 3
46
46
#define VMWGFX_DRIVER_PATCHLEVEL 0
47
47
#define VMWGFX_FILE_PAGE_OFFSET 0x00100000
48
48
#define VMWGFX_FIFO_STATIC_SIZE (1024*1024)
···
633
633
struct drm_vmw_fence_rep __user *user_fence_rep,
634
634
struct drm_vmw_rect *clips,
635
635
uint32_t num_clips);
636
+
int vmw_kms_update_layout_ioctl(struct drm_device *dev, void *data,
637
+
struct drm_file *file_priv);
636
638
637
639
/**
638
640
* Overlay control - vmwgfx_overlay.c
+132
-21
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+132
-21
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
···
111
111
if (!ret) {
112
112
if (!surface->snooper.image) {
113
113
DRM_ERROR("surface not suitable for cursor\n");
114
+
vmw_surface_unreference(&surface);
114
115
return -EINVAL;
115
116
}
116
117
} else {
···
177
176
return 0;
178
177
}
179
178
180
-
vmw_cursor_update_position(dev_priv, true, du->cursor_x, du->cursor_y);
179
+
vmw_cursor_update_position(dev_priv, true,
180
+
du->cursor_x + du->hotspot_x,
181
+
du->cursor_y + du->hotspot_y);
181
182
182
183
return 0;
183
184
}
···
194
191
du->cursor_y = y + crtc->y;
195
192
196
193
vmw_cursor_update_position(dev_priv, shown,
197
-
du->cursor_x, du->cursor_y);
194
+
du->cursor_x + du->hotspot_x,
195
+
du->cursor_y + du->hotspot_y);
198
196
199
197
return 0;
200
198
}
···
216
212
SVGA3dCmdHeader header;
217
213
SVGA3dCmdSurfaceDMA dma;
218
214
} *cmd;
219
-
int ret;
215
+
int i, ret;
220
216
221
217
cmd = container_of(header, struct vmw_dma_cmd, header);
222
218
···
238
234
box_count = (cmd->header.size - sizeof(SVGA3dCmdSurfaceDMA)) /
239
235
sizeof(SVGA3dCopyBox);
240
236
241
-
if (cmd->dma.guest.pitch != (64 * 4) ||
242
-
cmd->dma.guest.ptr.offset % PAGE_SIZE ||
237
+
if (cmd->dma.guest.ptr.offset % PAGE_SIZE ||
243
238
box->x != 0 || box->y != 0 || box->z != 0 ||
244
239
box->srcx != 0 || box->srcy != 0 || box->srcz != 0 ||
245
-
box->w != 64 || box->h != 64 || box->d != 1 ||
246
-
box_count != 1) {
240
+
box->d != 1 || box_count != 1) {
247
241
/* TODO handle none page aligned offsets */
248
-
/* TODO handle partial uploads and pitch != 256 */
249
-
/* TODO handle more then one copy (size != 64) */
250
-
DRM_ERROR("lazy programmer, can't handle weird stuff\n");
242
+
/* TODO handle more dst & src != 0 */
243
+
/* TODO handle more then one copy */
244
+
DRM_ERROR("Cant snoop dma request for cursor!\n");
245
+
DRM_ERROR("(%u, %u, %u) (%u, %u, %u) (%ux%ux%u) %u %u\n",
246
+
box->srcx, box->srcy, box->srcz,
247
+
box->x, box->y, box->z,
248
+
box->w, box->h, box->d, box_count,
249
+
cmd->dma.guest.ptr.offset);
251
250
return;
252
251
}
253
252
···
269
262
270
263
virtual = ttm_kmap_obj_virtual(&map, &dummy);
271
264
272
-
memcpy(srf->snooper.image, virtual, 64*64*4);
265
+
if (box->w == 64 && cmd->dma.guest.pitch == 64*4) {
266
+
memcpy(srf->snooper.image, virtual, 64*64*4);
267
+
} else {
268
+
/* Image is unsigned pointer. */
269
+
for (i = 0; i < box->h; i++)
270
+
memcpy(srf->snooper.image + i * 64,
271
+
virtual + i * cmd->dma.guest.pitch,
272
+
box->w * 4);
273
+
}
274
+
273
275
srf->snooper.age++;
274
276
275
277
/* we can't call this function from this function since execbuf has
···
1010
994
required_size = mode_cmd->pitch * mode_cmd->height;
1011
995
if (unlikely(required_size > (u64) dev_priv->vram_size)) {
1012
996
DRM_ERROR("VRAM size is too small for requested mode.\n");
1013
-
return NULL;
997
+
return ERR_PTR(-ENOMEM);
1014
998
}
1015
999
1016
1000
/*
···
1533
1517
du->pref_width = rects[du->unit].w;
1534
1518
du->pref_height = rects[du->unit].h;
1535
1519
du->pref_active = true;
1520
+
du->gui_x = rects[du->unit].x;
1521
+
du->gui_y = rects[du->unit].y;
1536
1522
} else {
1537
1523
du->pref_width = 800;
1538
1524
du->pref_height = 600;
···
1590
1572
uint32_t num_displays;
1591
1573
struct drm_device *dev = connector->dev;
1592
1574
struct vmw_private *dev_priv = vmw_priv(dev);
1575
+
struct vmw_display_unit *du = vmw_connector_to_du(connector);
1593
1576
1594
1577
mutex_lock(&dev_priv->hw_mutex);
1595
1578
num_displays = vmw_read(dev_priv, SVGA_REG_NUM_DISPLAYS);
1596
1579
mutex_unlock(&dev_priv->hw_mutex);
1597
1580
1598
-
return ((vmw_connector_to_du(connector)->unit < num_displays) ?
1581
+
return ((vmw_connector_to_du(connector)->unit < num_displays &&
1582
+
du->pref_active) ?
1599
1583
connector_status_connected : connector_status_disconnected);
1600
1584
}
1601
1585
···
1678
1658
{ DRM_MODE("", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) },
1679
1659
};
1680
1660
1661
+
/**
1662
+
* vmw_guess_mode_timing - Provide fake timings for a
1663
+
* 60Hz vrefresh mode.
1664
+
*
1665
+
* @mode - Pointer to a struct drm_display_mode with hdisplay and vdisplay
1666
+
* members filled in.
1667
+
*/
1668
+
static void vmw_guess_mode_timing(struct drm_display_mode *mode)
1669
+
{
1670
+
mode->hsync_start = mode->hdisplay + 50;
1671
+
mode->hsync_end = mode->hsync_start + 50;
1672
+
mode->htotal = mode->hsync_end + 50;
1673
+
1674
+
mode->vsync_start = mode->vdisplay + 50;
1675
+
mode->vsync_end = mode->vsync_start + 50;
1676
+
mode->vtotal = mode->vsync_end + 50;
1677
+
1678
+
mode->clock = (u32)mode->htotal * (u32)mode->vtotal / 100 * 6;
1679
+
mode->vrefresh = drm_mode_vrefresh(mode);
1680
+
}
1681
+
1682
+
1681
1683
int vmw_du_connector_fill_modes(struct drm_connector *connector,
1682
1684
uint32_t max_width, uint32_t max_height)
1683
1685
{
···
1722
1680
return 0;
1723
1681
mode->hdisplay = du->pref_width;
1724
1682
mode->vdisplay = du->pref_height;
1725
-
mode->vrefresh = drm_mode_vrefresh(mode);
1683
+
vmw_guess_mode_timing(mode);
1684
+
1726
1685
if (vmw_kms_validate_mode_vram(dev_priv, mode->hdisplay * 2,
1727
1686
mode->vdisplay)) {
1728
1687
drm_mode_probed_add(connector, mode);
1729
-
1730
-
if (du->pref_mode) {
1731
-
list_del_init(&du->pref_mode->head);
1732
-
drm_mode_destroy(dev, du->pref_mode);
1733
-
}
1734
-
1735
-
du->pref_mode = mode;
1688
+
} else {
1689
+
drm_mode_destroy(dev, mode);
1690
+
mode = NULL;
1736
1691
}
1692
+
1693
+
if (du->pref_mode) {
1694
+
list_del_init(&du->pref_mode->head);
1695
+
drm_mode_destroy(dev, du->pref_mode);
1696
+
}
1697
+
1698
+
/* mode might be null here, this is intended */
1699
+
du->pref_mode = mode;
1737
1700
}
1738
1701
1739
1702
for (i = 0; vmw_kms_connector_builtin[i].type != 0; i++) {
···
1759
1712
drm_mode_probed_add(connector, mode);
1760
1713
}
1761
1714
1715
+
/* Move the prefered mode first, help apps pick the right mode. */
1716
+
if (du->pref_mode)
1717
+
list_move(&du->pref_mode->head, &connector->probed_modes);
1718
+
1762
1719
drm_mode_connector_list_update(connector);
1763
1720
1764
1721
return 1;
···
1773
1722
uint64_t val)
1774
1723
{
1775
1724
return 0;
1725
+
}
1726
+
1727
+
1728
+
int vmw_kms_update_layout_ioctl(struct drm_device *dev, void *data,
1729
+
struct drm_file *file_priv)
1730
+
{
1731
+
struct vmw_private *dev_priv = vmw_priv(dev);
1732
+
struct drm_vmw_update_layout_arg *arg =
1733
+
(struct drm_vmw_update_layout_arg *)data;
1734
+
struct vmw_master *vmaster = vmw_master(file_priv->master);
1735
+
void __user *user_rects;
1736
+
struct drm_vmw_rect *rects;
1737
+
unsigned rects_size;
1738
+
int ret;
1739
+
int i;
1740
+
struct drm_mode_config *mode_config = &dev->mode_config;
1741
+
1742
+
ret = ttm_read_lock(&vmaster->lock, true);
1743
+
if (unlikely(ret != 0))
1744
+
return ret;
1745
+
1746
+
if (!arg->num_outputs) {
1747
+
struct drm_vmw_rect def_rect = {0, 0, 800, 600};
1748
+
vmw_du_update_layout(dev_priv, 1, &def_rect);
1749
+
goto out_unlock;
1750
+
}
1751
+
1752
+
rects_size = arg->num_outputs * sizeof(struct drm_vmw_rect);
1753
+
rects = kzalloc(rects_size, GFP_KERNEL);
1754
+
if (unlikely(!rects)) {
1755
+
ret = -ENOMEM;
1756
+
goto out_unlock;
1757
+
}
1758
+
1759
+
user_rects = (void __user *)(unsigned long)arg->rects;
1760
+
ret = copy_from_user(rects, user_rects, rects_size);
1761
+
if (unlikely(ret != 0)) {
1762
+
DRM_ERROR("Failed to get rects.\n");
1763
+
ret = -EFAULT;
1764
+
goto out_free;
1765
+
}
1766
+
1767
+
for (i = 0; i < arg->num_outputs; ++i) {
1768
+
if (rects->x < 0 ||
1769
+
rects->y < 0 ||
1770
+
rects->x + rects->w > mode_config->max_width ||
1771
+
rects->y + rects->h > mode_config->max_height) {
1772
+
DRM_ERROR("Invalid GUI layout.\n");
1773
+
ret = -EINVAL;
1774
+
goto out_free;
1775
+
}
1776
+
}
1777
+
1778
+
vmw_du_update_layout(dev_priv, arg->num_outputs, rects);
1779
+
1780
+
out_free:
1781
+
kfree(rects);
1782
+
out_unlock:
1783
+
ttm_read_unlock(&vmaster->lock);
1784
+
return ret;
1776
1785
}
+8
-2
drivers/gpu/drm/vmwgfx/vmwgfx_kms.h
+8
-2
drivers/gpu/drm/vmwgfx/vmwgfx_kms.h
···
96
96
unsigned pref_height;
97
97
bool pref_active;
98
98
struct drm_display_mode *pref_mode;
99
+
100
+
/*
101
+
* Gui positioning
102
+
*/
103
+
int gui_x;
104
+
int gui_y;
105
+
bool is_implicit;
99
106
};
100
107
101
108
#define vmw_crtc_to_du(x) \
···
133
126
int vmw_du_connector_set_property(struct drm_connector *connector,
134
127
struct drm_property *property,
135
128
uint64_t val);
136
-
int vmw_du_update_layout(struct vmw_private *dev_priv, unsigned num,
137
-
struct drm_vmw_rect *rects);
129
+
138
130
139
131
/*
140
132
* Legacy display unit functions - vmwgfx_ldu.c
+3
-2
drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
+3
-2
drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
···
337
337
ldu->base.pref_width = 800;
338
338
ldu->base.pref_height = 600;
339
339
ldu->base.pref_mode = NULL;
340
+
ldu->base.is_implicit = true;
340
341
341
342
drm_connector_init(dev, connector, &vmw_legacy_connector_funcs,
342
-
DRM_MODE_CONNECTOR_LVDS);
343
+
DRM_MODE_CONNECTOR_VIRTUAL);
343
344
connector->status = vmw_du_connector_detect(connector, true);
344
345
345
346
drm_encoder_init(dev, encoder, &vmw_legacy_encoder_funcs,
346
-
DRM_MODE_ENCODER_LVDS);
347
+
DRM_MODE_ENCODER_VIRTUAL);
347
348
drm_mode_connector_attach_encoder(connector, encoder);
348
349
encoder->possible_crtcs = (1 << unit);
349
350
encoder->possible_clones = 0;
+33
-63
drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
+33
-63
drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
···
36
36
container_of(x, struct vmw_screen_object_unit, base.connector)
37
37
38
38
struct vmw_screen_object_display {
39
-
struct list_head active;
39
+
unsigned num_implicit;
40
40
41
-
unsigned num_active;
42
-
unsigned last_num_active;
43
-
44
-
struct vmw_framebuffer *fb;
41
+
struct vmw_framebuffer *implicit_fb;
45
42
};
46
43
47
44
/**
···
51
54
struct vmw_dma_buffer *buffer; /**< Backing store buffer */
52
55
53
56
bool defined;
54
-
55
-
struct list_head active;
57
+
bool active_implicit;
56
58
};
57
59
58
60
static void vmw_sou_destroy(struct vmw_screen_object_unit *sou)
59
61
{
60
-
list_del_init(&sou->active);
61
62
vmw_display_unit_cleanup(&sou->base);
62
63
kfree(sou);
63
64
}
···
70
75
vmw_sou_destroy(vmw_crtc_to_sou(crtc));
71
76
}
72
77
73
-
static int vmw_sou_del_active(struct vmw_private *vmw_priv,
78
+
static void vmw_sou_del_active(struct vmw_private *vmw_priv,
74
79
struct vmw_screen_object_unit *sou)
75
80
{
76
81
struct vmw_screen_object_display *ld = vmw_priv->sou_priv;
77
-
if (list_empty(&sou->active))
78
-
return 0;
79
82
80
-
/* Must init otherwise list_empty(&sou->active) will not work. */
81
-
list_del_init(&sou->active);
82
-
if (--(ld->num_active) == 0) {
83
-
BUG_ON(!ld->fb);
84
-
if (ld->fb->unpin)
85
-
ld->fb->unpin(ld->fb);
86
-
ld->fb = NULL;
83
+
if (sou->active_implicit) {
84
+
if (--(ld->num_implicit) == 0)
85
+
ld->implicit_fb = NULL;
86
+
sou->active_implicit = false;
87
87
}
88
-
89
-
return 0;
90
88
}
91
89
92
-
static int vmw_sou_add_active(struct vmw_private *vmw_priv,
90
+
static void vmw_sou_add_active(struct vmw_private *vmw_priv,
93
91
struct vmw_screen_object_unit *sou,
94
92
struct vmw_framebuffer *vfb)
95
93
{
96
94
struct vmw_screen_object_display *ld = vmw_priv->sou_priv;
97
-
struct vmw_screen_object_unit *entry;
98
-
struct list_head *at;
99
95
100
-
BUG_ON(!ld->num_active && ld->fb);
101
-
if (vfb != ld->fb) {
102
-
if (ld->fb && ld->fb->unpin)
103
-
ld->fb->unpin(ld->fb);
104
-
if (vfb->pin)
105
-
vfb->pin(vfb);
106
-
ld->fb = vfb;
96
+
BUG_ON(!ld->num_implicit && ld->implicit_fb);
97
+
98
+
if (!sou->active_implicit && sou->base.is_implicit) {
99
+
ld->implicit_fb = vfb;
100
+
sou->active_implicit = true;
101
+
ld->num_implicit++;
107
102
}
108
-
109
-
if (!list_empty(&sou->active))
110
-
return 0;
111
-
112
-
at = &ld->active;
113
-
list_for_each_entry(entry, &ld->active, active) {
114
-
if (entry->base.unit > sou->base.unit)
115
-
break;
116
-
117
-
at = &entry->active;
118
-
}
119
-
120
-
list_add(&sou->active, at);
121
-
122
-
ld->num_active++;
123
-
124
-
return 0;
125
103
}
126
104
127
105
/**
···
132
164
(sou->base.unit == 0 ? SVGA_SCREEN_IS_PRIMARY : 0);
133
165
cmd->obj.size.width = mode->hdisplay;
134
166
cmd->obj.size.height = mode->vdisplay;
135
-
cmd->obj.root.x = x;
136
-
cmd->obj.root.y = y;
167
+
if (sou->base.is_implicit) {
168
+
cmd->obj.root.x = x;
169
+
cmd->obj.root.y = y;
170
+
} else {
171
+
cmd->obj.root.x = sou->base.gui_x;
172
+
cmd->obj.root.y = sou->base.gui_y;
173
+
}
137
174
138
175
/* Ok to assume that buffer is pinned in vram */
139
176
vmw_bo_get_guest_ptr(&sou->buffer->base, &cmd->obj.backingStore.ptr);
···
285
312
}
286
313
287
314
/* sou only supports one fb active at the time */
288
-
if (dev_priv->sou_priv->fb && vfb &&
289
-
!(dev_priv->sou_priv->num_active == 1 &&
290
-
!list_empty(&sou->active)) &&
291
-
dev_priv->sou_priv->fb != vfb) {
315
+
if (sou->base.is_implicit &&
316
+
dev_priv->sou_priv->implicit_fb && vfb &&
317
+
!(dev_priv->sou_priv->num_implicit == 1 &&
318
+
sou->active_implicit) &&
319
+
dev_priv->sou_priv->implicit_fb != vfb) {
292
320
DRM_ERROR("Multiple framebuffers not supported\n");
293
321
return -EINVAL;
294
322
}
···
445
471
encoder = &sou->base.encoder;
446
472
connector = &sou->base.connector;
447
473
448
-
INIT_LIST_HEAD(&sou->active);
474
+
sou->active_implicit = false;
449
475
450
476
sou->base.pref_active = (unit == 0);
451
477
sou->base.pref_width = 800;
452
478
sou->base.pref_height = 600;
453
479
sou->base.pref_mode = NULL;
480
+
sou->base.is_implicit = true;
454
481
455
482
drm_connector_init(dev, connector, &vmw_legacy_connector_funcs,
456
-
DRM_MODE_CONNECTOR_LVDS);
483
+
DRM_MODE_CONNECTOR_VIRTUAL);
457
484
connector->status = vmw_du_connector_detect(connector, true);
458
485
459
486
drm_encoder_init(dev, encoder, &vmw_screen_object_encoder_funcs,
460
-
DRM_MODE_ENCODER_LVDS);
487
+
DRM_MODE_ENCODER_VIRTUAL);
461
488
drm_mode_connector_attach_encoder(connector, encoder);
462
489
encoder->possible_crtcs = (1 << unit);
463
490
encoder->possible_clones = 0;
···
495
520
if (unlikely(!dev_priv->sou_priv))
496
521
goto err_no_mem;
497
522
498
-
INIT_LIST_HEAD(&dev_priv->sou_priv->active);
499
-
dev_priv->sou_priv->num_active = 0;
500
-
dev_priv->sou_priv->last_num_active = 0;
501
-
dev_priv->sou_priv->fb = NULL;
523
+
dev_priv->sou_priv->num_implicit = 0;
524
+
dev_priv->sou_priv->implicit_fb = NULL;
502
525
503
526
ret = drm_vblank_init(dev, VMWGFX_NUM_DISPLAY_UNITS);
504
527
if (unlikely(ret != 0))
···
530
557
return -ENOSYS;
531
558
532
559
drm_vblank_cleanup(dev);
533
-
534
-
if (!list_empty(&dev_priv->sou_priv->active))
535
-
DRM_ERROR("Still have active outputs when unloading driver");
536
560
537
561
kfree(dev_priv->sou_priv);
538
562
+3
include/drm/drm_dp_helper.h
+3
include/drm/drm_dp_helper.h
···
72
72
73
73
#define DP_MAIN_LINK_CHANNEL_CODING 0x006
74
74
75
+
#define DP_EDP_CONFIGURATION_CAP 0x00d
75
76
#define DP_TRAINING_AUX_RD_INTERVAL 0x00e
76
77
77
78
#define DP_PSR_SUPPORT 0x070
···
159
158
# define DP_AUTOMATED_TEST_REQUEST (1 << 1)
160
159
# define DP_CP_IRQ (1 << 2)
161
160
# define DP_SINK_SPECIFIC_IRQ (1 << 6)
161
+
162
+
#define DP_EDP_CONFIGURATION_SET 0x10a
162
163
163
164
#define DP_LANE0_1_STATUS 0x202
164
165
#define DP_LANE2_3_STATUS 0x203
+7
-5
include/drm/drm_mode.h
+7
-5
include/drm/drm_mode.h
···
120
120
struct drm_mode_modeinfo mode;
121
121
};
122
122
123
-
#define DRM_MODE_ENCODER_NONE 0
124
-
#define DRM_MODE_ENCODER_DAC 1
125
-
#define DRM_MODE_ENCODER_TMDS 2
126
-
#define DRM_MODE_ENCODER_LVDS 3
127
-
#define DRM_MODE_ENCODER_TVDAC 4
123
+
#define DRM_MODE_ENCODER_NONE 0
124
+
#define DRM_MODE_ENCODER_DAC 1
125
+
#define DRM_MODE_ENCODER_TMDS 2
126
+
#define DRM_MODE_ENCODER_LVDS 3
127
+
#define DRM_MODE_ENCODER_TVDAC 4
128
+
#define DRM_MODE_ENCODER_VIRTUAL 5
128
129
129
130
struct drm_mode_get_encoder {
130
131
__u32 encoder_id;
···
163
162
#define DRM_MODE_CONNECTOR_HDMIB 12
164
163
#define DRM_MODE_CONNECTOR_TV 13
165
164
#define DRM_MODE_CONNECTOR_eDP 14
165
+
#define DRM_MODE_CONNECTOR_VIRTUAL 15
166
166
167
167
struct drm_mode_get_connector {
168
168
+25
-26
include/drm/vmwgfx_drm.h
+25
-26
include/drm/vmwgfx_drm.h
···
54
54
#define DRM_VMW_FENCE_EVENT 17
55
55
#define DRM_VMW_PRESENT 18
56
56
#define DRM_VMW_PRESENT_READBACK 19
57
-
57
+
#define DRM_VMW_UPDATE_LAYOUT 20
58
58
59
59
/*************************************************************************/
60
60
/**
···
552
552
553
553
/*************************************************************************/
554
554
/**
555
-
* DRM_VMW_UPDATE_LAYOUT - Update layout
556
-
*
557
-
* Updates the preferred modes and connection status for connectors. The
558
-
* command conisits of one drm_vmw_update_layout_arg pointing out a array
559
-
* of num_outputs drm_vmw_rect's.
560
-
*/
561
-
562
-
/**
563
-
* struct drm_vmw_update_layout_arg
564
-
*
565
-
* @num_outputs: number of active
566
-
* @rects: pointer to array of drm_vmw_rect
567
-
*
568
-
* Input argument to the DRM_VMW_UPDATE_LAYOUT Ioctl.
569
-
*/
570
-
571
-
struct drm_vmw_update_layout_arg {
572
-
uint32_t num_outputs;
573
-
uint32_t pad64;
574
-
uint64_t rects;
575
-
};
576
-
577
-
578
-
/*************************************************************************/
579
-
/**
580
555
* DRM_VMW_FENCE_WAIT
581
556
*
582
557
* Waits for a fence object to signal. The wait is interruptible, so that
···
763
788
uint64_t clips_ptr;
764
789
uint64_t fence_rep;
765
790
};
791
+
792
+
/*************************************************************************/
793
+
/**
794
+
* DRM_VMW_UPDATE_LAYOUT - Update layout
795
+
*
796
+
* Updates the preferred modes and connection status for connectors. The
797
+
* command consists of one drm_vmw_update_layout_arg pointing to an array
798
+
* of num_outputs drm_vmw_rect's.
799
+
*/
800
+
801
+
/**
802
+
* struct drm_vmw_update_layout_arg
803
+
*
804
+
* @num_outputs: number of active connectors
805
+
* @rects: pointer to array of drm_vmw_rect cast to an uint64_t
806
+
*
807
+
* Input argument to the DRM_VMW_UPDATE_LAYOUT Ioctl.
808
+
*/
809
+
struct drm_vmw_update_layout_arg {
810
+
uint32_t num_outputs;
811
+
uint32_t pad64;
812
+
uint64_t rects;
813
+
};
814
+
766
815
#endif