Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/ast: Move detection code into PCI probe helper
Detect device type and config mode in the PCI probe helper, but leave
DRM device initialization where it is. Structures the driver probe and
setup code into a detection and an initialization phase.
A later patch can add branching to the device-initialization code. Each
chip type can have it own initializer function, if necessary.
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231116100240.22975-11-tzimmermann@suse.de
+274
-269
+255
-8
drivers/gpu/drm/ast/ast_drv.c
+255
-8
drivers/gpu/drm/ast/ast_drv.c
···
89
89
90
90
MODULE_DEVICE_TABLE(pci, ast_pciidlist);
91
91
92
+
static bool ast_is_vga_enabled(void __iomem *ioregs)
93
+
{
94
+
u8 vgaer = __ast_read8(ioregs, AST_IO_VGAER);
95
+
96
+
return vgaer & AST_IO_VGAER_VGA_ENABLE;
97
+
}
98
+
99
+
static void ast_enable_vga(void __iomem *ioregs)
100
+
{
101
+
__ast_write8(ioregs, AST_IO_VGAER, AST_IO_VGAER_VGA_ENABLE);
102
+
__ast_write8(ioregs, AST_IO_VGAMR_W, AST_IO_VGAMR_IOSEL);
103
+
}
104
+
105
+
/*
106
+
* Run this function as part of the HW device cleanup; not
107
+
* when the DRM device gets released.
108
+
*/
109
+
static void ast_enable_mmio_release(void *data)
110
+
{
111
+
void __iomem *ioregs = (void __force __iomem *)data;
112
+
113
+
/* enable standard VGA decode */
114
+
__ast_write8_i(ioregs, AST_IO_VGACRI, 0xa1, AST_IO_VGACRA1_MMIO_ENABLED);
115
+
}
116
+
117
+
static int ast_enable_mmio(struct device *dev, void __iomem *ioregs)
118
+
{
119
+
void *data = (void __force *)ioregs;
120
+
121
+
__ast_write8_i(ioregs, AST_IO_VGACRI, 0xa1,
122
+
AST_IO_VGACRA1_MMIO_ENABLED |
123
+
AST_IO_VGACRA1_VGAIO_DISABLED);
124
+
125
+
return devm_add_action_or_reset(dev, ast_enable_mmio_release, data);
126
+
}
127
+
128
+
static void ast_open_key(void __iomem *ioregs)
129
+
{
130
+
__ast_write8_i(ioregs, AST_IO_VGACRI, 0x80, AST_IO_VGACR80_PASSWORD);
131
+
}
132
+
133
+
static int ast_detect_chip(struct pci_dev *pdev,
134
+
void __iomem *regs, void __iomem *ioregs,
135
+
enum ast_chip *chip_out,
136
+
enum ast_config_mode *config_mode_out)
137
+
{
138
+
struct device *dev = &pdev->dev;
139
+
struct device_node *np = dev->of_node;
140
+
enum ast_config_mode config_mode = ast_use_defaults;
141
+
uint32_t scu_rev = 0xffffffff;
142
+
enum ast_chip chip;
143
+
u32 data;
144
+
u8 vgacrd0, vgacrd1;
145
+
146
+
/*
147
+
* Find configuration mode and read SCU revision
148
+
*/
149
+
150
+
/* Check if we have device-tree properties */
151
+
if (np && !of_property_read_u32(np, "aspeed,scu-revision-id", &data)) {
152
+
/* We do, disable P2A access */
153
+
config_mode = ast_use_dt;
154
+
scu_rev = data;
155
+
} else if (pdev->device == PCI_CHIP_AST2000) { // Not all families have a P2A bridge
156
+
/*
157
+
* The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge
158
+
* is disabled. We force using P2A if VGA only mode bit
159
+
* is set D[7]
160
+
*/
161
+
vgacrd0 = __ast_read8_i(ioregs, AST_IO_VGACRI, 0xd0);
162
+
vgacrd1 = __ast_read8_i(ioregs, AST_IO_VGACRI, 0xd1);
163
+
if (!(vgacrd0 & 0x80) || !(vgacrd1 & 0x10)) {
164
+
165
+
/*
166
+
* We have a P2A bridge and it is enabled.
167
+
*/
168
+
169
+
/* Patch AST2500/AST2510 */
170
+
if ((pdev->revision & 0xf0) == 0x40) {
171
+
if (!(vgacrd0 & AST_VRAM_INIT_STATUS_MASK))
172
+
ast_patch_ahb_2500(regs);
173
+
}
174
+
175
+
/* Double check that it's actually working */
176
+
data = __ast_read32(regs, 0xf004);
177
+
if ((data != 0xffffffff) && (data != 0x00)) {
178
+
config_mode = ast_use_p2a;
179
+
180
+
/* Read SCU7c (silicon revision register) */
181
+
__ast_write32(regs, 0xf004, 0x1e6e0000);
182
+
__ast_write32(regs, 0xf000, 0x1);
183
+
scu_rev = __ast_read32(regs, 0x1207c);
184
+
}
185
+
}
186
+
}
187
+
188
+
switch (config_mode) {
189
+
case ast_use_defaults:
190
+
dev_info(dev, "Using default configuration\n");
191
+
break;
192
+
case ast_use_dt:
193
+
dev_info(dev, "Using device-tree for configuration\n");
194
+
break;
195
+
case ast_use_p2a:
196
+
dev_info(dev, "Using P2A bridge for configuration\n");
197
+
break;
198
+
}
199
+
200
+
/*
201
+
* Identify chipset
202
+
*/
203
+
204
+
if (pdev->revision >= 0x50) {
205
+
chip = AST2600;
206
+
dev_info(dev, "AST 2600 detected\n");
207
+
} else if (pdev->revision >= 0x40) {
208
+
switch (scu_rev & 0x300) {
209
+
case 0x0100:
210
+
chip = AST2510;
211
+
dev_info(dev, "AST 2510 detected\n");
212
+
break;
213
+
default:
214
+
chip = AST2500;
215
+
dev_info(dev, "AST 2500 detected\n");
216
+
break;
217
+
}
218
+
} else if (pdev->revision >= 0x30) {
219
+
switch (scu_rev & 0x300) {
220
+
case 0x0100:
221
+
chip = AST1400;
222
+
dev_info(dev, "AST 1400 detected\n");
223
+
break;
224
+
default:
225
+
chip = AST2400;
226
+
dev_info(dev, "AST 2400 detected\n");
227
+
break;
228
+
}
229
+
} else if (pdev->revision >= 0x20) {
230
+
switch (scu_rev & 0x300) {
231
+
case 0x0000:
232
+
chip = AST1300;
233
+
dev_info(dev, "AST 1300 detected\n");
234
+
break;
235
+
default:
236
+
chip = AST2300;
237
+
dev_info(dev, "AST 2300 detected\n");
238
+
break;
239
+
}
240
+
} else if (pdev->revision >= 0x10) {
241
+
switch (scu_rev & 0x0300) {
242
+
case 0x0200:
243
+
chip = AST1100;
244
+
dev_info(dev, "AST 1100 detected\n");
245
+
break;
246
+
case 0x0100:
247
+
chip = AST2200;
248
+
dev_info(dev, "AST 2200 detected\n");
249
+
break;
250
+
case 0x0000:
251
+
chip = AST2150;
252
+
dev_info(dev, "AST 2150 detected\n");
253
+
break;
254
+
default:
255
+
chip = AST2100;
256
+
dev_info(dev, "AST 2100 detected\n");
257
+
break;
258
+
}
259
+
} else {
260
+
chip = AST2000;
261
+
dev_info(dev, "AST 2000 detected\n");
262
+
}
263
+
264
+
*chip_out = chip;
265
+
*config_mode_out = config_mode;
266
+
267
+
return 0;
268
+
}
269
+
92
270
static int ast_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
93
271
{
94
-
struct ast_device *ast;
95
-
struct drm_device *dev;
272
+
struct device *dev = &pdev->dev;
96
273
int ret;
274
+
void __iomem *regs;
275
+
void __iomem *ioregs;
276
+
enum ast_config_mode config_mode;
277
+
enum ast_chip chip;
278
+
struct drm_device *drm;
279
+
bool need_post = false;
97
280
98
281
ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &ast_driver);
99
282
if (ret)
···
286
103
if (ret)
287
104
return ret;
288
105
289
-
ast = ast_device_create(&ast_driver, pdev, ent->driver_data);
290
-
if (IS_ERR(ast))
291
-
return PTR_ERR(ast);
292
-
dev = &ast->base;
106
+
regs = pcim_iomap(pdev, 1, 0);
107
+
if (!regs)
108
+
return -EIO;
293
109
294
-
ret = drm_dev_register(dev, ent->driver_data);
110
+
if (pdev->revision >= 0x40) {
111
+
/*
112
+
* On AST2500 and later models, MMIO is enabled by
113
+
* default. Adopt it to be compatible with ARM.
114
+
*/
115
+
resource_size_t len = pci_resource_len(pdev, 1);
116
+
117
+
if (len < AST_IO_MM_OFFSET)
118
+
return -EIO;
119
+
if ((len - AST_IO_MM_OFFSET) < AST_IO_MM_LENGTH)
120
+
return -EIO;
121
+
ioregs = regs + AST_IO_MM_OFFSET;
122
+
} else if (pci_resource_flags(pdev, 2) & IORESOURCE_IO) {
123
+
/*
124
+
* Map I/O registers if we have a PCI BAR for I/O.
125
+
*/
126
+
resource_size_t len = pci_resource_len(pdev, 2);
127
+
128
+
if (len < AST_IO_MM_LENGTH)
129
+
return -EIO;
130
+
ioregs = pcim_iomap(pdev, 2, 0);
131
+
if (!ioregs)
132
+
return -EIO;
133
+
} else {
134
+
/*
135
+
* Anything else is best effort.
136
+
*/
137
+
resource_size_t len = pci_resource_len(pdev, 1);
138
+
139
+
if (len < AST_IO_MM_OFFSET)
140
+
return -EIO;
141
+
if ((len - AST_IO_MM_OFFSET) < AST_IO_MM_LENGTH)
142
+
return -EIO;
143
+
ioregs = regs + AST_IO_MM_OFFSET;
144
+
145
+
dev_info(dev, "Platform has no I/O space, using MMIO\n");
146
+
}
147
+
148
+
if (!ast_is_vga_enabled(ioregs)) {
149
+
dev_info(dev, "VGA not enabled on entry, requesting chip POST\n");
150
+
need_post = true;
151
+
}
152
+
153
+
/*
154
+
* If VGA isn't enabled, we need to enable now or subsequent
155
+
* access to the scratch registers will fail.
156
+
*/
157
+
if (need_post)
158
+
ast_enable_vga(ioregs);
159
+
/* Enable extended register access */
160
+
ast_open_key(ioregs);
161
+
162
+
ret = ast_enable_mmio(dev, ioregs);
295
163
if (ret)
296
164
return ret;
297
165
298
-
drm_fbdev_generic_setup(dev, 32);
166
+
ret = ast_detect_chip(pdev, regs, ioregs, &chip, &config_mode);
167
+
if (ret)
168
+
return ret;
169
+
170
+
drm = ast_device_create(pdev, &ast_driver, chip, config_mode, regs, ioregs, need_post);
171
+
if (IS_ERR(drm))
172
+
return PTR_ERR(drm);
173
+
pci_set_drvdata(pdev, drm);
174
+
175
+
ret = drm_dev_register(drm, ent->driver_data);
176
+
if (ret)
177
+
return ret;
178
+
179
+
drm_fbdev_generic_setup(drm, 32);
299
180
300
181
return 0;
301
182
}
+7
-3
drivers/gpu/drm/ast/ast_drv.h
+7
-3
drivers/gpu/drm/ast/ast_drv.h
···
254
254
return container_of(dev, struct ast_device, base);
255
255
}
256
256
257
-
struct ast_device *ast_device_create(const struct drm_driver *drv,
258
-
struct pci_dev *pdev,
259
-
unsigned long flags);
257
+
struct drm_device *ast_device_create(struct pci_dev *pdev,
258
+
const struct drm_driver *drv,
259
+
enum ast_chip chip,
260
+
enum ast_config_mode config_mode,
261
+
void __iomem *regs,
262
+
void __iomem *ioregs,
263
+
bool need_post);
260
264
261
265
static inline unsigned long __ast_gen(struct ast_device *ast)
262
266
{
+12
-258
drivers/gpu/drm/ast/ast_main.c
+12
-258
drivers/gpu/drm/ast/ast_main.c
···
35
35
36
36
#include "ast_drv.h"
37
37
38
-
static bool ast_is_vga_enabled(void __iomem *ioregs)
39
-
{
40
-
u8 vgaer = __ast_read8(ioregs, AST_IO_VGAER);
41
-
42
-
return vgaer & AST_IO_VGAER_VGA_ENABLE;
43
-
}
44
-
45
-
static void ast_enable_vga(void __iomem *ioregs)
46
-
{
47
-
__ast_write8(ioregs, AST_IO_VGAER, AST_IO_VGAER_VGA_ENABLE);
48
-
__ast_write8(ioregs, AST_IO_VGAMR_W, AST_IO_VGAMR_IOSEL);
49
-
}
50
-
51
-
/*
52
-
* Run this function as part of the HW device cleanup; not
53
-
* when the DRM device gets released.
54
-
*/
55
-
static void ast_enable_mmio_release(void *data)
56
-
{
57
-
void __iomem *ioregs = (void __force __iomem *)data;
58
-
59
-
/* enable standard VGA decode */
60
-
__ast_write8_i(ioregs, AST_IO_VGACRI, 0xa1, AST_IO_VGACRA1_MMIO_ENABLED);
61
-
}
62
-
63
-
static int ast_enable_mmio(struct device *dev, void __iomem *ioregs)
64
-
{
65
-
void *data = (void __force *)ioregs;
66
-
67
-
__ast_write8_i(ioregs, AST_IO_VGACRI, 0xa1,
68
-
AST_IO_VGACRA1_MMIO_ENABLED |
69
-
AST_IO_VGACRA1_VGAIO_DISABLED);
70
-
71
-
return devm_add_action_or_reset(dev, ast_enable_mmio_release, data);
72
-
}
73
-
74
-
static void ast_open_key(void __iomem *ioregs)
75
-
{
76
-
__ast_write8_i(ioregs, AST_IO_VGACRI, 0x80, AST_IO_VGACR80_PASSWORD);
77
-
}
78
-
79
-
static int ast_detect_chip(struct pci_dev *pdev,
80
-
void __iomem *regs, void __iomem *ioregs,
81
-
enum ast_chip *chip_out,
82
-
enum ast_config_mode *config_mode_out)
83
-
{
84
-
struct device *dev = &pdev->dev;
85
-
struct device_node *np = dev->of_node;
86
-
enum ast_config_mode config_mode = ast_use_defaults;
87
-
uint32_t scu_rev = 0xffffffff;
88
-
enum ast_chip chip;
89
-
u32 data;
90
-
u8 vgacrd0, vgacrd1;
91
-
92
-
/*
93
-
* Find configuration mode and read SCU revision
94
-
*/
95
-
96
-
/* Check if we have device-tree properties */
97
-
if (np && !of_property_read_u32(np, "aspeed,scu-revision-id", &data)) {
98
-
/* We do, disable P2A access */
99
-
config_mode = ast_use_dt;
100
-
scu_rev = data;
101
-
} else if (pdev->device == PCI_CHIP_AST2000) { // Not all families have a P2A bridge
102
-
/*
103
-
* The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge
104
-
* is disabled. We force using P2A if VGA only mode bit
105
-
* is set D[7]
106
-
*/
107
-
vgacrd0 = __ast_read8_i(ioregs, AST_IO_VGACRI, 0xd0);
108
-
vgacrd1 = __ast_read8_i(ioregs, AST_IO_VGACRI, 0xd1);
109
-
if (!(vgacrd0 & 0x80) || !(vgacrd1 & 0x10)) {
110
-
111
-
/*
112
-
* We have a P2A bridge and it is enabled.
113
-
*/
114
-
115
-
/* Patch AST2500/AST2510 */
116
-
if ((pdev->revision & 0xf0) == 0x40) {
117
-
if (!(vgacrd0 & AST_VRAM_INIT_STATUS_MASK))
118
-
ast_patch_ahb_2500(regs);
119
-
}
120
-
121
-
/* Double check that it's actually working */
122
-
data = __ast_read32(regs, 0xf004);
123
-
if ((data != 0xffffffff) && (data != 0x00)) {
124
-
config_mode = ast_use_p2a;
125
-
126
-
/* Read SCU7c (silicon revision register) */
127
-
__ast_write32(regs, 0xf004, 0x1e6e0000);
128
-
__ast_write32(regs, 0xf000, 0x1);
129
-
scu_rev = __ast_read32(regs, 0x1207c);
130
-
}
131
-
}
132
-
}
133
-
134
-
switch (config_mode) {
135
-
case ast_use_defaults:
136
-
dev_info(dev, "Using default configuration\n");
137
-
break;
138
-
case ast_use_dt:
139
-
dev_info(dev, "Using device-tree for configuration\n");
140
-
break;
141
-
case ast_use_p2a:
142
-
dev_info(dev, "Using P2A bridge for configuration\n");
143
-
break;
144
-
}
145
-
146
-
/*
147
-
* Identify chipset
148
-
*/
149
-
150
-
if (pdev->revision >= 0x50) {
151
-
chip = AST2600;
152
-
dev_info(dev, "AST 2600 detected\n");
153
-
} else if (pdev->revision >= 0x40) {
154
-
switch (scu_rev & 0x300) {
155
-
case 0x0100:
156
-
chip = AST2510;
157
-
dev_info(dev, "AST 2510 detected\n");
158
-
break;
159
-
default:
160
-
chip = AST2500;
161
-
dev_info(dev, "AST 2500 detected\n");
162
-
break;
163
-
}
164
-
} else if (pdev->revision >= 0x30) {
165
-
switch (scu_rev & 0x300) {
166
-
case 0x0100:
167
-
chip = AST1400;
168
-
dev_info(dev, "AST 1400 detected\n");
169
-
break;
170
-
default:
171
-
chip = AST2400;
172
-
dev_info(dev, "AST 2400 detected\n");
173
-
break;
174
-
}
175
-
} else if (pdev->revision >= 0x20) {
176
-
switch (scu_rev & 0x300) {
177
-
case 0x0000:
178
-
chip = AST1300;
179
-
dev_info(dev, "AST 1300 detected\n");
180
-
break;
181
-
default:
182
-
chip = AST2300;
183
-
dev_info(dev, "AST 2300 detected\n");
184
-
break;
185
-
}
186
-
} else if (pdev->revision >= 0x10) {
187
-
switch (scu_rev & 0x0300) {
188
-
case 0x0200:
189
-
chip = AST1100;
190
-
dev_info(dev, "AST 1100 detected\n");
191
-
break;
192
-
case 0x0100:
193
-
chip = AST2200;
194
-
dev_info(dev, "AST 2200 detected\n");
195
-
break;
196
-
case 0x0000:
197
-
chip = AST2150;
198
-
dev_info(dev, "AST 2150 detected\n");
199
-
break;
200
-
default:
201
-
chip = AST2100;
202
-
dev_info(dev, "AST 2100 detected\n");
203
-
break;
204
-
}
205
-
} else {
206
-
chip = AST2000;
207
-
dev_info(dev, "AST 2000 detected\n");
208
-
}
209
-
210
-
*chip_out = chip;
211
-
*config_mode_out = config_mode;
212
-
213
-
return 0;
214
-
}
215
-
216
38
static void ast_detect_widescreen(struct ast_device *ast)
217
39
{
218
40
u8 jreg;
···
250
428
return 0;
251
429
}
252
430
253
-
struct ast_device *ast_device_create(const struct drm_driver *drv,
254
-
struct pci_dev *pdev,
255
-
unsigned long flags)
431
+
struct drm_device *ast_device_create(struct pci_dev *pdev,
432
+
const struct drm_driver *drv,
433
+
enum ast_chip chip,
434
+
enum ast_config_mode config_mode,
435
+
void __iomem *regs,
436
+
void __iomem *ioregs,
437
+
bool need_post)
256
438
{
257
439
struct drm_device *dev;
258
440
struct ast_device *ast;
259
-
bool need_post = false;
260
-
int ret = 0;
261
-
void __iomem *regs;
262
-
void __iomem *ioregs;
263
-
enum ast_config_mode config_mode;
264
-
enum ast_chip chip;
441
+
int ret;
265
442
266
443
ast = devm_drm_dev_alloc(&pdev->dev, drv, struct ast_device, base);
267
444
if (IS_ERR(ast))
268
-
return ast;
445
+
return ERR_CAST(ast);
269
446
dev = &ast->base;
270
-
271
-
pci_set_drvdata(pdev, dev);
272
-
273
-
regs = pcim_iomap(pdev, 1, 0);
274
-
if (!regs)
275
-
return ERR_PTR(-EIO);
276
-
277
-
if (pdev->revision >= 0x40) {
278
-
/*
279
-
* On AST2500 and later models, MMIO is enabled by
280
-
* default. Adopt it to be compatible with ARM.
281
-
*/
282
-
resource_size_t len = pci_resource_len(pdev, 1);
283
-
284
-
if (len < AST_IO_MM_OFFSET)
285
-
return ERR_PTR(-EIO);
286
-
if ((len - AST_IO_MM_OFFSET) < AST_IO_MM_LENGTH)
287
-
return ERR_PTR(-EIO);
288
-
ioregs = regs + AST_IO_MM_OFFSET;
289
-
} else if (pci_resource_flags(pdev, 2) & IORESOURCE_IO) {
290
-
/*
291
-
* Map I/O registers if we have a PCI BAR for I/O.
292
-
*/
293
-
resource_size_t len = pci_resource_len(pdev, 2);
294
-
295
-
if (len < AST_IO_MM_LENGTH)
296
-
return -EIO;
297
-
ioregs = pcim_iomap(pdev, 2, 0);
298
-
if (!ioregs)
299
-
return ERR_PTR(-EIO);
300
-
} else {
301
-
/*
302
-
* Anything else is best effort.
303
-
*/
304
-
resource_size_t len = pci_resource_len(pdev, 1);
305
-
306
-
if (len < AST_IO_MM_OFFSET)
307
-
return ERR_PTR(-EIO);
308
-
if ((len - AST_IO_MM_OFFSET) < AST_IO_MM_LENGTH)
309
-
return ERR_PTR(-EIO);
310
-
ioregs = regs + AST_IO_MM_OFFSET;
311
-
312
-
drm_info(dev, "Platform has no I/O space, using MMIO\n");
313
-
}
314
-
315
-
ast->regs = regs;
316
-
ast->ioregs = ioregs;
317
-
318
-
if (!ast_is_vga_enabled(ioregs)) {
319
-
drm_info(dev, "VGA not enabled on entry, requesting chip POST\n");
320
-
need_post = true;
321
-
}
322
-
323
-
/*
324
-
* If VGA isn't enabled, we need to enable now or subsequent
325
-
* access to the scratch registers will fail.
326
-
*/
327
-
if (need_post)
328
-
ast_enable_vga(ioregs);
329
-
/* Enable extended register access */
330
-
ast_open_key(ioregs);
331
-
332
-
ret = ast_enable_mmio(&pdev->dev, ioregs);
333
-
if (ret)
334
-
return ERR_PTR(ret);
335
-
336
-
ret = ast_detect_chip(pdev, regs, ioregs, &chip, &config_mode);
337
-
if (ret)
338
-
return ERR_PTR(ret);
339
447
340
448
ast->chip = chip;
341
449
ast->config_mode = config_mode;
450
+
ast->regs = regs;
451
+
ast->ioregs = ioregs;
342
452
343
453
ast_detect_widescreen(ast);
344
454
ast_detect_tx_chip(ast, need_post);
···
301
547
if (ret)
302
548
return ERR_PTR(ret);
303
549
304
-
return ast;
550
+
return dev;
305
551
}