Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'stm32-dt-for-v6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
STM32 DT for v6.4, round 1
Highlights:
----------
- MPU:
- STM32MP13:
- Add FMC support.
- Add QSPI support.
- Add 8 UART instances nodes.
- Enable UART on STM32MP135F-DK:
-UART1/UART8 used on expansion connector.
-UART2 used for BT.
-UART4 used for console.
- STMP32MP15:
- Add STM32MP151 support ( documentation + machine).
- Uart fixes (slew rate, aliases clean-up).
- Fix GPU YAMl issue.
* tag 'stm32-dt-for-v6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
ARM: stm32: add initial documentation for STM32MP151
ARM: dts: stm32: Add QSPI support on STM32MP13x SoC family
ARM: dts: stm32: add FMC support on STM32MP13x SoC family
ARM: dts: stm32: YAML validation fails for Argon Boards
ARM: dts: stm32: YAML validation fails for Odyssey Boards
ARM: dts: stm32: YAML validation fails for STM32MP15 ST Boards
ARM: dts: stm32: add uart nodes and uart aliases on stm32mp135f-dk
ARM: dts: stm32: add pins for usart2/1/4/8 in stm32mp13-pinctrl
ARM: dts: stm32: add uart nodes on stm32mp13
ARM: dts: stm32: clean uart aliases on stm32mp15xx-exx boards
ARM: dts: stm32: clean uart aliases on stm32mp15xx-dkx boards
ARM: dts: stm32: fix slew-rate of USART2 on stm32mp15xx-dkx
ARM: stm32: add support for STM32MP151
ARM: dts: stm32: fix spi1 pin assignment on stm32mp15
ARM: dts: stm32: drop invalid simple-panel compatible on stm32mp157c-lxa
ARM: dts: stm32: Add coprocessor detach mbox on stm32mp15xx-osd32 SoM
Link: https://lore.kernel.org/r/63987ed6-2813-15ff-e058-73312a730d61@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+386
-74
+1
Documentation/arm/index.rst
+1
Documentation/arm/index.rst
+36
Documentation/arm/stm32/stm32mp151-overview.rst
+36
Documentation/arm/stm32/stm32mp151-overview.rst
···
1
+
===================
2
+
STM32MP151 Overview
3
+
===================
4
+
5
+
Introduction
6
+
------------
7
+
8
+
The STM32MP151 is a Cortex-A MPU aimed at various applications.
9
+
It features:
10
+
11
+
- Single Cortex-A7 application core
12
+
- Standard memories interface support
13
+
- Standard connectivity, widely inherited from the STM32 MCU family
14
+
- Comprehensive security support
15
+
16
+
More details:
17
+
18
+
- Cortex-A7 core running up to @800MHz
19
+
- FMC controller to connect SDRAM, NOR and NAND memories
20
+
- QSPI
21
+
- SD/MMC/SDIO support
22
+
- Ethernet controller
23
+
- ADC/DAC
24
+
- USB EHCI/OHCI controllers
25
+
- USB OTG
26
+
- I2C, SPI busses support
27
+
- Several general purpose timers
28
+
- Serial Audio interface
29
+
- LCD-TFT controller
30
+
- DCMIPP
31
+
- SPDIFRX
32
+
- DFSDM
33
+
34
+
:Authors:
35
+
36
+
- Roan van Dijk <roan@protonic.nl>
+129
arch/arm/boot/dts/stm32mp13-pinctrl.dtsi
+129
arch/arm/boot/dts/stm32mp13-pinctrl.dtsi
···
258
258
bias-disable;
259
259
};
260
260
};
261
+
262
+
uart4_idle_pins_a: uart4-idle-0 {
263
+
pins1 {
264
+
pinmux = <STM32_PINMUX('D', 6, ANALOG)>; /* UART4_TX */
265
+
};
266
+
pins2 {
267
+
pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
268
+
bias-disable;
269
+
};
270
+
};
271
+
272
+
uart4_sleep_pins_a: uart4-sleep-0 {
273
+
pins {
274
+
pinmux = <STM32_PINMUX('D', 6, ANALOG)>, /* UART4_TX */
275
+
<STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */
276
+
};
277
+
};
278
+
279
+
uart8_pins_a: uart8-0 {
280
+
pins1 {
281
+
pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
282
+
bias-disable;
283
+
drive-push-pull;
284
+
slew-rate = <0>;
285
+
};
286
+
pins2 {
287
+
pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
288
+
bias-pull-up;
289
+
};
290
+
};
291
+
292
+
uart8_idle_pins_a: uart8-idle-0 {
293
+
pins1 {
294
+
pinmux = <STM32_PINMUX('E', 1, ANALOG)>; /* UART8_TX */
295
+
};
296
+
pins2 {
297
+
pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
298
+
bias-pull-up;
299
+
};
300
+
};
301
+
302
+
uart8_sleep_pins_a: uart8-sleep-0 {
303
+
pins {
304
+
pinmux = <STM32_PINMUX('E', 1, ANALOG)>, /* UART8_TX */
305
+
<STM32_PINMUX('F', 9, ANALOG)>; /* UART8_RX */
306
+
};
307
+
};
308
+
309
+
usart1_pins_a: usart1-0 {
310
+
pins1 {
311
+
pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */
312
+
<STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
313
+
bias-disable;
314
+
drive-push-pull;
315
+
slew-rate = <0>;
316
+
};
317
+
pins2 {
318
+
pinmux = <STM32_PINMUX('B', 0, AF4)>, /* USART1_RX */
319
+
<STM32_PINMUX('A', 7, AF7)>; /* USART1_CTS_NSS */
320
+
bias-pull-up;
321
+
};
322
+
};
323
+
324
+
usart1_idle_pins_a: usart1-idle-0 {
325
+
pins1 {
326
+
pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
327
+
<STM32_PINMUX('A', 7, ANALOG)>; /* USART1_CTS_NSS */
328
+
};
329
+
pins2 {
330
+
pinmux = <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
331
+
bias-disable;
332
+
drive-push-pull;
333
+
slew-rate = <0>;
334
+
};
335
+
pins3 {
336
+
pinmux = <STM32_PINMUX('B', 0, AF4)>; /* USART1_RX */
337
+
bias-pull-up;
338
+
};
339
+
};
340
+
341
+
usart1_sleep_pins_a: usart1-sleep-0 {
342
+
pins {
343
+
pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
344
+
<STM32_PINMUX('C', 2, ANALOG)>, /* USART1_RTS */
345
+
<STM32_PINMUX('A', 7, ANALOG)>, /* USART1_CTS_NSS */
346
+
<STM32_PINMUX('B', 0, ANALOG)>; /* USART1_RX */
347
+
};
348
+
};
349
+
350
+
usart2_pins_a: usart2-0 {
351
+
pins1 {
352
+
pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */
353
+
<STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
354
+
bias-disable;
355
+
drive-push-pull;
356
+
slew-rate = <0>;
357
+
};
358
+
pins2 {
359
+
pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */
360
+
<STM32_PINMUX('E', 11, AF2)>; /* USART2_CTS_NSS */
361
+
bias-disable;
362
+
};
363
+
};
364
+
365
+
usart2_idle_pins_a: usart2-idle-0 {
366
+
pins1 {
367
+
pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
368
+
<STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
369
+
};
370
+
pins2 {
371
+
pinmux = <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
372
+
bias-disable;
373
+
drive-push-pull;
374
+
slew-rate = <0>;
375
+
};
376
+
pins3 {
377
+
pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */
378
+
bias-disable;
379
+
};
380
+
};
381
+
382
+
usart2_sleep_pins_a: usart2-sleep-0 {
383
+
pins {
384
+
pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
385
+
<STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
386
+
<STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */
387
+
<STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
388
+
};
389
+
};
261
390
};
+144
-1
arch/arm/boot/dts/stm32mp131.dtsi
+144
-1
arch/arm/boot/dts/stm32mp131.dtsi
···
397
397
status = "disabled";
398
398
};
399
399
400
+
usart3: serial@4000f000 {
401
+
compatible = "st,stm32h7-uart";
402
+
reg = <0x4000f000 0x400>;
403
+
interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
404
+
clocks = <&rcc USART3_K>;
405
+
resets = <&rcc USART3_R>;
406
+
wakeup-source;
407
+
dmas = <&dmamux1 45 0x400 0x5>,
408
+
<&dmamux1 46 0x400 0x1>;
409
+
dma-names = "rx", "tx";
410
+
status = "disabled";
411
+
};
412
+
400
413
uart4: serial@40010000 {
401
414
compatible = "st,stm32h7-uart";
402
415
reg = <0x40010000 0x400>;
403
-
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
416
+
interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
404
417
clocks = <&rcc UART4_K>;
405
418
resets = <&rcc UART4_R>;
419
+
wakeup-source;
420
+
dmas = <&dmamux1 63 0x400 0x5>,
421
+
<&dmamux1 64 0x400 0x1>;
422
+
dma-names = "rx", "tx";
423
+
status = "disabled";
424
+
};
425
+
426
+
uart5: serial@40011000 {
427
+
compatible = "st,stm32h7-uart";
428
+
reg = <0x40011000 0x400>;
429
+
interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
430
+
clocks = <&rcc UART5_K>;
431
+
resets = <&rcc UART5_R>;
432
+
wakeup-source;
433
+
dmas = <&dmamux1 65 0x400 0x5>,
434
+
<&dmamux1 66 0x400 0x1>;
435
+
dma-names = "rx", "tx";
406
436
status = "disabled";
407
437
};
408
438
···
469
439
dma-names = "rx", "tx";
470
440
st,syscfg-fmp = <&syscfg 0x4 0x2>;
471
441
i2c-analog-filter;
442
+
status = "disabled";
443
+
};
444
+
445
+
uart7: serial@40018000 {
446
+
compatible = "st,stm32h7-uart";
447
+
reg = <0x40018000 0x400>;
448
+
interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
449
+
clocks = <&rcc UART7_K>;
450
+
resets = <&rcc UART7_R>;
451
+
wakeup-source;
452
+
dmas = <&dmamux1 79 0x400 0x5>,
453
+
<&dmamux1 80 0x400 0x1>;
454
+
dma-names = "rx", "tx";
455
+
status = "disabled";
456
+
};
457
+
458
+
uart8: serial@40019000 {
459
+
compatible = "st,stm32h7-uart";
460
+
reg = <0x40019000 0x400>;
461
+
interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
462
+
clocks = <&rcc UART8_K>;
463
+
resets = <&rcc UART8_R>;
464
+
wakeup-source;
465
+
dmas = <&dmamux1 81 0x400 0x5>,
466
+
<&dmamux1 82 0x400 0x1>;
467
+
dma-names = "rx", "tx";
472
468
status = "disabled";
473
469
};
474
470
···
578
522
compatible = "st,stm32-timer-counter";
579
523
status = "disabled";
580
524
};
525
+
};
526
+
527
+
usart6: serial@44003000 {
528
+
compatible = "st,stm32h7-uart";
529
+
reg = <0x44003000 0x400>;
530
+
interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
531
+
clocks = <&rcc USART6_K>;
532
+
resets = <&rcc USART6_R>;
533
+
wakeup-source;
534
+
dmas = <&dmamux1 71 0x400 0x5>,
535
+
<&dmamux1 72 0x400 0x1>;
536
+
dma-names = "rx", "tx";
537
+
status = "disabled";
581
538
};
582
539
583
540
i2s1: audio-controller@44004000 {
···
814
745
dr_mode = "otg";
815
746
otg-rev = <0x200>;
816
747
usb33d-supply = <&usb33>;
748
+
status = "disabled";
749
+
};
750
+
751
+
usart1: serial@4c000000 {
752
+
compatible = "st,stm32h7-uart";
753
+
reg = <0x4c000000 0x400>;
754
+
interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
755
+
clocks = <&rcc USART1_K>;
756
+
resets = <&rcc USART1_R>;
757
+
wakeup-source;
758
+
dmas = <&dmamux1 41 0x400 0x5>,
759
+
<&dmamux1 42 0x400 0x1>;
760
+
dma-names = "rx", "tx";
761
+
status = "disabled";
762
+
};
763
+
764
+
usart2: serial@4c001000 {
765
+
compatible = "st,stm32h7-uart";
766
+
reg = <0x4c001000 0x400>;
767
+
interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
768
+
clocks = <&rcc USART2_K>;
769
+
resets = <&rcc USART2_R>;
770
+
wakeup-source;
771
+
dmas = <&dmamux1 43 0x400 0x5>,
772
+
<&dmamux1 44 0x400 0x1>;
773
+
dma-names = "rx", "tx";
817
774
status = "disabled";
818
775
};
819
776
···
1230
1135
#dma-cells = <5>;
1231
1136
dma-channels = <32>;
1232
1137
dma-requests = <48>;
1138
+
};
1139
+
1140
+
fmc: memory-controller@58002000 {
1141
+
compatible = "st,stm32mp1-fmc2-ebi";
1142
+
reg = <0x58002000 0x1000>;
1143
+
ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
1144
+
<1 0 0x64000000 0x04000000>, /* EBI CS 2 */
1145
+
<2 0 0x68000000 0x04000000>, /* EBI CS 3 */
1146
+
<3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
1147
+
<4 0 0x80000000 0x10000000>; /* NAND */
1148
+
#address-cells = <2>;
1149
+
#size-cells = <1>;
1150
+
clocks = <&rcc FMC_K>;
1151
+
resets = <&rcc FMC_R>;
1152
+
status = "disabled";
1153
+
1154
+
nand-controller@4,0 {
1155
+
compatible = "st,stm32mp1-fmc2-nfc";
1156
+
reg = <4 0x00000000 0x1000>,
1157
+
<4 0x08010000 0x1000>,
1158
+
<4 0x08020000 0x1000>,
1159
+
<4 0x01000000 0x1000>,
1160
+
<4 0x09010000 0x1000>,
1161
+
<4 0x09020000 0x1000>;
1162
+
#address-cells = <1>;
1163
+
#size-cells = <0>;
1164
+
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1165
+
dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>,
1166
+
<&mdma 24 0x2 0x12000a08 0x0 0x0>,
1167
+
<&mdma 25 0x2 0x12000a0a 0x0 0x0>;
1168
+
dma-names = "tx", "rx", "ecc";
1169
+
status = "disabled";
1170
+
};
1171
+
};
1172
+
1173
+
qspi: spi@58003000 {
1174
+
compatible = "st,stm32f469-qspi";
1175
+
reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1176
+
reg-names = "qspi", "qspi_mm";
1177
+
#address-cells = <1>;
1178
+
#size-cells = <0>;
1179
+
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1180
+
dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>,
1181
+
<&mdma 26 0x2 0x10100008 0x0 0x0>;
1182
+
dma-names = "tx", "rx";
1183
+
clocks = <&rcc QSPI_K>;
1184
+
resets = <&rcc QSPI_R>;
1185
+
status = "disabled";
1233
1186
};
1234
1187
1235
1188
sdmmc1: mmc@58005000 {
+41
-1
arch/arm/boot/dts/stm32mp135f-dk.dts
+41
-1
arch/arm/boot/dts/stm32mp135f-dk.dts
···
19
19
20
20
aliases {
21
21
serial0 = &uart4;
22
+
serial1 = &usart1;
23
+
serial2 = &uart8;
24
+
serial3 = &usart2;
25
+
};
26
+
27
+
chosen {
28
+
stdout-path = "serial0:115200n8";
22
29
};
23
30
24
31
memory@c0000000 {
···
274
267
};
275
268
276
269
&uart4 {
277
-
pinctrl-names = "default";
270
+
pinctrl-names = "default", "sleep", "idle";
278
271
pinctrl-0 = <&uart4_pins_a>;
272
+
pinctrl-1 = <&uart4_sleep_pins_a>;
273
+
pinctrl-2 = <&uart4_idle_pins_a>;
274
+
/delete-property/dmas;
275
+
/delete-property/dma-names;
276
+
status = "okay";
277
+
};
278
+
279
+
&uart8 {
280
+
pinctrl-names = "default", "sleep", "idle";
281
+
pinctrl-0 = <&uart8_pins_a>;
282
+
pinctrl-1 = <&uart8_sleep_pins_a>;
283
+
pinctrl-2 = <&uart8_idle_pins_a>;
284
+
/delete-property/dmas;
285
+
/delete-property/dma-names;
286
+
status = "disabled";
287
+
};
288
+
289
+
&usart1 {
290
+
pinctrl-names = "default", "sleep", "idle";
291
+
pinctrl-0 = <&usart1_pins_a>;
292
+
pinctrl-1 = <&usart1_sleep_pins_a>;
293
+
pinctrl-2 = <&usart1_idle_pins_a>;
294
+
uart-has-rtscts;
295
+
status = "disabled";
296
+
};
297
+
298
+
/* Bluetooth */
299
+
&usart2 {
300
+
pinctrl-names = "default", "sleep", "idle";
301
+
pinctrl-0 = <&usart2_pins_a>;
302
+
pinctrl-1 = <&usart2_sleep_pins_a>;
303
+
pinctrl-2 = <&usart2_idle_pins_a>;
304
+
uart-has-rtscts;
279
305
status = "okay";
280
306
};
281
307
+17
-17
arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
+17
-17
arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
···
1880
1880
};
1881
1881
};
1882
1882
1883
+
spi1_pins_b: spi1-1 {
1884
+
pins1 {
1885
+
pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */
1886
+
<STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */
1887
+
bias-disable;
1888
+
drive-push-pull;
1889
+
slew-rate = <1>;
1890
+
};
1891
+
1892
+
pins2 {
1893
+
pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */
1894
+
bias-disable;
1895
+
};
1896
+
};
1897
+
1883
1898
spi2_pins_a: spi2-0 {
1884
1899
pins1 {
1885
1900
pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */
···
2178
2163
<STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
2179
2164
bias-disable;
2180
2165
drive-push-pull;
2181
-
slew-rate = <3>;
2166
+
slew-rate = <0>;
2182
2167
};
2183
2168
pins2 {
2184
2169
pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
···
2196
2181
pinmux = <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
2197
2182
bias-disable;
2198
2183
drive-push-pull;
2199
-
slew-rate = <3>;
2184
+
slew-rate = <0>;
2200
2185
};
2201
2186
pins3 {
2202
2187
pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
···
2460
2445
2461
2446
pins2 {
2462
2447
pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
2463
-
bias-disable;
2464
-
};
2465
-
};
2466
-
2467
-
spi1_pins_b: spi1-1 {
2468
-
pins1 {
2469
-
pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */
2470
-
<STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */
2471
-
bias-disable;
2472
-
drive-push-pull;
2473
-
slew-rate = <1>;
2474
-
};
2475
-
2476
-
pins2 {
2477
-
pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */
2478
2448
bias-disable;
2479
2449
};
2480
2450
};
-3
arch/arm/boot/dts/stm32mp157a-dk1.dts
-3
arch/arm/boot/dts/stm32mp157a-dk1.dts
-3
arch/arm/boot/dts/stm32mp157c-dk2.dts
-3
arch/arm/boot/dts/stm32mp157c-dk2.dts
+4
-13
arch/arm/boot/dts/stm32mp157c-ed1.dts
+4
-13
arch/arm/boot/dts/stm32mp157c-ed1.dts
···
16
16
model = "STMicroelectronics STM32MP157C eval daughter";
17
17
compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
18
18
19
+
aliases {
20
+
serial0 = &uart4;
21
+
};
22
+
19
23
chosen {
20
24
stdout-path = "serial0:115200n8";
21
25
};
···
69
65
reg = <0x38000000 0x10000>;
70
66
no-map;
71
67
};
72
-
73
-
gpu_reserved: gpu@e8000000 {
74
-
reg = <0xe8000000 0x8000000>;
75
-
no-map;
76
-
};
77
-
};
78
-
79
-
aliases {
80
-
serial0 = &uart4;
81
68
};
82
69
83
70
sd_switch: regulator-sd_switch {
···
133
138
134
139
&dts {
135
140
status = "okay";
136
-
};
137
-
138
-
&gpu {
139
-
contiguous-area = <&gpu_reserved>;
140
141
};
141
142
142
143
&hash1 {
-9
arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi
-9
arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi
···
68
68
reg = <0x38000000 0x10000>;
69
69
no-map;
70
70
};
71
-
72
-
gpu_reserved: gpu@dc000000 {
73
-
reg = <0xdc000000 0x4000000>;
74
-
no-map;
75
-
};
76
71
};
77
72
78
73
led: gpio_leds {
···
176
181
reg = <0>;
177
182
};
178
183
};
179
-
};
180
-
181
-
&gpu {
182
-
contiguous-area = <&gpu_reserved>;
183
184
};
184
185
185
186
&hash1 {
+4
-5
arch/arm/boot/dts/stm32mp157c-ev1.dts
+4
-5
arch/arm/boot/dts/stm32mp157c-ev1.dts
···
14
14
model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
15
15
compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
16
16
17
-
chosen {
18
-
stdout-path = "serial0:115200n8";
19
-
};
20
-
21
17
aliases {
22
-
serial0 = &uart4;
23
18
serial1 = &usart3;
24
19
ethernet0 = ðernet0;
20
+
};
21
+
22
+
chosen {
23
+
stdout-path = "serial0:115200n8";
25
24
};
26
25
27
26
clocks {
+1
-1
arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts
+1
-1
arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts
-10
arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi
-10
arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi
···
62
62
reg = <0x38000000 0x10000>;
63
63
no-map;
64
64
};
65
-
66
-
gpu_reserved: gpu@d4000000 {
67
-
reg = <0xd4000000 0x4000000>;
68
-
no-map;
69
-
};
70
65
};
71
66
72
67
led {
···
73
78
linux,default-trigger = "heartbeat";
74
79
};
75
80
};
76
-
};
77
-
78
-
&gpu {
79
-
contiguous-area = <&gpu_reserved>;
80
-
status = "okay";
81
81
};
82
82
83
83
&i2c2 {
+6
-9
arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
+6
-9
arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
···
8
8
#include <dt-bindings/mfd/st,stpmic1.h>
9
9
10
10
/ {
11
+
aliases {
12
+
serial0 = &uart4;
13
+
serial1 = &usart3;
14
+
serial2 = &uart7;
15
+
};
16
+
11
17
memory@c0000000 {
12
18
device_type = "memory";
13
19
reg = <0xc0000000 0x20000000>;
···
57
51
retram: retram@38000000 {
58
52
compatible = "shared-dma-pool";
59
53
reg = <0x38000000 0x10000>;
60
-
no-map;
61
-
};
62
-
63
-
gpu_reserved: gpu@d4000000 {
64
-
reg = <0xd4000000 0x4000000>;
65
54
no-map;
66
55
};
67
56
};
···
150
149
reg = <0>;
151
150
};
152
151
};
153
-
};
154
-
155
-
&gpu {
156
-
contiguous-area = <&gpu_reserved>;
157
152
};
158
153
159
154
&hash1 {
+2
-2
arch/arm/boot/dts/stm32mp15xx-osd32.dtsi
+2
-2
arch/arm/boot/dts/stm32mp15xx-osd32.dtsi
···
210
210
&m4_rproc {
211
211
memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
212
212
<&vdev0vring1>, <&vdev0buffer>;
213
-
mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
214
-
mbox-names = "vq0", "vq1", "shutdown";
213
+
mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
214
+
mbox-names = "vq0", "vq1", "shutdown", "detach";
215
215
interrupt-parent = <&exti>;
216
216
interrupts = <68 1>;
217
217
status = "okay";