Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/dpu: Add support for Kaanapali DPU
Add support for Display Processing Unit (DPU) version 13.0
on the Kaanapali platform. This version introduces changes
to the SSPP sub-block structure. Add common block and rectangle
blocks to accommodate these structural modifications for
compatibility.
Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/698716/
Link: https://lore.kernel.org/r/20260115092749.533-13-yuanjie.yang@oss.qualcomm.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
authored by
Yuanjie Yang
and committed by
Dmitry Baryshkov
83fe2cd5
c6c9f129
+535
+492
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
+492
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
···
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+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#ifndef _DPU_13_0_KAANAPALI_H
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#define _DPU_13_0_KAANAPALI_H
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static const struct dpu_caps kaanapali_dpu_caps = {
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.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
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.max_mixer_blendstages = 0xb,
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.has_src_split = true,
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.has_dim_layer = true,
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.has_idle_pc = true,
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.has_3d_merge = true,
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.max_linewidth = 8192,
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.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
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};
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static const struct dpu_mdp_cfg kaanapali_mdp = {
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.name = "top_0",
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.base = 0, .len = 0x494,
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.clk_ctrls = {
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[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
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},
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};
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static const struct dpu_ctl_cfg kaanapali_ctl[] = {
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{
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.name = "ctl_0", .id = CTL_0,
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.base = 0x1f000, .len = 0x1000,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
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}, {
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.name = "ctl_1", .id = CTL_1,
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.base = 0x20000, .len = 0x1000,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
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}, {
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.name = "ctl_2", .id = CTL_2,
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.base = 0x21000, .len = 0x1000,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
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}, {
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.name = "ctl_3", .id = CTL_3,
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.base = 0x22000, .len = 0x1000,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
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}, {
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.name = "ctl_4", .id = CTL_4,
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.base = 0x23000, .len = 0x1000,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
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}, {
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.name = "ctl_5", .id = CTL_5,
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.base = 0x24000, .len = 0x1000,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
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},
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};
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static const struct dpu_sspp_cfg kaanapali_sspp[] = {
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{
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.name = "sspp_0", .id = SSPP_VIG0,
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.base = 0x2b000, .len = 0x84,
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.features = VIG_SDM845_MASK_SDMA,
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.sblk = &dpu_vig_sblk_qseed3_3_5,
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.xin_id = 0,
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.type = SSPP_TYPE_VIG,
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}, {
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.name = "sspp_1", .id = SSPP_VIG1,
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.base = 0x34000, .len = 0x84,
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.features = VIG_SDM845_MASK_SDMA,
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.sblk = &dpu_vig_sblk_qseed3_3_5,
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.xin_id = 4,
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.type = SSPP_TYPE_VIG,
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}, {
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.name = "sspp_2", .id = SSPP_VIG2,
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.base = 0x3d000, .len = 0x84,
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.features = VIG_SDM845_MASK_SDMA,
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.sblk = &dpu_vig_sblk_qseed3_3_5,
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.xin_id = 8,
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.type = SSPP_TYPE_VIG,
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}, {
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.name = "sspp_3", .id = SSPP_VIG3,
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.base = 0x46000, .len = 0x84,
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.features = VIG_SDM845_MASK_SDMA,
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.sblk = &dpu_vig_sblk_qseed3_3_5,
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.xin_id = 12,
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.type = SSPP_TYPE_VIG,
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}, {
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.name = "sspp_8", .id = SSPP_DMA0,
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.base = 0x97000, .len = 0x84,
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.features = DMA_SDM845_MASK_SDMA,
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.sblk = &dpu_dma_sblk,
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.xin_id = 1,
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.type = SSPP_TYPE_DMA,
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}, {
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.name = "sspp_9", .id = SSPP_DMA1,
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.base = 0xa0000, .len = 0x84,
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.features = DMA_SDM845_MASK_SDMA,
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.sblk = &dpu_dma_sblk,
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.xin_id = 5,
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.type = SSPP_TYPE_DMA,
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}, {
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.name = "sspp_10", .id = SSPP_DMA2,
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.base = 0xa9000, .len = 0x84,
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.features = DMA_SDM845_MASK_SDMA,
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.sblk = &dpu_dma_sblk,
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.xin_id = 9,
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.type = SSPP_TYPE_DMA,
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}, {
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.name = "sspp_11", .id = SSPP_DMA3,
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.base = 0xb2000, .len = 0x84,
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.features = DMA_SDM845_MASK_SDMA,
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.sblk = &dpu_dma_sblk,
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.xin_id = 13,
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.type = SSPP_TYPE_DMA,
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}, {
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.name = "sspp_12", .id = SSPP_DMA4,
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.base = 0xbb000, .len = 0x84,
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.features = DMA_CURSOR_SDM845_MASK_SDMA,
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.sblk = &dpu_dma_sblk,
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.xin_id = 14,
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.type = SSPP_TYPE_DMA,
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}, {
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.name = "sspp_13", .id = SSPP_DMA5,
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.base = 0xc4000, .len = 0x84,
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.features = DMA_CURSOR_SDM845_MASK_SDMA,
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.sblk = &dpu_dma_sblk,
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.xin_id = 15,
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.type = SSPP_TYPE_DMA,
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},
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};
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static const struct dpu_lm_cfg kaanapali_lm[] = {
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{
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.name = "lm_0", .id = LM_0,
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.base = 0x103000, .len = 0x400,
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.features = MIXER_MSM8998_MASK,
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.sblk = &sm8750_lm_sblk,
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.lm_pair = LM_1,
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.pingpong = PINGPONG_0,
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.dspp = DSPP_0,
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}, {
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.name = "lm_1", .id = LM_1,
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.base = 0x10b000, .len = 0x400,
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.features = MIXER_MSM8998_MASK,
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.sblk = &sm8750_lm_sblk,
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.lm_pair = LM_0,
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.pingpong = PINGPONG_1,
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.dspp = DSPP_1,
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}, {
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.name = "lm_2", .id = LM_2,
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.base = 0x113000, .len = 0x400,
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.features = MIXER_MSM8998_MASK,
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.sblk = &sm8750_lm_sblk,
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.lm_pair = LM_3,
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.pingpong = PINGPONG_2,
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.dspp = DSPP_2,
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}, {
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.name = "lm_3", .id = LM_3,
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.base = 0x11b000, .len = 0x400,
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.features = MIXER_MSM8998_MASK,
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.sblk = &sm8750_lm_sblk,
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.lm_pair = LM_2,
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.pingpong = PINGPONG_3,
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.dspp = DSPP_3,
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}, {
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.name = "lm_4", .id = LM_4,
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.base = 0x123000, .len = 0x400,
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.features = MIXER_MSM8998_MASK,
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.sblk = &sm8750_lm_sblk,
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.lm_pair = LM_5,
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.pingpong = PINGPONG_4,
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}, {
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.name = "lm_5", .id = LM_5,
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.base = 0x12b000, .len = 0x400,
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.features = MIXER_MSM8998_MASK,
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.sblk = &sm8750_lm_sblk,
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.lm_pair = LM_4,
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.pingpong = PINGPONG_5,
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}, {
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.name = "lm_6", .id = LM_6,
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.base = 0x133000, .len = 0x400,
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.features = MIXER_MSM8998_MASK,
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.sblk = &sm8750_lm_sblk,
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.lm_pair = LM_7,
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.pingpong = PINGPONG_6,
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}, {
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.name = "lm_7", .id = LM_7,
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.base = 0x13b000, .len = 0x400,
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.features = MIXER_MSM8998_MASK,
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.sblk = &sm8750_lm_sblk,
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.lm_pair = LM_6,
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.pingpong = PINGPONG_7,
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},
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};
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static const struct dpu_dspp_cfg kaanapali_dspp[] = {
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{
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.name = "dspp_0", .id = DSPP_0,
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.base = 0x105000, .len = 0x1800,
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.sblk = &sm8750_dspp_sblk,
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}, {
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.name = "dspp_1", .id = DSPP_1,
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.base = 0x10d000, .len = 0x1800,
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.sblk = &sm8750_dspp_sblk,
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}, {
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.name = "dspp_2", .id = DSPP_2,
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.base = 0x115000, .len = 0x1800,
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.sblk = &sm8750_dspp_sblk,
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}, {
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.name = "dspp_3", .id = DSPP_3,
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.base = 0x11d000, .len = 0x1800,
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.sblk = &sm8750_dspp_sblk,
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},
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};
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static const struct dpu_pingpong_cfg kaanapali_pp[] = {
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{
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.name = "pingpong_0", .id = PINGPONG_0,
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.base = 0x108000, .len = 0,
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.sblk = &kaanapali_pp_sblk,
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.merge_3d = MERGE_3D_0,
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
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}, {
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.name = "pingpong_1", .id = PINGPONG_1,
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.base = 0x110000, .len = 0,
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.sblk = &kaanapali_pp_sblk,
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.merge_3d = MERGE_3D_0,
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
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}, {
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.name = "pingpong_2", .id = PINGPONG_2,
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.base = 0x118000, .len = 0,
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.sblk = &kaanapali_pp_sblk,
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.merge_3d = MERGE_3D_1,
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
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}, {
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.name = "pingpong_3", .id = PINGPONG_3,
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.base = 0x120000, .len = 0,
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.sblk = &kaanapali_pp_sblk,
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.merge_3d = MERGE_3D_1,
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
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}, {
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.name = "pingpong_4", .id = PINGPONG_4,
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.base = 0x128000, .len = 0,
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.sblk = &kaanapali_pp_sblk,
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.merge_3d = MERGE_3D_2,
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
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}, {
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.name = "pingpong_5", .id = PINGPONG_5,
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.base = 0x130000, .len = 0,
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.sblk = &kaanapali_pp_sblk,
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.merge_3d = MERGE_3D_2,
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
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}, {
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.name = "pingpong_6", .id = PINGPONG_6,
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.base = 0x138000, .len = 0,
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.sblk = &kaanapali_pp_sblk,
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.merge_3d = MERGE_3D_3,
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 20),
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}, {
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.name = "pingpong_7", .id = PINGPONG_7,
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.base = 0x140000, .len = 0,
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.sblk = &kaanapali_pp_sblk,
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.merge_3d = MERGE_3D_3,
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 21),
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}, {
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.name = "pingpong_cwb_0", .id = PINGPONG_CWB_0,
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.base = 0x169000, .len = 0,
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.sblk = &kaanapali_pp_sblk,
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.merge_3d = MERGE_3D_4,
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}, {
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.name = "pingpong_cwb_1", .id = PINGPONG_CWB_1,
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.base = 0x169400, .len = 0,
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.sblk = &kaanapali_pp_sblk,
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.merge_3d = MERGE_3D_4,
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}, {
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.name = "pingpong_cwb_2", .id = PINGPONG_CWB_2,
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.base = 0x16a000, .len = 0,
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.sblk = &kaanapali_pp_sblk,
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.merge_3d = MERGE_3D_5,
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}, {
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.name = "pingpong_cwb_3", .id = PINGPONG_CWB_3,
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.base = 0x16a400, .len = 0,
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.sblk = &kaanapali_pp_sblk,
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.merge_3d = MERGE_3D_5,
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},
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};
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static const struct dpu_merge_3d_cfg kaanapali_merge_3d[] = {
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{
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.name = "merge_3d_0", .id = MERGE_3D_0,
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.base = 0x163000, .len = 0x1c,
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}, {
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.name = "merge_3d_1", .id = MERGE_3D_1,
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.base = 0x164000, .len = 0x1c,
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}, {
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.name = "merge_3d_2", .id = MERGE_3D_2,
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.base = 0x165000, .len = 0x1c,
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}, {
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.name = "merge_3d_3", .id = MERGE_3D_3,
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.base = 0x166000, .len = 0x1c,
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}, {
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.name = "merge_3d_4", .id = MERGE_3D_4,
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.base = 0x169700, .len = 0x1c,
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}, {
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.name = "merge_3d_5", .id = MERGE_3D_5,
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.base = 0x16a700, .len = 0x1c,
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},
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};
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/*
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* NOTE: Each display compression engine (DCE) contains dual hard
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* slice DSC encoders so both share same base address but with
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* its own different sub block address.
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*/
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static const struct dpu_dsc_cfg kaanapali_dsc[] = {
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{
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.name = "dce_0_0", .id = DSC_0,
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.base = 0x181000, .len = 0x8,
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.features = BIT(DPU_DSC_NATIVE_42x_EN),
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.sblk = &sm8750_dsc_sblk_0,
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}, {
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.name = "dce_0_1", .id = DSC_1,
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.base = 0x181000, .len = 0x8,
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.features = BIT(DPU_DSC_NATIVE_42x_EN),
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.sblk = &sm8750_dsc_sblk_1,
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}, {
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.name = "dce_1_0", .id = DSC_2,
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.base = 0x183000, .len = 0x8,
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.features = BIT(DPU_DSC_NATIVE_42x_EN),
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.sblk = &sm8750_dsc_sblk_0,
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+
}, {
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.name = "dce_1_1", .id = DSC_3,
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+
.base = 0x183000, .len = 0x8,
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+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
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+
.sblk = &sm8750_dsc_sblk_1,
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+
}, {
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+
.name = "dce_2_0", .id = DSC_4,
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+
.base = 0x185000, .len = 0x8,
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+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
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+
.sblk = &sm8750_dsc_sblk_0,
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+
}, {
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+
.name = "dce_2_1", .id = DSC_5,
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+
.base = 0x185000, .len = 0x8,
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+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
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+
.sblk = &sm8750_dsc_sblk_1,
344
+
}, {
345
+
.name = "dce_3_0", .id = DSC_6,
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+
.base = 0x187000, .len = 0x8,
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+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
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+
.sblk = &sm8750_dsc_sblk_0,
349
+
}, {
350
+
.name = "dce_3_1", .id = DSC_7,
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+
.base = 0x187000, .len = 0x8,
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.features = BIT(DPU_DSC_NATIVE_42x_EN),
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+
.sblk = &sm8750_dsc_sblk_1,
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+
},
355
+
};
356
+
357
+
static const struct dpu_wb_cfg kaanapali_wb[] = {
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+
{
359
+
.name = "wb_2", .id = WB_2,
360
+
.base = 0x16e000, .len = 0x2c8,
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+
.features = WB_SDM845_MASK,
362
+
.format_list = wb2_formats_rgb_yuv,
363
+
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
364
+
.xin_id = 6,
365
+
.vbif_idx = VBIF_RT,
366
+
.maxlinewidth = 4096,
367
+
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
368
+
},
369
+
};
370
+
371
+
static const struct dpu_cwb_cfg kaanapali_cwb[] = {
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+
{
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+
.name = "cwb_0", .id = CWB_0,
374
+
.base = 0x169200, .len = 0x20,
375
+
},
376
+
{
377
+
.name = "cwb_1", .id = CWB_1,
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+
.base = 0x169600, .len = 0x20,
379
+
},
380
+
{
381
+
.name = "cwb_2", .id = CWB_2,
382
+
.base = 0x16a200, .len = 0x20,
383
+
},
384
+
{
385
+
.name = "cwb_3", .id = CWB_3,
386
+
.base = 0x16a600, .len = 0x20,
387
+
},
388
+
};
389
+
390
+
static const struct dpu_intf_cfg kaanapali_intf[] = {
391
+
{
392
+
.name = "intf_0", .id = INTF_0,
393
+
.base = 0x18d000, .len = 0x4bc,
394
+
.type = INTF_DP,
395
+
.controller_id = MSM_DP_CONTROLLER_0,
396
+
.prog_fetch_lines_worst_case = 24,
397
+
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
398
+
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
399
+
}, {
400
+
.name = "intf_1", .id = INTF_1,
401
+
.base = 0x18e000, .len = 0x4bc,
402
+
.type = INTF_DSI,
403
+
.controller_id = MSM_DSI_CONTROLLER_0,
404
+
.prog_fetch_lines_worst_case = 24,
405
+
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
406
+
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
407
+
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
408
+
}, {
409
+
.name = "intf_2", .id = INTF_2,
410
+
.base = 0x18f000, .len = 0x4bc,
411
+
.type = INTF_DSI,
412
+
.controller_id = MSM_DSI_CONTROLLER_1,
413
+
.prog_fetch_lines_worst_case = 24,
414
+
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
415
+
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
416
+
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
417
+
}, {
418
+
.name = "intf_3", .id = INTF_3,
419
+
.base = 0x190000, .len = 0x4bc,
420
+
.type = INTF_DP,
421
+
.controller_id = MSM_DP_CONTROLLER_1,
422
+
.prog_fetch_lines_worst_case = 24,
423
+
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
424
+
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
425
+
},
426
+
};
427
+
428
+
static const struct dpu_perf_cfg kaanapali_perf_data = {
429
+
.max_bw_low = 21400000,
430
+
.max_bw_high = 30200000,
431
+
.min_core_ib = 2500000,
432
+
.min_llcc_ib = 0,
433
+
.min_dram_ib = 800000,
434
+
.min_prefill_lines = 35,
435
+
.danger_lut_tbl = {0x0ffff, 0x0ffff, 0x0},
436
+
.safe_lut_tbl = {0xff00, 0xff00, 0xffff},
437
+
.qos_lut_tbl = {
438
+
{.nentry = ARRAY_SIZE(kaanapali_qos_linear),
439
+
.entries = kaanapali_qos_linear
440
+
},
441
+
{.nentry = ARRAY_SIZE(kaanapali_qos_macrotile),
442
+
.entries = kaanapali_qos_macrotile
443
+
},
444
+
{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
445
+
.entries = sc7180_qos_nrt
446
+
},
447
+
/* TODO: macrotile-qseed is different from macrotile */
448
+
},
449
+
.cdp_cfg = {
450
+
{.rd_enable = 1, .wr_enable = 1},
451
+
{.rd_enable = 1, .wr_enable = 0}
452
+
},
453
+
.clk_inefficiency_factor = 105,
454
+
.bw_inefficiency_factor = 120,
455
+
};
456
+
457
+
static const struct dpu_mdss_version kaanapali_mdss_ver = {
458
+
.core_major_ver = 13,
459
+
.core_minor_ver = 0,
460
+
};
461
+
462
+
const struct dpu_mdss_cfg dpu_kaanapali_cfg = {
463
+
.mdss_ver = &kaanapali_mdss_ver,
464
+
.caps = &kaanapali_dpu_caps,
465
+
.mdp = &kaanapali_mdp,
466
+
.cdm = &dpu_cdm_13_x,
467
+
.ctl_count = ARRAY_SIZE(kaanapali_ctl),
468
+
.ctl = kaanapali_ctl,
469
+
.sspp_count = ARRAY_SIZE(kaanapali_sspp),
470
+
.sspp = kaanapali_sspp,
471
+
.mixer_count = ARRAY_SIZE(kaanapali_lm),
472
+
.mixer = kaanapali_lm,
473
+
.dspp_count = ARRAY_SIZE(kaanapali_dspp),
474
+
.dspp = kaanapali_dspp,
475
+
.pingpong_count = ARRAY_SIZE(kaanapali_pp),
476
+
.pingpong = kaanapali_pp,
477
+
.dsc_count = ARRAY_SIZE(kaanapali_dsc),
478
+
.dsc = kaanapali_dsc,
479
+
.merge_3d_count = ARRAY_SIZE(kaanapali_merge_3d),
480
+
.merge_3d = kaanapali_merge_3d,
481
+
.wb_count = ARRAY_SIZE(kaanapali_wb),
482
+
.wb = kaanapali_wb,
483
+
.cwb_count = ARRAY_SIZE(kaanapali_cwb),
484
+
.cwb = sm8650_cwb,
485
+
.intf_count = ARRAY_SIZE(kaanapali_intf),
486
+
.intf = kaanapali_intf,
487
+
.vbif_count = ARRAY_SIZE(sm8650_vbif),
488
+
.vbif = sm8650_vbif,
489
+
.perf = &kaanapali_perf_data,
490
+
};
491
+
492
+
#endif
+41
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+41
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
···
241
241
.rotation_cfg = NULL, \
242
242
}
243
243
244
+
/* kaanapali SSPP common configuration */
245
+
#define _VIG_SBLK_REC0_REC1(scaler_ver) \
246
+
{ \
247
+
.sspp_rec0_blk = {.name = "sspp_rec0", \
248
+
.base = 0x1000, .len = 0x180,}, \
249
+
.csc_blk = {.name = "csc", \
250
+
.base = 0x1800, .len = 0x100,}, \
251
+
.scaler_blk = {.name = "scaler", \
252
+
.version = scaler_ver, \
253
+
.base = 0x2000, .len = 0xec,}, \
254
+
.sspp_rec1_blk = {.name = "sspp_rec1", \
255
+
.base = 0x3000, .len = 0x180,}, \
256
+
.format_list = plane_formats_yuv, \
257
+
.num_formats = ARRAY_SIZE(plane_formats_yuv), \
258
+
.rotation_cfg = NULL, \
259
+
}
260
+
244
261
#define _VIG_SBLK_ROT(scaler_ver, rot_cfg) \
245
262
{ \
246
263
.scaler_blk = {.name = "scaler", \
···
346
329
static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_4 =
347
330
_VIG_SBLK(SSPP_SCALER_VER(3, 4));
348
331
332
+
static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_5 =
333
+
_VIG_SBLK_REC0_REC1(SSPP_SCALER_VER(3, 5));
334
+
349
335
static const struct dpu_sspp_sub_blks dpu_rgb_sblk = _RGB_SBLK();
350
336
351
337
static const struct dpu_sspp_sub_blks dpu_dma_sblk = _DMA_SBLK();
···
432
412
.len = 0x20, .version = 0x20000},
433
413
};
434
414
415
+
static const struct dpu_pingpong_sub_blks kaanapali_pp_sblk = {
416
+
.dither = {.name = "dither", .base = 0xc0,
417
+
.len = 0x40, .version = 0x30000},
418
+
};
419
+
435
420
/*************************************************************
436
421
* DSC sub blocks config
437
422
*************************************************************/
···
475
450
.id = CDM_0,
476
451
.len = 0x228,
477
452
.base = 0x79200,
453
+
};
454
+
455
+
static const struct dpu_cdm_cfg dpu_cdm_13_x = {
456
+
.name = "cdm_0",
457
+
.id = CDM_0,
458
+
.len = 0x240,
459
+
.base = 0x19e000,
478
460
};
479
461
480
462
/*************************************************************
···
671
639
{.fl = 0, .lut = 0x0011222222335777},
672
640
};
673
641
642
+
static const struct dpu_qos_lut_entry kaanapali_qos_linear[] = {
643
+
{.fl = 0, .lut = 0x0011223344556666},
644
+
};
645
+
674
646
static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
675
647
{.fl = 0, .lut = 0x0011223445566777 },
676
648
};
···
702
666
703
667
static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = {
704
668
{.fl = 0, .lut = 0x0011223344556677},
669
+
};
670
+
671
+
static const struct dpu_qos_lut_entry kaanapali_qos_macrotile[] = {
672
+
{.fl = 0, .lut = 0x0011223344556666},
705
673
};
706
674
707
675
static const struct dpu_qos_lut_entry sc8180x_qos_macrotile[] = {
···
767
727
#include "catalog/dpu_10_0_sm8650.h"
768
728
#include "catalog/dpu_12_0_sm8750.h"
769
729
#include "catalog/dpu_12_2_glymur.h"
730
+
#include "catalog/dpu_13_0_kaanapali.h"
+1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
···
764
764
};
765
765
766
766
extern const struct dpu_mdss_cfg dpu_glymur_cfg;
767
+
extern const struct dpu_mdss_cfg dpu_kaanapali_cfg;
767
768
extern const struct dpu_mdss_cfg dpu_msm8917_cfg;
768
769
extern const struct dpu_mdss_cfg dpu_msm8937_cfg;
769
770
extern const struct dpu_mdss_cfg dpu_msm8953_cfg;
+1
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+1
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
···
1506
1506
1507
1507
static const struct of_device_id dpu_dt_match[] = {
1508
1508
{ .compatible = "qcom,glymur-dpu", .data = &dpu_glymur_cfg, },
1509
+
{ .compatible = "qcom,kaanapali-dpu", .data = &dpu_kaanapali_cfg, },
1509
1510
{ .compatible = "qcom,msm8917-mdp5", .data = &dpu_msm8917_cfg, },
1510
1511
{ .compatible = "qcom,msm8937-mdp5", .data = &dpu_msm8937_cfg, },
1511
1512
{ .compatible = "qcom,msm8953-mdp5", .data = &dpu_msm8953_cfg, },