Merge tag 'mfd-next-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

-47

Documentation/devicetree/bindings/input/da9062-onkey.txt

··· 1 - * Dialog DA9061/62/63 OnKey Module 2 - 3 - This module is part of the DA9061/DA9062/DA9063. For more details about entire 4 - DA9062 and DA9061 chips see Documentation/devicetree/bindings/mfd/da9062.txt 5 - For DA9063 see Documentation/devicetree/bindings/mfd/dlg,da9063.yaml 6 - 7 - This module provides the KEY_POWER event. 8 - 9 - Required properties: 10 - 11 - - compatible: should be one of the following valid compatible string lines: 12 - "dlg,da9061-onkey", "dlg,da9062-onkey" 13 - "dlg,da9062-onkey" 14 - "dlg,da9063-onkey" 15 - 16 - Optional properties: 17 - 18 - - dlg,disable-key-power : Disable power-down using a long key-press. If this 19 - entry exists the OnKey driver will remove support for the KEY_POWER key 20 - press when triggered using a long press of the OnKey. 21 - 22 - Example: DA9063 23 - 24 - pmic0: da9063@58 { 25 - onkey { 26 - compatible = "dlg,da9063-onkey"; 27 - dlg,disable-key-power; 28 - }; 29 - }; 30 - 31 - Example: DA9062 32 - 33 - pmic0: da9062@58 { 34 - onkey { 35 - compatible = "dlg,da9062-onkey"; 36 - dlg,disable-key-power; 37 - }; 38 - }; 39 - 40 - Example: DA9061 using a fall-back compatible for the DA9062 onkey driver 41 - 42 - pmic0: da9061@58 { 43 - onkey { 44 - compatible = "dlg,da9061-onkey", "dlg,da9062-onkey"; 45 - dlg,disable-key-power; 46 - }; 47 - };

+38

Documentation/devicetree/bindings/input/dlg,da9062-onkey.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/input/dlg,da9062-onkey.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Dialog DA9061/62/63 OnKey Module 8 + 9 + maintainers: 10 + - Biju Das <biju.das.jz@bp.renesas.com> 11 + 12 + description: | 13 + This module is part of the DA9061/DA9062/DA9063. For more details about entire 14 + DA906{1,2,3} chips see Documentation/devicetree/bindings/mfd/dlg,da9063.yaml 15 + 16 + This module provides the KEY_POWER event. 17 + 18 + properties: 19 + compatible: 20 + oneOf: 21 + - enum: 22 + - dlg,da9062-onkey 23 + - dlg,da9063-onkey 24 + - items: 25 + - const: dlg,da9061-onkey 26 + - const: dlg,da9062-onkey 27 + 28 + dlg,disable-key-power: 29 + type: boolean 30 + description: 31 + Disable power-down using a long key-press. If this entry exists 32 + the OnKey driver will remove support for the KEY_POWER key press 33 + when triggered using a long press of the OnKey. 34 + 35 + required: 36 + - compatible 37 + 38 + additionalProperties: false

+99

Documentation/devicetree/bindings/mfd/atmel,hlcdc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/mfd/atmel,hlcdc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Atmel's HLCD Controller 8 + 9 + maintainers: 10 + - Nicolas Ferre <nicolas.ferre@microchip.com> 11 + - Alexandre Belloni <alexandre.belloni@bootlin.com> 12 + - Claudiu Beznea <claudiu.beznea@tuxon.dev> 13 + 14 + description: 15 + The Atmel HLCDC (HLCD Controller) IP available on Atmel SoCs exposes two 16 + subdevices, a PWM chip and a Display Controller. 17 + 18 + properties: 19 + compatible: 20 + enum: 21 + - atmel,at91sam9n12-hlcdc 22 + - atmel,at91sam9x5-hlcdc 23 + - atmel,sama5d2-hlcdc 24 + - atmel,sama5d3-hlcdc 25 + - atmel,sama5d4-hlcdc 26 + - microchip,sam9x60-hlcdc 27 + - microchip,sam9x75-xlcdc 28 + 29 + reg: 30 + maxItems: 1 31 + 32 + interrupts: 33 + maxItems: 1 34 + 35 + clocks: 36 + minItems: 3 37 + 38 + clock-names: 39 + items: 40 + - const: periph_clk 41 + - const: sys_clk 42 + - const: slow_clk 43 + - const: lvds_pll_clk 44 + minItems: 3 45 + 46 + display-controller: 47 + $ref: /schemas/display/atmel/atmel,hlcdc-display-controller.yaml 48 + 49 + pwm: 50 + $ref: /schemas/pwm/atmel,hlcdc-pwm.yaml 51 + 52 + required: 53 + - compatible 54 + - reg 55 + - clocks 56 + - clock-names 57 + - interrupts 58 + 59 + additionalProperties: false 60 + 61 + examples: 62 + - | 63 + #include <dt-bindings/clock/at91.h> 64 + #include <dt-bindings/dma/at91.h> 65 + #include <dt-bindings/interrupt-controller/arm-gic.h> 66 + 67 + lcd_controller: lcd-controller@f0030000 { 68 + compatible = "atmel,sama5d3-hlcdc"; 69 + reg = <0xf0030000 0x2000>; 70 + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; 71 + clock-names = "periph_clk", "sys_clk", "slow_clk"; 72 + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; 73 + 74 + display-controller { 75 + compatible = "atmel,hlcdc-display-controller"; 76 + pinctrl-names = "default"; 77 + pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; 78 + #address-cells = <1>; 79 + #size-cells = <0>; 80 + 81 + port@0 { 82 + #address-cells = <1>; 83 + #size-cells = <0>; 84 + reg = <0>; 85 + 86 + hlcdc_panel_output: endpoint@0 { 87 + reg = <0>; 88 + remote-endpoint = <&panel_input>; 89 + }; 90 + }; 91 + }; 92 + 93 + pwm { 94 + compatible = "atmel,hlcdc-pwm"; 95 + pinctrl-names = "default"; 96 + pinctrl-0 = <&pinctrl_lcd_pwm>; 97 + #pwm-cells = <3>; 98 + }; 99 + };

+99

Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/mfd/atmel,sama5d2-flexcom.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Microchip Flexcom (Flexible Serial Communication Unit) 8 + 9 + maintainers: 10 + - Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> 11 + 12 + description: 13 + The Microchip Flexcom is just a wrapper which embeds a SPI controller, 14 + an I2C controller and an USART. Only one function can be used at a 15 + time and is chosen at boot time according to the device tree. 16 + 17 + properties: 18 + compatible: 19 + oneOf: 20 + - const: atmel,sama5d2-flexcom 21 + - items: 22 + - const: microchip,sam9x7-flexcom 23 + - const: atmel,sama5d2-flexcom 24 + - items: 25 + - const: microchip,sama7g5-flexcom 26 + - const: atmel,sama5d2-flexcom 27 + 28 + 29 + reg: 30 + maxItems: 1 31 + 32 + clocks: 33 + maxItems: 1 34 + 35 + "#address-cells": 36 + const: 1 37 + 38 + "#size-cells": 39 + const: 1 40 + 41 + ranges: 42 + description: 43 + One range for the full I/O register region. (including USART, 44 + TWI and SPI registers). 45 + items: 46 + maxItems: 3 47 + 48 + atmel,flexcom-mode: 49 + description: | 50 + Specifies the flexcom mode as follows: 51 + 1: USART 52 + 2: SPI 53 + 3: I2C. 54 + $ref: /schemas/types.yaml#/definitions/uint32 55 + enum: [1, 2, 3] 56 + 57 + patternProperties: 58 + "^serial@[0-9a-f]+$": 59 + type: object 60 + description: 61 + Child node describing USART. See atmel-usart.txt for details 62 + of USART bindings. 63 + 64 + "^spi@[0-9a-f]+$": 65 + type: object 66 + description: 67 + Child node describing SPI. See ../spi/spi_atmel.txt for details 68 + of SPI bindings. 69 + 70 + "^i2c@[0-9a-f]+$": 71 + $ref: /schemas/i2c/atmel,at91sam-i2c.yaml 72 + description: 73 + Child node describing I2C. 74 + 75 + required: 76 + - compatible 77 + - reg 78 + - clocks 79 + - "#address-cells" 80 + - "#size-cells" 81 + - ranges 82 + - atmel,flexcom-mode 83 + 84 + additionalProperties: false 85 + 86 + examples: 87 + - | 88 + #include <dt-bindings/interrupt-controller/arm-gic.h> 89 + 90 + flx0: flexcom@f8034000 { 91 + compatible = "atmel,sama5d2-flexcom"; 92 + reg = <0xf8034000 0x200>; 93 + clocks = <&flx0_clk>; 94 + #address-cells = <1>; 95 + #size-cells = <1>; 96 + ranges = <0x0 0xf8034000 0x800>; 97 + atmel,flexcom-mode = <2>; 98 + }; 99 + ...

-64

Documentation/devicetree/bindings/mfd/atmel-flexcom.txt

··· 1 - * Device tree bindings for Atmel Flexcom (Flexible Serial Communication Unit) 2 - 3 - The Atmel Flexcom is just a wrapper which embeds a SPI controller, an I2C 4 - controller and an USART. Only one function can be used at a time and is chosen 5 - at boot time according to the device tree. 6 - 7 - Required properties: 8 - - compatible: Should be "atmel,sama5d2-flexcom" 9 - or "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom" 10 - - reg: Should be the offset/length value for Flexcom dedicated 11 - I/O registers (without USART, TWI or SPI registers). 12 - - clocks: Should be the Flexcom peripheral clock from PMC. 13 - - #address-cells: Should be <1> 14 - - #size-cells: Should be <1> 15 - - ranges: Should be one range for the full I/O register region 16 - (including USART, TWI and SPI registers). 17 - - atmel,flexcom-mode: Should be one of the following values: 18 - - <1> for USART 19 - - <2> for SPI 20 - - <3> for I2C 21 - 22 - Required child: 23 - A single available child device of type matching the "atmel,flexcom-mode" 24 - property. 25 - 26 - The phandle provided by the clocks property of the child is the same as one for 27 - the Flexcom parent. 28 - 29 - For other properties, please refer to the documentations of the respective 30 - device: 31 - - ../serial/atmel-usart.txt 32 - - ../spi/spi_atmel.txt 33 - - ../i2c/i2c-at91.txt 34 - 35 - Example: 36 - 37 - flexcom@f8034000 { 38 - compatible = "atmel,sama5d2-flexcom"; 39 - reg = <0xf8034000 0x200>; 40 - clocks = <&flx0_clk>; 41 - #address-cells = <1>; 42 - #size-cells = <1>; 43 - ranges = <0x0 0xf8034000 0x800>; 44 - atmel,flexcom-mode = <2>; 45 - 46 - spi@400 { 47 - compatible = "atmel,at91rm9200-spi"; 48 - reg = <0x400 0x200>; 49 - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 50 - pinctrl-names = "default"; 51 - pinctrl-0 = <&pinctrl_flx0_default>; 52 - #address-cells = <1>; 53 - #size-cells = <0>; 54 - clocks = <&flx0_clk>; 55 - clock-names = "spi_clk"; 56 - atmel,fifo-size = <32>; 57 - 58 - flash@0 { 59 - compatible = "atmel,at25f512b"; 60 - reg = <0>; 61 - spi-max-frequency = <20000000>; 62 - }; 63 - }; 64 - };

-56

Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt

··· 1 - Device-Tree bindings for Atmel's HLCDC (High LCD Controller) MFD driver 2 - 3 - Required properties: 4 - - compatible: value should be one of the following: 5 - "atmel,at91sam9n12-hlcdc" 6 - "atmel,at91sam9x5-hlcdc" 7 - "atmel,sama5d2-hlcdc" 8 - "atmel,sama5d3-hlcdc" 9 - "atmel,sama5d4-hlcdc" 10 - "microchip,sam9x60-hlcdc" 11 - "microchip,sam9x75-xlcdc" 12 - - reg: base address and size of the HLCDC device registers. 13 - - clock-names: the name of the 3 clocks requested by the HLCDC device. 14 - Should contain "periph_clk", "sys_clk" and "slow_clk". 15 - - clocks: should contain the 3 clocks requested by the HLCDC device. 16 - - interrupts: should contain the description of the HLCDC interrupt line 17 - 18 - The HLCDC IP exposes two subdevices: 19 - - a PWM chip: see ../pwm/atmel-hlcdc-pwm.txt 20 - - a Display Controller: see ../display/atmel/hlcdc-dc.txt 21 - 22 - Example: 23 - 24 - hlcdc: hlcdc@f0030000 { 25 - compatible = "atmel,sama5d3-hlcdc"; 26 - reg = <0xf0030000 0x2000>; 27 - clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; 28 - clock-names = "periph_clk","sys_clk", "slow_clk"; 29 - interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; 30 - 31 - hlcdc-display-controller { 32 - compatible = "atmel,hlcdc-display-controller"; 33 - pinctrl-names = "default"; 34 - pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; 35 - #address-cells = <1>; 36 - #size-cells = <0>; 37 - 38 - port@0 { 39 - #address-cells = <1>; 40 - #size-cells = <0>; 41 - reg = <0>; 42 - 43 - hlcdc_panel_output: endpoint@0 { 44 - reg = <0>; 45 - remote-endpoint = <&panel_input>; 46 - }; 47 - }; 48 - }; 49 - 50 - hlcdc_pwm: hlcdc-pwm { 51 - compatible = "atmel,hlcdc-pwm"; 52 - pinctrl-names = "default"; 53 - pinctrl-0 = <&pinctrl_lcd_pwm>; 54 - #pwm-cells = <3>; 55 - }; 56 - };

-124

Documentation/devicetree/bindings/mfd/da9062.txt

··· 1 - * Dialog DA9062 Power Management Integrated Circuit (PMIC) 2 - 3 - Product information for the DA9062 and DA9061 devices can be found here: 4 - - https://www.dialog-semiconductor.com/products/da9062 5 - - https://www.dialog-semiconductor.com/products/da9061 6 - 7 - The DA9062 PMIC consists of: 8 - 9 - Device Supply Names Description 10 - ------ ------------ ----------- 11 - da9062-regulator : : LDOs & BUCKs 12 - da9062-rtc : : Real-Time Clock 13 - da9062-onkey : : On Key 14 - da9062-watchdog : : Watchdog Timer 15 - da9062-thermal : : Thermal 16 - da9062-gpio : : GPIOs 17 - 18 - The DA9061 PMIC consists of: 19 - 20 - Device Supply Names Description 21 - ------ ------------ ----------- 22 - da9062-regulator : : LDOs & BUCKs 23 - da9062-onkey : : On Key 24 - da9062-watchdog : : Watchdog Timer 25 - da9062-thermal : : Thermal 26 - 27 - ====== 28 - 29 - Required properties: 30 - 31 - - compatible : Should be 32 - "dlg,da9062" for DA9062 33 - "dlg,da9061" for DA9061 34 - - reg : Specifies the I2C slave address (this defaults to 0x58 but it can be 35 - modified to match the chip's OTP settings). 36 - 37 - Optional properties: 38 - 39 - - gpio-controller : Marks the device as a gpio controller. 40 - - #gpio-cells : Should be two. The first cell is the pin number and the 41 - second cell is used to specify the gpio polarity. 42 - 43 - See Documentation/devicetree/bindings/gpio/gpio.txt for further information on 44 - GPIO bindings. 45 - 46 - - interrupts : IRQ line information. 47 - - interrupt-controller 48 - 49 - See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for 50 - further information on IRQ bindings. 51 - 52 - Sub-nodes: 53 - 54 - - regulators : This node defines the settings for the LDOs and BUCKs. 55 - The DA9062 regulators are bound using their names listed below: 56 - 57 - buck1 : BUCK_1 58 - buck2 : BUCK_2 59 - buck3 : BUCK_3 60 - buck4 : BUCK_4 61 - ldo1 : LDO_1 62 - ldo2 : LDO_2 63 - ldo3 : LDO_3 64 - ldo4 : LDO_4 65 - 66 - The DA9061 regulators are bound using their names listed below: 67 - 68 - buck1 : BUCK_1 69 - buck2 : BUCK_2 70 - buck3 : BUCK_3 71 - ldo1 : LDO_1 72 - ldo2 : LDO_2 73 - ldo3 : LDO_3 74 - ldo4 : LDO_4 75 - 76 - The component follows the standard regulator framework and the bindings 77 - details of individual regulator device can be found in: 78 - Documentation/devicetree/bindings/regulator/regulator.txt 79 - 80 - regulator-initial-mode may be specified for buck regulators using mode values 81 - from include/dt-bindings/regulator/dlg,da9063-regulator.h. 82 - 83 - - rtc : This node defines settings required for the Real-Time Clock associated 84 - with the DA9062. There are currently no entries in this binding, however 85 - compatible = "dlg,da9062-rtc" should be added if a node is created. 86 - 87 - - onkey : See ../input/da9062-onkey.txt 88 - 89 - - watchdog: See ../watchdog/da9062-wdt.txt 90 - 91 - - thermal : See ../thermal/da9062-thermal.txt 92 - 93 - Example: 94 - 95 - pmic0: da9062@58 { 96 - compatible = "dlg,da9062"; 97 - reg = <0x58>; 98 - interrupt-parent = <&gpio6>; 99 - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 100 - interrupt-controller; 101 - 102 - rtc { 103 - compatible = "dlg,da9062-rtc"; 104 - }; 105 - 106 - regulators { 107 - DA9062_BUCK1: buck1 { 108 - regulator-name = "BUCK1"; 109 - regulator-min-microvolt = <300000>; 110 - regulator-max-microvolt = <1570000>; 111 - regulator-min-microamp = <500000>; 112 - regulator-max-microamp = <2000000>; 113 - regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>; 114 - regulator-boot-on; 115 - }; 116 - DA9062_LDO1: ldo1 { 117 - regulator-name = "LDO_1"; 118 - regulator-min-microvolt = <900000>; 119 - regulator-max-microvolt = <3600000>; 120 - regulator-boot-on; 121 - }; 122 - }; 123 - }; 124 -

+217 -36

Documentation/devicetree/bindings/mfd/dlg,da9063.yaml

··· 4 4 $id: http://devicetree.org/schemas/mfd/dlg,da9063.yaml# 5 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 - title: Dialog DA9063/DA9063L Power Management Integrated Circuit (PMIC) 7 + title: Dialog DA906{3L,3,2,1} Power Management Integrated Circuit (PMIC) 8 8 9 9 maintainers: 10 10 - Steve Twiss <stwiss.opensource@diasemi.com> ··· 17 17 moment where all voltage monitors are disabled. Next, as da9063 only supports 18 18 UV *and* OV monitoring, both must be set to the same severity and value 19 19 (0: disable, 1: enable). 20 + Product information for the DA906{3L,3,2,1} devices can be found here: 21 + - https://www.dialog-semiconductor.com/products/da9063l 22 + - https://www.dialog-semiconductor.com/products/da9063 23 + - https://www.dialog-semiconductor.com/products/da9062 24 + - https://www.dialog-semiconductor.com/products/da9061 20 25 21 26 properties: 22 27 compatible: 23 28 enum: 29 + - dlg,da9061 30 + - dlg,da9062 24 31 - dlg,da9063 25 32 - dlg,da9063l 26 33 ··· 42 35 "#interrupt-cells": 43 36 const: 2 44 37 45 - dlg,use-sw-pm: 46 - type: boolean 47 - description: 48 - Disable the watchdog during suspend. 49 - Only use this option if you can't use the watchdog automatic suspend 50 - function during a suspend (see register CONTROL_B). 38 + gpio-controller: true 51 39 52 - watchdog: 40 + "#gpio-cells": 41 + const: 2 42 + 43 + gpio: 53 44 type: object 54 - $ref: /schemas/watchdog/watchdog.yaml# 55 - unevaluatedProperties: false 45 + additionalProperties: false 56 46 properties: 57 47 compatible: 58 - const: dlg,da9063-watchdog 48 + const: dlg,da9062-gpio 49 + 50 + onkey: 51 + $ref: /schemas/input/dlg,da9062-onkey.yaml 52 + 53 + regulators: 54 + type: object 55 + additionalProperties: false 56 + patternProperties: 57 + "^(ldo([1-9]|1[01])|bcore([1-2]|s-merged)|b(pro|mem|io|peri)|bmem-bio-merged|buck[1-4])$": 58 + $ref: /schemas/regulator/regulator.yaml 59 + unevaluatedProperties: false 59 60 60 61 rtc: 61 62 type: object ··· 71 56 unevaluatedProperties: false 72 57 properties: 73 58 compatible: 74 - const: dlg,da9063-rtc 59 + enum: 60 + - dlg,da9062-rtc 61 + - dlg,da9063-rtc 75 62 76 - onkey: 63 + thermal: 64 + $ref: /schemas/thermal/dlg,da9062-thermal.yaml 65 + 66 + watchdog: 67 + $ref: /schemas/watchdog/dlg,da9062-watchdog.yaml 68 + 69 + patternProperties: 70 + "^(.+-hog(-[0-9]+)?)$": 77 71 type: object 78 - $ref: /schemas/input/input.yaml# 79 - unevaluatedProperties: false 80 - properties: 81 - compatible: 82 - const: dlg,da9063-onkey 83 72 84 - dlg,disable-key-power: 85 - type: boolean 86 - description: | 87 - Disable power-down using a long key-press. 88 - If this entry does not exist then by default the key-press triggered 89 - power down is enabled and the OnKey will support both KEY_POWER and 90 - KEY_SLEEP. 91 - 92 - regulators: 93 - type: object 94 - additionalProperties: false 95 - patternProperties: 96 - "^(ldo([1-9]|1[01])|bcore([1-2]|s-merged)|b(pro|mem|io|peri)|bmem-bio-merged)$": 97 - $ref: /schemas/regulator/regulator.yaml 98 - unevaluatedProperties: false 73 + required: 74 + - gpio-hog 99 75 100 76 required: 101 77 - compatible 102 78 - reg 103 - - interrupts 104 - - interrupt-controller 79 + 80 + allOf: 81 + - if: 82 + properties: 83 + compatible: 84 + contains: 85 + enum: 86 + - dlg,da9063 87 + - dlg,da9063l 88 + then: 89 + properties: 90 + gpio-controller: false 91 + "#gpio-cells": false 92 + gpio: false 93 + regulators: 94 + patternProperties: 95 + "^buck[1-4]$": false 96 + thermal: false 97 + required: 98 + - interrupts 99 + - interrupt-controller 100 + - '#interrupt-cells' 101 + 102 + - if: 103 + properties: 104 + compatible: 105 + contains: 106 + enum: 107 + - dlg,da9062 108 + then: 109 + properties: 110 + regulators: 111 + patternProperties: 112 + "^(ldo([5-9]|10|11)|bcore([1-2]|s-merged)|b(pro|mem|io|peri)|bmem-bio-merged)$": false 113 + required: 114 + - gpio 115 + - onkey 116 + - rtc 117 + - thermal 118 + - watchdog 119 + 120 + - if: 121 + properties: 122 + compatible: 123 + contains: 124 + enum: 125 + - dlg,da9061 126 + then: 127 + properties: 128 + gpio-controller: false 129 + "#gpio-cells": false 130 + gpio: false 131 + regulators: 132 + patternProperties: 133 + "^(ldo([5-9]|10|11)|bcore([1-2]|s-merged)|b(pro|mem|io|peri)|bmem-bio-merged|buck4)$": false 134 + rtc: false 135 + required: 136 + - onkey 137 + - thermal 138 + - watchdog 105 139 106 140 additionalProperties: false 107 141 ··· 163 99 pmic@58 { 164 100 compatible = "dlg,da9063"; 165 101 reg = <0x58>; 166 - #interrupt-cells = <2>; 167 102 interrupt-parent = <&gpio6>; 168 103 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 169 104 interrupt-controller; 105 + #interrupt-cells = <2>; 170 106 171 107 rtc { 172 108 compatible = "dlg,da9063-rtc"; ··· 204 140 regulator-ov-protection-microvolt = <1>; 205 141 regulator-always-on; 206 142 }; 143 + }; 144 + }; 145 + }; 146 + 147 + - | 148 + #include <dt-bindings/interrupt-controller/irq.h> 149 + #include <dt-bindings/regulator/dlg,da9063-regulator.h> 150 + i2c { 151 + #address-cells = <1>; 152 + #size-cells = <0>; 153 + pmic@58 { 154 + compatible = "dlg,da9062"; 155 + reg = <0x58>; 156 + gpio-controller; 157 + #gpio-cells = <2>; 158 + 159 + sd0-pwr-sel-hog { 160 + gpio-hog; 161 + gpios = <1 0>; 162 + input; 163 + line-name = "SD0_PWR_SEL"; 164 + }; 165 + 166 + sd1-pwr-sel-hog { 167 + gpio-hog; 168 + gpios = <2 0>; 169 + input; 170 + line-name = "SD1_PWR_SEL"; 171 + }; 172 + 173 + sw-et0-en-hog { 174 + gpio-hog; 175 + gpios = <3 0>; 176 + input; 177 + line-name = "SW_ET0_EN#"; 178 + }; 179 + 180 + pmic-good-hog { 181 + gpio-hog; 182 + gpios = <4 0>; 183 + output-high; 184 + line-name = "PMIC_PGOOD"; 185 + }; 186 + 187 + gpio { 188 + compatible = "dlg,da9062-gpio"; 189 + }; 190 + 191 + onkey { 192 + compatible = "dlg,da9062-onkey"; 193 + }; 194 + 195 + regulators { 196 + buck1 { 197 + regulator-name = "vdd_arm"; 198 + regulator-min-microvolt = <925000>; 199 + regulator-max-microvolt = <1380000>; 200 + regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>; 201 + regulator-always-on; 202 + }; 203 + buck2 { 204 + regulator-name = "vdd_soc"; 205 + regulator-min-microvolt = <1150000>; 206 + regulator-max-microvolt = <1380000>; 207 + regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>; 208 + regulator-always-on; 209 + }; 210 + buck3 { 211 + regulator-name = "vdd_ddr3"; 212 + regulator-min-microvolt = <1500000>; 213 + regulator-max-microvolt = <1500000>; 214 + regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>; 215 + regulator-always-on; 216 + }; 217 + buck4 { 218 + regulator-name = "vdd_eth"; 219 + regulator-min-microvolt = <1200000>; 220 + regulator-max-microvolt = <1200000>; 221 + regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>; 222 + regulator-always-on; 223 + }; 224 + ldo1 { 225 + regulator-name = "vdd_snvs"; 226 + regulator-min-microvolt = <3000000>; 227 + regulator-max-microvolt = <3000000>; 228 + regulator-always-on; 229 + }; 230 + ldo2 { 231 + regulator-name = "vdd_high"; 232 + regulator-min-microvolt = <3000000>; 233 + regulator-max-microvolt = <3000000>; 234 + regulator-always-on; 235 + }; 236 + ldo3 { 237 + regulator-name = "vdd_eth_io"; 238 + regulator-min-microvolt = <2500000>; 239 + regulator-max-microvolt = <2500000>; 240 + }; 241 + ldo4 { 242 + regulator-name = "vdd_emmc"; 243 + regulator-min-microvolt = <1800000>; 244 + regulator-max-microvolt = <1800000>; 245 + regulator-always-on; 246 + }; 247 + }; 248 + 249 + rtc { 250 + compatible = "dlg,da9062-rtc"; 251 + }; 252 + 253 + thermal { 254 + compatible = "dlg,da9062-thermal"; 255 + }; 256 + 257 + watchdog { 258 + compatible = "dlg,da9062-watchdog"; 259 + dlg,use-sw-pm; 207 260 }; 208 261 }; 209 262 };

+7

Documentation/devicetree/bindings/mfd/google,cros-ec.yaml

··· 93 93 '#size-cells': 94 94 const: 0 95 95 96 + '#gpio-cells': 97 + const: 2 98 + 99 + gpio-controller: true 100 + 96 101 typec: 97 102 $ref: /schemas/chrome/google,cros-ec-typec.yaml# 98 103 ··· 280 275 interrupts = <99 0>; 281 276 interrupt-parent = <&gpio7>; 282 277 spi-max-frequency = <5000000>; 278 + #gpio-cells = <2>; 279 + gpio-controller; 283 280 284 281 proximity { 285 282 compatible = "google,cros-ec-mkbp-proximity";

+1 -1

Documentation/devicetree/bindings/mfd/iqs62x.yaml

··· 31 31 maxItems: 1 32 32 33 33 firmware-name: 34 - $ref: /schemas/types.yaml#/definitions/string 34 + maxItems: 1 35 35 description: 36 36 Specifies the name of the calibration and configuration file selected by 37 37 the driver. If this property is omitted, the name is chosen based on the

+2

Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml

··· 19 19 - enum: 20 20 - qcom,msm8976-tcsr 21 21 - qcom,msm8998-tcsr 22 + - qcom,qcm2290-tcsr 22 23 - qcom,qcs404-tcsr 23 24 - qcom,sc7180-tcsr 24 25 - qcom,sc7280-tcsr ··· 29 28 - qcom,sdx55-tcsr 30 29 - qcom,sdx65-tcsr 31 30 - qcom,sm4450-tcsr 31 + - qcom,sm6115-tcsr 32 32 - qcom,sm8150-tcsr 33 33 - qcom,sm8250-tcsr 34 34 - qcom,sm8350-tcsr

+3

Documentation/devicetree/bindings/mfd/syscon.yaml

··· 72 72 - rockchip,rk3588-qos 73 73 - rockchip,rv1126-qos 74 74 - starfive,jh7100-sysmain 75 + - ti,am62-usb-phy-ctrl 75 76 - ti,am654-dss-oldi-io-ctrl 77 + - ti,am654-serdes-ctrl 78 + - ti,j784s4-pcie-ctrl 76 79 77 80 - const: syscon 78 81

+2

Documentation/devicetree/bindings/mfd/ti,twl.yaml

··· 34 34 35 35 interrupt-controller: true 36 36 37 + system-power-controller: true 38 + 37 39 "#interrupt-cells": 38 40 const: 1 39 41

-36

Documentation/devicetree/bindings/thermal/da9062-thermal.txt

··· 1 - * Dialog DA9062/61 TJUNC Thermal Module 2 - 3 - This module is part of the DA9061/DA9062. For more details about entire 4 - DA9062 and DA9061 chips see Documentation/devicetree/bindings/mfd/da9062.txt 5 - 6 - Junction temperature thermal module uses an interrupt signal to identify 7 - high THERMAL_TRIP_HOT temperatures for the PMIC device. 8 - 9 - Required properties: 10 - 11 - - compatible: should be one of the following valid compatible string lines: 12 - "dlg,da9061-thermal", "dlg,da9062-thermal" 13 - "dlg,da9062-thermal" 14 - 15 - Optional properties: 16 - 17 - - polling-delay-passive : Specify the polling period, measured in 18 - milliseconds, between thermal zone device update checks. 19 - 20 - Example: DA9062 21 - 22 - pmic0: da9062@58 { 23 - thermal { 24 - compatible = "dlg,da9062-thermal"; 25 - polling-delay-passive = <3000>; 26 - }; 27 - }; 28 - 29 - Example: DA9061 using a fall-back compatible for the DA9062 onkey driver 30 - 31 - pmic0: da9061@58 { 32 - thermal { 33 - compatible = "dlg,da9061-thermal", "dlg,da9062-thermal"; 34 - polling-delay-passive = <3000>; 35 - }; 36 - };

+35

Documentation/devicetree/bindings/thermal/dlg,da9062-thermal.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/thermal/dlg,da9062-thermal.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Dialog DA9062/61 TJUNC Thermal Module 8 + 9 + maintainers: 10 + - Biju Das <biju.das.jz@bp.renesas.com> 11 + 12 + description: | 13 + This module is part of the DA9061/DA9062. For more details about entire 14 + DA906{1,2} chips see Documentation/devicetree/bindings/mfd/dlg,da9063.yaml 15 + 16 + Junction temperature thermal module uses an interrupt signal to identify 17 + high THERMAL_TRIP_HOT temperatures for the PMIC device. 18 + 19 + properties: 20 + compatible: 21 + oneOf: 22 + - const: dlg,da9062-thermal 23 + - items: 24 + - const: dlg,da9061-thermal 25 + - const: dlg,da9062-thermal 26 + 27 + polling-delay-passive: 28 + description: 29 + Specify the polling period, measured in milliseconds, between 30 + thermal zone device update checks. 31 + 32 + required: 33 + - compatible 34 + 35 + additionalProperties: false

+9 -3

MAINTAINERS

··· 5012 5012 S: Maintained 5013 5013 F: drivers/platform/chrome/cros_hps_i2c.c 5014 5014 5015 + CHROMEOS EC WATCHDOG 5016 + M: Lukasz Majczak <lma@chromium.org> 5017 + L: chrome-platform@lists.linux.dev 5018 + S: Maintained 5019 + F: drivers/watchdog/cros_ec_wdt.c 5020 + 5015 5021 CHRONTEL CH7322 CEC DRIVER 5016 5022 M: Joe Tessler <jrt@google.com> 5017 5023 L: linux-media@vger.kernel.org ··· 6187 6181 M: Support Opensource <support.opensource@diasemi.com> 6188 6182 S: Supported 6189 6183 W: http://www.dialog-semiconductor.com/products 6190 - F: Documentation/devicetree/bindings/input/da90??-onkey.txt 6191 6184 F: Documentation/devicetree/bindings/input/dlg,da72??.txt 6185 + F: Documentation/devicetree/bindings/input/dlg,da9062-onkey.yaml 6192 6186 F: Documentation/devicetree/bindings/mfd/da90*.txt 6193 6187 F: Documentation/devicetree/bindings/mfd/dlg,da90*.yaml 6194 6188 F: Documentation/devicetree/bindings/regulator/da92*.txt 6195 6189 F: Documentation/devicetree/bindings/regulator/dlg,da9*.yaml 6196 6190 F: Documentation/devicetree/bindings/regulator/dlg,slg51000.yaml 6197 6191 F: Documentation/devicetree/bindings/sound/da[79]*.txt 6198 - F: Documentation/devicetree/bindings/thermal/da90??-thermal.txt 6199 - F: Documentation/devicetree/bindings/watchdog/dlg,da90??-watchdog.yaml 6192 + F: Documentation/devicetree/bindings/thermal/dlg,da9062-thermal.yaml 6193 + F: Documentation/devicetree/bindings/watchdog/dlg,da9062-watchdog.yaml 6200 6194 F: Documentation/hwmon/da90??.rst 6201 6195 F: drivers/gpio/gpio-da90??.c 6202 6196 F: drivers/hwmon/da90??-hwmon.c

+1

drivers/mfd/Kconfig

··· 1773 1773 bool "TI TWL4030/TWL5030/TWL6030/TPS659x0 Support" 1774 1774 depends on I2C=y 1775 1775 select IRQ_DOMAIN 1776 + select MFD_CORE 1776 1777 select REGMAP_I2C 1777 1778 help 1778 1779 Say yes here if you have TWL4030 / TWL6030 family chip on your board.

+1 -1

drivers/mfd/ac100.c

··· 72 72 .wr_table = &ac100_writeable_table, 73 73 .volatile_table = &ac100_volatile_table, 74 74 .max_register = AC100_RTC_GP(15), 75 - .cache_type = REGCACHE_RBTREE, 75 + .cache_type = REGCACHE_MAPLE, 76 76 }; 77 77 78 78 static struct mfd_cell ac100_cells[] = {

+3 -1

drivers/mfd/altera-sysmgr.c

··· 109 109 110 110 dev = driver_find_device_by_of_node(&altr_sysmgr_driver.driver, 111 111 (void *)sysmgr_np); 112 - of_node_put(sysmgr_np); 112 + if (property) 113 + of_node_put(sysmgr_np); 114 + 113 115 if (!dev) 114 116 return ERR_PTR(-EPROBE_DEFER); 115 117

+1 -1

drivers/mfd/as3711.c

··· 106 106 .precious_reg = as3711_precious_reg, 107 107 .max_register = AS3711_MAX_REG, 108 108 .num_reg_defaults_raw = AS3711_NUM_REGS, 109 - .cache_type = REGCACHE_RBTREE, 109 + .cache_type = REGCACHE_MAPLE, 110 110 }; 111 111 112 112 #ifdef CONFIG_OF

+1 -1

drivers/mfd/as3722.c

··· 299 299 .reg_bits = 8, 300 300 .val_bits = 8, 301 301 .max_register = AS3722_MAX_REGISTER, 302 - .cache_type = REGCACHE_RBTREE, 302 + .cache_type = REGCACHE_MAPLE, 303 303 .rd_table = &as3722_readable_table, 304 304 .wr_table = &as3722_writable_table, 305 305 .volatile_table = &as3722_volatile_table,

+2 -2

drivers/mfd/axp20x.c

··· 352 352 .wr_table = &axp192_writeable_table, 353 353 .volatile_table = &axp192_volatile_table, 354 354 .max_register = AXP20X_CC_CTRL, 355 - .cache_type = REGCACHE_RBTREE, 355 + .cache_type = REGCACHE_MAPLE, 356 356 }; 357 357 358 358 static const struct regmap_config axp20x_regmap_config = { ··· 388 388 .wr_table = &axp313a_writeable_table, 389 389 .volatile_table = &axp313a_volatile_table, 390 390 .max_register = AXP313A_IRQ_STATE, 391 - .cache_type = REGCACHE_RBTREE, 391 + .cache_type = REGCACHE_MAPLE, 392 392 }; 393 393 394 394 static const struct regmap_config axp806_regmap_config = {

+2 -2

drivers/mfd/bcm590xx.c

··· 27 27 .reg_bits = 8, 28 28 .val_bits = 8, 29 29 .max_register = BCM590XX_MAX_REGISTER_PRI, 30 - .cache_type = REGCACHE_RBTREE, 30 + .cache_type = REGCACHE_MAPLE, 31 31 }; 32 32 33 33 static const struct regmap_config bcm590xx_regmap_config_sec = { 34 34 .reg_bits = 8, 35 35 .val_bits = 8, 36 36 .max_register = BCM590XX_MAX_REGISTER_SEC, 37 - .cache_type = REGCACHE_RBTREE, 37 + .cache_type = REGCACHE_MAPLE, 38 38 }; 39 39 40 40 static int bcm590xx_i2c_probe(struct i2c_client *i2c_pri)

+2 -2

drivers/mfd/bd9571mwv.c

··· 67 67 static const struct regmap_config bd9571mwv_regmap_config = { 68 68 .reg_bits = 8, 69 69 .val_bits = 8, 70 - .cache_type = REGCACHE_RBTREE, 70 + .cache_type = REGCACHE_MAPLE, 71 71 .rd_table = &bd9571mwv_readable_table, 72 72 .wr_table = &bd9571mwv_writable_table, 73 73 .volatile_table = &bd9571mwv_volatile_table, ··· 152 152 static const struct regmap_config bd9574mwf_regmap_config = { 153 153 .reg_bits = 8, 154 154 .val_bits = 8, 155 - .cache_type = REGCACHE_RBTREE, 155 + .cache_type = REGCACHE_MAPLE, 156 156 .rd_table = &bd9574mwf_readable_table, 157 157 .wr_table = &bd9574mwf_writable_table, 158 158 .volatile_table = &bd9574mwf_volatile_table,

+18

drivers/mfd/cros_ec_dev.c

··· 74 74 { .name = "cros-ec-cec", }, 75 75 }; 76 76 77 + static const struct mfd_cell cros_ec_gpio_cells[] = { 78 + { .name = "cros-ec-gpio", }, 79 + }; 80 + 77 81 static const struct mfd_cell cros_ec_rtc_cells[] = { 78 82 { .name = "cros-ec-rtc", }, 79 83 }; ··· 95 91 { .name = "cros-usbpd-notify", }, 96 92 }; 97 93 94 + static const struct mfd_cell cros_ec_wdt_cells[] = { 95 + { .name = "cros-ec-wdt", } 96 + }; 97 + 98 98 static const struct cros_feature_to_cells cros_subdevices[] = { 99 99 { 100 100 .id = EC_FEATURE_CEC, 101 101 .mfd_cells = cros_ec_cec_cells, 102 102 .num_cells = ARRAY_SIZE(cros_ec_cec_cells), 103 + }, 104 + { 105 + .id = EC_FEATURE_GPIO, 106 + .mfd_cells = cros_ec_gpio_cells, 107 + .num_cells = ARRAY_SIZE(cros_ec_gpio_cells), 103 108 }, 104 109 { 105 110 .id = EC_FEATURE_RTC, ··· 119 106 .id = EC_FEATURE_USB_PD, 120 107 .mfd_cells = cros_usbpd_charger_cells, 121 108 .num_cells = ARRAY_SIZE(cros_usbpd_charger_cells), 109 + }, 110 + { 111 + .id = EC_FEATURE_HANG_DETECT, 112 + .mfd_cells = cros_ec_wdt_cells, 113 + .num_cells = ARRAY_SIZE(cros_ec_wdt_cells), 122 114 }, 123 115 }; 124 116

+8 -7

drivers/mfd/cs42l43-i2c.c

··· 6 6 * Cirrus Logic International Semiconductor Ltd. 7 7 */ 8 8 9 + #include <linux/array_size.h> 9 10 #include <linux/err.h> 10 - #include <linux/errno.h> 11 11 #include <linux/i2c.h> 12 + #include <linux/mfd/cs42l43.h> 12 13 #include <linux/mfd/cs42l43-regs.h> 14 + #include <linux/mod_devicetable.h> 13 15 #include <linux/module.h> 16 + #include <linux/pm.h> 17 + #include <linux/regmap.h> 14 18 15 19 #include "cs42l43.h" 16 20 ··· 38 34 static int cs42l43_i2c_probe(struct i2c_client *i2c) 39 35 { 40 36 struct cs42l43 *cs42l43; 41 - int ret; 42 37 43 38 cs42l43 = devm_kzalloc(&i2c->dev, sizeof(*cs42l43), GFP_KERNEL); 44 39 if (!cs42l43) ··· 49 46 cs42l43->attached = true; 50 47 51 48 cs42l43->regmap = devm_regmap_init_i2c(i2c, &cs42l43_i2c_regmap); 52 - if (IS_ERR(cs42l43->regmap)) { 53 - ret = PTR_ERR(cs42l43->regmap); 54 - dev_err(cs42l43->dev, "Failed to allocate regmap: %d\n", ret); 55 - return ret; 56 - } 49 + if (IS_ERR(cs42l43->regmap)) 50 + return dev_err_probe(cs42l43->dev, PTR_ERR(cs42l43->regmap), 51 + "Failed to allocate regmap\n"); 57 52 58 53 return cs42l43_dev_probe(cs42l43); 59 54 }

+8 -7

drivers/mfd/cs42l43-sdw.c

··· 6 6 * Cirrus Logic International Semiconductor Ltd. 7 7 */ 8 8 9 + #include <linux/array_size.h> 9 10 #include <linux/device.h> 10 11 #include <linux/err.h> 11 - #include <linux/errno.h> 12 + #include <linux/mfd/cs42l43.h> 12 13 #include <linux/mfd/cs42l43-regs.h> 14 + #include <linux/mod_devicetable.h> 13 15 #include <linux/module.h> 16 + #include <linux/pm.h> 17 + #include <linux/regmap.h> 14 18 #include <linux/soundwire/sdw.h> 15 19 #include <linux/soundwire/sdw_registers.h> 16 20 #include <linux/soundwire/sdw_type.h> ··· 171 167 { 172 168 struct cs42l43 *cs42l43; 173 169 struct device *dev = &sdw->dev; 174 - int ret; 175 170 176 171 cs42l43 = devm_kzalloc(dev, sizeof(*cs42l43), GFP_KERNEL); 177 172 if (!cs42l43) ··· 180 177 cs42l43->sdw = sdw; 181 178 182 179 cs42l43->regmap = devm_regmap_init_sdw(sdw, &cs42l43_sdw_regmap); 183 - if (IS_ERR(cs42l43->regmap)) { 184 - ret = PTR_ERR(cs42l43->regmap); 185 - dev_err(cs42l43->dev, "Failed to allocate regmap: %d\n", ret); 186 - return ret; 187 - } 180 + if (IS_ERR(cs42l43->regmap)) 181 + return dev_err_probe(cs42l43->dev, PTR_ERR(cs42l43->regmap), 182 + "Failed to allocate regmap\n"); 188 183 189 184 return cs42l43_dev_probe(cs42l43); 190 185 }

+66 -58

drivers/mfd/cs42l43.c

··· 6 6 * Cirrus Logic International Semiconductor Ltd. 7 7 */ 8 8 9 + #include <linux/array_size.h> 9 10 #include <linux/bitops.h> 10 11 #include <linux/build_bug.h> 11 12 #include <linux/delay.h> 13 + #include <linux/device.h> 12 14 #include <linux/err.h> 13 - #include <linux/errno.h> 14 15 #include <linux/firmware.h> 16 + #include <linux/gpio/consumer.h> 15 17 #include <linux/jiffies.h> 16 18 #include <linux/mfd/core.h> 19 + #include <linux/mfd/cs42l43.h> 17 20 #include <linux/mfd/cs42l43-regs.h> 18 21 #include <linux/module.h> 22 + #include <linux/pm.h> 19 23 #include <linux/pm_runtime.h> 24 + #include <linux/regmap.h> 20 25 #include <linux/soundwire/sdw.h> 26 + #include <linux/types.h> 21 27 22 28 #include "cs42l43.h" 23 29 24 - #define CS42L43_RESET_DELAY 20 30 + #define CS42L43_RESET_DELAY_MS 20 25 31 26 - #define CS42L43_SDW_ATTACH_TIMEOUT 500 27 - #define CS42L43_SDW_DETACH_TIMEOUT 100 32 + #define CS42L43_SDW_ATTACH_TIMEOUT_MS 500 33 + #define CS42L43_SDW_DETACH_TIMEOUT_MS 100 28 34 29 35 #define CS42L43_MCU_BOOT_STAGE1 1 30 36 #define CS42L43_MCU_BOOT_STAGE2 2 31 37 #define CS42L43_MCU_BOOT_STAGE3 3 32 38 #define CS42L43_MCU_BOOT_STAGE4 4 33 - #define CS42L43_MCU_POLL 5000 34 - #define CS42L43_MCU_CMD_TIMEOUT 20000 39 + #define CS42L43_MCU_POLL_US 5000 40 + #define CS42L43_MCU_CMD_TIMEOUT_US 20000 35 41 #define CS42L43_MCU_UPDATE_FORMAT 3 36 42 #define CS42L43_MCU_UPDATE_OFFSET 0x100000 37 - #define CS42L43_MCU_UPDATE_TIMEOUT 500000 43 + #define CS42L43_MCU_UPDATE_TIMEOUT_US 500000 38 44 #define CS42L43_MCU_UPDATE_RETRIES 5 39 45 40 46 #define CS42L43_MCU_SUPPORTED_REV 0x2105 41 47 #define CS42L43_MCU_SHADOW_REGS_REQUIRED_REV 0x2200 42 48 #define CS42L43_MCU_SUPPORTED_BIOS_REV 0x0001 43 49 44 - #define CS42L43_VDDP_DELAY 50 45 - #define CS42L43_VDDD_DELAY 1000 50 + #define CS42L43_VDDP_DELAY_US 50 51 + #define CS42L43_VDDD_DELAY_US 1000 46 52 47 - #define CS42L43_AUTOSUSPEND_TIME 250 53 + #define CS42L43_AUTOSUSPEND_TIME_MS 250 48 54 49 55 struct cs42l43_patch_header { 50 56 __le16 version; 51 57 __le16 size; 52 - u8 reserved; 53 - u8 secure; 58 + __u8 reserved; 59 + __u8 secure; 54 60 __le16 bss_size; 55 61 __le32 apply_addr; 56 62 __le32 checksum; ··· 90 84 { CS42L43_DRV_CTRL_5, 0x136C00C0 }, 91 85 { CS42L43_GPIO_CTRL1, 0x00000707 }, 92 86 { CS42L43_GPIO_CTRL2, 0x00000000 }, 93 - { CS42L43_GPIO_FN_SEL, 0x00000000 }, 87 + { CS42L43_GPIO_FN_SEL, 0x00000004 }, 94 88 { CS42L43_MCLK_SRC_SEL, 0x00000000 }, 95 89 { CS42L43_SAMPLE_RATE1, 0x00000003 }, 96 90 { CS42L43_SAMPLE_RATE2, 0x00000003 }, ··· 137 131 { CS42L43_ASP_TX_CH4_CTRL, 0x00170091 }, 138 132 { CS42L43_ASP_TX_CH5_CTRL, 0x001700C1 }, 139 133 { CS42L43_ASP_TX_CH6_CTRL, 0x001700F1 }, 140 - { CS42L43_ASPTX1_INPUT, 0x00800000 }, 141 - { CS42L43_ASPTX2_INPUT, 0x00800000 }, 142 - { CS42L43_ASPTX3_INPUT, 0x00800000 }, 143 - { CS42L43_ASPTX4_INPUT, 0x00800000 }, 144 - { CS42L43_ASPTX5_INPUT, 0x00800000 }, 145 - { CS42L43_ASPTX6_INPUT, 0x00800000 }, 146 - { CS42L43_SWIRE_DP1_CH1_INPUT, 0x00800000 }, 147 - { CS42L43_SWIRE_DP1_CH2_INPUT, 0x00800000 }, 148 - { CS42L43_SWIRE_DP1_CH3_INPUT, 0x00800000 }, 149 - { CS42L43_SWIRE_DP1_CH4_INPUT, 0x00800000 }, 150 - { CS42L43_SWIRE_DP2_CH1_INPUT, 0x00800000 }, 151 - { CS42L43_SWIRE_DP2_CH2_INPUT, 0x00800000 }, 152 - { CS42L43_SWIRE_DP3_CH1_INPUT, 0x00800000 }, 153 - { CS42L43_SWIRE_DP3_CH2_INPUT, 0x00800000 }, 154 - { CS42L43_SWIRE_DP4_CH1_INPUT, 0x00800000 }, 155 - { CS42L43_SWIRE_DP4_CH2_INPUT, 0x00800000 }, 156 - { CS42L43_ASRC_INT1_INPUT1, 0x00800000 }, 157 - { CS42L43_ASRC_INT2_INPUT1, 0x00800000 }, 158 - { CS42L43_ASRC_INT3_INPUT1, 0x00800000 }, 159 - { CS42L43_ASRC_INT4_INPUT1, 0x00800000 }, 160 - { CS42L43_ASRC_DEC1_INPUT1, 0x00800000 }, 161 - { CS42L43_ASRC_DEC2_INPUT1, 0x00800000 }, 162 - { CS42L43_ASRC_DEC3_INPUT1, 0x00800000 }, 163 - { CS42L43_ASRC_DEC4_INPUT1, 0x00800000 }, 164 - { CS42L43_ISRC1INT1_INPUT1, 0x00800000 }, 165 - { CS42L43_ISRC1INT2_INPUT1, 0x00800000 }, 166 - { CS42L43_ISRC1DEC1_INPUT1, 0x00800000 }, 167 - { CS42L43_ISRC1DEC2_INPUT1, 0x00800000 }, 168 - { CS42L43_ISRC2INT1_INPUT1, 0x00800000 }, 169 - { CS42L43_ISRC2INT2_INPUT1, 0x00800000 }, 170 - { CS42L43_ISRC2DEC1_INPUT1, 0x00800000 }, 171 - { CS42L43_ISRC2DEC2_INPUT1, 0x00800000 }, 134 + { CS42L43_ASPTX1_INPUT, 0x00000000 }, 135 + { CS42L43_ASPTX2_INPUT, 0x00000000 }, 136 + { CS42L43_ASPTX3_INPUT, 0x00000000 }, 137 + { CS42L43_ASPTX4_INPUT, 0x00000000 }, 138 + { CS42L43_ASPTX5_INPUT, 0x00000000 }, 139 + { CS42L43_ASPTX6_INPUT, 0x00000000 }, 140 + { CS42L43_SWIRE_DP1_CH1_INPUT, 0x00000000 }, 141 + { CS42L43_SWIRE_DP1_CH2_INPUT, 0x00000000 }, 142 + { CS42L43_SWIRE_DP1_CH3_INPUT, 0x00000000 }, 143 + { CS42L43_SWIRE_DP1_CH4_INPUT, 0x00000000 }, 144 + { CS42L43_SWIRE_DP2_CH1_INPUT, 0x00000000 }, 145 + { CS42L43_SWIRE_DP2_CH2_INPUT, 0x00000000 }, 146 + { CS42L43_SWIRE_DP3_CH1_INPUT, 0x00000000 }, 147 + { CS42L43_SWIRE_DP3_CH2_INPUT, 0x00000000 }, 148 + { CS42L43_SWIRE_DP4_CH1_INPUT, 0x00000000 }, 149 + { CS42L43_SWIRE_DP4_CH2_INPUT, 0x00000000 }, 150 + { CS42L43_ASRC_INT1_INPUT1, 0x00000000 }, 151 + { CS42L43_ASRC_INT2_INPUT1, 0x00000000 }, 152 + { CS42L43_ASRC_INT3_INPUT1, 0x00000000 }, 153 + { CS42L43_ASRC_INT4_INPUT1, 0x00000000 }, 154 + { CS42L43_ASRC_DEC1_INPUT1, 0x00000000 }, 155 + { CS42L43_ASRC_DEC2_INPUT1, 0x00000000 }, 156 + { CS42L43_ASRC_DEC3_INPUT1, 0x00000000 }, 157 + { CS42L43_ASRC_DEC4_INPUT1, 0x00000000 }, 158 + { CS42L43_ISRC1INT1_INPUT1, 0x00000000 }, 159 + { CS42L43_ISRC1INT2_INPUT1, 0x00000000 }, 160 + { CS42L43_ISRC1DEC1_INPUT1, 0x00000000 }, 161 + { CS42L43_ISRC1DEC2_INPUT1, 0x00000000 }, 162 + { CS42L43_ISRC2INT1_INPUT1, 0x00000000 }, 163 + { CS42L43_ISRC2INT2_INPUT1, 0x00000000 }, 164 + { CS42L43_ISRC2DEC1_INPUT1, 0x00000000 }, 165 + { CS42L43_ISRC2DEC2_INPUT1, 0x00000000 }, 172 166 { CS42L43_EQ1MIX_INPUT1, 0x00800000 }, 173 167 { CS42L43_EQ1MIX_INPUT2, 0x00800000 }, 174 168 { CS42L43_EQ1MIX_INPUT3, 0x00800000 }, ··· 177 171 { CS42L43_EQ2MIX_INPUT2, 0x00800000 }, 178 172 { CS42L43_EQ2MIX_INPUT3, 0x00800000 }, 179 173 { CS42L43_EQ2MIX_INPUT4, 0x00800000 }, 180 - { CS42L43_SPDIF1_INPUT1, 0x00800000 }, 181 - { CS42L43_SPDIF2_INPUT1, 0x00800000 }, 174 + { CS42L43_SPDIF1_INPUT1, 0x00000000 }, 175 + { CS42L43_SPDIF2_INPUT1, 0x00000000 }, 182 176 { CS42L43_AMP1MIX_INPUT1, 0x00800000 }, 183 177 { CS42L43_AMP1MIX_INPUT2, 0x00800000 }, 184 178 { CS42L43_AMP1MIX_INPUT3, 0x00800000 }, ··· 223 217 { CS42L43_CTRL_REG, 0x00000006 }, 224 218 { CS42L43_FDIV_FRAC, 0x40000000 }, 225 219 { CS42L43_CAL_RATIO, 0x00000080 }, 226 - { CS42L43_SPI_CLK_CONFIG1, 0x00000000 }, 220 + { CS42L43_SPI_CLK_CONFIG1, 0x00000001 }, 227 221 { CS42L43_SPI_CONFIG1, 0x00000000 }, 228 222 { CS42L43_SPI_CONFIG2, 0x00000000 }, 229 223 { CS42L43_SPI_CONFIG3, 0x00000001 }, ··· 538 532 regcache_cache_only(cs42l43->regmap, true); 539 533 regmap_multi_reg_write_bypassed(cs42l43->regmap, reset, ARRAY_SIZE(reset)); 540 534 541 - msleep(CS42L43_RESET_DELAY); 535 + msleep(CS42L43_RESET_DELAY_MS); 542 536 543 537 if (cs42l43->sdw) { 544 - unsigned long timeout = msecs_to_jiffies(CS42L43_SDW_DETACH_TIMEOUT); 538 + unsigned long timeout = msecs_to_jiffies(CS42L43_SDW_DETACH_TIMEOUT_MS); 545 539 unsigned long time; 546 540 547 541 time = wait_for_completion_timeout(&cs42l43->device_detach, timeout); ··· 561 555 static int cs42l43_wait_for_attach(struct cs42l43 *cs42l43) 562 556 { 563 557 if (!cs42l43->attached) { 564 - unsigned long timeout = msecs_to_jiffies(CS42L43_SDW_ATTACH_TIMEOUT); 558 + unsigned long timeout = msecs_to_jiffies(CS42L43_SDW_ATTACH_TIMEOUT_MS); 565 559 unsigned long time; 566 560 567 561 time = wait_for_completion_timeout(&cs42l43->device_attach, timeout); ··· 603 597 604 598 ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_BOOT_STATUS, 605 599 val, (val == CS42L43_MCU_BOOT_STAGE3), 606 - CS42L43_MCU_POLL, CS42L43_MCU_CMD_TIMEOUT); 600 + CS42L43_MCU_POLL_US, CS42L43_MCU_CMD_TIMEOUT_US); 607 601 if (ret) { 608 602 dev_err(cs42l43->dev, "Failed to move to stage 3: %d, 0x%x\n", ret, val); 609 603 return ret; ··· 652 646 653 647 ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_SOFT_INT_SHADOW, val, 654 648 (val & CS42L43_CONTROL_APPLIED_INT_MASK), 655 - CS42L43_MCU_POLL, CS42L43_MCU_CMD_TIMEOUT); 649 + CS42L43_MCU_POLL_US, CS42L43_MCU_CMD_TIMEOUT_US); 656 650 if (ret) { 657 651 dev_err(cs42l43->dev, "Failed to disable firmware: %d, 0x%x\n", ret, val); 658 652 return ret; ··· 696 690 697 691 ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_SOFT_INT_SHADOW, val, 698 692 (val & CS42L43_PATCH_APPLIED_INT_MASK), 699 - CS42L43_MCU_POLL, CS42L43_MCU_UPDATE_TIMEOUT); 693 + CS42L43_MCU_POLL_US, CS42L43_MCU_UPDATE_TIMEOUT_US); 700 694 if (ret) { 701 695 dev_err(cs42l43->dev, "Failed to update firmware: %d, 0x%x\n", ret, val); 702 696 cs42l43->firmware_error = ret; ··· 957 951 } 958 952 959 953 /* vdd-p must be on for 50uS before any other supply */ 960 - usleep_range(CS42L43_VDDP_DELAY, 2 * CS42L43_VDDP_DELAY); 954 + usleep_range(CS42L43_VDDP_DELAY_US, 2 * CS42L43_VDDP_DELAY_US); 961 955 962 956 gpiod_set_value_cansleep(cs42l43->reset, 1); 963 957 ··· 973 967 goto err_core_supplies; 974 968 } 975 969 976 - usleep_range(CS42L43_VDDD_DELAY, 2 * CS42L43_VDDD_DELAY); 970 + usleep_range(CS42L43_VDDD_DELAY_US, 2 * CS42L43_VDDD_DELAY_US); 977 971 978 972 return 0; 979 973 ··· 1057 1051 if (ret) 1058 1052 return ret; 1059 1053 1060 - pm_runtime_set_autosuspend_delay(cs42l43->dev, CS42L43_AUTOSUSPEND_TIME); 1054 + pm_runtime_set_autosuspend_delay(cs42l43->dev, CS42L43_AUTOSUSPEND_TIME_MS); 1061 1055 pm_runtime_use_autosuspend(cs42l43->dev); 1062 1056 pm_runtime_set_active(cs42l43->dev); 1063 1057 /* ··· 1065 1059 * the boot work runs. 1066 1060 */ 1067 1061 pm_runtime_get_noresume(cs42l43->dev); 1068 - devm_pm_runtime_enable(cs42l43->dev); 1062 + ret = devm_pm_runtime_enable(cs42l43->dev); 1063 + if (ret) 1064 + return ret; 1069 1065 1070 1066 queue_work(system_long_wq, &cs42l43->boot_work); 1071 1067

+6 -4

drivers/mfd/cs42l43.h

··· 6 6 * Cirrus Logic International Semiconductor Ltd. 7 7 */ 8 8 9 - #include <linux/mfd/cs42l43.h> 10 - #include <linux/pm.h> 11 - #include <linux/regmap.h> 12 - 13 9 #ifndef CS42L43_CORE_INT_H 14 10 #define CS42L43_CORE_INT_H 15 11 16 12 #define CS42L43_N_DEFAULTS 176 13 + 14 + struct dev_pm_ops; 15 + struct device; 16 + struct reg_default; 17 + 18 + struct cs42l43; 17 19 18 20 extern const struct dev_pm_ops cs42l43_pm_ops; 19 21 extern const struct reg_default cs42l43_reg_default[CS42L43_N_DEFAULTS];

+1 -1

drivers/mfd/da9052-core.c

··· 533 533 .reg_bits = 8, 534 534 .val_bits = 8, 535 535 536 - .cache_type = REGCACHE_RBTREE, 536 + .cache_type = REGCACHE_MAPLE, 537 537 538 538 .max_register = DA9052_PAGE1_CON_REG, 539 539 .readable_reg = da9052_reg_readable,

+1 -1

drivers/mfd/da9055-core.c

··· 245 245 .reg_bits = 8, 246 246 .val_bits = 8, 247 247 248 - .cache_type = REGCACHE_RBTREE, 248 + .cache_type = REGCACHE_MAPLE, 249 249 250 250 .max_register = DA9055_MAX_REGISTER_CNT, 251 251 .readable_reg = da9055_register_readable,

+2 -2

drivers/mfd/da9062-core.c

··· 476 476 .ranges = da9061_range_cfg, 477 477 .num_ranges = ARRAY_SIZE(da9061_range_cfg), 478 478 .max_register = DA9062AA_CONFIG_ID, 479 - .cache_type = REGCACHE_RBTREE, 479 + .cache_type = REGCACHE_MAPLE, 480 480 .rd_table = &da9061_aa_readable_table, 481 481 .wr_table = &da9061_aa_writeable_table, 482 482 .volatile_table = &da9061_aa_volatile_table, ··· 582 582 .ranges = da9062_range_cfg, 583 583 .num_ranges = ARRAY_SIZE(da9062_range_cfg), 584 584 .max_register = DA9062AA_CONFIG_ID, 585 - .cache_type = REGCACHE_RBTREE, 585 + .cache_type = REGCACHE_MAPLE, 586 586 .rd_table = &da9062_aa_readable_table, 587 587 .wr_table = &da9062_aa_writeable_table, 588 588 .volatile_table = &da9062_aa_volatile_table,

+1 -1

drivers/mfd/da9063-i2c.c

··· 342 342 .num_ranges = ARRAY_SIZE(da9063_range_cfg), 343 343 .max_register = DA9063_REG_CONFIG_ID, 344 344 345 - .cache_type = REGCACHE_RBTREE, 345 + .cache_type = REGCACHE_MAPLE, 346 346 }; 347 347 348 348 static const struct of_device_id da9063_dt_ids[] = {

+1 -1

drivers/mfd/da9150-core.c

··· 169 169 .num_ranges = ARRAY_SIZE(da9150_range_cfg), 170 170 .max_register = DA9150_TBAT_RES_B, 171 171 172 - .cache_type = REGCACHE_RBTREE, 172 + .cache_type = REGCACHE_MAPLE, 173 173 174 174 .volatile_reg = da9150_volatile_reg, 175 175 };

+20 -8

drivers/mfd/intel-lpss-pci.c

··· 23 23 24 24 #include "intel-lpss.h" 25 25 26 - /* Some DSDTs have an unused GEXP ACPI device conflicting with I2C4 resources */ 27 - static const struct pci_device_id ignore_resource_conflicts_ids[] = { 28 - /* Microsoft Surface Go (version 1) I2C4 */ 29 - { PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, 0x9d64, 0x152d, 0x1182), }, 30 - /* Microsoft Surface Go 2 I2C4 */ 31 - { PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, 0x9d64, 0x152d, 0x1237), }, 26 + static const struct pci_device_id quirk_ids[] = { 27 + { 28 + /* Microsoft Surface Go (version 1) I2C4 */ 29 + PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, 0x9d64, 0x152d, 0x1182), 30 + .driver_data = QUIRK_IGNORE_RESOURCE_CONFLICTS, 31 + }, 32 + { 33 + /* Microsoft Surface Go 2 I2C4 */ 34 + PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, 0x9d64, 0x152d, 0x1237), 35 + .driver_data = QUIRK_IGNORE_RESOURCE_CONFLICTS, 36 + }, 37 + { 38 + /* Dell XPS 9530 (2023) */ 39 + PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, 0x51fb, 0x1028, 0x0beb), 40 + .driver_data = QUIRK_CLOCK_DIVIDER_UNITY, 41 + }, 32 42 { } 33 43 }; 34 44 ··· 46 36 const struct pci_device_id *id) 47 37 { 48 38 const struct intel_lpss_platform_info *data = (void *)id->driver_data; 39 + const struct pci_device_id *quirk_pci_info; 49 40 struct intel_lpss_platform_info *info; 50 41 int ret; 51 42 ··· 66 55 info->mem = pci_resource_n(pdev, 0); 67 56 info->irq = pci_irq_vector(pdev, 0); 68 57 69 - if (pci_match_id(ignore_resource_conflicts_ids, pdev)) 70 - info->ignore_resource_conflicts = true; 58 + quirk_pci_info = pci_match_id(quirk_ids, pdev); 59 + if (quirk_pci_info) 60 + info->quirks = quirk_pci_info->driver_data; 71 61 72 62 pdev->d3cold_delay = 0; 73 63

+8 -1

drivers/mfd/intel-lpss.c

··· 300 300 { 301 301 char name[32]; 302 302 struct clk *tmp = *clk; 303 + int ret; 303 304 304 305 snprintf(name, sizeof(name), "%s-enable", devname); 305 306 tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 0, ··· 316 315 if (IS_ERR(tmp)) 317 316 return PTR_ERR(tmp); 318 317 *clk = tmp; 318 + 319 + if (lpss->info->quirks & QUIRK_CLOCK_DIVIDER_UNITY) { 320 + ret = clk_set_rate(tmp, lpss->info->clk_rate); 321 + if (ret) 322 + return ret; 323 + } 319 324 320 325 snprintf(name, sizeof(name), "%s-update", devname); 321 326 tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), ··· 419 412 return ret; 420 413 421 414 lpss->cell->swnode = info->swnode; 422 - lpss->cell->ignore_resource_conflicts = info->ignore_resource_conflicts; 415 + lpss->cell->ignore_resource_conflicts = info->quirks & QUIRK_IGNORE_RESOURCE_CONFLICTS; 423 416 424 417 intel_lpss_init_dev(lpss); 425 418

+13 -1

drivers/mfd/intel-lpss.h

··· 11 11 #ifndef __MFD_INTEL_LPSS_H 12 12 #define __MFD_INTEL_LPSS_H 13 13 14 + #include <linux/bits.h> 14 15 #include <linux/pm.h> 16 + 17 + /* 18 + * Some DSDTs have an unused GEXP ACPI device conflicting with I2C4 resources. 19 + * Set to ignore resource conflicts with ACPI declared SystemMemory regions. 20 + */ 21 + #define QUIRK_IGNORE_RESOURCE_CONFLICTS BIT(0) 22 + /* 23 + * Some devices have misconfigured clock divider due to a firmware bug. 24 + * Set this to force the clock divider to 1:1 ratio. 25 + */ 26 + #define QUIRK_CLOCK_DIVIDER_UNITY BIT(1) 15 27 16 28 struct device; 17 29 struct resource; ··· 31 19 32 20 struct intel_lpss_platform_info { 33 21 struct resource *mem; 34 - bool ignore_resource_conflicts; 35 22 int irq; 23 + unsigned int quirks; 36 24 unsigned long clk_rate; 37 25 const char *clk_con_id; 38 26 const struct software_node *swnode;

-37

drivers/mfd/kempld-core.c

··· 428 428 #ifdef CONFIG_ACPI 429 429 static int kempld_get_acpi_data(struct platform_device *pdev) 430 430 { 431 - struct list_head resource_list; 432 - struct resource *resources; 433 - struct resource_entry *rentry; 434 431 struct device *dev = &pdev->dev; 435 - struct acpi_device *acpi_dev = ACPI_COMPANION(dev); 436 432 const struct kempld_platform_data *pdata; 437 433 int ret; 438 - int count; 439 434 440 435 pdata = acpi_device_get_match_data(dev); 441 436 ret = platform_device_add_data(pdev, pdata, 442 437 sizeof(struct kempld_platform_data)); 443 - if (ret) 444 - return ret; 445 - 446 - INIT_LIST_HEAD(&resource_list); 447 - ret = acpi_dev_get_resources(acpi_dev, &resource_list, NULL, NULL); 448 - if (ret < 0) 449 - goto out; 450 - 451 - count = ret; 452 - 453 - if (count == 0) { 454 - ret = platform_device_add_resources(pdev, pdata->ioresource, 1); 455 - goto out; 456 - } 457 - 458 - resources = devm_kcalloc(&acpi_dev->dev, count, sizeof(*resources), 459 - GFP_KERNEL); 460 - if (!resources) { 461 - ret = -ENOMEM; 462 - goto out; 463 - } 464 - 465 - count = 0; 466 - list_for_each_entry(rentry, &resource_list, node) { 467 - memcpy(&resources[count], rentry->res, 468 - sizeof(*resources)); 469 - count++; 470 - } 471 - ret = platform_device_add_resources(pdev, resources, count); 472 - 473 - out: 474 - acpi_dev_free_resource_list(&resource_list); 475 438 476 439 return ret; 477 440 }

+1 -1

drivers/mfd/khadas-mcu.c

··· 72 72 .max_register = KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG, 73 73 .volatile_reg = khadas_mcu_reg_volatile, 74 74 .writeable_reg = khadas_mcu_reg_writeable, 75 - .cache_type = REGCACHE_RBTREE, 75 + .cache_type = REGCACHE_MAPLE, 76 76 }; 77 77 78 78 static struct mfd_cell khadas_mcu_fan_cells[] = {

+2 -2

drivers/mfd/lochnagar-i2c.c

··· 70 70 .use_single_read = true, 71 71 .use_single_write = true, 72 72 73 - .cache_type = REGCACHE_RBTREE, 73 + .cache_type = REGCACHE_MAPLE, 74 74 }; 75 75 76 76 static const struct reg_sequence lochnagar1_patch[] = { ··· 163 163 .readable_reg = lochnagar2_readable_register, 164 164 .volatile_reg = lochnagar2_volatile_register, 165 165 166 - .cache_type = REGCACHE_RBTREE, 166 + .cache_type = REGCACHE_MAPLE, 167 167 }; 168 168 169 169 static const struct reg_sequence lochnagar2_patch[] = {

+2 -1

drivers/mfd/lpc_ich.c

··· 38 38 39 39 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 40 40 41 + #include <linux/align.h> 41 42 #include <linux/kernel.h> 42 43 #include <linux/module.h> 43 44 #include <linux/errno.h> ··· 1322 1321 case INTEL_SPI_BYT: 1323 1322 pci_read_config_dword(dev, SPIBASE_BYT, &spi_base); 1324 1323 if (spi_base & SPIBASE_BYT_EN) { 1325 - res->start = spi_base & ~(SPIBASE_BYT_SZ - 1); 1324 + res->start = ALIGN_DOWN(spi_base, SPIBASE_BYT_SZ); 1326 1325 res->end = res->start + SPIBASE_BYT_SZ - 1; 1327 1326 1328 1327 info->set_writeable = lpc_ich_byt_set_writeable;

+11 -11

drivers/mfd/mc13xxx-core.c

··· 7 7 * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 8 8 */ 9 9 10 + #include <linux/bitfield.h> 10 11 #include <linux/module.h> 11 12 #include <linux/of.h> 12 13 #include <linux/of_device.h> ··· 175 174 } 176 175 EXPORT_SYMBOL(mc13xxx_irq_free); 177 176 178 - #define maskval(reg, mask) (((reg) & (mask)) >> __ffs(mask)) 179 177 static void mc13xxx_print_revision(struct mc13xxx *mc13xxx, u32 revision) 180 178 { 181 179 dev_info(mc13xxx->dev, "%s: rev: %d.%d, " 182 180 "fin: %d, fab: %d, icid: %d/%d\n", 183 181 mc13xxx->variant->name, 184 - maskval(revision, MC13XXX_REVISION_REVFULL), 185 - maskval(revision, MC13XXX_REVISION_REVMETAL), 186 - maskval(revision, MC13XXX_REVISION_FIN), 187 - maskval(revision, MC13XXX_REVISION_FAB), 188 - maskval(revision, MC13XXX_REVISION_ICID), 189 - maskval(revision, MC13XXX_REVISION_ICIDCODE)); 182 + FIELD_GET(MC13XXX_REVISION_REVFULL, revision), 183 + FIELD_GET(MC13XXX_REVISION_REVMETAL, revision), 184 + FIELD_GET(MC13XXX_REVISION_FIN, revision), 185 + FIELD_GET(MC13XXX_REVISION_FAB, revision), 186 + FIELD_GET(MC13XXX_REVISION_ICID, revision), 187 + FIELD_GET(MC13XXX_REVISION_ICIDCODE, revision)); 190 188 } 191 189 192 190 static void mc34708_print_revision(struct mc13xxx *mc13xxx, u32 revision) 193 191 { 194 192 dev_info(mc13xxx->dev, "%s: rev %d.%d, fin: %d, fab: %d\n", 195 193 mc13xxx->variant->name, 196 - maskval(revision, MC34708_REVISION_REVFULL), 197 - maskval(revision, MC34708_REVISION_REVMETAL), 198 - maskval(revision, MC34708_REVISION_FIN), 199 - maskval(revision, MC34708_REVISION_FAB)); 194 + FIELD_GET(MC34708_REVISION_REVFULL, revision), 195 + FIELD_GET(MC34708_REVISION_REVMETAL, revision), 196 + FIELD_GET(MC34708_REVISION_FIN, revision), 197 + FIELD_GET(MC34708_REVISION_FAB, revision)); 200 198 } 201 199 202 200 /* These are only exported for mc13xxx-i2c and mc13xxx-spi */

+1 -1

drivers/mfd/mcp-core.c

··· 41 41 drv->remove(mcp); 42 42 } 43 43 44 - static struct bus_type mcp_bus_type = { 44 + static const struct bus_type mcp_bus_type = { 45 45 .name = "mcp", 46 46 .match = mcp_bus_match, 47 47 .probe = mcp_bus_probe,

+1 -1

drivers/mfd/mfd-core.c

··· 29 29 struct device_node *np; 30 30 }; 31 31 32 - static struct device_type mfd_dev_type = { 32 + static const struct device_type mfd_dev_type = { 33 33 .name = "mfd_device", 34 34 }; 35 35

+3

drivers/mfd/mt6397-core.c

··· 142 142 .resources = mt6357_rtc_resources, 143 143 .of_compatible = "mediatek,mt6357-rtc", 144 144 }, { 145 + .name = "mt6357-sound", 146 + .of_compatible = "mediatek,mt6357-sound" 147 + }, { 145 148 .name = "mtk-pmic-keys", 146 149 .num_resources = ARRAY_SIZE(mt6357_keys_resources), 147 150 .resources = mt6357_keys_resources,

+1 -1

drivers/mfd/omap-usb-host.c

··· 699 699 } 700 700 701 701 for (i = 0; i < omap->nports; i++) { 702 - char clkname[30]; 702 + char clkname[40]; 703 703 704 704 /* clock names are indexed from 1*/ 705 705 snprintf(clkname, sizeof(clkname),

+1 -1

drivers/mfd/rave-sp.c

··· 358 358 359 359 ackid = atomic_inc_return(&sp->ackid); 360 360 reply.ackid = ackid; 361 - reply.code = rave_sp_reply_code((u8)command), 361 + reply.code = rave_sp_reply_code((u8)command); 362 362 363 363 mutex_lock(&sp->bus_lock); 364 364

+1 -1

drivers/mfd/rc5t583.c

··· 230 230 .volatile_reg = volatile_reg, 231 231 .max_register = RC5T583_MAX_REG, 232 232 .num_reg_defaults_raw = RC5T583_NUM_REGS, 233 - .cache_type = REGCACHE_RBTREE, 233 + .cache_type = REGCACHE_MAPLE, 234 234 }; 235 235 236 236 static int rc5t583_i2c_probe(struct i2c_client *i2c)

+1 -1

drivers/mfd/rk8xx-core.c

··· 43 43 }; 44 44 45 45 static const struct resource rk817_pwrkey_resources[] = { 46 - DEFINE_RES_IRQ(RK817_IRQ_PWRON_RISE), 47 46 DEFINE_RES_IRQ(RK817_IRQ_PWRON_FALL), 47 + DEFINE_RES_IRQ(RK817_IRQ_PWRON_RISE), 48 48 }; 49 49 50 50 static const struct resource rk817_charger_resources[] = {

+1 -1

drivers/mfd/rk8xx-spi.c

··· 34 34 .reg_bits = 16, 35 35 .val_bits = 8, 36 36 .max_register = RK806_BUCK_RSERVE_REG5, 37 - .cache_type = REGCACHE_RBTREE, 37 + .cache_type = REGCACHE_MAPLE, 38 38 .volatile_table = &rk806_volatile_table, 39 39 }; 40 40

+1 -1

drivers/mfd/rn5t618.c

··· 62 62 .val_bits = 8, 63 63 .volatile_reg = rn5t618_volatile_reg, 64 64 .max_register = RN5T618_MAX_REG, 65 - .cache_type = REGCACHE_RBTREE, 65 + .cache_type = REGCACHE_MAPLE, 66 66 }; 67 67 68 68 static const struct regmap_irq rc5t619_irqs[] = {

+2 -2

drivers/mfd/rohm-bd71828.c

··· 197 197 .val_bits = 8, 198 198 .volatile_table = &bd71815_volatile_regs, 199 199 .max_register = BD71815_MAX_REGISTER - 1, 200 - .cache_type = REGCACHE_RBTREE, 200 + .cache_type = REGCACHE_MAPLE, 201 201 }; 202 202 203 203 static const struct regmap_config bd71828_regmap = { ··· 205 205 .val_bits = 8, 206 206 .volatile_table = &bd71828_volatile_regs, 207 207 .max_register = BD71828_MAX_REGISTER, 208 - .cache_type = REGCACHE_RBTREE, 208 + .cache_type = REGCACHE_MAPLE, 209 209 }; 210 210 211 211 /*

+1 -1

drivers/mfd/rohm-bd718x7.c

··· 87 87 .val_bits = 8, 88 88 .volatile_table = &volatile_regs, 89 89 .max_register = BD718XX_MAX_REGISTER - 1, 90 - .cache_type = REGCACHE_RBTREE, 90 + .cache_type = REGCACHE_MAPLE, 91 91 }; 92 92 93 93 static int bd718xx_init_press_duration(struct regmap *regmap,

+1 -1

drivers/mfd/rohm-bd9576.c

··· 62 62 .val_bits = 8, 63 63 .volatile_table = &volatile_regs, 64 64 .max_register = BD957X_MAX_REGISTER, 65 - .cache_type = REGCACHE_RBTREE, 65 + .cache_type = REGCACHE_MAPLE, 66 66 }; 67 67 68 68 static struct regmap_irq bd9576_irqs[] = {

+1 -1

drivers/mfd/rsmu_i2c.c

··· 188 188 .ranges = rsmu_sabre_range_cfg, 189 189 .num_ranges = ARRAY_SIZE(rsmu_sabre_range_cfg), 190 190 .volatile_reg = rsmu_sabre_volatile_reg, 191 - .cache_type = REGCACHE_RBTREE, 191 + .cache_type = REGCACHE_MAPLE, 192 192 .can_multi_write = true, 193 193 }; 194 194

+1 -1

drivers/mfd/si476x-prop.c

··· 222 222 .reg_read = si476x_core_regmap_read, 223 223 .reg_write = si476x_core_regmap_write, 224 224 225 - .cache_type = REGCACHE_RBTREE, 225 + .cache_type = REGCACHE_MAPLE, 226 226 }; 227 227 228 228 struct regmap *devm_regmap_init_si476x(struct si476x_core *core)

+1 -1

drivers/mfd/stmfx.c

··· 53 53 .max_register = STMFX_REG_MAX, 54 54 .volatile_reg = stmfx_reg_volatile, 55 55 .writeable_reg = stmfx_reg_writeable, 56 - .cache_type = REGCACHE_RBTREE, 56 + .cache_type = REGCACHE_MAPLE, 57 57 }; 58 58 59 59 static const struct resource stmfx_pinctrl_resources[] = {

+1 -1

drivers/mfd/stpmic1.c

··· 63 63 static const struct regmap_config stpmic1_regmap_config = { 64 64 .reg_bits = 8, 65 65 .val_bits = 8, 66 - .cache_type = REGCACHE_RBTREE, 66 + .cache_type = REGCACHE_MAPLE, 67 67 .max_register = PMIC_MAX_REGISTER_ADDRESS, 68 68 .rd_table = &stpmic1_readable_table, 69 69 .wr_table = &stpmic1_writeable_table,

+3 -1

drivers/mfd/syscon.c

··· 238 238 return ERR_PTR(-ENODEV); 239 239 240 240 regmap = syscon_node_to_regmap(syscon_np); 241 - of_node_put(syscon_np); 241 + 242 + if (property) 243 + of_node_put(syscon_np); 242 244 243 245 return regmap; 244 246 }

+28

drivers/mfd/twl-core.c

··· 124 124 #define TWL6030_BASEADD_RSV 0x0000 125 125 #define TWL6030_BASEADD_ZERO 0x0000 126 126 127 + /* Some fields in TWL6030_PHOENIX_DEV_ON */ 128 + #define TWL6030_APP_DEVOFF BIT(0) 129 + #define TWL6030_CON_DEVOFF BIT(1) 130 + #define TWL6030_MOD_DEVOFF BIT(2) 131 + 127 132 /* Few power values */ 128 133 #define R_CFG_BOOT 0x05 129 134 ··· 692 687 twl_priv->ready = false; 693 688 } 694 689 690 + static void twl6030_power_off(void) 691 + { 692 + int err; 693 + u8 val; 694 + 695 + err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &val, TWL6030_PHOENIX_DEV_ON); 696 + if (err) 697 + return; 698 + 699 + val |= TWL6030_APP_DEVOFF | TWL6030_CON_DEVOFF | TWL6030_MOD_DEVOFF; 700 + twl_i2c_write_u8(TWL_MODULE_PM_MASTER, val, TWL6030_PHOENIX_DEV_ON); 701 + } 702 + 703 + 695 704 static struct of_dev_auxdata twl_auxdata_lookup[] = { 696 705 OF_DEV_AUXDATA("ti,twl4030-gpio", 0, "twl4030-gpio", NULL), 697 706 { /* sentinel */ }, ··· 869 850 NULL, 0, NULL); 870 851 if (status < 0) 871 852 goto free; 853 + } 854 + 855 + if (twl_class_is_6030()) { 856 + if (of_device_is_system_power_controller(node)) { 857 + if (!pm_power_off) 858 + pm_power_off = twl6030_power_off; 859 + else 860 + dev_warn(&client->dev, "Poweroff callback already assigned\n"); 861 + } 872 862 } 873 863 874 864 status = of_platform_populate(node, NULL, twl_auxdata_lookup,

+3

drivers/mfd/twl4030-power.c

··· 686 686 if (of_property_read_bool(node, "ti,use_poweroff")) 687 687 return true; 688 688 689 + if (of_device_is_system_power_controller(node->parent)) 690 + return true; 691 + 689 692 return false; 690 693 } 691 694

+1 -1

drivers/mfd/wm5102-tables.c

··· 1922 1922 .readable_reg = wm5102_readable_register, 1923 1923 .volatile_reg = wm5102_volatile_register, 1924 1924 1925 - .cache_type = REGCACHE_RBTREE, 1925 + .cache_type = REGCACHE_MAPLE, 1926 1926 .reg_defaults = wm5102_reg_default, 1927 1927 .num_reg_defaults = ARRAY_SIZE(wm5102_reg_default), 1928 1928 };

+1 -1

drivers/mfd/wm5110-tables.c

··· 3202 3202 .readable_reg = wm5110_readable_register, 3203 3203 .volatile_reg = wm5110_volatile_register, 3204 3204 3205 - .cache_type = REGCACHE_RBTREE, 3205 + .cache_type = REGCACHE_MAPLE, 3206 3206 .reg_defaults = wm5110_reg_default, 3207 3207 .num_reg_defaults = ARRAY_SIZE(wm5110_reg_default), 3208 3208 };

+18 -25

drivers/mfd/wm831x-auxadc.c

··· 152 152 static int wm831x_auxadc_read_polled(struct wm831x *wm831x, 153 153 enum wm831x_auxadc input) 154 154 { 155 - int ret, src, timeout; 155 + int ret, src; 156 156 157 157 mutex_lock(&wm831x->auxadc_lock); 158 158 ··· 179 179 goto disable; 180 180 } 181 181 182 - /* If we're not using interrupts then poll the 183 - * interrupt status register */ 184 - timeout = 5; 185 - while (timeout) { 186 - msleep(1); 182 + /* If we're not using interrupts then read the interrupt status register */ 183 + msleep(20); 187 184 188 - ret = wm831x_reg_read(wm831x, 189 - WM831X_INTERRUPT_STATUS_1); 190 - if (ret < 0) { 191 - dev_err(wm831x->dev, 192 - "ISR 1 read failed: %d\n", ret); 193 - goto disable; 194 - } 185 + ret = wm831x_reg_read(wm831x, WM831X_INTERRUPT_STATUS_1); 186 + if (ret < 0) { 187 + dev_err(wm831x->dev, 188 + "ISR 1 read failed: %d\n", ret); 189 + goto disable; 190 + } 195 191 196 - /* Did it complete? */ 197 - if (ret & WM831X_AUXADC_DATA_EINT) { 198 - wm831x_reg_write(wm831x, 199 - WM831X_INTERRUPT_STATUS_1, 200 - WM831X_AUXADC_DATA_EINT); 201 - break; 202 - } else { 203 - dev_err(wm831x->dev, 204 - "AUXADC conversion timeout\n"); 205 - ret = -EBUSY; 206 - goto disable; 207 - } 192 + /* Did it complete? */ 193 + if (ret & WM831X_AUXADC_DATA_EINT) { 194 + wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1, 195 + WM831X_AUXADC_DATA_EINT); 196 + } else { 197 + dev_err(wm831x->dev, 198 + "AUXADC conversion timeout\n"); 199 + ret = -EBUSY; 200 + goto disable; 208 201 } 209 202 210 203 ret = wm831x_reg_read(wm831x, WM831X_AUXADC_DATA);

+1 -1

drivers/mfd/wm8350-regmap.c

··· 325 325 .reg_bits = 8, 326 326 .val_bits = 16, 327 327 328 - .cache_type = REGCACHE_RBTREE, 328 + .cache_type = REGCACHE_MAPLE, 329 329 330 330 .max_register = WM8350_MAX_REGISTER, 331 331 .readable_reg = wm8350_readable,

+1 -1

drivers/mfd/wm8400-core.c

··· 100 100 101 101 .volatile_reg = wm8400_volatile, 102 102 103 - .cache_type = REGCACHE_RBTREE, 103 + .cache_type = REGCACHE_MAPLE, 104 104 }; 105 105 106 106 /**

+3 -3

drivers/mfd/wm97xx-core.c

··· 95 95 .reg_stride = 2, 96 96 .val_bits = 16, 97 97 .max_register = 0x7e, 98 - .cache_type = REGCACHE_RBTREE, 98 + .cache_type = REGCACHE_MAPLE, 99 99 100 100 .reg_defaults = wm9705_reg_defaults, 101 101 .num_reg_defaults = ARRAY_SIZE(wm9705_reg_defaults), ··· 163 163 .reg_stride = 2, 164 164 .val_bits = 16, 165 165 .max_register = 0x7e, 166 - .cache_type = REGCACHE_RBTREE, 166 + .cache_type = REGCACHE_MAPLE, 167 167 168 168 .reg_defaults = wm9712_reg_defaults, 169 169 .num_reg_defaults = ARRAY_SIZE(wm9712_reg_defaults), ··· 234 234 .reg_stride = 2, 235 235 .val_bits = 16, 236 236 .max_register = 0x7e, 237 - .cache_type = REGCACHE_RBTREE, 237 + .cache_type = REGCACHE_MAPLE, 238 238 239 239 .reg_defaults = wm9713_reg_defaults, 240 240 .num_reg_defaults = ARRAY_SIZE(wm9713_reg_defaults),

+2

drivers/spi/spi-cs42l43.c

··· 11 11 #include <linux/errno.h> 12 12 #include <linux/mfd/cs42l43.h> 13 13 #include <linux/mfd/cs42l43-regs.h> 14 + #include <linux/mod_devicetable.h> 14 15 #include <linux/module.h> 16 + #include <linux/of.h> 15 17 #include <linux/platform_device.h> 16 18 #include <linux/pm_runtime.h> 17 19 #include <linux/regmap.h>

+11

drivers/watchdog/Kconfig

··· 181 181 watchdog. Alternatively say M to compile the driver as a module, 182 182 which will be called bd9576_wdt. 183 183 184 + config CROS_EC_WATCHDOG 185 + tristate "ChromeOS EC-based watchdog" 186 + select WATCHDOG_CORE 187 + depends on CROS_EC 188 + help 189 + Watchdog driver for Chromebook devices equipped with embedded controller. 190 + Trigger event is recorded in EC and checked on the subsequent boot. 191 + 192 + To compile this driver as a module, choose M here: the 193 + module will be called cros_ec_wdt. 194 + 184 195 config DA9052_WATCHDOG 185 196 tristate "Dialog DA9052 Watchdog" 186 197 depends on PMIC_DA9052 || COMPILE_TEST

+1

drivers/watchdog/Makefile

··· 217 217 218 218 # Architecture Independent 219 219 obj-$(CONFIG_BD957XMUF_WATCHDOG) += bd9576_wdt.o 220 + obj-$(CONFIG_CROS_EC_WATCHDOG) += cros_ec_wdt.o 220 221 obj-$(CONFIG_DA9052_WATCHDOG) += da9052_wdt.o 221 222 obj-$(CONFIG_DA9055_WATCHDOG) += da9055_wdt.o 222 223 obj-$(CONFIG_DA9062_WATCHDOG) += da9062_wdt.o

+204

drivers/watchdog/cros_ec_wdt.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Copyright 2024 Google LLC. 4 + * Author: Lukasz Majczak <lma@chromium.com> 5 + */ 6 + 7 + #include <linux/err.h> 8 + #include <linux/kernel.h> 9 + #include <linux/module.h> 10 + #include <linux/mod_devicetable.h> 11 + #include <linux/platform_data/cros_ec_commands.h> 12 + #include <linux/platform_data/cros_ec_proto.h> 13 + #include <linux/platform_device.h> 14 + #include <linux/watchdog.h> 15 + 16 + #define CROS_EC_WATCHDOG_DEFAULT_TIME 30 /* seconds */ 17 + #define DRV_NAME "cros-ec-wdt" 18 + 19 + union cros_ec_wdt_data { 20 + struct ec_params_hang_detect req; 21 + struct ec_response_hang_detect resp; 22 + } __packed; 23 + 24 + static int cros_ec_wdt_send_cmd(struct cros_ec_device *cros_ec, 25 + union cros_ec_wdt_data *arg) 26 + { 27 + int ret; 28 + struct { 29 + struct cros_ec_command msg; 30 + union cros_ec_wdt_data data; 31 + } __packed buf = { 32 + .msg = { 33 + .version = 0, 34 + .command = EC_CMD_HANG_DETECT, 35 + .insize = (arg->req.command == EC_HANG_DETECT_CMD_GET_STATUS) ? 36 + sizeof(struct ec_response_hang_detect) : 37 + 0, 38 + .outsize = sizeof(struct ec_params_hang_detect), 39 + }, 40 + .data.req = arg->req 41 + }; 42 + 43 + ret = cros_ec_cmd_xfer_status(cros_ec, &buf.msg); 44 + if (ret < 0) 45 + return ret; 46 + 47 + arg->resp = buf.data.resp; 48 + 49 + return 0; 50 + } 51 + 52 + static int cros_ec_wdt_ping(struct watchdog_device *wdd) 53 + { 54 + struct cros_ec_device *cros_ec = watchdog_get_drvdata(wdd); 55 + union cros_ec_wdt_data arg; 56 + int ret; 57 + 58 + arg.req.command = EC_HANG_DETECT_CMD_RELOAD; 59 + ret = cros_ec_wdt_send_cmd(cros_ec, &arg); 60 + if (ret < 0) 61 + dev_dbg(wdd->parent, "Failed to ping watchdog (%d)", ret); 62 + 63 + return ret; 64 + } 65 + 66 + static int cros_ec_wdt_start(struct watchdog_device *wdd) 67 + { 68 + struct cros_ec_device *cros_ec = watchdog_get_drvdata(wdd); 69 + union cros_ec_wdt_data arg; 70 + int ret; 71 + 72 + /* Prepare watchdog on EC side */ 73 + arg.req.command = EC_HANG_DETECT_CMD_SET_TIMEOUT; 74 + arg.req.reboot_timeout_sec = wdd->timeout; 75 + ret = cros_ec_wdt_send_cmd(cros_ec, &arg); 76 + if (ret < 0) 77 + dev_dbg(wdd->parent, "Failed to start watchdog (%d)", ret); 78 + 79 + return ret; 80 + } 81 + 82 + static int cros_ec_wdt_stop(struct watchdog_device *wdd) 83 + { 84 + struct cros_ec_device *cros_ec = watchdog_get_drvdata(wdd); 85 + union cros_ec_wdt_data arg; 86 + int ret; 87 + 88 + arg.req.command = EC_HANG_DETECT_CMD_CANCEL; 89 + ret = cros_ec_wdt_send_cmd(cros_ec, &arg); 90 + if (ret < 0) 91 + dev_dbg(wdd->parent, "Failed to stop watchdog (%d)", ret); 92 + 93 + return ret; 94 + } 95 + 96 + static int cros_ec_wdt_set_timeout(struct watchdog_device *wdd, unsigned int t) 97 + { 98 + unsigned int old_timeout = wdd->timeout; 99 + int ret; 100 + 101 + wdd->timeout = t; 102 + ret = cros_ec_wdt_start(wdd); 103 + if (ret < 0) 104 + wdd->timeout = old_timeout; 105 + 106 + return ret; 107 + } 108 + 109 + static const struct watchdog_info cros_ec_wdt_ident = { 110 + .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, 111 + .firmware_version = 0, 112 + .identity = DRV_NAME, 113 + }; 114 + 115 + static const struct watchdog_ops cros_ec_wdt_ops = { 116 + .owner = THIS_MODULE, 117 + .ping = cros_ec_wdt_ping, 118 + .start = cros_ec_wdt_start, 119 + .stop = cros_ec_wdt_stop, 120 + .set_timeout = cros_ec_wdt_set_timeout, 121 + }; 122 + 123 + static int cros_ec_wdt_probe(struct platform_device *pdev) 124 + { 125 + struct device *dev = &pdev->dev; 126 + struct cros_ec_dev *ec_dev = dev_get_drvdata(dev->parent); 127 + struct cros_ec_device *cros_ec = ec_dev->ec_dev; 128 + struct watchdog_device *wdd; 129 + union cros_ec_wdt_data arg; 130 + int ret = 0; 131 + 132 + wdd = devm_kzalloc(&pdev->dev, sizeof(*wdd), GFP_KERNEL); 133 + if (!wdd) 134 + return -ENOMEM; 135 + 136 + arg.req.command = EC_HANG_DETECT_CMD_GET_STATUS; 137 + ret = cros_ec_wdt_send_cmd(cros_ec, &arg); 138 + if (ret < 0) 139 + return dev_err_probe(dev, ret, "Failed to get watchdog bootstatus"); 140 + 141 + wdd->parent = &pdev->dev; 142 + wdd->info = &cros_ec_wdt_ident; 143 + wdd->ops = &cros_ec_wdt_ops; 144 + wdd->timeout = CROS_EC_WATCHDOG_DEFAULT_TIME; 145 + wdd->min_timeout = EC_HANG_DETECT_MIN_TIMEOUT; 146 + wdd->max_timeout = EC_HANG_DETECT_MAX_TIMEOUT; 147 + if (arg.resp.status == EC_HANG_DETECT_AP_BOOT_EC_WDT) 148 + wdd->bootstatus = WDIOF_CARDRESET; 149 + 150 + arg.req.command = EC_HANG_DETECT_CMD_CLEAR_STATUS; 151 + ret = cros_ec_wdt_send_cmd(cros_ec, &arg); 152 + if (ret < 0) 153 + return dev_err_probe(dev, ret, "Failed to clear watchdog bootstatus"); 154 + 155 + watchdog_stop_on_reboot(wdd); 156 + watchdog_stop_on_unregister(wdd); 157 + watchdog_set_drvdata(wdd, cros_ec); 158 + platform_set_drvdata(pdev, wdd); 159 + 160 + return devm_watchdog_register_device(dev, wdd); 161 + } 162 + 163 + static int __maybe_unused cros_ec_wdt_suspend(struct platform_device *pdev, pm_message_t state) 164 + { 165 + struct watchdog_device *wdd = platform_get_drvdata(pdev); 166 + int ret = 0; 167 + 168 + if (watchdog_active(wdd)) 169 + ret = cros_ec_wdt_stop(wdd); 170 + 171 + return ret; 172 + } 173 + 174 + static int __maybe_unused cros_ec_wdt_resume(struct platform_device *pdev) 175 + { 176 + struct watchdog_device *wdd = platform_get_drvdata(pdev); 177 + int ret = 0; 178 + 179 + if (watchdog_active(wdd)) 180 + ret = cros_ec_wdt_start(wdd); 181 + 182 + return ret; 183 + } 184 + 185 + static const struct platform_device_id cros_ec_wdt_id[] = { 186 + { DRV_NAME, 0 }, 187 + {} 188 + }; 189 + 190 + static struct platform_driver cros_ec_wdt_driver = { 191 + .probe = cros_ec_wdt_probe, 192 + .suspend = pm_ptr(cros_ec_wdt_suspend), 193 + .resume = pm_ptr(cros_ec_wdt_resume), 194 + .driver = { 195 + .name = DRV_NAME, 196 + }, 197 + .id_table = cros_ec_wdt_id, 198 + }; 199 + 200 + module_platform_driver(cros_ec_wdt_driver); 201 + 202 + MODULE_DEVICE_TABLE(platform, cros_ec_wdt_id); 203 + MODULE_DESCRIPTION("Cros EC Watchdog Device Driver"); 204 + MODULE_LICENSE("GPL");

+10 -9

include/linux/mfd/cs42l43.h

··· 6 6 * Cirrus Logic International Semiconductor Ltd. 7 7 */ 8 8 9 - #include <linux/completion.h> 10 - #include <linux/device.h> 11 - #include <linux/gpio/consumer.h> 12 - #include <linux/mutex.h> 13 - #include <linux/regmap.h> 14 - #include <linux/regulator/consumer.h> 15 - #include <linux/soundwire/sdw.h> 16 - #include <linux/workqueue.h> 17 - 18 9 #ifndef CS42L43_CORE_EXT_H 19 10 #define CS42L43_CORE_EXT_H 20 11 12 + #include <linux/completion.h> 13 + #include <linux/mutex.h> 14 + #include <linux/regmap.h> 15 + #include <linux/regulator/consumer.h> 16 + #include <linux/workqueue.h> 17 + 21 18 #define CS42L43_N_SUPPLIES 3 19 + 20 + struct device; 21 + struct gpio_desc; 22 + struct sdw_slave; 22 23 23 24 enum cs42l43_irq_numbers { 24 25 CS42L43_PLL_LOST_LOCK,

+2 -2

include/linux/mfd/sun4i-gpadc.h

··· 81 81 #define SUN4I_GPADC_TEMP_DATA 0x20 82 82 #define SUN4I_GPADC_DATA 0x24 83 83 84 - #define SUN4I_GPADC_IRQ_FIFO_DATA 0 85 - #define SUN4I_GPADC_IRQ_TEMP_DATA 1 84 + #define SUN4I_GPADC_IRQ_FIFO_DATA 1 85 + #define SUN4I_GPADC_IRQ_TEMP_DATA 2 86 86 87 87 /* 10s delay before suspending the IP */ 88 88 #define SUN4I_GPADC_AUTOSUSPEND_DELAY 10000

+11 -14

include/linux/mfd/syscon.h

··· 17 17 struct device_node; 18 18 19 19 #ifdef CONFIG_MFD_SYSCON 20 - extern struct regmap *device_node_to_regmap(struct device_node *np); 21 - extern struct regmap *syscon_node_to_regmap(struct device_node *np); 22 - extern struct regmap *syscon_regmap_lookup_by_compatible(const char *s); 23 - extern struct regmap *syscon_regmap_lookup_by_phandle( 24 - struct device_node *np, 25 - const char *property); 26 - extern struct regmap *syscon_regmap_lookup_by_phandle_args( 27 - struct device_node *np, 28 - const char *property, 29 - int arg_count, 30 - unsigned int *out_args); 31 - extern struct regmap *syscon_regmap_lookup_by_phandle_optional( 32 - struct device_node *np, 33 - const char *property); 20 + struct regmap *device_node_to_regmap(struct device_node *np); 21 + struct regmap *syscon_node_to_regmap(struct device_node *np); 22 + struct regmap *syscon_regmap_lookup_by_compatible(const char *s); 23 + struct regmap *syscon_regmap_lookup_by_phandle(struct device_node *np, 24 + const char *property); 25 + struct regmap *syscon_regmap_lookup_by_phandle_args(struct device_node *np, 26 + const char *property, 27 + int arg_count, 28 + unsigned int *out_args); 29 + struct regmap *syscon_regmap_lookup_by_phandle_optional(struct device_node *np, 30 + const char *property); 34 31 #else 35 32 static inline struct regmap *device_node_to_regmap(struct device_node *np) 36 33 {

+1

include/linux/mfd/twl.h

··· 461 461 462 462 #define TWL4030_PM_MASTER_GLOBAL_TST 0xb6 463 463 464 + #define TWL6030_PHOENIX_DEV_ON 0x06 464 465 /*----------------------------------------------------------------------*/ 465 466 466 467 /* Power bus message definitions */

+35 -43

include/linux/platform_data/cros_ec_commands.h

··· 3961 3961 } __ec_align1; 3962 3962 3963 3963 /*****************************************************************************/ 3964 - /* Power button hang detect */ 3965 - 3964 + /* AP hang detect */ 3966 3965 #define EC_CMD_HANG_DETECT 0x009F 3967 3966 3968 - /* Reasons to start hang detection timer */ 3969 - /* Power button pressed */ 3970 - #define EC_HANG_START_ON_POWER_PRESS BIT(0) 3967 + #define EC_HANG_DETECT_MIN_TIMEOUT 5 3968 + #define EC_HANG_DETECT_MAX_TIMEOUT 65535 3971 3969 3972 - /* Lid closed */ 3973 - #define EC_HANG_START_ON_LID_CLOSE BIT(1) 3970 + /* EC hang detect commands */ 3971 + enum ec_hang_detect_cmds { 3972 + /* Reload AP hang detect timer. */ 3973 + EC_HANG_DETECT_CMD_RELOAD = 0x0, 3974 3974 3975 - /* Lid opened */ 3976 - #define EC_HANG_START_ON_LID_OPEN BIT(2) 3975 + /* Stop AP hang detect timer. */ 3976 + EC_HANG_DETECT_CMD_CANCEL = 0x1, 3977 3977 3978 - /* Start of AP S3->S0 transition (booting or resuming from suspend) */ 3979 - #define EC_HANG_START_ON_RESUME BIT(3) 3978 + /* Configure watchdog with given reboot timeout and 3979 + * cancel currently running AP hang detect timer. 3980 + */ 3981 + EC_HANG_DETECT_CMD_SET_TIMEOUT = 0x2, 3980 3982 3981 - /* Reasons to cancel hang detection */ 3983 + /* Get last hang status - whether the AP boot was clear or not */ 3984 + EC_HANG_DETECT_CMD_GET_STATUS = 0x3, 3982 3985 3983 - /* Power button released */ 3984 - #define EC_HANG_STOP_ON_POWER_RELEASE BIT(8) 3985 - 3986 - /* Any host command from AP received */ 3987 - #define EC_HANG_STOP_ON_HOST_COMMAND BIT(9) 3988 - 3989 - /* Stop on end of AP S0->S3 transition (suspending or shutting down) */ 3990 - #define EC_HANG_STOP_ON_SUSPEND BIT(10) 3991 - 3992 - /* 3993 - * If this flag is set, all the other fields are ignored, and the hang detect 3994 - * timer is started. This provides the AP a way to start the hang timer 3995 - * without reconfiguring any of the other hang detect settings. Note that 3996 - * you must previously have configured the timeouts. 3997 - */ 3998 - #define EC_HANG_START_NOW BIT(30) 3999 - 4000 - /* 4001 - * If this flag is set, all the other fields are ignored (including 4002 - * EC_HANG_START_NOW). This provides the AP a way to stop the hang timer 4003 - * without reconfiguring any of the other hang detect settings. 4004 - */ 4005 - #define EC_HANG_STOP_NOW BIT(31) 3986 + /* Clear last hang status. Called when AP is rebooting/shutting down 3987 + * gracefully. 3988 + */ 3989 + EC_HANG_DETECT_CMD_CLEAR_STATUS = 0x4 3990 + }; 4006 3991 4007 3992 struct ec_params_hang_detect { 4008 - /* Flags; see EC_HANG_* */ 4009 - uint32_t flags; 3993 + uint16_t command; /* enum ec_hang_detect_cmds */ 3994 + /* Timeout in seconds before generating reboot */ 3995 + uint16_t reboot_timeout_sec; 3996 + } __ec_align2; 4010 3997 4011 - /* Timeout in msec before generating host event, if enabled */ 4012 - uint16_t host_event_timeout_msec; 3998 + /* Status codes that describe whether AP has boot normally or the hang has been 3999 + * detected and EC has reset AP 4000 + */ 4001 + enum ec_hang_detect_status { 4002 + EC_HANG_DETECT_AP_BOOT_NORMAL = 0x0, 4003 + EC_HANG_DETECT_AP_BOOT_EC_WDT = 0x1, 4004 + EC_HANG_DETECT_AP_BOOT_COUNT, 4005 + }; 4013 4006 4014 - /* Timeout in msec before generating warm reboot, if enabled */ 4015 - uint16_t warm_reboot_timeout_msec; 4016 - } __ec_align4; 4017 - 4007 + struct ec_response_hang_detect { 4008 + uint8_t status; /* enum ec_hang_detect_status */ 4009 + } __ec_align1; 4018 4010 /*****************************************************************************/ 4019 4011 /* Commands for battery charging */ 4020 4012

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