tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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dt-bindings: clock: rockchip: Add RK3506 clock and reset unit

Add device tree bindings for clock and reset unit on RK3506 SoC.
Add clock and reset IDs for RK3506 SoC.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20251121075350.2564860-2-zhangqing@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

authored by

Finley Xiao and committed by
Heiko Stuebner 84898f8e 652c108c

+551
+55
Documentation/devicetree/bindings/clock/rockchip,rk3506-cru.yaml
··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/rockchip,rk3506-cru.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Rockchip RK3506 Clock and Reset Unit (CRU) 8 + 9 + maintainers: 10 + - Finley Xiao <finley.xiao@rock-chips.com> 11 + - Heiko Stuebner <heiko@sntech.de> 12 + 13 + description: 14 + The RK3506 CRU generates the clock and also implements reset for SoC 15 + peripherals. 16 + 17 + properties: 18 + compatible: 19 + const: rockchip,rk3506-cru 20 + 21 + reg: 22 + maxItems: 1 23 + 24 + "#clock-cells": 25 + const: 1 26 + 27 + "#reset-cells": 28 + const: 1 29 + 30 + clocks: 31 + maxItems: 1 32 + 33 + clock-names: 34 + const: xin 35 + 36 + required: 37 + - compatible 38 + - reg 39 + - "#clock-cells" 40 + - "#reset-cells" 41 + - clocks 42 + - clock-names 43 + 44 + additionalProperties: false 45 + 46 + examples: 47 + - | 48 + clock-controller@ff9a0000 { 49 + compatible = "rockchip,rk3506-cru"; 50 + reg = <0xff9a0000 0x20000>; 51 + #clock-cells = <1>; 52 + #reset-cells = <1>; 53 + clocks = <&xin24m>; 54 + clock-names = "xin"; 55 + };
+285
include/dt-bindings/clock/rockchip,rk3506-cru.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) 2023-2025 Rockchip Electronics Co., Ltd. 4 + * Author: Finley Xiao <finley.xiao@rock-chips.com> 5 + */ 6 + 7 + #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3506_H 8 + #define _DT_BINDINGS_CLK_ROCKCHIP_RK3506_H 9 + 10 + /* cru plls */ 11 + #define PLL_GPLL 0 12 + #define PLL_V0PLL 1 13 + #define PLL_V1PLL 2 14 + 15 + /* cru-clocks indices */ 16 + #define ARMCLK 3 17 + #define CLK_DDR 4 18 + #define XIN24M_GATE 5 19 + #define CLK_GPLL_GATE 6 20 + #define CLK_V0PLL_GATE 7 21 + #define CLK_V1PLL_GATE 8 22 + #define CLK_GPLL_DIV 9 23 + #define CLK_GPLL_DIV_100M 10 24 + #define CLK_V0PLL_DIV 11 25 + #define CLK_V1PLL_DIV 12 26 + #define CLK_INT_VOICE_MATRIX0 13 27 + #define CLK_INT_VOICE_MATRIX1 14 28 + #define CLK_INT_VOICE_MATRIX2 15 29 + #define CLK_FRAC_UART_MATRIX0_MUX 16 30 + #define CLK_FRAC_UART_MATRIX1_MUX 17 31 + #define CLK_FRAC_VOICE_MATRIX0_MUX 18 32 + #define CLK_FRAC_VOICE_MATRIX1_MUX 19 33 + #define CLK_FRAC_COMMON_MATRIX0_MUX 20 34 + #define CLK_FRAC_COMMON_MATRIX1_MUX 21 35 + #define CLK_FRAC_COMMON_MATRIX2_MUX 22 36 + #define CLK_FRAC_UART_MATRIX0 23 37 + #define CLK_FRAC_UART_MATRIX1 24 38 + #define CLK_FRAC_VOICE_MATRIX0 25 39 + #define CLK_FRAC_VOICE_MATRIX1 26 40 + #define CLK_FRAC_COMMON_MATRIX0 27 41 + #define CLK_FRAC_COMMON_MATRIX1 28 42 + #define CLK_FRAC_COMMON_MATRIX2 29 43 + #define CLK_REF_USBPHY_TOP 30 44 + #define CLK_REF_DPHY_TOP 31 45 + #define ACLK_CORE_ROOT 32 46 + #define PCLK_CORE_ROOT 33 47 + #define PCLK_DBG 34 48 + #define PCLK_CORE_GRF 35 49 + #define PCLK_CORE_CRU 36 50 + #define CLK_CORE_EMA_DETECT 37 51 + #define CLK_REF_PVTPLL_CORE 38 52 + #define PCLK_GPIO1 39 53 + #define DBCLK_GPIO1 40 54 + #define ACLK_CORE_PERI_ROOT 41 55 + #define HCLK_CORE_PERI_ROOT 42 56 + #define PCLK_CORE_PERI_ROOT 43 57 + #define CLK_DSMC 44 58 + #define ACLK_DSMC 45 59 + #define PCLK_DSMC 46 60 + #define CLK_FLEXBUS_TX 47 61 + #define CLK_FLEXBUS_RX 48 62 + #define ACLK_FLEXBUS 49 63 + #define HCLK_FLEXBUS 50 64 + #define ACLK_DSMC_SLV 51 65 + #define HCLK_DSMC_SLV 52 66 + #define ACLK_BUS_ROOT 53 67 + #define HCLK_BUS_ROOT 54 68 + #define PCLK_BUS_ROOT 55 69 + #define ACLK_SYSRAM 56 70 + #define HCLK_SYSRAM 57 71 + #define ACLK_DMAC0 58 72 + #define ACLK_DMAC1 59 73 + #define HCLK_M0 60 74 + #define PCLK_BUS_GRF 61 75 + #define PCLK_TIMER 62 76 + #define CLK_TIMER0_CH0 63 77 + #define CLK_TIMER0_CH1 64 78 + #define CLK_TIMER0_CH2 65 79 + #define CLK_TIMER0_CH3 66 80 + #define CLK_TIMER0_CH4 67 81 + #define CLK_TIMER0_CH5 68 82 + #define PCLK_WDT0 69 83 + #define TCLK_WDT0 70 84 + #define PCLK_WDT1 71 85 + #define TCLK_WDT1 72 86 + #define PCLK_MAILBOX 73 87 + #define PCLK_INTMUX 74 88 + #define PCLK_SPINLOCK 75 89 + #define PCLK_DDRC 76 90 + #define HCLK_DDRPHY 77 91 + #define PCLK_DDRMON 78 92 + #define CLK_DDRMON_OSC 79 93 + #define PCLK_STDBY 80 94 + #define HCLK_USBOTG0 81 95 + #define HCLK_USBOTG0_PMU 82 96 + #define CLK_USBOTG0_ADP 83 97 + #define HCLK_USBOTG1 84 98 + #define HCLK_USBOTG1_PMU 85 99 + #define CLK_USBOTG1_ADP 86 100 + #define PCLK_USBPHY 87 101 + #define ACLK_DMA2DDR 88 102 + #define PCLK_DMA2DDR 89 103 + #define STCLK_M0 90 104 + #define CLK_DDRPHY 91 105 + #define CLK_DDRC_SRC 92 106 + #define ACLK_DDRC_0 93 107 + #define ACLK_DDRC_1 94 108 + #define CLK_DDRC 95 109 + #define CLK_DDRMON 96 110 + #define HCLK_LSPERI_ROOT 97 111 + #define PCLK_LSPERI_ROOT 98 112 + #define PCLK_UART0 99 113 + #define PCLK_UART1 100 114 + #define PCLK_UART2 101 115 + #define PCLK_UART3 102 116 + #define PCLK_UART4 103 117 + #define SCLK_UART0 104 118 + #define SCLK_UART1 105 119 + #define SCLK_UART2 106 120 + #define SCLK_UART3 107 121 + #define SCLK_UART4 108 122 + #define PCLK_I2C0 109 123 + #define CLK_I2C0 110 124 + #define PCLK_I2C1 111 125 + #define CLK_I2C1 112 126 + #define PCLK_I2C2 113 127 + #define CLK_I2C2 114 128 + #define PCLK_PWM1 115 129 + #define CLK_PWM1 116 130 + #define CLK_OSC_PWM1 117 131 + #define CLK_RC_PWM1 118 132 + #define CLK_FREQ_PWM1 119 133 + #define CLK_COUNTER_PWM1 120 134 + #define PCLK_SPI0 121 135 + #define CLK_SPI0 122 136 + #define PCLK_SPI1 123 137 + #define CLK_SPI1 124 138 + #define PCLK_GPIO2 125 139 + #define DBCLK_GPIO2 126 140 + #define PCLK_GPIO3 127 141 + #define DBCLK_GPIO3 128 142 + #define PCLK_GPIO4 129 143 + #define DBCLK_GPIO4 130 144 + #define HCLK_CAN0 131 145 + #define CLK_CAN0 132 146 + #define HCLK_CAN1 133 147 + #define CLK_CAN1 134 148 + #define HCLK_PDM 135 149 + #define MCLK_PDM 136 150 + #define CLKOUT_PDM 137 151 + #define MCLK_SPDIFTX 138 152 + #define HCLK_SPDIFTX 139 153 + #define HCLK_SPDIFRX 140 154 + #define MCLK_SPDIFRX 141 155 + #define MCLK_SAI0 142 156 + #define HCLK_SAI0 143 157 + #define MCLK_OUT_SAI0 144 158 + #define MCLK_SAI1 145 159 + #define HCLK_SAI1 146 160 + #define MCLK_OUT_SAI1 147 161 + #define HCLK_ASRC0 148 162 + #define CLK_ASRC0 149 163 + #define HCLK_ASRC1 150 164 + #define CLK_ASRC1 151 165 + #define PCLK_CRU 152 166 + #define PCLK_PMU_ROOT 153 167 + #define MCLK_ASRC0 154 168 + #define MCLK_ASRC1 155 169 + #define MCLK_ASRC2 156 170 + #define MCLK_ASRC3 157 171 + #define LRCK_ASRC0_SRC 158 172 + #define LRCK_ASRC0_DST 159 173 + #define LRCK_ASRC1_SRC 160 174 + #define LRCK_ASRC1_DST 161 175 + #define ACLK_HSPERI_ROOT 162 176 + #define HCLK_HSPERI_ROOT 163 177 + #define PCLK_HSPERI_ROOT 164 178 + #define CCLK_SRC_SDMMC 165 179 + #define HCLK_SDMMC 166 180 + #define HCLK_FSPI 167 181 + #define SCLK_FSPI 168 182 + #define PCLK_SPI2 169 183 + #define ACLK_MAC0 170 184 + #define ACLK_MAC1 171 185 + #define PCLK_MAC0 172 186 + #define PCLK_MAC1 173 187 + #define CLK_MAC_ROOT 174 188 + #define CLK_MAC0 175 189 + #define CLK_MAC1 176 190 + #define MCLK_SAI2 177 191 + #define HCLK_SAI2 178 192 + #define MCLK_OUT_SAI2 179 193 + #define MCLK_SAI3_SRC 180 194 + #define HCLK_SAI3 181 195 + #define MCLK_SAI3 182 196 + #define MCLK_OUT_SAI3 183 197 + #define MCLK_SAI4_SRC 184 198 + #define HCLK_SAI4 185 199 + #define MCLK_SAI4 186 200 + #define HCLK_DSM 187 201 + #define MCLK_DSM 188 202 + #define PCLK_AUDIO_ADC 189 203 + #define MCLK_AUDIO_ADC 190 204 + #define MCLK_AUDIO_ADC_DIV4 191 205 + #define PCLK_SARADC 192 206 + #define CLK_SARADC 193 207 + #define PCLK_OTPC_NS 194 208 + #define CLK_SBPI_OTPC_NS 195 209 + #define CLK_USER_OTPC_NS 196 210 + #define PCLK_UART5 197 211 + #define SCLK_UART5 198 212 + #define PCLK_GPIO234_IOC 199 213 + #define CLK_MAC_PTP_ROOT 200 214 + #define CLK_MAC0_PTP 201 215 + #define CLK_MAC1_PTP 202 216 + #define CLK_SPI2 203 217 + #define ACLK_VIO_ROOT 204 218 + #define HCLK_VIO_ROOT 205 219 + #define PCLK_VIO_ROOT 206 220 + #define HCLK_RGA 207 221 + #define ACLK_RGA 208 222 + #define CLK_CORE_RGA 209 223 + #define ACLK_VOP 210 224 + #define HCLK_VOP 211 225 + #define DCLK_VOP 212 226 + #define PCLK_DPHY 213 227 + #define PCLK_DSI_HOST 214 228 + #define PCLK_TSADC 215 229 + #define CLK_TSADC 216 230 + #define CLK_TSADC_TSEN 217 231 + #define PCLK_GPIO1_IOC 218 232 + #define PCLK_OTPC_S 219 233 + #define CLK_SBPI_OTPC_S 220 234 + #define CLK_USER_OTPC_S 221 235 + #define PCLK_OTP_MASK 222 236 + #define PCLK_KEYREADER 223 237 + #define HCLK_BOOTROM 224 238 + #define PCLK_DDR_SERVICE 225 239 + #define HCLK_CRYPTO_S 226 240 + #define HCLK_KEYLAD 227 241 + #define CLK_CORE_CRYPTO 228 242 + #define CLK_PKA_CRYPTO 229 243 + #define CLK_CORE_CRYPTO_S 230 244 + #define CLK_PKA_CRYPTO_S 231 245 + #define ACLK_CRYPTO_S 232 246 + #define HCLK_RNG_S 233 247 + #define CLK_CORE_CRYPTO_NS 234 248 + #define CLK_PKA_CRYPTO_NS 235 249 + #define ACLK_CRYPTO_NS 236 250 + #define HCLK_CRYPTO_NS 237 251 + #define HCLK_RNG 238 252 + #define CLK_PMU 239 253 + #define PCLK_PMU 240 254 + #define CLK_PMU_32K 241 255 + #define PCLK_PMU_CRU 242 256 + #define PCLK_PMU_GRF 243 257 + #define PCLK_GPIO0_IOC 244 258 + #define PCLK_GPIO0 245 259 + #define DBCLK_GPIO0 246 260 + #define PCLK_GPIO1_SHADOW 247 261 + #define DBCLK_GPIO1_SHADOW 248 262 + #define PCLK_PMU_HP_TIMER 249 263 + #define CLK_PMU_HP_TIMER 250 264 + #define CLK_PMU_HP_TIMER_32K 251 265 + #define PCLK_PWM0 252 266 + #define CLK_PWM0 253 267 + #define CLK_OSC_PWM0 254 268 + #define CLK_RC_PWM0 255 269 + #define CLK_MAC_OUT 256 270 + #define CLK_REF_OUT0 257 271 + #define CLK_REF_OUT1 258 272 + #define CLK_32K_FRAC 259 273 + #define CLK_32K_RC 260 274 + #define CLK_32K 261 275 + #define CLK_32K_PMU 262 276 + #define PCLK_TOUCH_KEY 263 277 + #define CLK_TOUCH_KEY 264 278 + #define CLK_REF_PHY_PLL 265 279 + #define CLK_REF_PHY_PMU_MUX 266 280 + #define CLK_WIFI_OUT 267 281 + #define CLK_V0PLL_REF 268 282 + #define CLK_V1PLL_REF 269 283 + #define CLK_32K_FRAC_MUX 270 284 + 285 + #endif
+211
include/dt-bindings/reset/rockchip,rk3506-cru.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) 2023-2025 Rockchip Electronics Co., Ltd. 4 + * Author: Finley Xiao <finley.xiao@rock-chips.com> 5 + */ 6 + 7 + #ifndef _DT_BINDINGS_REST_ROCKCHIP_RK3506_H 8 + #define _DT_BINDINGS_REST_ROCKCHIP_RK3506_H 9 + 10 + /* CRU-->SOFTRST_CON00 */ 11 + #define SRST_NCOREPORESET0_AC 0 12 + #define SRST_NCOREPORESET1_AC 1 13 + #define SRST_NCOREPORESET2_AC 2 14 + #define SRST_NCORESET0_AC 3 15 + #define SRST_NCORESET1_AC 4 16 + #define SRST_NCORESET2_AC 5 17 + #define SRST_NL2RESET_AC 6 18 + #define SRST_A_CORE_BIU_AC 7 19 + #define SRST_H_M0_AC 8 20 + 21 + /* CRU-->SOFTRST_CON02 */ 22 + #define SRST_NDBGRESET 9 23 + #define SRST_P_CORE_BIU 10 24 + #define SRST_PMU 11 25 + 26 + /* CRU-->SOFTRST_CON03 */ 27 + #define SRST_P_DBG 12 28 + #define SRST_POT_DBG 13 29 + #define SRST_P_CORE_GRF 14 30 + #define SRST_CORE_EMA_DETECT 15 31 + #define SRST_REF_PVTPLL_CORE 16 32 + #define SRST_P_GPIO1 17 33 + #define SRST_DB_GPIO1 18 34 + 35 + /* CRU-->SOFTRST_CON04 */ 36 + #define SRST_A_CORE_PERI_BIU 19 37 + #define SRST_A_DSMC 20 38 + #define SRST_P_DSMC 21 39 + #define SRST_FLEXBUS 22 40 + #define SRST_A_FLEXBUS 23 41 + #define SRST_H_FLEXBUS 24 42 + #define SRST_A_DSMC_SLV 25 43 + #define SRST_H_DSMC_SLV 26 44 + #define SRST_DSMC_SLV 27 45 + 46 + /* CRU-->SOFTRST_CON05 */ 47 + #define SRST_A_BUS_BIU 28 48 + #define SRST_H_BUS_BIU 29 49 + #define SRST_P_BUS_BIU 30 50 + #define SRST_A_SYSRAM 31 51 + #define SRST_H_SYSRAM 32 52 + #define SRST_A_DMAC0 33 53 + #define SRST_A_DMAC1 34 54 + #define SRST_H_M0 35 55 + #define SRST_M0_JTAG 36 56 + #define SRST_H_CRYPTO 37 57 + 58 + /* CRU-->SOFTRST_CON06 */ 59 + #define SRST_H_RNG 38 60 + #define SRST_P_BUS_GRF 39 61 + #define SRST_P_TIMER0 40 62 + #define SRST_TIMER0_CH0 41 63 + #define SRST_TIMER0_CH1 42 64 + #define SRST_TIMER0_CH2 43 65 + #define SRST_TIMER0_CH3 44 66 + #define SRST_TIMER0_CH4 45 67 + #define SRST_TIMER0_CH5 46 68 + #define SRST_P_WDT0 47 69 + #define SRST_T_WDT0 48 70 + #define SRST_P_WDT1 49 71 + #define SRST_T_WDT1 50 72 + #define SRST_P_MAILBOX 51 73 + #define SRST_P_INTMUX 52 74 + #define SRST_P_SPINLOCK 53 75 + 76 + /* CRU-->SOFTRST_CON07 */ 77 + #define SRST_P_DDRC 54 78 + #define SRST_H_DDRPHY 55 79 + #define SRST_P_DDRMON 56 80 + #define SRST_DDRMON_OSC 57 81 + #define SRST_P_DDR_LPC 58 82 + #define SRST_H_USBOTG0 59 83 + #define SRST_USBOTG0_ADP 60 84 + #define SRST_H_USBOTG1 61 85 + #define SRST_USBOTG1_ADP 62 86 + #define SRST_P_USBPHY 63 87 + #define SRST_USBPHY_POR 64 88 + #define SRST_USBPHY_OTG0 65 89 + #define SRST_USBPHY_OTG1 66 90 + 91 + /* CRU-->SOFTRST_CON08 */ 92 + #define SRST_A_DMA2DDR 67 93 + #define SRST_P_DMA2DDR 68 94 + 95 + /* CRU-->SOFTRST_CON09 */ 96 + #define SRST_USBOTG0_UTMI 69 97 + #define SRST_USBOTG1_UTMI 70 98 + 99 + /* CRU-->SOFTRST_CON10 */ 100 + #define SRST_A_DDRC_0 71 101 + #define SRST_A_DDRC_1 72 102 + #define SRST_A_DDR_BIU 73 103 + #define SRST_DDRC 74 104 + #define SRST_DDRMON 75 105 + 106 + /* CRU-->SOFTRST_CON11 */ 107 + #define SRST_H_LSPERI_BIU 76 108 + #define SRST_P_UART0 77 109 + #define SRST_P_UART1 78 110 + #define SRST_P_UART2 79 111 + #define SRST_P_UART3 80 112 + #define SRST_P_UART4 81 113 + #define SRST_UART0 82 114 + #define SRST_UART1 83 115 + #define SRST_UART2 84 116 + #define SRST_UART3 85 117 + #define SRST_UART4 86 118 + #define SRST_P_I2C0 87 119 + #define SRST_I2C0 88 120 + 121 + /* CRU-->SOFTRST_CON12 */ 122 + #define SRST_P_I2C1 89 123 + #define SRST_I2C1 90 124 + #define SRST_P_I2C2 91 125 + #define SRST_I2C2 92 126 + #define SRST_P_PWM1 93 127 + #define SRST_PWM1 94 128 + #define SRST_P_SPI0 95 129 + #define SRST_SPI0 96 130 + #define SRST_P_SPI1 97 131 + #define SRST_SPI1 98 132 + #define SRST_P_GPIO2 99 133 + #define SRST_DB_GPIO2 100 134 + 135 + /* CRU-->SOFTRST_CON13 */ 136 + #define SRST_P_GPIO3 101 137 + #define SRST_DB_GPIO3 102 138 + #define SRST_P_GPIO4 103 139 + #define SRST_DB_GPIO4 104 140 + #define SRST_H_CAN0 105 141 + #define SRST_CAN0 106 142 + #define SRST_H_CAN1 107 143 + #define SRST_CAN1 108 144 + #define SRST_H_PDM 109 145 + #define SRST_M_PDM 110 146 + #define SRST_PDM 111 147 + #define SRST_SPDIFTX 112 148 + #define SRST_H_SPDIFTX 113 149 + #define SRST_H_SPDIFRX 114 150 + #define SRST_SPDIFRX 115 151 + #define SRST_M_SAI0 116 152 + 153 + /* CRU-->SOFTRST_CON14 */ 154 + #define SRST_H_SAI0 117 155 + #define SRST_M_SAI1 118 156 + #define SRST_H_SAI1 119 157 + #define SRST_H_ASRC0 120 158 + #define SRST_ASRC0 121 159 + #define SRST_H_ASRC1 122 160 + #define SRST_ASRC1 123 161 + 162 + /* CRU-->SOFTRST_CON17 */ 163 + #define SRST_H_HSPERI_BIU 124 164 + #define SRST_H_SDMMC 125 165 + #define SRST_H_FSPI 126 166 + #define SRST_S_FSPI 127 167 + #define SRST_P_SPI2 128 168 + #define SRST_A_MAC0 129 169 + #define SRST_A_MAC1 130 170 + 171 + /* CRU-->SOFTRST_CON18 */ 172 + #define SRST_M_SAI2 131 173 + #define SRST_H_SAI2 132 174 + #define SRST_H_SAI3 133 175 + #define SRST_M_SAI3 134 176 + #define SRST_H_SAI4 135 177 + #define SRST_M_SAI4 136 178 + #define SRST_H_DSM 137 179 + #define SRST_M_DSM 138 180 + #define SRST_P_AUDIO_ADC 139 181 + #define SRST_M_AUDIO_ADC 140 182 + 183 + /* CRU-->SOFTRST_CON19 */ 184 + #define SRST_P_SARADC 141 185 + #define SRST_SARADC 142 186 + #define SRST_SARADC_PHY 143 187 + #define SRST_P_OTPC_NS 144 188 + #define SRST_SBPI_OTPC_NS 145 189 + #define SRST_USER_OTPC_NS 146 190 + #define SRST_P_UART5 147 191 + #define SRST_UART5 148 192 + #define SRST_P_GPIO234_IOC 149 193 + 194 + /* CRU-->SOFTRST_CON21 */ 195 + #define SRST_A_VIO_BIU 150 196 + #define SRST_H_VIO_BIU 151 197 + #define SRST_H_RGA 152 198 + #define SRST_A_RGA 153 199 + #define SRST_CORE_RGA 154 200 + #define SRST_A_VOP 155 201 + #define SRST_H_VOP 156 202 + #define SRST_VOP 157 203 + #define SRST_P_DPHY 158 204 + #define SRST_P_DSI_HOST 159 205 + #define SRST_P_TSADC 160 206 + #define SRST_TSADC 161 207 + 208 + /* CRU-->SOFTRST_CON22 */ 209 + #define SRST_P_GPIO1_IOC 162 210 + 211 + #endif